Display panel and display device

Abstract

A display panel and a display device. The display panel comprises a substrate, a first semiconductor layer, a first insulating layer, a second semiconductor layer, a second insulating layer, a third gate conductive layer, a third insulating layer, and a first source-drain conductive layer which are sequentially stacked. The insulating layers are provided with first openings and first through holes, the orthographic projection of the first openings on the substrate covers a bending area and passes through the first insulating layer and the second insulating layer, the third insulating layer is partially located within the first openings, the first through holes are located in a main body area, the third gate conductive layer extends into the first through holes and is connected to the first semiconductor layer, and the first openings and the first through holes are formed synchronously. The insulating layers are further provided with second openings and second through holes, the orthographic projection of the second openings on the substrate is within the range of the orthographic projection of the first openings on the substrate and covers the bending area, the second openings pass through the third insulating layer, the second through holes are located in the main body area, the first source-drain conductive layer extends into the second through holes and is connected to the first semiconductor layer, and the second openings and the second through holes are formed synchronously.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, display devices such as mobile phones, notebook computers or tablet computers are increasingly applied to people's lives. Organic light-emitting diode (OLED) display devices have the advantages of active light-emitting, wide viewing angle, high contrast, fast response speed, low power consumption, ultra-thin, etc., and therefore are widely concerned.

[0003] SUMMARY

[0004] In one aspect, a display panel is provided. The display panel includes a substrate, a first semiconductor layer, a first insulating layer, a second semiconductor layer, a second insulating layer, a third gate conductive layer, a third insulating layer, and a first source-drain conductive layer, which are sequentially stacked. The insulating layer has a first opening and a first via. A projection of the first opening on the substrate covers the bending region and penetrates through the first insulating layer and the second insulating layer. The third insulating layer is partially located in the first opening. The first via is located in the main body region and penetrates through the first insulating layer and the second insulating layer. The third gate conductive layer extends into the first via and is connected with the first semiconductor layer. The first opening and the first via are formed synchronously. The insulating layer also has a second opening and a second via. In the projection on the substrate, the second opening is located in the range of the first opening and covers the bending region. The second opening penetrates through the third insulating layer. The second via is located in the main body region and penetrates through the first insulating layer, the second insulating layer, and the third insulating layer. The first source-drain conductive layer extends into the second via and is connected with the first semiconductor layer. The second opening and the second via are formed synchronously.

[0005] In some embodiments, the display panel further includes a plurality of pixel circuits, and the plurality of pixel circuits are located on the substrate. Each pixel circuit includes a driving transistor. A control electrode of the driving transistor is connected with a first node, a first electrode is connected with a second node, and a second electrode is connected with a third node.

[0006] In some embodiments, the pixel circuit further comprises a first reset transistor. A first electrode of the first reset transistor is connected with a first initialization signal terminal, a second electrode is connected with the second node, and a control electrode is connected with a first reset signal terminal. The first semiconductor layer comprises a channel portion of the first reset transistor. The third gate conductive layer further comprises a first initialization signal line, which is connected with the first initialization signal terminal, and the first initialization signal line is connected with the first electrode of the first reset transistor through the first via hole.

[0007] In some embodiments, the pixel circuit further comprises a second reset transistor. A first electrode of the second reset transistor is connected with a second initialization signal terminal, a second electrode is connected with a fourth node, and a control electrode is connected with a second reset signal terminal. The first semiconductor layer comprises a channel portion of the second reset transistor. The third gate conductive layer further comprises a second initialization signal line, which is connected with the second initialization signal terminal, and the second initialization signal line is connected with the first electrode of the second reset transistor through the second via hole.

[0008] In some embodiments, the display panel further comprises a second gate conductive layer and a fifth insulating layer. The second gate conductive layer is located between the first insulating layer and the second semiconductor layer. The fifth insulating layer is located between the second gate conductive layer and the second semiconductor layer. The first opening, the first via hole and the second via hole penetrate through the fifth insulating layer. The insulating layer has a third via hole, which is located in the main body area, and the third via hole penetrates through the second insulating layer and the fifth insulating layer. The third gate conductive layer extends into the third via hole and is connected with the second gate conductive layer. The third via hole is formed synchronously with the first via hole.

[0009] In some embodiments, the pixel circuit further comprises a compensation transistor, a first electrode of the compensation transistor is connected with the first node, and a second electrode is connected with a third node. A control electrode is connected with a first scan signal end. The second semiconductor layer comprises a channel portion of the compensation transistor. The second gate conductive layer comprises a plurality of first scan signal lines, the first scan signal lines are connected with the first scan signal end, extend along a first direction, and are arranged along a second direction in an interval manner; the first scan signal lines comprise first main body segments and first connection segments connected alternately, in a normal projection to the substrate, the first main body segments overlap the channel portion of the compensation transistor, and the first connection segments are arranged away from the channel portion of the compensation transistor; wherein the first direction and the second direction intersect; the third gate conductive layer comprises a plurality of first conductive blocks arranged in an interval manner, a normal projection of the first conductive blocks on the substrate overlaps a normal projection of the channel portion of the compensation transistor on the substrate; wherein, in the normal projection to the substrate, the first conductive blocks overlap the first main body segments and are arranged away from the first connection segments, and the first conductive blocks are connected with the first main body segments through the third via holes.

[0010] In some embodiments, the pixel circuit further comprises a first storage capacitor, a first plate of the first storage capacitor is connected with the first node, and a second plate is connected with the first power signal end. In the normal projection to the substrate, one of the first scan signal lines is located between a row of the first storage capacitors and a row of the first electrodes of the compensation transistors. The first source-drain conductive layer further comprises a plurality of first connection lines, one end of the first connection lines is connected with the first electrode of the compensation transistor, and the other end is connected with the first plate, in the normal projection to the substrate, the first connection lines partially overlap the first connection segments and are arranged away from the first conductive blocks.

[0011] In some embodiments, the pixel circuit further includes a third reset transistor. A first electrode of the third reset transistor is connected to a third initialization signal terminal, a second electrode is connected to the first node, and a control electrode is connected to a third reset signal terminal. The second semiconductor layer includes a channel portion of the third reset transistor. The second gate conductive layer includes a plurality of third reset signal lines extending along a first direction and being spaced apart along a second direction. The third reset signal line includes a second main segment and a second connection segment alternately connected. In the orthogonal projection onto the substrate, the second main segment overlaps the channel portion of the third reset transistor, and the second connection segment is arranged away from the channel portion of the third reset transistor. The first direction and the second direction intersect. The third gate conductive layer includes a plurality of second conductive blocks spaced apart. The orthogonal projection of the second conductive block onto the substrate overlaps the orthogonal projection of the channel portion of the third reset transistor onto the substrate. In the orthogonal projection onto the substrate, the second conductive block overlaps the second main segment and is arranged away from the second connection segment. The second conductive block is connected to the second main segment through the third via hole.

[0012] In some embodiments, the display panel further includes a first gate conductive layer and a sixth insulating layer. The first gate conductive layer is located between the first insulating layer and the second gate conductive layer. The sixth insulating layer is located between the first gate conductive layer and the second gate conductive layer. The first opening, the first via hole, and the second via hole penetrate the sixth insulating layer. The insulating layer has a fourth via hole located in the main body area. The fourth via hole penetrates the second insulating layer, the fifth insulating layer, and the sixth insulating layer. The third gate conductive layer extends into the fourth via hole and is connected to the first gate conductive layer. The fourth via hole is formed synchronously with the first via hole.

[0013] In some embodiments, the pixel circuit further includes a first light emitting transistor. A first electrode of the first light emitting transistor is connected to the second node, a second electrode is connected to a first power signal terminal, and a control electrode is connected to a light emitting signal terminal. The first semiconductor layer includes a channel portion of the first light emitting transistor. The first gate conductive layer includes a plurality of third conductive blocks spaced apart. The orthogonal projection of the third conductive block onto the substrate overlaps the channel portion of the first light emitting transistor. The third gate conductive layer includes a plurality of light emitting signal lines extending along a first direction and being spaced apart along a second direction. The light emitting signal line and the third conductive block are connected through the fourth via hole. The first direction and the second direction intersect.

[0014] In some embodiments, the pixel circuit further comprises a first reset transistor. A first electrode of the first reset transistor is connected with a first initialization signal terminal, a second electrode is connected with the fourth node, and a control electrode is connected with a first reset signal terminal. The first semiconductor layer further comprises a channel portion of the driving transistor, a channel portion of the first reset transistor, and a first connection portion. A row of the channel portions of the first light emitting transistor is located on one side of a row of the channel portions of the driving transistor, a row of the channel portions of the first reset transistor is located on a side of a row of the first light emitting transistor away from the channel portions of the driving transistor, and the first connection portion is directly connected with the channel portions of the driving transistor, the channel portions of the first light emitting transistor, and the channel portions of the first reset transistor. In the orthographic projection onto the substrate, the third conductive block and the channel portions of the first reset transistor overlap, and the first connection portion is arranged staggered.

[0015] In some embodiments, the first semiconductor layer further comprises a second connection portion, the second connection portion is directly connected with the channel portions of the first light emitting transistor, and is connected with the first power signal terminal through the second via hole. The second connection portion is located on a side of a row of the channel portions of the first light emitting transistor away from a row of the channel portions of the first reset transistor.

[0016] In some embodiments, the pixel circuit further comprises a second light emitting transistor, a first electrode of the second light emitting transistor is connected with the third node, a second electrode is connected with the fourth node, and a control electrode is connected with a light emitting signal terminal. The first gate conductive layer comprises a plurality of fourth conductive blocks arranged at intervals, and an orthographic projection of the fourth conductive block onto the substrate overlaps with an orthographic projection of the channel portion of the second light emitting transistor onto the substrate. The light emitting signal line is further connected with the fourth conductive block through the fourth via hole.

[0017] In some embodiments, the pixel circuit further comprises a first storage capacitor and a second reset transistor. A first plate of the first storage capacitor is connected with the first node, and a second plate is connected with the first power signal terminal. A first electrode of the second reset transistor is connected with the second initialization signal terminal, a second electrode is connected with the fourth node, and a control electrode is connected with the second reset signal terminal. The first semiconductor layer further comprises a channel portion of the driving transistor, a channel portion of the second light-emitting transistor, a channel portion of the second reset transistor, and a third connection portion. The first gate conductive layer comprises a first plate of the first storage capacitor. A normal projection of the first plate of the first storage capacitor on the substrate covers the channel portion of the driving transistor. A row of the channel portions of the second light-emitting transistor is located on one side of a row of the channel portions of the driving transistor, and the channel portion of the second light-emitting transistor is at least partially located between two adjacent first storage capacitors. A row of the channel portions of the second reset transistor is located on a side of a row of the channel portions of the second light-emitting transistor, away from a row of the channel portions of the driving transistor. The channel portion of the second reset transistor is located on one side of the first plate of the first storage capacitor. One end of the third connection portion is directly connected with the channel portion of the second light-emitting transistor, and the other end is directly connected with the channel portion of the first reset transistor.

[0018] In another aspect, a display device is provided. The display device comprises the display panel according to any one of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings described in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0020] FIG. 1 is a structural diagram of a display device according to some embodiments;

[0021] FIG. 2 is another structural diagram of a display device according to some embodiments;

[0022] FIG. 3 is a structural diagram of a display panel according to some embodiments;

[0023] FIG. 4 is a sectional view along the section line C-C in FIG. 3;

[0024] FIG. 5 is a structural diagram of a display panel having a main area and a bending area according to some embodiments;

[0025] FIG. 6 is another structure diagram of a display panel having a main area and a bending area, according to some embodiments;

[0026] FIG. 7 is a structure diagram of a display panel having a main area, a bending area and a binding area in a flat state, according to some embodiments;

[0027] FIG. 8 is a structure diagram of a display panel having a main area, a bending area and a binding area in a bending state, according to some embodiments;

[0028] FIG. 9 is a structure diagram of a display panel having a first opening and a second opening, according to some embodiments;

[0029] FIG. 10 is a structure diagram of a display panel having a first via hole, a second via hole, a third via hole, a fourth via hole and a fifth via hole, according to some embodiments;

[0030] FIG. 11 is a structure diagram of a pixel circuit being 7T1C, according to some embodiments;

[0031] FIG. 12 is a structure diagram of a pixel circuit being 8T1C, according to some embodiments;

[0032] FIG. 13 is a structure diagram of a film layer of a display panel, according to some embodiments;

[0033] FIG. 14 is another structure diagram of a film layer of a display panel, according to some embodiments;

[0034] FIG. 15 is yet another structure diagram of a film layer of a display panel, according to some embodiments;

[0035] FIG. 16 is yet another structure diagram of a film layer of a display panel, according to some embodiments;

[0036] FIG. 17 is yet another structure diagram of a film layer of a display panel, according to some embodiments;

[0037] FIG. 18 is yet another structure diagram of a film layer of a display panel, according to some embodiments;

[0038] FIG. 19 is yet another structure diagram of a film layer of a display panel, according to some embodiments;

[0039] FIG. 20 is yet another structure diagram of a film layer of a display panel, according to some embodiments;

[0040] FIG. 21 is a sectional view along the section line C-C in FIG. 3;

[0041] FIG. 22 is yet another structure diagram of a film layer of a display panel, according to some embodiments. DETAILED DESCRIPTION

[0042] In the following, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0043] Unless otherwise required by context, the term "comprise" and its other forms such as "comprises" and "comprising" are to be construed as open-ended, i.e. as "including, but not limited to", in the description and the claims. In the description, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are not necessarily referring to the same embodiment or example. Furthermore, the described features, structures, materials or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0044] In the following, the terms "first", "second", etc. are used only for the purpose of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0045] In describing some embodiments, "coupled" and "connected" and their derivatives can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" or "communicatively coupled" can also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0046] “A, B, and C at least one of” has the same meaning as “at least one of A, B, or C,” and includes the following combinations: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0047] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0048] As used herein, the term “if’ is optionally interpreted as meaning “when” or “upon” or “in response to a determination” or “in response to a detection” depending on the context. Similarly, the phrase “if determined” or “if detected [a stated condition or event]” is optionally interpreted as meaning “upon a determination” or “in response to a determination” or “upon a detection” or “in response to a detection” of [a stated condition or event] depending on the context.

[0049] Use of “adapted to” or “configured to” herein means open and inclusive language that does not exclude devices that are adapted to or configured to perform additional tasks or steps.

[0050] Additionally, use of “based on” means open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values can in practice be based on additional conditions or values beyond those stated.

[0051] As used herein, “about,” “approximately,” or “circa” includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0052] As used herein, “parallel,” “perpendicular,” “equal” includes the recited condition and conditions that approximate the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallel and near parallel, where near parallel can have an acceptable range of deviation of, e.g., within 5°; “perpendicular” includes absolute perpendicular and near perpendicular, where near perpendicular can also have an acceptable range of deviation of, e.g., within 5°. “Equal” includes absolute equality and near equality, where near equality can have an acceptable range of deviation of, e.g., a difference between the two that is less than or equal to 5% of either.

[0053] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0054] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the individual features of actual implementations are necessarily shown in a particular figure. Additionally, it will be understood that when a feature is shown in a particular figure, that feature can also be used in other figures, unless specifically noted otherwise. Furthermore, examples of processes, steps, procedures and / or algorithms presented herein are intended to be simplistic representations of actual implementation that can have additional steps, procedures, and / or features that are not present in this example. Additionally, any process, step, procedure, and / or algorithm can be performed sequentially, in parallel, and / or in an order other than that shown herein. Therefore, the exemplary embodiments should not be interpreted as being limited to the specific examples presented herein, but rather are provided for illustrative purposes.

[0055] As shown in FIG. 1, some embodiments of the disclosure provide a display device 1000, which can be any device that displays anything whether moving (e.g., video) or stationary (e.g., still image) and whether text or image.

[0056] Exemplarily, the display device 1000 can be any product or component having a display function, such as a television, a notebook computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigation device, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, an in-vehicle display, a flight display, etc.

[0057] In some examples, the display device 1000 can be a portable display product. For example, the display device 1000 can be a mobile phone.

[0058] In yet other examples, the display device 1000 can be a wearable device. For example, the display device 1000 can be a watch.

[0059] In some embodiments, as shown in FIG. 2, the display device 1000 includes a display panel 100, a driving circuit board 200, a housing 300, and a cover plate 400.

[0060] The display panel 100 has an opposite light-emitting side 100A and a non-light-emitting side 100B. The light-emitting side 100A refers to a side (the upper side of the display panel 100 in FIG. 2) from which the display panel 100 can emit light. The non-light-emitting side 100B refers to the other side (the lower side of the display panel 100 in FIG. 2) opposite the light-emitting side 100A.

[0061] The driving circuit board 200 is disposed on the non-light-emitting side of the display panel 100 and is connected to the display panel 100 to provide a light-emitting signal to the display panel 100.

[0062] The housing 300 can have a box-like structure with an opening. The display panel 100 and the driving circuit board 200 can be disposed in the housing 300. The cover plate 400 is disposed on the light-emitting side of the display panel 100 and is located at the opening of the housing 300.

[0063] As shown in FIG. 2, the longitudinal section of the housing 300 can be, for example, in a U shape. The display panel 100 and the driving circuit board 200 are disposed in the housing 300. The cover plate 400 is disposed at the opening of the housing 300.

[0064] The type of the display panel 100 described above includes various types, which can be selected and disposed according to actual needs.

[0065] Exemplarily, the display panel 100 described above can be an organic light-emitting diode (OLED) display panel 100, a quantum dot light-emitting diode (QLED) display panel 100, an active matrix organic light-emitting diode (AMOLED) display panel 100, a liquid crystal display (LCD) display panel 100, or a mini / micro light-emitting display (MLED) display panel 100, and the like. The embodiments of the present disclosure are not specifically limited herein.

[0066] Hereinafter, some embodiments of the present disclosure will be described schematically with the display panel 100 being an OLED display panel 100 as an example.

[0067] In some embodiments, as shown in FIGS. 3 and 4, the display panel 100 includes a substrate 10 and a plurality of sub-pixels 20.

[0068] The material used for the substrate 10 can include a polymer resin or glass. Exemplarily, the substrate 10 can be flexible, and the material used for the substrate 10 includes one of a polymer resin such as Polyethersulfone (PES), Polyarylate (PAR), Polyetherimide (PEI), Polyethylene Naphthalate Two Formic Acid Glycol Ester (PEN), Polyethylene Terephthalate (PET), Polyphenyl Sulfide Granula (PPS), Polyimide (PI), Polycarbonate (PC), and Cellulose Acetate Propionate (CAP). Exemplarily, the substrate 10 can be rigid, and include a glass material containing SiO2 as a main component.

[0069] As shown in FIG. 3, the plurality of sub-pixels 20 are disposed on the substrate 10.

[0070] Exemplarily, as shown in FIG. 3, the plurality of sub-pixels 20 can be arranged in multiple rows and multiple columns, each row of sub-pixels 20 includes at least two sub-pixels 20 arranged along a first direction X, and each column of sub-pixels 20 includes at least two sub-pixels 20 arranged along a second direction Y. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular.

[0071] In some examples, the plurality of sub-pixels 20 can include first sub-pixels with a first color, second sub-pixels with a second color, and third sub-pixels with a third color. The first color, the second color, and the third color are three primary colors. For example, the first color is red, the second color is blue, and the third color is green, which are not specifically limited in the embodiments of the present disclosure.

[0072] In other examples, the plurality of sub-pixels 20 can include first sub-pixels with a first color, second sub-pixels with a second color, third sub-pixels with a third color, and fourth sub-pixels with a fourth color. The first color, the second color, and the third color are three primary colors, and the fourth color is white. For example, the first color is red, the second color is blue, and the third color is green.

[0073] As shown in FIG. 4, it can be understood that the sub-pixel 20 includes a pixel circuit 21 and a light emitting device 22. Each pixel circuit 21 includes a plurality of transistors 211 and a storage capacitor 212 (English: Capacitor, for short: C).

[0074] The transistor 211 used in the pixel circuit provided by the embodiments of the present disclosure can be a thin film transistor, a field effect transistor or other switch devices with the same characteristics, and the embodiments of the present disclosure are all described by taking the thin film transistor as an example.

[0075] For example, the transistor 211 is an oxide thin film transistor, and the carrier mobility of the oxide thin film transistor is relatively high.

[0076] Alternatively, for example, the transistor 211 is a low-temperature polysilicon thin film transistor, and the low-temperature polysilicon thin film transistor has high mobility and fast charging.

[0077] In some examples, as shown in FIG. 4, the plurality of transistors 211 includes a low-temperature polysilicon thin film transistor and an oxide thin film transistor. In this way, the low-temperature polysilicon transistor and the oxide transistor can be integrated on one display panel 100, which can reduce the power consumption of the display panel 100 and improve the display quality of the display panel 100.

[0078] As shown in FIG. 4, the transistor 211 includes an active part 2111, a source 2112, a drain 2113 and a gate 2114, and the source 2112 and the drain 2113 are in contact with the active part 2111, respectively. The storage capacitor 212 includes a first plate 2121 and a second plate 2122 arranged oppositely.

[0079] It should be noted that the source 2112 and the drain 2113 described above can be interchangeable, that is, 2112 in FIG. 4 represents the drain, and 2113 represents the source.

[0080] The structure of the pixel circuit 21 described above includes a plurality of structures, which can be selected and arranged according to actual needs. For example, the structure of the pixel circuit 21 can include a “2T1C”, “3T1C”, “6T1C”, “7T1C”, “6T2C” or “7T2C” structure. Among them, “T” represents the transistor 211, the number before “T” represents the number of transistors 211, and “C” represents the storage capacitor 212, and the number before “C” represents the number of storage capacitors 212.

[0081] In some examples, the plurality of transistors in the pixel circuit 21 can include P-type transistors and N-type transistors. In other examples, the plurality of transistors in the pixel circuit 21 can all be P-type transistors or can all be N-type transistors, which can simplify the process flow, reduce the process difficulty of the display panel 100, and improve the yield of the product.

[0082] In the following, an example is described in which each pixel circuit includes a low-temperature polysilicon thin-film transistor and an oxide thin-film transistor.

[0083] In some embodiments, as shown in FIGS. 5 and 6, the display panel 100 includes at least two main areas 101 and at least one bending area 102.

[0084] In some examples, as shown in FIGS. 5 and 6, the display panel 100 can include one bending area 102 and two main areas 101.

[0085] For example, as shown in FIG. 5, the bending area 102 extends along the first direction X, and the two main areas 101 are respectively arranged on two sides of the bending area 102 along the second direction Y. The two adjacent main areas 101 are connected through the bending area 102. That is, the at least two main areas 101 are arranged at intervals along the second direction Y, and any two adjacent main areas 101 are connected through one bending area 102.

[0086] Alternatively, for example, as shown in FIG. 6, the bending area 102 extends along the second direction Y, and the two main areas 101 are respectively arranged on two sides of the bending area 102 along the first direction X. The two adjacent main areas 101 are connected through the bending area 102. That is, the at least two main areas 101 are arranged at intervals along the first direction X, and any two adjacent main areas 101 are connected through one bending area 102.

[0087] For example, as shown in FIGS. 5 and 6, the two main areas 101 can be symmetrically arranged about the bending area 102, so that after the display panel 100 is bent, the two main areas 101 are flush at the ends away from the bending area 102.

[0088] It can be understood that, during the bending (rolling or folding) of the display panel 100, the bending area 102 is bent, and the main area 101 remains flat. It can be understood that the division of the bending area 102 and the main area 101 is based on whether deformation occurs during the bending of the display device, and the structures of the two areas can be the same.

[0089] Exemplarily, in the process of manufacturing the display panel 100, a plurality of sub-pixels P are formed on the same substrate 10, for example, a substrate made of polyimide. Then, a first region and second regions located on both sides of the first region are divided on the display panel 100. The substrate 10 and the sub-pixels P contained in the first region constitute the bending region 102, and the substrate 10 and the sub-pixels P contained in the second region constitute the main body region 101.

[0090] As can be seen from the above, the bending region 102 and the main body region 101 can be the same in structure. However, the two are different in state when the display panel 100 is bent. For example, in the bending process of the display panel 100, the bending region 102 will be bent, and the main body region 101 will remain in the original state (in a flat state).

[0091] In other embodiments, as shown in FIG. 7, the display panel 100 has a main body region 101, a binding region 103, and a bending region 102 located between the main body region 101 and the binding region 103.

[0092] As shown in FIG. 8, by a bending process, the display panel 100 located in the bending region 102 can be bent along the bending axis of the first direction X towards the non-light-emitting side 100B of the display panel 100 located in the main body region 101, so that the display panel 100 located in the binding region 103 is bent to the non-light-emitting side 100B of the display panel 100 located in the main body region 101, thereby reducing the frame of the display device 1000 (as shown in FIG. 1). The bending axis is not an actual structure existing in the display panel 100, but a concept proposed only to illustrate the bending process of the display panel 100.

[0093] It should be noted that the bending radius of the display panel 100 located in the bending region 102 can be 0.1 mm to 0.5 mm; for example, the bending radius of the display panel 100 located in the bending region 102 can be any one of 0.1 mm, 0.2 mm, 0.3 mm, 0.35 mm, 0.4 mm and 0.5 mm.

[0094] It should be understood that the smaller the bending radius of the display panel 100 located in the bending region 102, the narrower the frame of the display device 1000 corresponding to the display panel 100 located in the bending region 102 (such as the lower frame in FIG. 1) can be designed, which is more conducive to the narrow frame design of the display device 1000. Exemplarily, the bending radius of the display panel 100 located in the bending region 102 can be 0.1 mm to 0.2 mm, for example, the bending radius of the display panel 100 located in the bending region 102 can be any one of 0.12 mm, 0.15 mm and 0.18 mm, so that the frame of the display device 1000 corresponding to the display panel 100 located in the bending region 102 (such as the lower frame in FIG. 1) can be made narrower.

[0095] It should be noted that the bending radius of the display panel 100 located in the bending area 102 can be 0.1mm-0.5mm. For example, the bending radius of the display panel 100 located in the bending area 102 can be any one of 0.1mm, 0.2mm, 0.3mm, 0.35mm, 0.4mm and 0.5mm.

[0096] It should be understood that the smaller the bending radius of the display panel 100 located in the bending area 102, the narrower the frame (such as the lower frame in FIG. 1) of the display device 1000 corresponding to the display panel 100 located in the bending area 102 can be designed, which is more conducive to the narrow frame design of the display device 1000.

[0097] In some embodiments, as shown in FIG. 4, the display panel 100 further includes a first semiconductor layer ACT1, a first insulating layer 1, a second semiconductor layer ACT2, a second insulating layer 2, a third gate conductive layer GT3, a third insulating layer 3 and a first source-drain conductive layer SD1 which are sequentially stacked. The first semiconductor layer ACT1 is closer to the substrate 10 than the first source-drain conductive layer SD1.

[0098] The first semiconductor layer ACT1 includes the active part of the low-temperature polysilicon thin film transistor, the second semiconductor layer ACT2 includes the active part of the oxide thin film transistor, and the first source-drain conductive layer SD1 includes the source and drain of the low-temperature polysilicon thin film transistor and the source and drain of the oxide thin film transistor. The first insulating layer 1, the second insulating layer 2 and the third insulating layer 3 are inorganic layers, and the inorganic layers are more brittle and prone to breakage.

[0099] In some embodiments, as shown in FIG. 4, on the basis of the above-mentioned embodiments, the display panel 100 further includes a fourth insulating layer 4 located between the substrate and the first semiconductor layer ACT1. The fourth insulating layer 4 is also an inorganic layer. The fourth insulating layer 4 provides a good foundation for the first semiconductor layer ACT1 when the first semiconductor layer ACT1 is made on the substrate 10.

[0100] In related technologies, the insulating layer has a first type of opening, the orthographic projection of the first type of opening on the substrate covers the orthographic projection of the bending area on the substrate, and penetrates the first insulating layer, the second insulating layer and the third insulating layer. In the case where the display panel further includes a fourth insulating layer, the insulating layer also has a second type of opening, the second type of opening is located within the range of the first type of opening and covers the bending area, and the second type of opening penetrates the fourth insulating layer. In this way, the first type of opening and the second type of opening can remove the inorganic layer located in the bending area, and in the process of bending the display panel, the risk of breaking the display panel located in the bending area can be reduced, thereby improving the reliability of the display panel and prolonging the service life of the display panel.

[0101] The light transmittance and the pixel resolution of the display panel are large. The inventor has found that the insulating layer also has a first type of via hole and a second type of via hole, the first type of via hole penetrating the first insulating layer, the second insulating layer and the third insulating layer. The first source-drain conductive layer and the first semiconductor layer are connected through the first type of via hole, the second type of via hole penetrates the third insulating layer, and the first source-drain conductive layer and the third gate conductive layer are connected through the second type of via hole. Among them, the first type of via hole and the first opening are formed synchronously, and the second type of via hole and the second type of opening are formed synchronously.

[0102] The third gate conductive layer and the first semiconductor layer are connected through the first type of via hole and the second type of via hole (the first source-drain conductive layer as an adapter layer), that is, the third gate conductive layer and the first semiconductor layer are connected through two side-by-side via holes, on the one hand, the size of the pixel circuit is large, and the size of the sub-pixel is large, thereby resulting in a small pixel resolution of the display panel. On the other hand, the first type of via hole and the second type of via hole have metal, resulting in a large metal area (non-light transmission area) of the display panel and a small non-metal area (light transmission area), thereby resulting in a small light transmittance of the display panel and a poor effect of the display panel.

[0103] In order to solve the above technical problems, as shown in FIG. 9, an embodiment of the present disclosure provides a display panel 100, in which the insulating layer has a first opening 1001 and a second opening 1002. The first opening 1001 has a projection on the substrate 10, covers the projection of the bending area 102 on the substrate 10, and penetrates the first insulating layer 1 and the second insulating layer 2. The third insulating layer 3 is partially located in the first opening 1001. In the projection on the substrate 10, the second opening 1002 is located in the range of the first opening 1001 and covers the bending area 102, and the second opening 1002 penetrates the third insulating layer 3.

[0104] In this way, the first opening 1001 and the second opening 1002 can remove the inorganic layer located in the bending area 102, and in the process of bending the display panel 100, the risk of breaking the display panel 100 located in the bending area 102 can be reduced, thereby improving the reliability of the display panel 100 and prolonging the service life of the display panel 100.

[0105] It should be noted that in the case where the display panel 100 also includes a fourth insulating layer 4, the second opening 1002 also penetrates the fourth insulating layer 4.

[0106] In some examples, the depth of the first opening 1001 along the direction perpendicular to the substrate 10 is 0.6 μm to 1.2 μm, for example, the depth of the first opening 1001 along the direction perpendicular to the substrate 10 is 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm or 1.3 μm.

[0107] The second opening 1002 has a depth of 1-1.6 μm in a direction perpendicular to the substrate 10. For example, the second opening 1002 has a depth of 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, or 1.6 μm in a direction perpendicular to the substrate 10.

[0108] On the basis of the above-mentioned embodiments, as shown in FIG. 10, the insulating layer further has a first via hole 2001. The first via hole 2001 is located in the main body region 101, the first via hole 2001 penetrates the first insulating layer 1 and the second insulating layer 2, and the third gate conductive layer GT3 extends into the first via hole 2001 and is connected with the first semiconductor layer ACT1.

[0109] In this way, on the one hand, the third gate conductive layer GT3 extends into the first via hole 2001 and is connected with the first semiconductor layer ACT1, that is, the third gate conductive layer GT3 is connected with the first semiconductor layer ACT1 only through one via hole, which can make the size of the pixel circuit 21 smaller, the size of the sub-pixel 20 smaller, and be beneficial to improving the pixel resolution of the display panel 100. On the other hand, the metal area (non-transparent area) of the display panel 100 can be smaller, and the non-metal area (transparent area) of the display panel 100 can be larger, which is beneficial to improving the light transmittance of the display panel 100, so as to improve the effect of the display panel 100.

[0110] In some examples, the first via hole 2001 has a depth of 0.7-1.2 μm in a direction perpendicular to the substrate 10. For example, the first via hole 2001 has a depth of 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, or 1.2 μm in a direction perpendicular to the substrate 10.

[0111] In some embodiments, the first opening 1001 and the first via hole 2001 can be formed synchronously. The synchronous formation of the first opening 1001 and the first via hole 2001 refers to that the first opening 1001 and the first via hole 2001 are formed in the same process step.

[0112] In this way, the steps for preparing the display panel 100 can be reduced, the preparation time of the display panel 100 can be shortened, and the preparation efficiency of the display panel 100 can be improved.

[0113] In some embodiments, as shown in FIG. 10, the insulating layer further has a second via hole 2002, the second via hole 2002 is located in the main body region 101, the second via hole 2002 penetrates the first insulating layer 1, the second insulating layer 2, and the third insulating layer 3, and the first source-drain conductive layer SD1 extends into the second via hole 2002 and is connected with the first semiconductor layer ACT1.

[0114] In some examples, the second via hole 2002 has a depth of 1.1-1.5 μm in a direction perpendicular to the substrate 10. For example, the second via hole 2002 has a depth of 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, or 1.6 μm in a direction perpendicular to the substrate 10.

[0115] In some embodiments, the second opening 1002 and the second via hole 2002 are formed synchronously. In this case, the second opening 1002 and the second via hole 2002 are formed in the same process step.

[0116] In this way, the number of steps for manufacturing the display panel 100 can be further reduced, the manufacturing time of the display panel 100 can be shortened, and the manufacturing efficiency of the display panel 100 can be improved.

[0117] In some embodiments, the insulating layer further has a fifth via hole 2005 located in the main body region 101, the fifth via hole 2005 penetrates the second insulating layer 2 and the third insulating layer 3, and the first source-drain conductive layer SD1 extends into the fifth via hole 2005 to be connected with the second semiconductor layer ACT2. As known from the above, the first source-drain conductive layer SD1 includes the source and the drain of the oxide thin film transistor, and the second semiconductor layer ACT2 includes the active part of the oxide thin film transistor. In this way, the depth of the fifth via hole 2005 can be adapted to the thickness of the second insulating layer 2 and the third insulating layer 3, the risk of over-etching of the second semiconductor layer ACT2 can be reduced, the difference in contact resistance between the plurality of transistors with the same function can be reduced, the risk of Mura of the display panel 100 can be reduced, and the display effect of the display panel 100 can be improved.

[0118] In some embodiments, as shown in FIG. 11, the pixel circuit 21 is of an 8T1C structure. The pixel circuit 21 includes a driving transistor T1, a compensation transistor T2, a first light-emitting transistor T3, a second light-emitting transistor T4, a first reset transistor T5, a second reset transistor T6, a third reset transistor T7, a data writing transistor T8, and a first storage capacitor C1. Among them, the compensation transistor T2 is an N-type transistor, and the driving transistor T1, the first light-emitting transistor T3, the second light-emitting transistor T4, the first reset transistor T5, the second reset transistor T6, the third reset transistor T7, and the data writing transistor T8 are P-type transistors.

[0119] As shown in FIG. 11, the control electrode of the driving transistor T1 is connected with the first node N1, the first electrode is connected with the second node N2, and the second electrode is connected with the third node N3.

[0120] The first electrode of the compensation transistor T2 is connected with the third node N3, the second electrode is connected with the second node N2, and the control electrode is connected with the first scan signal terminal Gate1.

[0121] The first electrode of the first light emitting transistor T3 is connected with the first power signal terminal Vdd, the second electrode is connected with the second node N2, and the control electrode is connected with the light emitting signal terminal EM.

[0122] The first electrode of the second light emitting transistor T4 is connected with the third node N3, the second electrode is connected with the fourth node N4, and the control electrode is connected with the light emitting signal terminal EM. The fourth node N4 is used for connecting with the anode of the light emitting device 22.

[0123] The first electrode of the first reset transistor T5 is connected with the first initialization signal terminal Vinit1, the second electrode is connected with the second node N2, and the control electrode is connected with the first reset signal terminal Rst1. In this way, the first initialization signal received at the first initialization signal terminal Vinit1 can be written into the second node N2 through the first reset transistor, so as to initialize the second node N2, and the problem that the potential of the last image frame remaining in the second node N2 affects the display image of the next image frame can be improved, thereby improving the brightness uniformity of the display device 1000.

[0124] The first electrode of the second reset transistor T6 is connected with the second initialization signal terminal Vinit2, the second electrode is connected with the fourth node N4, and the control electrode is connected with the second reset signal terminal Rst2. In this way, the second initialization signal received at the second initialization signal terminal Vinit2 can be written into the fourth node through the second reset transistor T6, so as to initialize the fourth node N2, and the problem that the potential of the last image frame remaining in the fourth node N2 affects the display image of the next image frame can be improved, thereby improving the brightness uniformity of the display device 1000. The signal received at the second reset signal terminal Rst2 can be the same as the signal received at the first reset signal terminal Rst1.

[0125] The first electrode of the third reset transistor T7 is connected with the third initialization signal terminal Vinit3, the second electrode is connected with the third node N3, and the control electrode is connected with the third reset signal terminal Rst3. In this way, the third initialization signal received at the third initialization signal terminal Vinit3 can be written into the third node N3 through the third reset transistor T7, so as to initialize the third node N3, and the problem that the potential of the last image frame remaining in the third node N3 affects the display image of the next image frame can be improved, thereby improving the brightness uniformity of the display device 1000.

[0126] The first electrode of the data writing transistor T8 is connected with the data signal terminal Data, the second electrode is connected with the second node N2, and the control electrode is connected with the second scanning signal terminal Gate2.

[0127] The first plate 2121 of the first storage capacitor C1 is connected with the first node N1, and the second plate 2122 is connected with the first power signal terminal VDD.

[0128] In some other embodiments, as shown in FIG. 12, the pixel circuit 21 is of a 7T1C structure. The pixel circuit 21 includes a driving transistor T1, a compensation transistor T2, a first light-emitting transistor T3, a second light-emitting transistor T4, a second reset transistor T6, a third reset transistor T7, a data writing transistor T8, and a first storage capacitor C1. Among them, the compensation transistor T2 and the third reset transistor T7 are N-type transistors, and the driving transistor T1, the first light-emitting transistor T3, the second light-emitting transistor T4, the second reset transistor T6, and the data writing transistor T8 are P-type transistors. Among them, the signal received at the control electrode of the data writing transistor T8 is the same as the signal received at the second reset transistor T6.

[0129] The first electrode of the third reset transistor T7 is connected with the third initialization signal terminal Vinit3, the second electrode is connected with the first node N1, and the control electrode is connected with the third reset signal terminal Rst3. In this way, the third initialization signal received at the third initialization signal terminal Vinit3 can be written to the first node N1 through the third reset transistor, so as to initialize the first node N1, and can improve the problem that the residual of the previous image frame in the potential of the first node N1 affects the display image of the next image frame, thereby improving the brightness uniformity of the display device 1000.

[0130] In some embodiments, as shown in FIG. 13 and as shown in FIG. 14, the pixel circuit 21 is of an 8T1C structure, and the first semiconductor layer ACT1 includes a channel portion of the first reset transistor T5. The third gate conductive layer GT3 further includes a first initialization signal line VL1, the first initialization signal line VL1 is connected with the first initialization signal terminal Vinit1, and the first initialization signal line VL1 is connected with the first electrode (source electrode or drain electrode) of the first reset transistor T5 through the first via hole 2001.

[0131] In this way, compared with the case where the first initialization signal line and the first electrode of the first reset transistor are connected through the first type connection hole and the second type connection hole in the related art, the first initialization signal line VL1 and the first electrode of the first reset transistor T5 are connected through the first via hole 2001 in the embodiments of the present disclosure. On the one hand, the pixel resolution of the display panel 100 is improved. On the other hand, the light transmittance of the display panel 100 can be improved.

[0132] In some examples, as shown in FIGS. 13 and 14, the first initialization signal line VL1 includes a first wire segment VL11 and a plurality of second wire segments VL12. The first wire segment VL11 extends along the first direction X. The plurality of second wire segments VL12 extend along the second direction Y and are arranged at intervals along the first direction X. One end of the second wire segment VL12 is connected to the first wire segment VL11, and the other end is connected to the first electrode of the first reset transistor T5 through the first via hole 2001.

[0133] In some embodiments, as shown in FIGS. 13 and 14, the pixel circuit 21 is of an 8T1C structure, and the first semiconductor layer ACT1 further includes a channel portion of a second reset transistor T6. The third gate conductive layer GT3 further includes a second initialization signal line VL2, the second initialization signal line VL2 is connected to a second initialization signal end Vinit2, and the second initialization signal line VL2 is connected to the first electrode of the second reset transistor T6 through a second via hole 2002.

[0134] In this way, compared with the case where the second initialization signal line V and the first electrode of the second reset transistor are connected through the first type of connection hole and the second type of connection hole in the related art, the second initialization signal line VL2 and the first electrode of the second reset transistor T6 are connected through the first via hole 2001 in the embodiments of the present disclosure. On the one hand, the pixel resolution of the display panel 100 is improved. On the other hand, the light transmittance of the display panel 100 can be improved.

[0135] In some examples, as shown in FIGS. 13 and 14, the second initialization signal line VL2 includes a third wire segment VL21 and a plurality of fourth wire segments VL22. The third wire segment VL21 extends along the first direction X. The plurality of fourth wire segments VL22 extend along the second direction Y and are arranged at intervals along the first direction X. One end of the fourth wire segment VL22 is connected to the third wire segment VL21, and the other end is connected to the first electrode of the second reset transistor T6 through the first via hole 2001.

[0136] In some embodiments, as shown in FIGS. 13 and 14, the first gate conductive layer further includes a plurality of first reset signal lines RL1, the plurality of first reset signal lines RL1 extend along the first direction X and are arranged at intervals along the second direction Y. The orthogonal projection of the first reset signal line RL1 on the substrate 10 overlaps the channel portion of the first reset transistor T5 and the channel portion of the second reset transistor T6. That is, the portion of the first reset signal line RL1 overlapping the first reset transistor T5 forms the gate of the first reset transistor T5, and the portion overlapping the second reset transistor T6 forms the gate of the second reset transistor T6.

[0137] In some embodiments, as shown in FIG. 11, the display panel 100 further comprises a second gate conductive layer GT2 and a fifth insulating layer 5. The second gate conductive layer GT2 is located between the first insulating layer 1 and the second semiconductor layer ACT2. The fifth insulating layer 5 is located between the second gate conductive layer GT2 and the second semiconductor layer ACT2. The first opening 1001, the first via hole 2001 and the second via hole 2002 penetrate the fifth insulating layer 5.

[0138] In addition, the insulating layer has a third via hole 2003, the third via hole 2003 is located in the main body area 101, and the third via hole 2003 penetrates the second insulating layer 2 and the fifth insulating layer 5. The third gate conductive layer GT3 extends into the third via hole 2003 and is connected with the second gate conductive layer GT2. The third via hole 2003 is formed synchronously with the first via hole 2001.

[0139] In this way, the number of steps for manufacturing the display panel 100 can be further reduced, the manufacturing time of the display panel 100 can be shortened, and the manufacturing efficiency of the display panel 100 can be improved.

[0140] It should be noted that the thickness of the second gate conductive layer GT2 is relatively thick, for example, the thickness of the second gate conductive layer GT2 is 3000 angstroms, and the material of the second gate conductive layer GT2 is metal, for example, copper. Therefore, the second gate conductive layer GT2 can act as an etching stop layer. In the process of etching the inorganic layer to form the first via hole 2001 and the third via hole 2003, the second gate conductive layer GT2 will not be over-etched, or will be over-etched very thin.

[0141] In some embodiments, as shown in FIG. 15, FIG. 16 and FIG. 17, the pixel circuit 21 is a 7T1C structure or an 8T1C structure. The second semiconductor layer ACT2 includes a channel portion of a compensation transistor T2. The second gate conductive layer GT2 includes a plurality of first scan signal lines GL1, the first scan signal lines GL1 are connected with a first scan signal end Gate1, and the orthogonal projection of the first scan signal lines GL1 on the substrate 10 overlaps with the orthogonal projection of the channel portion of the compensation transistor T2 on the substrate 10. The third gate conductive layer GT3 includes a plurality of first conductive blocks 3001 arranged at intervals, in the orthogonal projection on the substrate 10, the first conductive blocks 3001 overlap with the first scan signal lines GL1 and the channel portion of the compensation transistor T2, and the first conductive blocks 3001 are connected with the first scan signal lines GL1 through the third via hole 2003. That is, the first conductive blocks 3001 act as the top gate of the compensation transistor T2, and the part of the first scan signal lines GL1 overlapping with the channel portion of the compensation transistor T2 acts as the bottom gate of the compensation transistor T2.

[0142] In this way, the first conductive block 3001 and the first scan signal line GL1 overlap less, the light transmission area in the display panel 100 can be increased, the light transmission rate of the display panel 100 is improved, and the display effect of the display panel 100 is improved.

[0143] In some examples, as shown in FIGS. 15, 16 and 17, the plurality of first scan signal lines GL1 extend along the first direction X and are spaced apart along the second direction Y. The first scan signal line GL1 includes first body segments GL11 and first connection segments GL12 alternately connected. In the orthogonal projection onto the substrate 10, the first body segment GL11 overlaps the channel portion of the compensation transistor T2 and the first conductive block 3001, and the first connection segment GL12 is arranged away from the channel portion of the compensation transistor T2 and the first conductive block 3001. The first conductive block 3001 is connected by the third via hole 2003 and the first body segment GL11. That is, the first body segment GL11 serves as the bottom gate of the compensation transistor T2.

[0144] In this way, the first connection segment GL12 and the first conductive block 3001 do not overlap, the difference in the light reflection area of the first connection segment GL12 in different regions can be reduced, the display consistency of the display panel 100 is improved, and the display effect of the display panel 100 is improved.

[0145] In some examples, as shown in FIGS. 15, 16 and 17, the line width of the first body segment GL11 is greater than the line width of the first connection segment GL12.

[0146] In some embodiments, as shown in FIGS. 15, 16 and 17, on the basis of the above-mentioned embodiments, the orthogonal projection of the first conductive block 3001 onto the substrate 10 is located within the range of the orthogonal projection of the first body segment GL11 onto the substrate 10.

[0147] In this way, the difference in the light reflection area of the first conductive block 3001 and the first body segment GL11 in different regions can be reduced, the display consistency of the display panel 100 is further improved, and the display effect of the display panel 100 is improved.

[0148] On the basis of the above-mentioned embodiments, as shown in FIGS. 18, 19 and 20, in the orthogonal projection onto the substrate 10, one first scan signal line GL1 is located between one row of first storage capacitors C1 and one row of first poles of compensation transistors T2. The first source-drain conductive layer SD1 further includes a plurality of first connection lines 4001, one end of the first connection line 4001 is connected to the first pole of the compensation transistor T2, the other end is connected to the first pole plate 2121, and in the orthogonal projection onto the substrate 10, the first connection line 4001 partially overlaps the first connection segment GL12 and is arranged away from the first conductive block 3001.

[0149] In this way, the first connection line 4001 only overlaps with the first scan signal line GL1, which can make the parasitic capacitance generated by the first connection line 4001 smaller, can reduce the difference in parasitic capacitance generated by multiple first connection lines 4001, and is beneficial to improve the display consistency of the display panel 100, so as to improve the display effect of the display panel 100.

[0150] In some embodiments, as shown in FIG. 15, the pixel circuit 21 is a 7T1C structure, and the second semiconductor layer ACT2 includes a channel portion of a third reset transistor T7. The second gate conductive layer GT2 includes a plurality of third reset signal lines RL3, the third reset signal lines RL3 are connected with a third reset signal end Rst3, and the orthogonal projection of the third reset signal lines RL3 on the substrate 10 overlaps with the orthogonal projection of the channel portion of the third reset transistor T7 on the substrate 10. The third gate conductive layer GT3 includes a plurality of second conductive blocks 3002 arranged at intervals, and in the orthogonal projection on the substrate 10, the second conductive blocks 3002 overlap with the third reset signal lines RL3 and the channel portion of the third reset transistor T7. The second conductive blocks 3002 are connected with the third reset signal lines RL3 through the third via holes 2003.

[0151] In this way, the second conductive blocks 3002 and the third reset signal lines RL3 overlap less, which can increase the light transmission area in the display panel 100, thereby improving the light transmission rate of the display panel 100, and is beneficial to improve the display effect of the display panel 100.

[0152] In some examples, as shown in FIG. 15, the plurality of third reset signal lines RL3 extend along the first direction X and are arranged at intervals along the second direction Y. The third reset signal lines RL3 include second main segments RL31 and second connection segments RL32 connected alternately, in the orthogonal projection on the substrate 10, the second main segments RL31 overlap with the channel portion of the third reset transistor T7 and the second conductive blocks 3002, and the second connection segments RL32 are arranged away from the channel portion of the third reset transistor T7 and the second conductive blocks 3002. The second conductive blocks 3002 are connected with the second main segments RL31 through the third via holes 2003.

[0153] In this way, the second connection segments RL32 and the second conductive blocks 3002 do not overlap, which can reduce the difference in the light reflection area of the second connection segments RL32 in different areas, and is beneficial to improve the display consistency of the display panel 100, so as to improve the display effect of the display panel 100.

[0154] In some examples, as shown in FIG. 15, the line width of the second main segments RL31 is greater than the line width of the second connection segments RL32.

[0155] In some embodiments, as shown in FIG. 15, on the basis of the above-mentioned embodiments, the orthographic projection of the second conductive block 3002 on the substrate 10 is located within the range of the orthographic projection of the second main body section RL31 on the substrate 10.

[0156] In this way, the difference between the reflective areas of the second conductive block 3002 and the second main body section RL31 in different areas can be reduced, which is conducive to further improving the display consistency of the display panel 100 and improving the display effect of the display panel 100.

[0157] In some embodiments, as shown in FIG. 3, the display panel 100 includes a display area A and a peripheral area B arranged on at least one side of the display area A. For example, as shown in FIGS. 5 and 6, the peripheral area B surrounds the display area A.

[0158] As shown in FIG. 3, the display area A is an area for displaying images and is configured to arrange a plurality of pixel units 13. The peripheral area B is an area for not displaying images and is configured to arrange display driving circuits, such as gate driving circuits and source driving circuits.

[0159] In some examples, as shown in FIGS. 5 and 6, the main body area 101 can be an area including a part of the display panel 100 for displaying images. That is, the above-mentioned display area A is located in the main body area 101, that is, the main body area 101 includes the display area A.

[0160] As shown in FIGS. 5 and 6, the main body area 101 can further include a part of the peripheral area B. For example, the orthographic projection of the main body area 101 on a reference plane is substantially any one of a circle, an ellipse, and a rectangle, and the like, which is not specifically limited in the embodiments of the present disclosure.

[0161] It should be noted that the reference plane is a plane in which the display panel 100 in the main body area 101 is located. The display surface refers to a side surface of the display panel 100 in the main body area 101 for displaying image information.

[0162] In this document, “substantially circular or elliptical” means that the shape as a whole is circular or elliptical, but is not limited to a standard circle or ellipse. That is, “circular or elliptical” here not only includes a substantially circular or elliptical shape, but also includes a shape similar to a circular or elliptical shape.

[0163] In the present disclosure, "substantially rectangular" means that the shape is generally rectangular, but is not limited to a standard rectangular shape. That is, the "rectangular" shape herein includes not only a substantially rectangular shape, but also a shape similar to a rectangular shape. For example, the long side and the short side of the rectangular shape are curved at each intersection (i.e., at the corners), that is, the corners are smooth, and the shape is a rounded rectangular shape. Hereinafter, the main body region 101 shown in FIGS. 5 and 6 is taken as an example in which the normal projection of the main body region 101 on the reference plane is a substantially rounded rectangular shape.

[0164] In some embodiments, as shown in FIG. 21, in the case where the display panel 100 includes the first scan signal line GL1, the first conductive block 3001, the third reset signal line RL3, and the second conductive block 3002, the first scan signal line GL1 and the first initialization signal line VL1 are extended from the display region A to the peripheral region B, and the first conductive block 3001 and the second conductive block 3002 are located in the display region.

[0165] In addition, the display panel 100 further includes a gate drive circuit 30, a first signal line 40, and a second signal line 50. The gate drive circuit 30 is located in the peripheral region B. The first signal line 40 is located in the peripheral region B, one end of the first signal line 40 is connected to a first output end in the gate drive circuit 30, and the other end is connected to the first scan signal line GL1 located in the peripheral region B. The second signal line 50 is located in the peripheral region B, one end of the second signal line 50 is connected to a third output end in the gate drive circuit 30, and the other end is connected to the third reset signal line RL3 located in the peripheral region B.

[0166] In this way, the first signal line 40 is connected only to the first scan signal line GL1 of one layer, and the second signal line 50 is connected only to the third reset signal line RL3 of one layer, so that the size of the connection of the first signal line 40 and the size of the connection of the second signal line 50 can be small. Thus, the peripheral region B can be narrowed.

[0167] In some examples, the inventor has found that the size of the narrowed peripheral region B can be greater than or equal to 10 μm. For example, the size of the narrowed peripheral region B can be 10 μm, 11 μm, 13 μm, 14 μm, 15 μm, 18 μm, 19 μm, 22 μm, 25 μm, or 30 μm.

[0168] In some embodiments, as shown in FIG. 10, the display panel 100 further includes a first gate conductive layer GT1 and a sixth insulating layer 6. The first gate conductive layer GT1 is located between the first insulating layer 1 and the second gate conductive layer GT2. The sixth insulating layer 6 is located between the first gate conductive layer GT1 and the second gate conductive layer GT2, and the first opening 1001, the first via hole 2001, and the second via hole 2002 penetrate the sixth insulating layer 6.

[0169] In addition, the insulating layer has a fourth via hole 2004 located in the main body area 101, the fourth via hole 2004 penetrating the second insulating layer 2, the fifth insulating layer 5 and the sixth insulating layer 6. The third gate conductive layer GT3 extends into the fourth via hole 2004 and is connected with the first gate conductive layer GT1. The fourth via hole 2004 is formed synchronously with the first via hole 2001.

[0170] In this way, the number of steps for manufacturing the display panel 100 can be further reduced, the manufacturing time of the display panel 100 can be shortened, and the manufacturing efficiency of the display panel 100 can be improved.

[0171] It should be noted that the first gate conductive layer GT1 has a relatively large thickness, for example, the thickness of the first gate conductive layer GT1 is 3000 angstroms, and the material of the first gate conductive layer GT1 is metal, for example, copper. Therefore, the first gate conductive layer GT1 can act as an etching stop layer. In the process of etching the inorganic layer to form the first via hole 2001 and the fourth via hole 2004, the first gate conductive layer GT1 will not be over-etched, or will be over-etched very thin.

[0172] In some embodiments, as shown in FIG. 22, the pixel circuit 21 is of an 8T1C structure, and the first semiconductor layer ACT1 includes a channel portion of a first light emitting transistor T3. The first gate conductive layer GT1 includes a plurality of third conductive blocks 3003 arranged at intervals, and the orthogonal projection of the third conductive blocks 3003 on the substrate 10 overlaps with the channel portion of the first light emitting transistor T3. The third gate conductive layer GT3 includes a plurality of light emitting signal lines EL, and the plurality of light emitting signal lines EL extend along the first direction X and are arranged at intervals along the second direction Y. The light emitting signal lines EL and the third conductive blocks 3003 are connected through the fourth via hole 2004.

[0173] In this way, along the first direction X, there is a gap between the two adjacent third conductive blocks 3003, and other signal lines or conductive blocks can be prepared in the gap.

[0174] In some examples, as shown in FIG. 22, the first semiconductor layer ACT1 further includes a channel portion of a driving transistor T1, a channel portion of a first reset transistor T5, and a first connection portion 6001. A row of channel portions of the first light emitting transistor T3 is located on one side of a row of channel portions of the driving transistor T1, and a row of channel portions of the first reset transistor T5 is located on a side of the row of channel portions of the first light emitting transistor T3 away from the row of channel portions of the driving transistor T1. The first connection portion 6001 is directly connected with the channel portion of the driving transistor T1, the channel portion of the first light emitting transistor T3 and the channel portion of the first reset transistor T5. In the orthogonal projection on the substrate 10, the third conductive block 3003 and the channel portion of the first reset transistor T5 overlap, and the first connection portion 6001 is arranged staggered.

[0175] In this way, the channel portion of the driving transistor T1, the channel portion of the first light-emitting transistor T3, and the channel portion of the first reset transistor T5 do not need to be connected by a via. On the one hand, the size of the pixel circuit 21 can be reduced, and the pixel resolution of the display panel 100 can be increased. On the other hand, the number of vias in the display panel 100 can be reduced, the non-light-transmitting area of the display panel 100 can be reduced, and the light-transmitting area of the display panel 100 can be increased, which is beneficial to improving the light transmittance of the display panel 100 and improving the display effect of the display panel 100.

[0176] It should be noted that the direct connection of the first connection portion 6001 and the channel portion means that the first connection portion 6001 is connected to the channel portion without any connecting lines and connecting holes, that is, the first connection portion 6001 is integrally formed with the channel portion.

[0177] In some examples, as shown in FIG. 22, the first semiconductor layer ACT1 further includes a second connection portion 6002, the second connection portion 6002 is directly connected to the channel portion of the first light-emitting transistor T3 and connected through a second via 2002 and a first power signal end VDD, and the second connection portion 6002 is located on the side of a row of channel portions of the first light-emitting transistor T3 away from a row of channel portions of the first reset transistor T5.

[0178] In this way, the size of the first connection portion 6001 between a row of channel portions of the first light-emitting transistor T3 and a row of channel portions of the first reset transistor T5 can be reduced, and the size of the pixel circuit 21 can be further reduced, and the pixel resolution of the display panel 100 can be increased.

[0179] In some examples, as shown in FIG. 22, the first gate conductive layer GT1 includes a plurality of fourth conductive blocks 3004 arranged at intervals, the orthographic projection of the fourth conductive block 3004 on the substrate 10 overlaps the orthographic projection of the channel portion of the second light-emitting transistor T4 on the substrate 10, and the light-emitting signal line EL is further connected to the fourth conductive block 3004 through a fourth via 2004.

[0180] In this way, along the first direction X, there is a gap between two adjacent fourth conductive blocks 3004, and other signal lines or conductive blocks can be prepared in the gap.

[0181] In some examples, as shown in FIG. 22, the first semiconductor layer ACT1 further includes the channel portion of the driving transistor T1, the channel portion of the second light-emitting transistor T4, the channel portion of the second reset transistor T6, and a third connection portion 6003, and the first gate conductive layer GT1 includes the first plate 2121 of the first storage capacitor C1.

[0182] The first plate 2121 of the first storage capacitor C1 covers the channel portion of the driving transistor T1 in the orthogonal projection on the substrate 10. The channel portion of the second light-emitting transistor T4 is located on the side of the channel portion of the driving transistor T1 in a row, and is at least partially located between two adjacent first storage capacitors C1. The channel portion of the second reset transistor T6 is located on the side of the channel portion of the second light-emitting transistor T4 in a row, away from the channel portion of the driving transistor T1 in a row. The channel portion of the second reset transistor T6 is located on the side of the first plate 2121 of the first storage capacitor C1. One end of the third connection portion 6003 is directly connected to the channel portion of the second light-emitting transistor T4, and the other end is directly connected to the channel portion of the first reset transistor T5.

[0183] In this way, in the orthogonal projection on the substrate 10, no signal line or conductive block can be arranged in the first gate conductive layer GT1 between the first plate 2121 and the channel portion of the second reset transistor T6, so that the distance between the first plate 2121 and the third connection portion 6003 between the first plate 2121 and the channel portion of the second light-emitting transistor T4 can be reduced, the size of the pixel circuit 21 can be further reduced, and the pixel resolution of the display panel 100 can be increased.

[0184] In some examples, as shown in FIG. 22, the third connection portion 6003 includes a first sub-portion 60031, a second sub-portion 60032 and a third sub-portion 60033 connected in sequence. The first sub-portion 60031 extends along the second direction Y, one end of which is connected to the channel portion of the second light-emitting transistor T4, and the other end of which is connected to one end of the second sub-portion 60032. The third sub-portion 60033 extends along the second direction Y, one end of which is connected to the channel portion of the second reset transistor T6, and the other end of which is connected to the other end of the second sub-portion 60032. The second sub-portion 60032 extends along the first direction X.

[0185] Based on the above structure, the display panel 100 provided by the embodiments of the present disclosure has a larger light transmittance and a larger pixel resolution, for example, the pixel resolution is 520.

[0186] In some examples, as shown in FIG. 20, the pixel circuit is of an 8T1C structure, the first semiconductor layer ACT1 further includes a channel portion of a third reset transistor T7, and the first gate conductive layer further includes a plurality of third reset signal lines RL3. The plurality of third reset signal lines RL3 extend along the first direction X and are arranged at intervals along the second direction Y. The orthogonal projection of the third reset signal line RL3 on the substrate 10 overlaps the orthogonal projection of the channel portion of the third reset transistor T7 on the substrate 10, that is, the portion of the third reset signal line RL3 overlapping the third reset transistor T7 forms the gate electrode of the third reset transistor T7.

[0187] On the basis of the above-mentioned embodiments, the second gate conductive layer GT2 further comprises a plurality of third initialization signal lines VL3, the third initialization signal lines VL3 extend along the first direction X and are arranged at intervals along the second direction Y, and the third initialization signal lines VL3 are connected with the third reset transistors T7.

[0188] In some embodiments, as shown in FIGS. 19 and 20, the first source / drain conductive layer SD1 further comprises a third trace 703, the third trace 703 extends along the second direction Y, and the third trace 703 is connected with the plurality of third initialization signal lines VL3 which extend along the second direction Y.

[0189] In this way, the third initialization signal lines VL3 and the first trace 701 are arranged in parallel, the voltage drop on the third initialization signal lines VL3 is reduced, and the display effect of the display panel 100 is improved.

[0190] In some embodiments, as shown in FIGS. 19 and 20, the first source / drain conductive layer SD1 further comprises a second trace 702, the second trace 702 extends along the second direction Y, and the second trace 702 is connected with the plurality of second initialization signal lines VL2 which extend along the second direction Y.

[0191] In this way, the second initialization signal lines VL2 and the second trace 702 are arranged in parallel, the voltage drop on the second initialization signal lines VL2 is reduced, and the display effect of the display panel 100 is improved.

[0192] In some embodiments, as shown in FIGS. 18, 19 and 20, the first semiconductor layer ACT1 further comprises a channel portion of a data writing transistor T8, and the first gate conductive layer GT1 further comprises a plurality of second scan signal lines GL2, the second scan signal lines GL2 extend along the first direction X and are arranged at intervals along the second direction Y. The orthogonal projection of the second scan signal lines GL2 on the substrate 10 overlaps the orthogonal projection of the channel portion of the data writing transistor T8 on the substrate 10, that is, the portion of the second scan signal lines GL2 overlapping the channel portion of the data writing transistor T8 forms the gate of the data writing transistor T8.

[0193] In some embodiments, as shown in FIG. 18, the pixel circuit is of a 7T1C structure, and the orthogonal projection of the second scan signal lines GL2 on the substrate 10 overlaps the orthogonal projection of the channel portion of the second reset transistor T6 on the substrate 10, that is, the portion of the second scan signal lines GL2 overlapping the channel portion of the second reset transistor T6 forms the gate of the second reset transistor T6.

[0194] On the basis of the above-mentioned embodiments, as shown in the figure, the first source-drain conductive layer SD1 further comprises a plurality of second initialization signal lines VL2 and a plurality of second wires 702. The plurality of second initialization signal lines VL2 extend in the first direction X and are arranged at intervals along the second direction Y. The second initialization signal lines VL2 are connected with the second reset transistors T6. One second wire 702 is located between and connected with two adjacent second initialization signal lines VL2. The plurality of second wires 702 are arranged at intervals along the first direction X.

[0195] In this way, the second initialization signal lines VL2 and the second wires 702 are arranged in parallel, the voltage drop on the second initialization signal lines VL2 is reduced, and the display effect of the display panel 100 is improved.

[0196] In some embodiments, as shown in FIGS. 18, 19 and 20, the display panel further comprises a light-blocking layer BSM located between the substrate 10 and the first semiconductor layer ACT1. The light-blocking layer BSM comprises a plurality of light-blocking blocks, and the orthogonal projection of the light-blocking blocks on the substrate 10 and the orthogonal projection of the channel portion of the driving transistor T1 on the substrate 10 overlap.

[0197] In some embodiments, as shown in FIG. 4, the light-emitting device 22 comprises a first electrode 221, a light-emitting functional layer 222 and a second electrode 223. The first electrode 221 can be electrically connected with the source 2112 or the drain 2113 of the thin-film transistor 211 serving as the driving transistor T1 in the plurality of thin-film transistors 211, for example. In FIG. 4, the first electrode 221 is electrically connected with the drain 2113 of the thin-film transistor 211. The material of the first electrode 221 comprises indium tin oxide (English: Indium Tin Oxide, ITO) or silver (Ag). The material of the second electrode 223 comprises aluminum (Al), Ag or magnesium (Mg).

[0198] It should be noted that the first electrode 221 is the anode of the light-emitting device 22, and the second electrode 223 is the cathode of the light-emitting device 22; or the first electrode 221 is the cathode of the light-emitting device 22, and the second electrode 223 is the anode of the light-emitting device 22. Hereinafter, the first electrode 221 is taken as the anode of the light-emitting device 22, and the second electrode 223 is taken as the cathode of the light-emitting device 22 as an example to illustrate the embodiments of the present disclosure. As shown in FIG. 4, the second electrode 221 (cathode) is an integral layer structure, that is, the voltage values on the second electrodes 221 of different light-emitting devices 22 are equal.

[0199] The light-emitting functional layer 222 can include at least one of an electron transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer (HIL) in addition to the light-emitting layer.

[0200] In some embodiments, as shown in the drawings, the display panel further includes an encapsulation layer 60 located on the side of the second electrode 222 away from the first electrode 221. The encapsulation layer 60 can be an encapsulation film. In some embodiments, the encapsulation layer 60 can include one encapsulation film, or two or more encapsulation films stacked. For example, the encapsulation layer 60 includes three encapsulation films stacked in sequence.

[0201] In the case where the encapsulation layer 60 includes three encapsulation films stacked in sequence, the encapsulation film in the middle layer is made of an organic material, and the encapsulation films on the two sides are made of an inorganic material. The organic material can be, for example, polymethyl methacrylate (PMMA) or PI.

[0202] In other embodiments, the light-emitting device can include a Micro LED and / or a Mini LED.

[0203] In some embodiments, as shown in the drawings, as shown in FIGS. 13 and 14, the plurality of active layer patterns 1011 includes a plurality of first active layer patterns 1111 and a plurality of second active layer patterns 1112. The plurality of active layer patterns 1011 is arranged in multiple rows and multiple columns, and one row of active layer patterns 1011 is divided into a plurality of active layer pattern groups 1011, one active layer pattern group 1011 including one first active layer pattern 1111 and one second active layer pattern 1112 adjacent to each other, and the first active layer pattern 1111 and the second active layer pattern 1112 in the same active layer pattern group 1011 are substantially symmetrical about a first axis S1 extending in the second direction Y.

[0204] In the description of the present specification, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0205] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, having a main area and a bending area located at at least one side of the main area; The display panel comprises a substrate, a first semiconductor layer, a first insulating layer, a second semiconductor layer, a second insulating layer, a third gate conductive layer, a third insulating layer and a first source-drain conductive layer which are sequentially stacked; The insulating layer has a first opening and a first through hole, a normal projection of the first opening on the substrate covers the bending region, and the first opening penetrates the first insulating layer and the second insulating layer, and the third insulating layer is partially located in the first opening; the first through hole is located in the main body region, the first through hole penetrates the first insulating layer and the second insulating layer, and the third gate conductive layer extends into the first through hole and is connected with the first semiconductor layer; wherein, The first opening and the first via are formed synchronously; The insulating layer further has a second opening and a second via, in the orthographic projection to the substrate, the second opening is located in the range of the first opening and covers the bending area, the second opening penetrates the third insulating layer; The second via is located in the main area, the second via penetrates the first insulating layer, the second insulating layer and the third insulating layer, the first source-drain conductive layer extends into the second via and is connected with the first semiconductor layer; The second opening and the second via are formed synchronously. 2.The display panel according to claim 1, further comprising: a plurality of pixel circuits located on the substrate, the pixel circuit comprising a drive transistor, the control electrode of the drive transistor being connected with a first node, the first electrode being connected with a second node, and the second electrode being connected with a third node.

3. The display panel of claim 2, wherein, The pixel circuit further comprises a first reset transistor, the first electrode of the first reset transistor being connected with a first initialization signal terminal, the second electrode being connected with the second node, and the control electrode being connected with a first reset signal terminal; The first semiconductor layer comprises a channel portion of the first reset transistor; The third gate conductive layer further comprises: a first initialization signal line connected with the first initialization signal terminal, the first initialization signal line being connected with the first electrode of the first reset transistor through the first via.

4. The display panel of claim 2 or 3, wherein, The pixel circuit further comprises: a second reset transistor, the first electrode of the second reset transistor being connected with a second initialization signal terminal, the second electrode being connected with a fourth node, and the control electrode being connected with a second reset signal terminal; The first semiconductor layer comprises a channel portion of the second reset transistor; The third gate conductive layer further comprises: a second initialization signal line connected with the second initialization signal terminal, the second initialization signal line being connected with the first electrode of the second reset transistor through the second via. 5.The display panel according to any one of claims 2-4, further comprising: a second gate conductive layer located between the first insulating layer and the second semiconductor layer; a fifth insulating layer located between the second gate conductive layer and the second semiconductor layer; The first opening, the first via and the second via penetrate the fifth insulating layer; The insulating layer has a third via, the third via is located in the main area, the third via penetrates the second insulating layer and the fifth insulating layer; The third gate conductive layer extends into the third via and is connected with the second gate conductive layer; The third via is formed synchronously with the first via. The pixel circuit further comprises:

6. The display panel of claim 5, wherein, a compensation transistor, the first electrode of the compensation transistor being connected with the first node, the second electrode being connected with the third node, and the control electrode being connected with a first scan signal terminal; The second semiconductor layer comprises a channel portion of the compensation transistor; ​ The second gate conductive layer comprises a plurality of first scan signal lines, the first scan signal lines are connected with the first scan signal end, the plurality of first scan signal lines extend along a first direction and are arranged at intervals along a second direction; the first scan signal line comprises alternately connected first main body segments and first connection segments, in the orthographic projection onto the substrate, the first main body segments overlap the channel portions of the compensation transistors, and the first connection segments are arranged away from the channel portions of the compensation transistors; wherein the first direction and the second direction intersect; The third gate conductive layer comprises a plurality of first conductive blocks arranged at intervals, the orthographic projection of the first conductive block onto the substrate overlaps the orthographic projection of the channel portion of the compensation transistor onto the substrate; In the orthographic projection onto the substrate, the first conductive block overlaps the first main body segment and is arranged away from the first connection segment, and the first conductive block is connected with the first main body segment through the third via hole.

7. The display panel of claim 6, wherein, The pixel circuit further comprises: a first storage capacitor, a first plate of the first storage capacitor is connected with the first node, and a second plate is connected with the first power supply signal end; In the orthographic projection onto the substrate, one of the first scan signal lines is located between a row of first storage capacitors and a row of first poles of the compensation transistors; The first source-drain conductive layer further comprises a plurality of first connection lines, one end of the first connection line is connected with the first pole of the compensation transistor, the other end is connected with the first plate, and in the orthographic projection onto the substrate, the first connection line partially overlaps the first connection segment and is arranged away from the first conductive block.

8. The display panel according to any one of claims 5 to 7, wherein, The pixel circuit further comprises: a third reset transistor, a first pole of the third reset transistor is connected with a third initialization signal end, a second pole is connected with the first node, and a control pole is connected with a third reset signal end; The second semiconductor layer comprises the channel portion of the third reset transistor; The second gate conductive layer comprises a plurality of third reset signal lines, the plurality of third reset signal lines extend along a first direction and are arranged at intervals along a second direction; the third reset signal line comprises alternately connected second main body segments and second connection segments, in the orthographic projection onto the substrate, the second main body segments overlap the channel portions of the third reset transistors, and the second connection segments are arranged away from the channel portions of the third reset transistors; wherein the first direction and the second direction intersect; The third gate conductive layer comprises a plurality of second conductive blocks arranged at intervals, the orthographic projection of the second conductive block onto the substrate overlaps the orthographic projection of the channel portion of the third reset transistor onto the substrate; In the orthographic projection onto the substrate, the second conductive block overlaps the second main body segment and is arranged away from the second connection segment, and the second conductive block is connected with the second main body segment through the third via hole.

9. The display panel according to any one of claims 2-8, further comprising: a first gate conductive layer, located between the first insulating layer and the second gate conductive layer, ​ A sixth insulating layer is located between the first gate conductive layer and the second gate conductive layer; the first opening, the first via hole and the second via hole penetrate the sixth insulating layer; The insulating layer has a fourth via hole located in the main body area, the fourth via hole penetrates the second insulating layer, the fifth insulating layer and the sixth insulating layer; the third gate conductive layer extends into the fourth via hole and is connected with the first gate conductive layer; the fourth via hole is formed synchronously with the first via hole.

10. The display panel of claim 9, wherein, The pixel circuit further comprises: A first light emitting transistor, a first electrode of the first light emitting transistor is connected with the second node, a second electrode is connected with the first power signal end, and a control electrode is connected with the light emitting signal end; The first semiconductor layer comprises a channel part of the first light emitting transistor; The first gate conductive layer comprises a plurality of third conductive blocks arranged at intervals, and a projection of the third conductive block on the substrate overlaps with the channel part of the first light emitting transistor; The third gate conductive layer comprises a plurality of light emitting signal lines, the plurality of light emitting signal lines extend along a first direction and are arranged at intervals along a second direction; the light emitting signal line and the third conductive block are connected through the fourth via hole; wherein the first direction and the second direction intersect.

11. The display panel of claim 10, wherein, The pixel circuit further comprises: A first reset transistor, a first electrode of the first reset transistor is connected with the first initialization signal end, a second electrode is connected with the fourth node, and a control electrode is connected with the first reset signal end; The first semiconductor layer further comprises a channel part of the driving transistor, a channel part of the first reset transistor and a first connection part, a row of channel parts of the first light emitting transistor is located on one side of a row of channel parts of the driving transistor, a row of channel parts of the first reset transistor is located on a side of a row of the first light emitting transistor away from the channel part of the driving transistor, the first connection part is directly connected with the channel part of the driving transistor, the channel part of the first light emitting transistor and the channel part of the first reset transistor; in the orthographic projection of the substrate, the third conductive block and the channel part of the first reset transistor overlap, and the first connection part is arranged staggered.

12. The display panel of claim 11, wherein, The first semiconductor layer further comprises a second connection part, the second connection part is directly connected with the channel part of the first light emitting transistor and connected with the first power signal end through the second via hole, and the second connection part is located on a side of a row of channel parts of the first light emitting transistor away from a row of channel parts of the first reset transistor.

13. The display panel of any of claims 9-13, wherein, The pixel circuit further comprises: A second light emitting transistor, a first electrode of the second light emitting transistor is connected with the third node, a second electrode is connected with the fourth node, and a control electrode is connected with the light emitting signal end; The first gate conductive layer comprises a plurality of fourth conductive blocks arranged at intervals, a projection of the fourth conductive block on the substrate overlaps with a projection of the channel part of the second light emitting transistor on the substrate; the light emitting signal line is further connected with the fourth conductive block through the fourth via hole.

14. The display panel of claim 13, wherein, The pixel circuit further comprises: a first storage capacitor, a first plate of the first storage capacitor being connected with the first node, and a second plate being connected with the first power signal terminal; a second reset transistor, a first electrode of the second reset transistor being connected with the second initialization signal terminal, a second electrode being connected with the fourth node, and a control electrode being connected with the second reset signal terminal; the first semiconductor layer further comprises a channel portion of a driving transistor, a channel portion of the second light emitting transistor, a channel portion of the second reset transistor, and a third connection portion, and the first gate conductive layer comprises a first plate of the first storage capacitor; a first plate of the first storage capacitor covers the channel portion of the driving transistor in a normal projection on the substrate, a row of the channel portions of the second light emitting transistor is located on one side of a row of the channel portions of the driving transistor, and the channel portions of the second light emitting transistor are at least partially located between two adjacent first storage capacitors; a row of the channel portions of the second reset transistor is located on a side of a row of the channel portions of the second light emitting transistor, away from a row of the channel portions of the driving transistor; the channel portion of the second reset transistor is located on one side of the first plate of the first storage capacitor, one end of the third connection portion is directly connected with the channel portion of the second light emitting transistor, and the other end is directly connected with the channel portion of the first reset transistor.

15. A display device comprising the display panel according to any one of claims 1 to 14.

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