Structure of infrared thermopile sensor chip and manufacturing method therefor

Abstract

A structure of an infrared thermopile sensor chip and a manufacturing method therefor. The manufacturing method comprises the following steps: a, providing a substrate layer (100), the substrate layer (100) having an upper surface (110) and a lower surface (120); b, depositing a dielectric-dipole layer group (200) on the upper surface (110) of the substrate layer (100), wherein the steps of depositing the dielectric-dipole layer group (200) comprise: b1, depositing a first dielectric (211b) on the upper surface (110) of the substrate layer (100), and patterning the first dielectric (211b) to obtain a first dielectric layer (211) having a plurality of dielectric holes (420), the dielectric holes (420) being communicated with an upper surface of the first dielectric layer (211) and the substrate layer (100); and b2, depositing a first dipole layer (221) on the upper surface of the first dielectric layer (211), the first dipole layer (221) filling the dielectric holes (420); and e, from the lower surface (120) of the substrate layer (100), etching the substrate layer (100) and the first dipole layer (221) in the dielectric holes (420), so as to manufacture an infrared thermopile sensor chip having a back cavity (400), thereby improving heat dissipation capability, and increasing thermopile signal quantity.

Description

Structure and manufacturing method of infrared thermoelectric sensor chip TECHNICAL FIELD

[0001] The present application relates to the technical field of infrared thermoelectric sensor, and particularly relates to a structure and manufacturing method of infrared thermoelectric sensor chip.

[0002] TECHNICAL FIELD

[0003] The infrared thermoelectric sensor chip is a sensor based on the principle of Seebeck effect, and its core is to convert the infrared light radiated by an object into an electrical signal, thereby realizing the measurement of temperature. Specifically, when infrared light irradiates the absorbing film of the sensor, thermal energy is generated, and the thermal energy is further transmitted to the thermocouple in the thermoelectric pile, so that a thermoelectric electromotive force is generated. The thermoelectric electromotive force is proportional to the temperature difference between the two ends of the thermocouple, and by measuring the voltage signal, the temperature of the target can be calculated. The infrared thermoelectric sensor chip has the characteristics of wide measurement range, high precision, fast response, high reliability, etc., and is widely used in household appliances, industrial detection and other scenes.

[0004] For example, the patent with the publication number CN112670397A discloses a thermoelectric infrared detector and a manufacturing method thereof. The thermoelectric infrared detector includes a thermoelectric structure, a substrate and a back cavity located on one side of the thermoelectric structure, and the thermoelectric structure includes a dielectric layer, a thermocouple layer and a solder pad. The number of dielectric layers and thermocouple layers is multiple, and the first layer of dielectric layer is arranged between the substrate and the first layer of thermocouple layer.

[0005] Among them, the first layer of dielectric layer has a large area, which is not conducive to heat dissipation. The heat dissipation capacity directly affects the temperature difference between the two ends of the thermocouple. If the heat dissipation capacity is insufficient, the temperature of the hot end of the thermocouple will continuously rise, resulting in an increase in the temperature difference, and thus a larger thermoelectric electromotive force is generated. Therefore, good heat dissipation capacity helps to maintain the stability of the temperature of the thermocouple, thereby improving the stability of the signal output, and thus generating sufficient signal amount. SUMMARY

[0006] The purpose of the present application is to overcome the shortcomings of the prior art, and to provide a structure and manufacturing method of infrared thermoelectric sensor chip, which improves the heat dissipation capacity, increases the thermoelectric pile signal amount, and thus improves the sensitivity of the sensor.

[0007] In order to achieve the above-mentioned purpose, the present application provides the following technical scheme:

[0008] A manufacturing method of an infrared thermoelectric sensor chip, comprising the following steps:

[0009] a. providing a substrate layer having an upper surface and a lower surface;

[0010] b. depositing a dielectric-electrode layer group on the upper surface of the substrate layer, wherein the step of depositing the dielectric-electrode layer group comprises:

[0011] b1. depositing a first dielectric on the upper surface of the substrate layer and patterning the first dielectric to obtain a first dielectric layer having a plurality of dielectric holes, the dielectric holes being connected to the upper surface of the first dielectric layer and the substrate layer;

[0012] b2. depositing a first electrode layer on the upper surface of the first dielectric layer, the first electrode layer filling the dielectric holes;

[0013] e. etching the substrate layer and the first electrode layer in the dielectric holes on the lower surface of the substrate layer to obtain an infrared thermopile sensor chip with a back cavity.

[0014] As a preferred embodiment, after the step b2, the step b further comprises the following steps:

[0015] b3. depositing a second dielectric layer on the upper surface of the first electrode layer;

[0016] b4. depositing a second electrode on the upper surface of the second dielectric layer and patterning the second electrode to obtain a second electrode layer having a plurality of electrode holes, the electrode holes being connected to the upper surface of the second electrode layer and the second dielectric layer;

[0017] b5. depositing a third dielectric layer on the upper surface of the second electrode layer, the third dielectric layer filling the electrode holes.

[0018] As a preferred embodiment, the step b4 comprises:

[0019] patterning the second electrode in a manner that the electrode holes of the second electrode layer are staggered with the dielectric holes.

[0020] As a preferred embodiment, between the steps b and e, the method further comprises the following steps:

[0021] c. perforating the dielectric-electrode layer group, the upper ends of the holes being exposed on the upper surface of the dielectric-electrode layer group, and the lower ends of the holes being connected to the electrode layers;

[0022] d. depositing a metal on the upper surface of the dielectric-electrode layer group, so that the metal fills the inside of the holes and forms a pad on the upper surface of the dielectric-electrode layer group.

[0023] As a preferred embodiment, the medium electric couple layer group comprises a first medium layer, a second medium layer, a third medium layer, a first electric couple layer and a second electric couple layer, the first medium layer, the first electric couple layer, the second medium layer, the second electric couple layer and the third medium layer are arranged from bottom to top on the substrate layer, and the step c comprises the following steps:

[0024] c1, a hole is formed above the second electric couple layer, the hole above the second electric couple layer communicates the upper surface of the third medium layer and the second electric couple layer;

[0025] c2, a hole is formed above the first electric couple layer, the hole above the first electric couple layer communicates the upper surface of the third medium layer and the first electric couple layer.

[0026] As a preferred embodiment, the second electric couple layer has three electric couple holes, and the second electric couple layer is divided into two parts by the three electric couple holes, each part corresponding to a pad.

[0027] As a preferred embodiment, the back cavity comprises a substrate cavity, a medium hole and a first electric couple cavity which are communicated in sequence, and the step e comprises the following steps:

[0028] e1, etching the substrate layer to form a substrate cavity penetrating through the substrate layer on the substrate layer;

[0029] e2, etching the second electric couple layer in the medium hole;

[0030] e3, etching the first electric couple layer along the medium hole to form a first electric couple cavity penetrating through the first electric couple layer on the first electric couple layer.

[0031] The application also provides a structure of an infrared thermoelectric sensor chip, comprising:

[0032] a substrate layer, the substrate layer having an upper surface and a lower surface;

[0033] a medium electric couple layer group, the medium electric couple layer group comprising a first medium layer and a first electric couple layer, the first medium layer being located between the substrate layer and the first electric couple layer;

[0034] the lower surface of the substrate layer is provided with a back cavity, the back cavity penetrating through the substrate layer, the first medium layer and the second medium layer.

[0035] As a preferred embodiment, the back cavity comprises:

[0036] a substrate cavity, the substrate cavity penetrating through the substrate layer;

[0037] a medium hole, the medium hole penetrating through the first medium layer;

[0038] A first electric double cavity, the first electric double cavity penetrating the first electric double layer, the first electric double cavity corresponding to the medium hole.

[0039] As a preferred embodiment, further comprising:

[0040] A pad, the pad being disposed on the upper surface of the medium electric double layer group, the pad being connected with each electric double layer of the medium electric double layer group.

[0041] Compared with the prior art, the technical scheme has the following advantages:

[0042] The first medium is image processed to obtain a first medium layer with a plurality of medium holes, the first electric double layer is filled in the medium hole and covers the upper surface of the first medium layer, in the step e, the first electric double layer in the medium hole and the substrate layer are etched to form the back cavity on the lower surface of the substrate layer, greatly reducing the area of the first medium layer, enhancing the thermal isolation of the thermoelectric pile, thereby enhancing the signal amount of the sensor.

[0043] The present application is further described below in conjunction with the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0044] Fig. 1 is a flow chart of the manufacturing method of the infrared thermoelectric pile sensor chip according to the present application;

[0045] Fig. 2 is a structural schematic diagram of the infrared thermoelectric pile sensor chip according to the present application;

[0046] Figs. 3 to 7 are process diagrams of the manufacturing method of the infrared thermoelectric pile sensor chip according to the present application.

[0047] In the drawings: 100 substrate layer, 110 upper surface, 120 lower surface, 200 medium electric double layer group, 211 first medium layer, 211b first medium, 212 second medium layer, 213 third medium layer, 221 first electric double layer, 222 second electric double layer, 222b second electric double, 300 pad, 400 back cavity, 410 substrate cavity, 420 medium hole, 430 first electric double cavity, 500 hole. DETAILED DESCRIPTION

[0048] The following description is provided to enable any person skilled in the art to practice the present application. The preferred embodiments in the following description are only examples of implementing the present application and other obvious modifications are possible to those skilled in the art. The principles defined in the following description can be applied to other embodiments, variations, improvements, equivalents and other technical solutions without departing from the spirit and scope of the present application.

[0049] First embodiment

[0050] As shown in FIG. 1 to FIG. 7, the method for manufacturing the infrared thermoelectric sensor chip comprises the following steps:

[0051] a. providing a substrate layer 100, the substrate layer 100 having an upper surface 110 and a lower surface 120;

[0052] b. depositing a dielectric couple layer group 200 on the upper surface of the substrate layer 100, wherein the deposition step of the dielectric couple layer group 200 comprises:

[0053] b1. depositing a first dielectric 211b on the upper surface of the substrate layer 100, and performing image processing on the first dielectric 211b to obtain a first dielectric layer 211 having a plurality of dielectric holes 420, the dielectric holes 420 being communicated with the upper surface of the first dielectric layer 211 and the substrate layer 100;

[0054] b2. depositing a first couple layer 221 on the upper surface of the first dielectric layer 211, the first couple layer 221 being filled in the dielectric holes 420;

[0055] e. etching the substrate layer 100 and the first couple layer 210 in the dielectric holes 420 on the lower surface of the substrate layer 100 to obtain an infrared thermoelectric sensor chip with a back cavity 400.

[0056] The first dielectric 211b is image processed to obtain a first dielectric layer 211 having a plurality of dielectric holes 420, the first couple layer 221 being filled in the dielectric holes 420 and covering the upper surface of the first dielectric layer 211, in the step e, the first couple layer 221 in the dielectric holes 420 and the substrate layer 100 are etched to form the back cavity 400 on the lower surface of the substrate layer 100, which greatly reduces the area of the first dielectric layer 211, enhances the thermal isolation of the thermoelectric pile, and thus enhances the signal amount of the sensor.

[0057] As shown in FIG. 3, in the step a, the substrate layer 100 can be made of monocrystalline silicon, alumina or the like, for supporting the dielectric couple layer group 200. The alumina has high thermal conductivity and low thermal expansion coefficient, which can significantly improve the rated current and output thermoelectric potential of the thermoelectric converter, and thus enhance the signal amount of the sensor.

[0058] As shown in FIGS. 3-6, in the step b, the medium electric couple layer group 200 includes a first medium layer 211, a second medium layer 212, a third medium layer 213, a first electric couple layer 221 and a second electric couple layer 222, which are arranged from bottom to top on the substrate layer 100.

[0059] The first medium layer 211, the second medium layer 212 and the third medium layer 213 can be made of aluminum oxide, silicon nitride, silicon oxide and the like, which have high thermal resistance (low thermal conductivity) to prevent the heat converted from infrared radiation from being dissipated through the medium layer and reduce the performance of the detector, and also have good mechanical strength and thermal stability to support the upper structure and withstand the high-temperature processing in the preparation process.

[0060] The first electric couple layer 221 and the second electric couple layer 222 are usually composed of materials having thermoelectric effect, including polysilicon, aluminum and other metals and alloys, which can generate potential difference under temperature difference to realize thermoelectric conversion.

[0061] Referring to FIGS. 3 and 4, the step b1 includes depositing a first medium 211b on the upper surface of the substrate layer 100 and performing image processing on the first medium 211b to obtain the first medium layer 211 having a plurality of medium holes 420, which are connected to the upper surface of the first medium layer 211 and the substrate layer 100.

[0062] The image processing can be performed by photolithography and etching and the like to form the medium holes 420 in the first medium layer 211, so as to etch the first electric couple layer 221 in the medium holes 420 and etch the substrate layer 100 to form a back cavity in the step e, which not only reduces the area of the first medium layer 211, but also allows the first medium layer 211 and the first electric couple layer 221 and the like to be directly cooled through the back cavity, so as to keep the thermoelectric pile working in a relatively stable temperature range, which helps to reduce the thermoelectric potential fluctuation caused by temperature change, improve the stability of signal quantity, and further enhance the signal quantity of the sensor.

[0063] Referring to FIG. 5, the step b2 includes depositing the first electric couple layer 221 on the upper surface of the first medium layer 211, which is filled in the medium holes 420.

[0064] The first electric couple layer 221 not only fills the medium holes 420, but also covers the upper surface of the first medium layer 211.

[0065] The lower surface of the first dielectric layer 211 is connected with the substrate layer 100, wherein the first dielectric layer 211 is located between the first electrode layer 221 and the substrate layer 100, which provides stable support and effectively prevents direct contact between the first electrode layer 221 and the substrate layer 100, thereby avoiding performance degradation caused by short circuit or heat conduction. In the step e, after etching the first electrode layer 221 in the dielectric hole 420, the first dielectric layer 211 is supported between the first electrode layer 221 and the substrate layer 100, and the first electrode layer 221 and the substrate layer 100 are not in direct contact.

[0066] It should be noted that the dielectric hole 420 is first formed on the first dielectric layer 211 by imaging, and then in the step b2, the first electrode layer 221 is filled in the dielectric hole 420, and finally in the step e, the substrate layer 100 is etched and the first electrode layer 221 in the dielectric hole 420 is etched to form a back cavity, which reduces the difficulty of forming the back cavity and provides a range for the formation of the back cavity.

[0067] If the dielectric hole 420 is not formed on the first dielectric layer 211 first, but the first dielectric layer 211 is etched directly in the step e, the supporting ability of the first dielectric layer 211 is easily damaged, and in the step e, the dielectric hole 420 of the first dielectric layer 211 does not need to be etched, which reduces the processing difficulty and the difficulty of forming the back cavity.

[0068] Referring to FIG. 5, after the step b2, the step b further includes the following steps:

[0069] b3, depositing a second dielectric layer 212 on the upper surface of the first electrode layer 221;

[0070] b4, depositing a second electrode 222b on the upper surface of the second dielectric layer 212, and performing imaging treatment on the second electrode 222b to obtain a second electrode layer 222 with a plurality of electrode holes 222a, the electrode holes 222a being connected with the upper surface of the second electrode layer 222 and the second dielectric layer 212;

[0071] b5, depositing a third dielectric layer 213 on the upper surface of the second electrode layer 222, the third dielectric layer 213 filling the electrode holes 222a.

[0072] The second dielectric layer 212 is supported between the first electrode layer 221 and the second electrode layer 222. By opening the electrode hole 222a on the second electrode 222b, the third dielectric layer 213 fills the electrode hole 222a, and the third dielectric layer 213 is perforated.

[0073] With reference to FIG. 5, the step b4 comprises:

[0074] The second electrode 222b is patterned in a staggered manner with the medium holes 420, so that the electrode holes 222b of the second electrode layer 222 and the medium holes 420 are staggered.

[0075] The number of the electrode holes 222b is three, and the number of the medium holes 420 is two, and one medium hole 420 is arranged between two adjacent electrode holes 222b, so that the third medium layer 213 and the second medium layer 212 have a connecting part, and the connecting part can be punched to form a hole 500 above the first electrode layer 221.

[0076] As shown in FIGS. 6 and 7, between the steps b and e, the method further comprises the following steps:

[0077] c, the medium electrode layer group 200 is subjected to hole opening treatment, the upper end of the hole 500 is exposed on the upper surface of the medium electrode layer group 200, and the lower end of the hole 500 is connected with each electrode layer;

[0078] d, depositing metal on the upper surface of the medium electrode layer group 200, so that the metal fills the inside of the hole 500, and forms a pad 300 on the upper surface of the medium electrode layer group 200.

[0079] Referring to FIG. 6, the medium electrode layer group 200 comprises a first medium layer 211, a second medium layer 212, a third medium layer 213, a first electrode layer 221 and a second electrode layer 222, and the first medium layer 211, the first electrode layer 221, the second medium layer 212, the second electrode layer 222 and the third medium layer 213 are arranged on the substrate layer 100 from bottom to top, and then the step c comprises the following steps:

[0080] c1, hole opening is performed above the second electrode layer 222, and the hole 500 above the second electrode layer 222 is connected with the upper surface of the third medium layer 213 and the second electrode layer 222;

[0081] c2, hole opening is performed above the first electrode layer 221, and the hole 500 above the first electrode layer 221 is connected with the upper surface of the third medium layer 213 and the first electrode layer 221.

[0082] In the step c1, the second electrode layer 222 is wrapped between the third dielectric layer 213 and the second dielectric layer 212, so that a hole 500 is formed in the third dielectric layer 213 to connect the upper surface of the third dielectric layer 213 and the second electrode layer 222.

[0083] In the step c2, the electrode hole 222b of the second electrode layer 222 and the dielectric hole 420 are staggered, and the upper surface of the second dielectric layer 212 is connected with the third dielectric layer 213 and the second electrode layer 222, and the lower surface of the second dielectric layer 212 is connected with the first electrode layer 221, so that the third dielectric layer 213 and the second dielectric layer 212 have a connected part, and a hole 500 is formed in the connected part to form a hole 500 above the first electrode layer 221.

[0084] Referring to FIG. 6, the second electrode layer 222 has three electrode holes 222a, and the second electrode layer 222 is divided into two parts by the three electrode holes 222a, each part corresponding to a pad 300.

[0085] Referring to FIG. 7, the metal fills the inside of the hole 500 and forms a pad 300 on the upper surface of the dielectric electrode layer group 200, which serves as an electrical connection point between the thermoelectric pile and the circuit board or other electronic components.

[0086] As shown in FIG. 2, the back cavity 400 includes a substrate cavity 410, a dielectric hole 420, and a first electrode cavity 430 connected in sequence, and the step e includes the following steps:

[0087] e1, etching the substrate layer 100 to form a substrate cavity 410 through the substrate layer 100;

[0088] e2, etching the second electrode layer 222 in the dielectric hole 420;

[0089] e3, etching the first electrode layer 221 along the dielectric hole 420 to form a first electrode cavity 430 through the first electrode layer 221.

[0090] The etching can be performed by wet etching, dry etching, etc. Wet etching includes chemical dissolution of the substrate material by etching solution (such as tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), etc.). Dry etching includes etching of the substrate material by physical or chemical methods (such as plasma etching, reactive ion etching, etc.) to form a back cavity.

[0091] The first electric couple cavity 430 has the same area as the medium hole 420, and the two are coincident. The area of the substrate cavity 410 is larger, and each first electric couple cavity 430 is located in the area surrounded by the substrate cavity 410, that is, the first medium layer 211, the first electric couple layer 221, and the second medium layer 212 are directly exposed to the back cavity 400, improving the heat dissipation capacity and enhancing the signal amount of the sensor.

[0092] In summary, without adding additional process steps, the first medium layer 211 can be etched to form a medium hole 420, that is, the structure of the thermoelectric pile is changed to enhance the thermal isolation of the thermoelectric pile, thereby enhancing the signal amount of the sensor. Specifically, the first medium 211b is image processed to obtain a first medium layer 211 with a plurality of medium holes 420, the first electric couple layer 221 is filled in the medium hole 420 and covers the upper surface of the first medium layer 211, in step e, the first electric couple layer 221 in the medium hole 420 and the substrate layer 100 are etched to form the back cavity 400 on the lower surface of the substrate layer 100, greatly reducing the area of the first medium layer 211 to enhance the thermal isolation of the thermoelectric pile, thereby enhancing the signal amount of the sensor.

[0093] By forming a back cavity 400 under the sensor, the thermal coupling with the substrate layer 100 is significantly reduced, the thermal response speed and sensitivity of the sensor are improved, the structural strength and stability are enhanced: the back release process (i.e. the formation of the back cavity 400) allows more precise control of the shape and size of the microstructure, thereby improving the mechanical stability and durability of the structure.

[0094] Without adding additional process steps, that is, the first medium layer 211 is first patterned, and the first layer of electric couple layer 221 can be realized by combining the "first layer of medium layer pattern" with the back cavity etching step to realize self-aligned patterning, to realize the reduction of the thermal conductivity of the device.

[0095] Second embodiment

[0096] As shown in FIG. 2, the structure of the infrared thermoelectric pile sensor chip includes:

[0097] The substrate layer 100 has an upper surface 110 and a lower surface 120;

[0098] The medium electric couple layer group 200 includes a first medium layer 211 and a first electric couple layer 221, the first medium layer 211 is located between the substrate layer 100 and the first electric couple layer 221;

[0099] The lower surface of the substrate layer 100 is provided with a back cavity 400, which penetrates the substrate layer 100, the first dielectric layer 211 and the second dielectric layer 212.

[0100] The structure of the infrared thermocouple sensor chip of the second embodiment is obtained by the manufacturing method of the first embodiment, and thus the beneficial effects of the structure of the infrared thermocouple sensor chip can be referred to the first embodiment, that is, the area of the first dielectric layer 211 is greatly reduced to enhance the thermal isolation of the thermocouple, thereby enhancing the signal quantity of the sensor.

[0101] Referring to FIG. 2, the back cavity 400 includes:

[0102] a substrate cavity 410, which penetrates the substrate layer 100;

[0103] a dielectric hole 420, which penetrates the first dielectric layer 211;

[0104] a first thermocouple cavity 430, which penetrates the first thermocouple layer 221, and which corresponds to the dielectric hole 420.

[0105] Referring to FIG. 2, the structure of the infrared thermocouple sensor chip further includes:

[0106] a pad 300, which is provided on the upper surface of the dielectric thermocouple layer group 200, and which is connected to each thermocouple layer of the dielectric thermocouple layer group 200. The pad 300 serves as an electrical connection point between the thermocouple and a circuit board or other electronic components.

[0107] The above-described embodiments are only used to illustrate the technical ideas and characteristics of the present application, and the purpose is to enable those skilled in the art to understand the content of the present application and to implement it, and cannot be limited to the patent application range of the present application only by the above-described embodiments, that is, any equivalent changes or modifications made according to the disclosed spirit of the present application still fall within the patent scope of the present application.

Claims

1. A method of fabricating an infrared thermopile sensor chip, characterized by, The method comprises the following steps: a. providing a substrate layer (100) having an upper surface (110) and a lower surface (120); b. depositing a dielectric-electrode layer group (200) on the upper surface of the substrate layer (100), wherein the deposition step of the dielectric-electrode layer group (200) comprises: b1. depositing a first dielectric layer (211b) on the upper surface of the substrate layer (100) and performing image processing on the first dielectric layer (211b) to obtain a first dielectric layer (211) having a plurality of dielectric holes (420) that are in communication with the upper surface of the first dielectric layer (211) and the substrate layer (100); b2. depositing a first electrode layer (221) on the upper surface of the first dielectric layer (211), the first electrode layer (221) being filled in the dielectric holes (420); e. etching the substrate layer (100) and the first electrode layer (210) in the dielectric holes (420) on the lower surface of the substrate layer (100) to obtain an infrared thermopile sensor chip with a back cavity (400).

2. The method of claim 1, wherein the step of forming the infrared thermopile sensor chip is performed by a process comprising: After the step b2, the step b further comprises the following steps: b3. depositing a second dielectric layer (212) on the upper surface of the first electrode layer (221); b4. depositing a second electrode layer (222b) on the upper surface of the second dielectric layer (212) and performing image processing on the second electrode layer (222b) to obtain a second electrode layer (222) having a plurality of electrode holes (222a) that are in communication with the upper surface of the second electrode layer (222) and the second dielectric layer (212); b5. depositing a third dielectric layer (213) on the upper surface of the second electrode layer (222), the third dielectric layer (213) being filled in the electrode holes (222a).

3. The method of claim 2, wherein the step of forming the infrared thermopile sensor chip is performed by a process comprising: The step b4 comprises: performing image processing on the second electrode layer (222b) in a staggered manner with respect to the dielectric holes (420) so that the electrode holes (222b) of the second electrode layer (222) are staggered with respect to the dielectric holes (420).

4. The method of claim 1, wherein the step of forming the infrared thermopile sensor chip is performed by a process comprising: Between the steps b and e, the method further comprises the following steps: ​ c. performing a hole processing on the dielectric-electrode layer group (200), the upper end of the hole (500) being exposed on the upper surface of the dielectric-electrode layer group (200), and the lower end of the hole (500) being connected with each electrode layer; d. depositing a metal on the upper surface of the dielectric-electrode layer group (200) so that the metal fills the inside of the hole (500) and forms a pad (300) on the upper surface of the dielectric-electrode layer group (200).

5. The method of claim 4, wherein the step of forming the infrared thermopile sensor chip is performed by a process comprising: The medium electrically-coupled layer group (200) comprises a first medium layer (211), a second medium layer (212), a third medium layer (213), a first electrically-coupled layer (221) and a second electrically-coupled layer (222), the first medium layer (211), the first electrically-coupled layer (221), the second medium layer (212), the second electrically-coupled layer (222) and the third medium layer (213) are arranged from bottom to top on the substrate layer (100), and the step c comprises the following steps: ​ c1, a hole is formed above the second electrically-coupled layer (222), the hole (500) above the second electrically-coupled layer (222) communicates the upper surface of the third medium layer (213) and the second electrically-coupled layer (222); c2, a hole is formed above the first electrically-coupled layer (221), the hole (500) above the first electrically-coupled layer (221) communicates the upper surface of the third medium layer (213) and the first electrically-coupled layer (221).

6. The method of claim 5, wherein the step of forming the infrared thermopile sensor chip is performed by a process comprising: The second electrically-coupled layer (222) has three electrically-coupled holes (222a), and the second electrically-coupled layer (222) is divided into two parts by the three electrically-coupled holes (222a), each part corresponding to a pad (300). ​ 7. The method of claim 5, wherein the step of forming the infrared thermopile sensor chip is performed by a process comprising: The back cavity (400) comprises a substrate cavity (410), a medium hole (420) and a first electrically-coupled cavity (430) communicated in sequence, and the step e comprises the following steps: ​ e1, etching the substrate layer (100) to form a substrate cavity (410) penetrating through the substrate layer (100) on the substrate layer (100); e2, etching the second electrically-coupled layer (222) in the medium hole (420); e3, etching the first electrically-coupled layer (221) along the medium hole (420) to form a first electrically-coupled cavity (430) penetrating through the first electrically-coupled layer (221) on the first electrically-coupled layer (221).

8. A structure of an infrared thermopile sensor chip, characterized by comprising: Comprise: a substrate layer (100), the substrate layer (100) has an upper surface (110) and a lower surface (120); a medium electrically-coupled layer group (200), the medium electrically-coupled layer group (200) comprises a first medium layer (211) and a first electrically-coupled layer (221), the first medium layer (211) is located between the substrate layer (100) and the first electrically-coupled layer (221); The lower surface of the substrate layer (100) is provided with a back cavity (400), and the back cavity (400) penetrates through the substrate layer (100), the first medium layer (211) and the second medium layer (212).

9. The structure of an infrared thermopile sensor chip as defined in claim 8, wherein, The back cavity (400) comprises: a substrate cavity (410) penetrating through the substrate layer (100); a medium hole (420) penetrating through the first medium layer (211); a first electrically-coupled cavity (430) penetrating through the first electrically-coupled layer (221), the first electrically-coupled cavity (430) corresponds to the medium hole (420).

10. The structure of an infrared thermopile sensor chip as defined in claim 8, wherein, Further comprise: A soldering pad (300) is arranged on the upper surface of the medium galvanic layer group (200), and the soldering pad (300) is connected with each galvanic layer of the medium galvanic layer group (200).

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