Interrupt processing method and apparatus

Abstract

An interrupt processing method. The method comprises: acquiring a first interrupt request; processing the first interrupt request by means of a first interrupt processing method; acquiring a second interrupt request; and processing the second interrupt request by means of a second interrupt processing method, wherein the first interrupt request and the second interrupt request are different interrupt requests, and the first interrupt processing method is different from the second interrupt processing method. In the present application, different interrupt processing methods may be used to process different interrupt requests. Since various types of interrupt requests are not processed by means of a fixed interrupt processing method, a corresponding interrupt request may be configured on the basis of a service scenario corresponding to the interrupt request.

Description

Interrupt processing method and device thereof

[0001] The present application claims priority from the Chinese patent application No. 202411319711.5 filed on September 20, 2024, and entitled "Interrupt processing method and device thereof", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of communication technology, in particular to an interrupt processing method and device thereof. BACKGROUND

[0003] With the rapid development of computer technology and its wide application in various fields, business software needs to frequently interact with external devices or respond to requests from external devices. By introducing interrupt technology, the processor can immediately return to perform other tasks after issuing a device request, and the device sends an interrupt signal to the processor after completing the work, and the latter can obtain the relevant results. In this way, during the work of the external device, the processor can do more meaningful work, while paying only a small context switching cost.

[0004] The interrupt request (which can be referred to as an interrupt or an interrupt signal) generated by the device is reported to the central processing unit (CPU) through a unified interrupt entry and enters the kernel interrupt processing framework. With the evolution of the kernel architecture and the development of the ecosystem, interrupts are increasingly widely used in the entire system, such as for device request response, task scheduling, network communication, performance monitoring, etc.

[0005] In the prior art, all interrupts are processed through the same processing process, which results in consistent processing of each interrupt. Moreover, more and more features are being added to the interrupt processing process, resulting in many functions unrelated to interrupts being added to the interrupt processing, such as scheduling points, signal processing, deadlock detection, etc. If the interrupt processing process is too complex and has high latency, since all interrupts are processed through the same processing process, the processing of each interrupt request will be complex and have high latency. SUMMARY

[0006] In a first aspect, the present application provides an interrupt processing method, which comprises: obtaining a first interrupt request; processing the first interrupt request through a first interrupt processing method; obtaining a second interrupt request; processing the second interrupt request through a second interrupt processing method; wherein the first interrupt request and the second interrupt request are different interrupt requests, and the first interrupt processing method and the second interrupt processing method are different.

[0007] In the embodiments of the present application, different interrupt processing methods can be used to process different interrupt requests (first interrupt request and second interrupt request). Since various types (for example, different interrupt sources) of interrupt requests are not processed by a fixed interrupt processing method, the corresponding interrupt request can be configured in combination with the service scenario corresponding to the interrupt request, for example, for some interrupt requests, the process irrelevant to interrupt processing (that is, lightweight processing) can be cut off, and the corresponding optimization mechanism is used to achieve the goal of quickly processing interrupts, that is, to reduce the complexity and delay of the interrupt processing process.

[0008] In a possible implementation, the processing of the first interrupt request by the first interrupt processing method includes: when the interrupt identifier of the first interrupt request is a first interrupt identifier, processing the first interrupt request by the first interrupt processing method; and the processing of the second interrupt request by the second interrupt processing method includes: when the interrupt identifier of the second interrupt request is a second interrupt identifier, processing the second interrupt request by the second interrupt processing method.

[0009] In the embodiments of the present application, the software can be used to determine which interrupt processing method is needed to process the interrupt request (that is, software diversion). In a possible implementation, when the interrupt identifier of the first interrupt request is a first interrupt identifier, the first interrupt request is processed by the first interrupt processing method; and when the interrupt identifier of the second interrupt request is a second interrupt identifier, the second interrupt request is processed by the second interrupt processing method. A specific interrupt source can be configured with a corresponding interrupt request processing method for processing. Since the interrupt identifier (for example, interrupt number) can indicate the interrupt source corresponding to the interrupt request, the mapping relationship between the interrupt identifier and the interrupt request processing method can be set in advance, for example, the first interrupt identifier corresponds to the first interrupt request processing method, and the second interrupt identifier corresponds to the second interrupt request processing method. After the interrupt request is obtained, it can be determined which interrupt request processing method is used to process the interrupt request based on the interrupt identifier of the interrupt request.

[0010] In a possible implementation, the method further includes: before the first interrupt request is obtained, receiving first configuration information; the first configuration information indicates that the interrupt request corresponding to the first interrupt identifier needs to be processed by the first interrupt processing method; or, before the second interrupt request is obtained, receiving second configuration information; the second configuration information indicates that the interrupt request corresponding to the second interrupt identifier needs to be processed by the second interrupt processing method.

[0011] The user can determine, in a configured manner, which interrupt processing method the interrupt identification corresponding to the interrupt request needs to pass through for processing. In a possible implementation, first configuration information can be received; the first configuration information indicates that the interrupt request corresponding to the first interrupt identification needs to be processed by the first interrupt processing method; or second configuration information can be received; the second configuration information indicates that the interrupt request corresponding to the second interrupt identification needs to be processed by the second interrupt processing method.

[0012] For example, different interrupt processing methods can be indicated by a unique corresponding identifier, and the configuration information (the first configuration information or the second configuration information) can include the interrupt identification and the identifier of the corresponding interrupt processing method.

[0013] In a possible implementation, the first interrupt request and the second interrupt request are interrupt requests received through the same hardware interface. That is, the processor can determine, in a software manner, which interrupt processing method to use to process the interrupt request based on the interrupt request received through the same hardware interface.

[0014] In a possible implementation, the first interrupt request is processed by the first interrupt processing method, including: when the interrupt identification of the first interrupt request is an interrupt request received through a first hardware interface, the first interrupt request is processed by the first interrupt processing method; the second interrupt request is processed by the second interrupt processing method, including: when the interrupt identification of the second interrupt request is an interrupt request received through a second hardware interface, the second interrupt request is processed by the second interrupt processing method; and the first hardware interface and the second hardware interface are different hardware interfaces.

[0015] In the embodiments of the present application, the hardware can be used to distinguish which interrupt processing method the interrupt request needs to use for processing (that is, hardware distribution), for example, a plurality of hardware interfaces can be configured on the processor, and the interrupt requests received through different hardware interfaces can be processed by different interrupt processing methods. For hardware distribution interrupts, the register needs to be modified to change the hardware path, for example, to report the time delay sensitive interrupt from a separate hardware entry, which can directly enter the corresponding lightweight interrupt processing framework, and the software judgment process is omitted to realize faster processing process. For the interrupt reported from the separate hardware path, it will automatically enter the lightweight interrupt processing framework. This part can be quickly processed due to the logic simplification, and the system performance is improved.

[0016] In a possible implementation, the first interrupt processing method is a process of switching from a kernel mode to a user mode and processing the interrupt request, and the second interrupt processing method is a process of processing the interrupt in the kernel mode.

[0017] In a possible implementation, the first interrupt processing method comprises: saving context information of a processor (for example, a CPU) when it is determined that the interrupt can be returned to the user mode for processing, and installing an interrupt processing function of the user mode on a hardware register.

[0018] In a possible implementation, the first interrupt request has a greater impact on the service performance of the user mode than on the service performance of the kernel mode; and the second interrupt request has a greater impact on the service performance of the kernel mode than on the service performance of the user mode.

[0019] In a possible implementation, the first interrupt processing method has a lower complexity than the second interrupt processing method.

[0020] In a possible implementation, the first interrupt processing method is used to implement a plurality of first functions; the second interrupt processing method is used to implement a plurality of second functions; the number of the plurality of first functions is less than the number of the plurality of second functions; or the execution time delay of the plurality of first functions is lower than the execution time delay of the plurality of second functions.

[0021] In a possible implementation, the first interrupt request is obtained by a first processor.

[0022] The first interrupt request is processed by the first interrupt processing method, comprising:

[0023] The first processor triggers a second processor to process the first interrupt request by the first interrupt processing method; wherein the second processor is an AI processor.

[0024] In a second aspect, the present application provides an interrupt processing apparatus, comprising:

[0025] An obtaining module is configured to obtain a first interrupt request and a second interrupt request.

[0026] A processing module is configured to process the first interrupt request by a first interrupt processing apparatus and process the second interrupt request by a second interrupt processing apparatus; wherein

[0027] The first interrupt request and the second interrupt request are different interrupt requests, and the first interrupt processing apparatus and the second interrupt processing apparatus are different.

[0028] In a possible implementation,

[0029] The first interrupt request is processed by the first interrupt processing apparatus, comprising: when an interrupt identifier of the first interrupt request is a first interrupt identifier, the first interrupt request is processed by the first interrupt processing apparatus.

[0030] The processing of the second interrupt request by the second interrupt processing apparatus comprises: when the interrupt identification of the second interrupt request is a second interrupt identification, processing the second interrupt request by the second interrupt processing apparatus.

[0031] In a possible implementation, the obtaining module is further configured to:

[0032] Before the first interrupt request is obtained, first configuration information is received; the first configuration information indicates that an interrupt request for the first interrupt identification needs to be processed by the first interrupt processing apparatus; or

[0033] Before the second interrupt request is obtained, second configuration information is received; the second configuration information indicates that an interrupt request for the second interrupt identification needs to be processed by the second interrupt processing apparatus.

[0034] In a possible implementation, the first interrupt request and the second interrupt request are interrupt requests received through a same hardware interface.

[0035] In a possible implementation, the processing module is specifically configured to:

[0036] When the interrupt identification of the first interrupt request is an interrupt request received by the obtaining module through a first hardware interface, the first interrupt request is processed by a first interrupt processing apparatus;

[0037] The processing of the second interrupt request by the second interrupt processing apparatus comprises: when the interrupt identification of the second interrupt request is an interrupt request received by the obtaining module through a second hardware interface, the second interrupt request is processed by a second interrupt processing apparatus; the first hardware interface and the second hardware interface are different hardware interfaces.

[0038] In a possible implementation, the first interrupt processing apparatus is a process of switching from a kernel mode to a user mode and processing an interrupt request, and the second interrupt processing apparatus is a process of processing an interrupt in the kernel mode.

[0039] In a possible implementation, the first interrupt request has a greater impact on the service performance of the user mode than on the service performance of the kernel mode; and the second interrupt request has a greater impact on the service performance of the kernel mode than on the service performance of the user mode.

[0040] In a possible implementation, the first interrupt processing apparatus has a lower complexity than the second interrupt processing apparatus.

[0041] In a possible implementation, the first interrupt processing apparatus is configured to implement a plurality of first functions; the second interrupt processing apparatus is configured to implement a plurality of second functions; the number of the plurality of first functions is less than the number of the plurality of second functions; or, the execution time delay of the plurality of first functions is lower than the execution time delay of the plurality of second functions.

[0042] In a possible implementation, the first interrupt request is obtained by the first processor.

[0043] The first interrupt request is processed by the first interrupt processing apparatus, including:

[0044] The first processor triggers the second processor to process the first interrupt request by the first interrupt processing apparatus; and the second processor is an AI processor.

[0045] In a third aspect, an embodiment of the present application provides an interrupt processing apparatus, which can include a memory, a processor and a bus system, wherein the memory is configured to store a program, and the processor is configured to execute the program in the memory to perform the method in the first aspect and any optional method.

[0046] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program, and when the computer program is run on a computer, the computer is caused to perform the method in the first aspect and any optional method.

[0047] In a fifth aspect, an embodiment of the present application provides a computer program, which, when run on a computer, causes the computer to perform the method in the first aspect and any optional method.

[0048] In a sixth aspect, the present application provides a chip system, which includes a processor configured to support the execution of an interrupt processing apparatus to implement the functions involved in the above aspects, for example, to send or process the data involved in the above method; or, information. In a possible design, the chip system further includes a memory, and the memory is configured to store necessary program instructions and data for the execution device or the training device. The chip system can be composed of a chip, or can include a chip and other discrete devices. BRIEF DESCRIPTION OF DRAWINGS

[0049] FIG. 1 is a flowchart of an interrupt processing method according to an embodiment of the present application;

[0050] FIG. 2 is a schematic diagram of a system architecture;

[0051] FIG. 3 is a functional diagram of an interrupt processing method;

[0052] FIG. 4 and FIG. 5 are schematic diagrams of system architectures;

[0053] Figure 6 is a flowchart illustrating an interruption handling method provided in an embodiment of this application;

[0054] Figure 7 is a schematic diagram of an interrupt handling device provided in an embodiment of this application;

[0055] Figure 8 is a schematic diagram of an interrupt handling device provided in an embodiment of this application;

[0056] Figure 9 is a schematic diagram of a terminal device provided in an embodiment of this application;

[0057] Figure 10 is a schematic diagram of a server structure provided in an embodiment of this application. Detailed Implementation

[0058] The embodiments of the present invention will now be described with reference to the accompanying drawings. The terminology used in the embodiments section is for illustrative purposes only and is not intended to limit the scope of the invention.

[0059] The embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0060] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0061] The terms “substantially,” “about,” and similar terms used herein are used as approximations rather than as terms of degree, and are intended to take into account the inherent biases of measurements or calculations known to those skilled in the art. Furthermore, the use of “may” in describing embodiments of the invention refers to “one or more possible embodiments.” The terms “use,” “using,” and “used” used herein are to be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively. Additionally, the term “exemplary” is intended to refer to an instance or illustration.

[0062] The following briefly introduces several basic concepts related to embodiments of the present application.

[0063] Interrupt request (IRQ): An interrupt request is an event sent by an interrupt controller to a central processing unit (CPU). When the CPU receives an IRQ, the CPU needs to store the current program being executed, suspend the program, and execute the program corresponding to the IRQ. An IRQ can be triggered by hardware or software, and in this application, an interrupt request can be referred to as an interrupt.

[0064] Interrupt controller: An interrupt controller is disposed between hardware and a CPU, and is mainly used to collect IRQs generated by various hardware and send the IRQs to the CPU. In this application, an interrupt controller is a general term, and has different names and different functional components in different systems. For example, for an ARM architecture, the name of the interrupt controller is a generic interrupt controller (GIC), and the GIC includes an interrupt acknowledge register (IAR). There is a certain coupling between the GIC and the CPU, and the CPU can read the IAR in the GIC in a kernel state. For an x86 architecture, the name of the interrupt controller is an advanced programmable interrupt controller (A)PIC, and the (A)PIC includes an in-service register (ISR) and an interrupt mask register (IMR). There is also a certain coupling between the (A)PIC and the CPU, and the CPU can read and write the ISR and the IMR in the (A)PIC in a kernel state.

[0065] When the interrupt controller receives an IRQ from hardware, an interrupt trigger is formed, and there are two forms of interrupt triggers, one is a level trigger, and the other is an edge trigger. For a level trigger, the GIC / (A)PIC sends an IRQ to the CPU after recognizing that the level of an interrupt signal line is low or high, and the CPU will immediately stop the current task and jump to execute an interrupt exception handling program. For an edge trigger, the GIC / (A)PIC notifies the CPU after recognizing that the level of an interrupt signal line changes in a pulse, that is, the GIC / (A)PIC notifies the CPU after recognizing that the level of an interrupt signal line changes from high to low or from low to high, and the CPU will immediately stop the current task and jump to execute an interrupt exception handling program.

[0066] Thread: Thread is the smallest unit of operation that can be scheduled by the operating system. It is contained within a process and is the basic unit of execution of a process. A thread refers to a single sequence of control flow within a process. A process can contain multiple threads, each of which performs different tasks in parallel.

[0067] Process: Process is a program that is running in a computer and is a way for a computer to manage running programs. A program itself is only a description of instructions and data and their organization form, and a process is a real running example of a program. In a process-oriented design system, a process is the basic execution entity of a program; in a thread-oriented design system, a process itself is not a basic running unit, but a container of threads.

[0068] When a CPU executes a process, the process has five basic states, as follows. The process is in a new state, that is, the CPU registers a new process; the process is in a ready state, that is, a process has a running condition and is waiting for the system to allocate the CPU to run; the process is in a running state, that is, the process has obtained the CPU and the CPU is running the process; the process is in a waiting state, also called a blocking state or a sleep state, that is, a process suspends running and is waiting for an event to occur, for example, a process waits for a resource to be used, a process waits for a peripheral to transmit; the process is in a terminated state, that is, a process completes a task and ends normally, or abnormally terminates due to an error that cannot be overcome, or is terminated by an operating system and a process with termination right. Threads also have these five basic states, which are not described in detail here for brevity.

[0069] Context: Context is a static description of a process / thread at a certain running time in a dynamic process. Process / thread running is a dynamic process, and if it is paused, the context is the CPU state related to the process / thread at this time, which generally includes the values of general registers and state registers. When the context is restored, the CPU can continue to execute from the paused place, and the process / thread can continue to run.

[0070] Context switch: During the running of a user-mode program, if a system call, exception, or interrupt occurs, the kernel mode needs to be handled. At this time, the system will dive into the kernel mode, the kernel mode will save the current context of the user mode and restore the original context of the kernel mode. This process is a case of context switch.

[0071] CPU privilege level: now general chip will support user state and kernel state two privilege levels. Various software systems run under different privilege levels. These software systems have different access permissions to the underlying hardware, for example, the OS running in the kernel state can directly operate the printer and network card. Programs running in the user state must rely on the OS to operate hardware devices, such as text editors printing files and web browsers accessing the Internet.

[0072] The method of the embodiments of the present application can be applied in various processor architectures, for example, can be applied to ARM architecture or x86 architecture, and can also be applied to other existing or future processor architectures.

[0073] It should be understood that the interrupt controller can be a GIC under ARM architecture or an APIC under x86 architecture, and the type of the interrupt controller is not limited in the embodiments of the present application.

[0074] With the rapid development of computer technology and its wide application in various fields, business software needs to frequently interact with external devices or respond to requests from external devices. By introducing interrupt technology, when the processor issues a device request, it can immediately return to perform other tasks, and the device sends an interrupt signal to the processor after completing the work, and the latter can obtain the relevant results. In this way, during the work of the external device, the processor can do more meaningful work, and only pay a small context switching cost.

[0075] The interrupt request (which can be referred to as an interrupt or an interrupt signal) generated by the device is reported to the central processing unit (CPU) through a unified interrupt entry, and is uniformly entered into the kernel interrupt processing framework. With the evolution of kernel architecture and the development of ecology, interrupts are increasingly widely used in the entire system, such as for device request response, task scheduling, network communication, performance monitoring, etc.

[0076] In the prior art, all interrupts are processed through the same processing process, which will cause the processing of each interrupt to be consistent, and more and more features are added to the interrupt processing process, which will cause many functions unrelated to interrupts to be also added to the interrupt processing, such as scheduling points, signal processing, deadlock detection, etc. If the interrupt processing process is too complex and has high latency, since all interrupts are processed through the same processing process, the processing process of each interrupt request will be complex and have high latency.

[0077] To solve the above problems, the embodiments of the present application provide an interrupt processing method. The interrupt processing method of the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0078] Referring to FIG. 1, FIG. 1 is a flow diagram of an interrupt processing method provided by an embodiment of the present application. As shown in FIG. 1, the interrupt processing method provided by an embodiment of the present application can include steps 101-104, which are described in detail as follows.

[0079] 101, obtaining a first interrupt request;

[0080] 102, processing the first interrupt request by using a first interrupt processing method;

[0081] 103, obtaining a second interrupt request;

[0082] 104, processing the second interrupt request by using a second interrupt processing method; wherein the first interrupt request and the second interrupt request are different interrupt requests, and the first interrupt processing method and the second interrupt processing method are different.

[0083] The processor can receive the first interrupt request and the second interrupt request. For example, the processor can receive the first interrupt request and the second interrupt request sent by the GIC.

[0084] For example, the GIC can receive an interrupt request IRQ.

[0085] The GIC can receive different interrupt requests, and can use IRQ X to represent different interrupt requests. The interrupt request can be a software interrupt or a hardware interrupt. The GIC can send the IRQ to the kernel mode software in the CPU.

[0086] In an embodiment of the present application, different interrupt processing methods can be used to process different interrupt requests (the first interrupt request and the second interrupt request). Since various types (for example, different interrupt sources) of interrupt requests are not processed by a fixed interrupt processing method, the corresponding interrupt request can be configured in combination with the business scenario corresponding to the interrupt request. For example, for some interrupt requests, the process unrelated to interrupt processing (that is, lightweight processing) can be cut off, and the corresponding optimization mechanism can be used to achieve the goal of quickly processing the interrupt, that is, to reduce the complexity and delay of the interrupt processing process.

[0087] In an embodiment of the present application, a software manner can be used to determine which interrupt processing method is needed to process the interrupt request (i.e., software distribution), in a possible implementation, when the interrupt identifier of the first interrupt request is the first interrupt identifier, the first interrupt processing method can be used to process the first interrupt request; when the interrupt identifier of the second interrupt request is the second interrupt identifier, the second interrupt processing method can be used to process the second interrupt request. A specific interrupt source can be configured with a corresponding interrupt request processing method for processing. Since the interrupt identifier (e.g., interrupt number) can indicate the interrupt source corresponding to the interrupt request, the mapping relationship between the interrupt identifier and the interrupt request processing method can be set in advance, for example, the first interrupt identifier corresponds to the first interrupt request processing method, and the second interrupt identifier corresponds to the second interrupt request processing method. After the interrupt request is obtained, the interrupt request processing method used to process the interrupt request can be determined based on the interrupt identifier of the interrupt request.

[0088] The user can determine which interrupt processing method is needed to process the interrupt request corresponding to the interrupt identifier through configuration, in a possible implementation, the first configuration information can be received; the first configuration information indicates that the interrupt request corresponding to the first interrupt identifier needs to be processed by the first interrupt processing method; or the second configuration information can be received; the second configuration information indicates that the interrupt request corresponding to the second interrupt identifier needs to be processed by the second interrupt processing method.

[0089] For example, different interrupt processing methods can be indicated by a unique identifier corresponding to one identifier, and the configuration information (first configuration information or second configuration information) can include the interrupt identifier and the identifier of the corresponding interrupt processing method.

[0090] In a possible implementation, the first interrupt request and the second interrupt request are interrupt requests received through the same hardware interface. That is, the processor can determine which interrupt processing method is needed to process the interrupt request based on the software manner through the same hardware interface.

[0091] In a possible implementation, when the interrupt identifier of the first interrupt request is an interrupt request received through the first hardware interface, the first interrupt processing method is used to process the first interrupt request; when the interrupt identifier of the second interrupt request is an interrupt request received through the second hardware interface, the second interrupt processing method is used to process the second interrupt request; the first hardware interface and the second hardware interface are different hardware interfaces.

[0092] In the embodiments of the present application, the hardware can be used to distinguish which interrupt request needs which interrupt processing method (i.e., hardware distribution), for example, a plurality of hardware interfaces can be configured on the processor, and the interrupt requests received through different hardware interfaces can be processed through different interrupt processing methods, for example, the LINT interface and the FIQ interface can be configured, and the interrupt of the user state service performance key is configured for LINT processing, and the interrupt of the kernel state service performance key is configured for FIQ processing.

[0093] In a possible implementation, the complexity of the first interrupt processing method is lower than that of the second interrupt processing method. That is, a lightweight interrupt processing method can be configured.

[0094] In a possible implementation, the first interrupt processing method is used to implement a plurality of first functions; the second interrupt processing method is used to implement a plurality of second functions; and the number of the plurality of first functions is less than that of the plurality of second functions, or the execution time delay of the plurality of first functions is lower than that of the plurality of second functions.

[0095] For example, referring to FIG. 3, the first interrupt processing method or the second interrupt processing method can be a combination of part of the functions shown in FIG. 3.

[0096] For example, the first interrupt processing method can be a lightweight processing process, and the user can determine the main influencing factor of the key interrupt on the system performance according to the service scenario, for example, whether the user state service or the kernel state service is frequently interrupted, whether the key interrupt is configured in the user state processing or must be processed in the kernel state, and whether the key interrupt can implement hardware entry distribution or software distribution and the like. According to various combinations, the corresponding interrupt processing strategy is configured.

[0097] The user transmits the interrupt configuration information to the kernel through the proc interface, and the configurations correspond to different lightweight levels, different interrupt processing entries and interrupt processing frameworks. Each lightweight level maintains a separate data structure, and the corresponding data is saved in advance, so that the data can be quickly indexed and jumped to the driver ISR for processing during interrupt processing. The interrupt controller register configuration is modified to implement the interrupt hardware entry distribution. The proc interface first establishes the data structure to avoid data anomalies during code running, and then modifies the interrupt controller register according to the configuration.

[0098] For the software distribution interrupt, the external device interrupt signal is still reported from the unified interrupt entry, and the register does not need to be modified to change the hardware path, and in the software execution flow, it is judged according to the data structure which interrupt processing framework to go.

[0099] All interrupts have configured data management structure and hardware path according to business situation, after the interrupt signal is reported, it automatically enters the corresponding interrupt processing framework. For the interrupt entering the native interrupt processing framework, the whole processing process has no difference before the device is introduced, and the system and business are completely insensitive. For the interrupt reported from the unified interrupt entry but walking the light weight interrupt processing, a judgment needs to be made in the software execution flow and jump from the native interrupt processing framework to the light weight interrupt processing framework.

[0100] For the hardware shunt interrupt, the register needs to be modified to change the hardware path, for example, the time delay sensitive interrupt is reported from the separate hardware entry, which can directly enter the corresponding light weight interrupt processing framework, and the software judgment process is saved to realize faster processing process. For the interrupt reported from the separate hardware path, it will automatically enter the light weight interrupt processing framework. This part can quickly process the interrupt due to the logic simplification, and can improve the performance of the system.

[0101] Referring to FIG. 2, FIG. 2 is a system architecture diagram of an embodiment of the present application, which includes software modules: a native interrupt processing framework, wherein a new module (or optimization module) is added: a light weight interrupt processing framework (LINT), which includes hardware modules: a CPU hardware IRQ interface, a GIC interrupt controller, and external devices such as an AI task scheduling unit and a NIC, wherein a new module (or optimization module) is added: a CPU hardware FIQ / LINT interface; their functions are as follows:

[0102] External device: CPU external device triggering interrupt signal, such as network card, disk, etc.

[0103] GIC interrupt controller: manages the interrupt signal sent by the external device, and selects the appropriate interrupt to report to the CPU;

[0104] CPU hardware IRQ / FIQ / LINT interface: CPU pin receiving interrupt signal;

[0105] The functions of each software module are as follows:

[0106] Native interrupt processing framework: existing kernel interrupt processing framework, responsible for all interrupt processing flow

[0107] Light weight interrupt processing framework: a light weight interrupt software processing flow, supporting fast processing of time delay sensitive interrupts.

[0108] In one possible implementation, the first interrupt processing method is the process of switching from the kernel state to the user state and processing the interrupt request, and the second interrupt processing method is the process of processing the interrupt in the kernel state.

[0109] In a possible implementation, the first interrupt request has a greater impact on the performance of the user mode service than on the performance of the kernel mode service; and the second interrupt request has a greater impact on the performance of the kernel mode service than on the performance of the user mode service.

[0110] For example, referring to FIG. 4, FIG. 4 shows an example of executing an interrupt in a user mode, which includes: a server task registers an interrupt processing function in advance, which is used to respond to an IPC request, and is actually equivalent to a signal processing function. The kernel allocates an available interrupt number for subsequent IPC communication, and registers the interrupt processing function into the system through a normal interrupt registration process, to form a real interrupt for the kernel. The server interrupt lightweight processing strategy is configured to enable the server to report an interrupt through a separate LINT interrupt processing entry. A client initiates an IPC request, enters the kernel mode through a system call, queries a CPU where the server task is located and an interrupt number corresponding to the IPC, writes a GIC interrupt controller register to send a specific interrupt to a target CPU, and the target CPU receives the interrupt reported from the LINT entry and directly enters a lightweight interrupt processing framework. Context is saved, an interrupt processing function corresponding to the interrupt number is installed on a hook point, and a jump is made to the user mode for execution. The interrupt processing function is executed in the user mode, IPC service logic is processed, and then the kernel mode is returned. The context is restored in the lightweight interrupt processing framework, and the entire interrupt processing process is completed.

[0111] For example, referring to FIG. 5, FIG. 5 shows a system architecture diagram, in which an interrupt request received by a hardware interface LINT can be executed in a user mode, an interrupt request received by a hardware interface FIQ can be executed in a kernel mode through a lightweight interrupt processing method, and an interrupt request received by a hardware interface IRQ can be executed in a kernel mode through a non-lightweight interrupt processing method.

[0112] In a possible implementation, when applied in the field of AI heterogeneous computing, a first processor (for example, a control processor) obtains a first interrupt request sent by an interrupt controller; the first processor can trigger a second processor to process the first interrupt request through a first interrupt processing method; and the second processor is an AI processor.

[0113] In the field of AI heterogeneous computing, in a large model training scenario, a Host is usually responsible for managing the overall training of a large model, and operators are generated during the training process and need to be executed by a device. Generally, these operators have a small splitting granularity, and the training process and thread scheduling delay are basically equivalent. Therefore, reducing the operator thread scheduling delay will greatly improve the performance of the system.

[0114] Referring to FIG. 6, in the AI CPU operator service scenario, the hardware part mainly consists of an AI task scheduling unit, a GIC interrupt controller, a CTRL CPU, and an AI task running unit, etc. In the operator processing process, first, the AI task scheduling unit judges whether there is an operator to be processed. When it is found that there is an operator to be processed, the AI task scheduling unit reports an interrupt to the CTRL CPU through the GIC. The interrupt processing function of the CTRL CPU saves the relevant data and awakens a tasklet to execute the interrupt lower half. By reading the mailbox, querying the target thread, and converting the eventinfo structure, the specific processing thread of the operator is identified, and the operator processing thread AI task running unit_scheduler is awakened by the operating system to execute the corresponding operator. If the operator thread is not on the current CPU, an additional IPI interrupt is also needed. Through the analysis of the whole operator thread scheduling process, on the one hand, the kernel interrupt framework itself is relatively complex, which brings some interrupt delay noise, and on the other hand, the tasklet soft interrupt mechanism is used in the interrupt lower half, which has a large delay uncertainty.

[0115] To solve the problem, the optimization scheme of the embodiment of the present application in the operator scheduling scenario is as follows:

[0116] Referring to FIG. 7, the AI task scheduling unit driver registers the interrupt according to the normal process, and configures the lightweight processing strategy of the AI task scheduling unit through the proc interface. The internal implementation is divided into two parts. On the one hand, the interrupt controller register is modified to report the interrupt to the CPU through the FIQ pin, and on the other hand, the interrupt descriptor is saved to the FIQ data management structure. After the AI task scheduling unit triggers the interrupt, it automatically enters the lightweight interrupt processing framework through the FIQ pin, realizes the shunt with the kernel native interrupt processing framework from the hardware, saves the basic general register context in the lightweight interrupt processing framework, ensures that there is no interrupt loss and interrupt nesting through the lightweight flow control layer, quickly retrieves the interrupt descriptor from the FIQ data management structure and jumps to the interrupt processing function for processing, and reduces the upper half interrupt delay. In the interrupt processing function, the tasklet soft interrupt is awakened to execute the lower half interrupt. The tasklet fusion feature is used to reduce the lower half delay. The specific method is that for the interrupt configured with the lightweight interrupt strategy, the awakened tasklet is mounted to a separate linked list, which is separated from the tasklet linked list in the kernel native interrupt processing framework. After the upper half interrupt is executed, the tasklet linked list is executed immediately, and no other type of soft interrupt is executed between the two, so as to ensure the lower half delay certainty. The tasklet soft interrupt of the AI task scheduling unit is normally executed, and the thread matched with the operator is awakened.

[0117] By configuring the AI task scheduling unit interrupt to the lightweight interrupt processing framework, the interrupt delay noise is reduced from 5.65us to 2us, the optimization ratio is 64%, the total thread scheduling delay of the operator is reduced from 19.5us to 15.65us, the optimization ratio is 18.7%, and the system performance in the AI heterogeneous training scene is greatly improved.

[0118] Referring to FIG. 8, FIG. 8 is a structure diagram of an interrupt processing apparatus provided by an embodiment of the present application. As shown in FIG. 8, the interrupt processing apparatus provided by an embodiment of the present application includes:

[0119] The acquisition module 801 is configured to acquire a first interrupt request and a second interrupt request.

[0120] The processing module 802 is configured to process the first interrupt request by a first interrupt processing apparatus and process the second interrupt request by a second interrupt processing apparatus.

[0121] The first interrupt request and the second interrupt request are different interrupt requests, and the first interrupt processing apparatus and the second interrupt processing apparatus are different.

[0122] In a possible implementation,

[0123] The processing of the first interrupt request by the first interrupt processing apparatus includes processing the first interrupt request by the first interrupt processing apparatus when an interrupt identifier of the first interrupt request is a first interrupt identifier.

[0124] The processing of the second interrupt request by the second interrupt processing apparatus includes processing the second interrupt request by the second interrupt processing apparatus when an interrupt identifier of the second interrupt request is a second interrupt identifier.

[0125] In a possible implementation, the acquisition module 801 is further configured to:

[0126] Before the first interrupt request is acquired, first configuration information is received, and the first configuration information indicates that an interrupt request for the first interrupt identifier needs to be processed by the first interrupt processing apparatus; or

[0127] Before the second interrupt request is acquired, second configuration information is received, and the second configuration information indicates that an interrupt request for the second interrupt identifier needs to be processed by the second interrupt processing apparatus.

[0128] In a possible implementation, the first interrupt request and the second interrupt request are interrupt requests received through the same hardware interface.

[0129] In a possible implementation, the processing module 802 is specifically configured to:

[0130] when the interrupt identifier of the first interrupt request is an interrupt request received by the acquisition module 801 through a first hardware interface, processing the first interrupt request by a first interrupt processing apparatus;

[0131] processing the second interrupt request by a second interrupt processing apparatus includes: when the interrupt identifier of the second interrupt request is an interrupt request received by the acquisition module 801 through a second hardware interface, processing the second interrupt request by a second interrupt processing apparatus; the first hardware interface and the second hardware interface are different hardware interfaces.

[0132] In a possible implementation, the first interrupt processing apparatus is a process of switching from a kernel state to a user state and processing an interrupt request, and the second interrupt processing apparatus is a process of processing an interrupt in the kernel state.

[0133] In a possible implementation, the first interrupt request has a greater impact on the service performance of the user state than on the service performance of the kernel state; and the second interrupt request has a greater impact on the service performance of the kernel state than on the service performance of the user state.

[0134] In a possible implementation, the complexity of the first interrupt processing apparatus is lower than that of the second interrupt processing apparatus.

[0135] In a possible implementation, the first interrupt processing apparatus is configured to implement a plurality of first functions; the second interrupt processing apparatus is configured to implement a plurality of second functions; the number of the plurality of first functions is less than that of the plurality of second functions; or the execution time delay of the plurality of first functions is lower than that of the plurality of second functions.

[0136] In a possible implementation, the first interrupt request includes: the first processor acquires a first interrupt request sent by an interrupt controller.

[0137] processing the first interrupt request by the first interrupt processing apparatus includes:

[0138] the first processor triggers the second processor to process the first interrupt request by the first interrupt processing apparatus; the second processor is an AI processor.

[0139] Next, a terminal device provided in an embodiment of the present application is introduced. Referring to FIG. 9, FIG. 9 is a structural schematic diagram of a terminal device provided in an embodiment of the present application. The terminal device 900 can specifically be a virtual reality (VR) device, a mobile phone, a tablet, a notebook computer, a smart wearable device, etc., which is not limited herein. Specifically, the terminal device 900 includes a receiver 901, a transmitter 902, a processor 903 and a memory 904 (wherein the number of the processor 903 in the terminal device 900 can be one or more, and one processor is taken as an example in FIG. 9). The processor 903 can include an application processor 9031 and a communication processor 9032. In some embodiments of the present application, the receiver 901, the transmitter 902, the processor 903 and the memory 904 can be connected through a bus or other means.

[0140] The memory 904 can include a read-only memory and a random access memory, and provide the processor 903 with instructions and data. A part of the memory 904 can also include a non-volatile random access memory (NVRAM). The memory 904 stores processor and operation instructions, executable modules or data structures, or a subset thereof, or an extended set thereof, wherein the operation instructions can include various operation instructions for implementing various operations.

[0141] The processor 903 controls the operation of the terminal device. In a specific application, various components of the terminal device are coupled together through a bus system, wherein the bus system can include a data bus, a power bus, a control bus and a status signal bus, etc. in addition to the data bus. However, for the sake of clarity, all kinds of buses are referred to as a bus system in the figure.

[0142] The method disclosed in the embodiments of the present application can be applied to the processor 903 or implemented by the processor 903. The processor 903 can be an integrated circuit chip having a signal processing capability. In the implementation process, the steps of the above method can be completed by hardware integrated logic circuits in the processor 903 or by instructions in the form of software. The processor 903 described above can be a general processor, a digital signal processor (DSP), a microprocessor or a microcontroller, and can further include an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. The processor 903 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processor can be a microprocessor or the processor can also be any conventional processor or the like. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the memory 904, and the processor 903 reads the information in the memory 904, and combines the hardware to complete the steps of the method related to model training or model inference process.

[0143] The receiver 901 can be used to receive input digital or character information, and generate signal input related to the relevant settings and function control of the terminal device. The transmitter 902 can be used to output digital or character information through the first interface; the transmitter 902 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group; the transmitter 902 can also include a display device such as a display screen.

[0144] The server provided in the embodiments of the present application can have a large difference due to different configurations or performances, and can include one or more central processing units (CPUs) 1010 (for example, one or more processors) and a memory 1032, one or more storage media 1030 (for example, one or more mass storage devices) for storing application programs 1042 or data 1044. The memory 1032 and the storage media 1030 can be temporary storage or persistent storage. The programs stored in the storage media 1030 can include one or more modules (not shown in the figure), and each module can include a series of instruction operations in the server. Further, the central processing unit 1010 can be configured to communicate with the storage media 1030 and execute the series of instruction operations in the storage media 1030 on the server 1000.

[0145] The server 1000 can also include one or more power supplies 1026, one or more wired or wireless network interfaces 1050, one or more input and output interfaces 1058, or one or more operating systems 1041, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, and the like.

[0146] In the embodiments of the present application, the central processing unit 1010 is configured to perform the actions related to model training or model inference in the above embodiments.

[0147] The embodiments of the present application also provide a computer program product including a computer program for performing the steps performed by the terminal device or the steps performed by the server when the computer program product is run on a computer.

[0148] The embodiments of the present application also provide a computer readable storage medium having a program for performing signal processing stored therein, which causes a computer to perform the steps performed by the terminal device or the steps performed by the server when the program is run on the computer.

[0149] The terminal device, the server or the terminal device provided in the embodiments of the present application can be a chip, which includes a processing unit, for example, a processor, and a communication unit, for example, an input / output interface, a pin or a circuit. The processing unit can execute computer execution instructions stored in a storage unit, so that the chip in the terminal device executes the interrupt processing method described in the above embodiments, or so that the chip in the server executes the interrupt processing method described in the above embodiments. Alternatively, the storage unit is a storage unit in the chip, such as a register, a cache or the like. The storage unit can also be a storage unit outside the chip in the wireless access device, such as a read-only memory (ROM) or other types of static storage device that can store static information and instructions, a random access memory (RAM) or the like.

[0150] The processor mentioned in any of the above can be a general central processing unit, a microprocessor, an ASIC, or one or more integrated circuits for controlling execution of the above programs.

[0151] It should be further noted that the apparatus embodiments described above are only schematic, and the units described as separate units can or can not be physically separate, and the units displayed as units can or can not be physical units, that is, they can be located in one place, or distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiments. In addition, the connection relationship between the modules in the device embodiment provided in the present application indicates that there is a communication connection between them, which can be implemented as one or more communication buses or signal lines.

[0152] Those skilled in the art can clearly understand that the application can be implemented by means of software plus necessary universal hardware, and of course can also be implemented by means of dedicated hardware including special integrated circuit, special CPU, special memory, special component, etc. Generally, any function completed by computer program can be easily implemented by corresponding hardware, and the specific hardware structure for implementing the same function can also be various, such as analog circuit, digital circuit or special circuit, etc. However, for the application, software program implementation is a better embodiment. Based on such understanding, the technical solution of the application or the part of the application which makes contribution to the prior art can be embodied in the form of software product, which is stored in readable storage medium, such as floppy disk, U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc., and includes a plurality of instructions for making a computer device (which can be personal computer, server or network device, etc.) execute the method described in various embodiments of the application.

[0153] In the above embodiments, the implementation can be achieved by software, hardware, firmware or any combination thereof, entirely or partially. When implemented by software, the implementation can be in the form of computer program product entirely or partially.

[0154] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the flow or function described in the embodiments of the application is generated entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be stored by the computer or a data storage device such as server, data center, etc. integrated with one or more available media. The available medium can be magnetic medium (such as floppy disk, hard disk, magnetic tape), optical medium (such as DVD) or semiconductor medium (such as solid state disk (SSD)) etc.

Claims

1. An interrupt processing method characterized by comprising: The method comprises: obtaining a first interrupt request; processing the first interrupt request by a first interrupt processing method; obtaining a second interrupt request; processing the second interrupt request by a second interrupt processing method; wherein the first interrupt request and the second interrupt request are different interrupt requests, and the first interrupt processing method and the second interrupt processing method are different.

2. The method of claim 1, wherein, The complexity of the first interrupt processing method is lower than that of the second interrupt processing method.

3. The method according to claim 1 or 2, characterized in that, The first interrupt processing method is used to implement a plurality of first functions; the second interrupt processing method is used to implement a plurality of second functions; the number of the plurality of first functions is less than that of the plurality of second functions; or the execution time delay of the plurality of first functions is lower than that of the plurality of second functions.

4. The method according to any one of claims 1 to 3, characterized in that, The processing of the first interrupt request by the first interrupt processing method comprises: when the interrupt identifier of the first interrupt request is a first interrupt identifier, processing the first interrupt request by the first interrupt processing method. The processing of the second interrupt request by the second interrupt processing method comprises: when the interrupt identifier of the second interrupt request is a second interrupt identifier, processing the second interrupt request by the second interrupt processing method.

5. The method of claim 4, wherein, The method further comprises: before the first interrupt request is obtained, first configuration information is received; the first configuration information indicates that the interrupt request for the first interrupt identifier needs to be processed by the first interrupt processing method; or before the second interrupt request is obtained, second configuration information is received; the second configuration information indicates that the interrupt request for the second interrupt identifier needs to be processed by the second interrupt processing method.

6. The method according to any one of claims 1 to 5, characterized in that, The first interrupt request and the second interrupt request are interrupt requests received through the same hardware interface.

7. The method of claim 6, wherein, The processing of the first interrupt request by the first interrupt processing method comprises: when the interrupt identifier of the first interrupt request is an interrupt request received through a first hardware interface, processing the first interrupt request by the first interrupt processing method; The processing of the second interrupt request by the second interrupt processing method comprises: when the interrupt identifier of the second interrupt request is an interrupt request received through a second hardware interface, processing the second interrupt request by the second interrupt processing method; the first hardware interface and the second hardware interface are different hardware interfaces.

8. The method according to any one of claims 1 to 7, characterized in that, The first interrupt processing method is a process of switching from a kernel state to a user state and processing an interrupt request, and the second interrupt processing method is a process of processing an interrupt in the kernel state.

9. The method according to any one of claims 1 to 8, characterized in that, The first interrupt processing method comprises: when it is determined that the interrupt can be returned to the user state for processing, saving the context information of the processor, and installing an interrupt processing function of the user state on a hardware register.

10. The method according to claim 8 or 9, characterized in that, The first interrupt request has a greater impact on the service performance of the user state than on the service performance of the kernel state; The second interrupt request has a greater impact on the service performance of the kernel state than on the service performance of the user state.

11. The method according to any one of claims 1 to 10, characterized in that, The obtaining of the first interrupt request comprises: a first processor obtaining a first interrupt request sent by an interrupt controller; The first interrupt request is processed by the first interrupt processing method, including: The first processor triggers the second processor to process the first interrupt request by the first interrupt processing method; wherein the second processor is an AI processor.

12. An interrupt processing apparatus characterized by comprising: The device comprises: An acquisition module configured to acquire a first interrupt request and a second interrupt request; A processing module configured to process the first interrupt request by a first interrupt processing device and process the second interrupt request by a second interrupt processing device; wherein The first interrupt request and the second interrupt request are different interrupt requests, and the first interrupt processing device and the second interrupt processing device are different.

13. The device of claim 12, wherein The first interrupt request is processed by the first interrupt processing device, including: when the interrupt identifier of the first interrupt request is a first interrupt identifier, processing the first interrupt request by the first interrupt processing device; The second interrupt request is processed by the second interrupt processing device, including: when the interrupt identifier of the second interrupt request is a second interrupt identifier, processing the second interrupt request by the second interrupt processing device.

14. The apparatus of claim 13, wherein, The acquisition module is further configured to: Before acquiring the first interrupt request, receive first configuration information; the first configuration information indicates that the interrupt request for the first interrupt identifier needs to be processed by the first interrupt processing device; or Before acquiring the second interrupt request, receive second configuration information; the second configuration information indicates that the interrupt request for the second interrupt identifier needs to be processed by the second interrupt processing device.

15. The apparatus of any one of claims 12 to 13, wherein, The first interrupt request and the second interrupt request are interrupt requests received through the same hardware interface.

16. The apparatus of claim 12, wherein, The processing module is specifically configured to: When the interrupt identifier of the first interrupt request is an interrupt request received by the acquisition module through a first hardware interface, process the first interrupt request by the first interrupt processing device; The second interrupt request is processed by the second interrupt processing device, including: when the interrupt identifier of the second interrupt request is an interrupt request received by the acquisition module through a second hardware interface, processing the second interrupt request by the second interrupt processing device; the first hardware interface and the second hardware interface are different hardware interfaces.

17. The apparatus of any one of claims 12 to 16, wherein, The first interrupt processing device is a process of switching from a kernel state to a user state and processing an interrupt request, and the second interrupt processing device is a process of processing an interrupt in a kernel state.

18. The apparatus of any of claims 12 to 17, wherein, The first interrupt processing method includes: When it is determined that the processor can return to the user state to process the interrupt, save the context information of the processor, and install an interrupt processing function of the user state on a hardware register.

19. The apparatus of claim 17 or 18, wherein, The first interrupt request has a greater impact on the service performance of the user state than on the service performance of the kernel state; The second interrupt request has a greater impact on the service performance of the kernel state than on the service performance of the user state.

20. The apparatus of any of claims 12 to 19, wherein, The complexity of the first interrupt processing device is lower than that of the second interrupt processing device.

21. The apparatus of claim 20, wherein, The first interrupt processing device is configured to implement a plurality of first functions; the second interrupt processing device is configured to implement a plurality of second functions; the number of the plurality of first functions is less than the number of the plurality of second functions; or, the execution time delay of the plurality of first functions is lower than the execution time delay of the plurality of second functions.

22. The apparatus of any one of claims 12 to 21, wherein, The first interrupt request is obtained by the first processor. The first interrupt request is processed by the first interrupt processing device. The first processor triggers the second processor to process the first interrupt request by the first interrupt processing device; the second processor is an AI processor.

23. A computer program product, characterised in that, The computer readable instructions, when executed on a computer device, cause the computer device to perform the method of any one of claims 1-11.

24. A system, comprising: The at least one processor, the at least one memory, and the communication bus are connected and complete mutual communication. The at least one memory is configured to store code. The at least one processor is configured to execute the code to perform the method of any one of claims 1-11.

25. A chip comprising a processor, wherein: The processor is configured to support the interrupt processing device to implement the method of any one of claims 1-11.

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