Package substrate and preparation method therefor, semiconductor stack structure, and electronic device

Abstract

The embodiments of the present application belong to the technical field of semiconductors, and in particular relate to a package substrate and a preparation method therefor, a semiconductor stack structure, and an electronic device, aiming to mitigate warpage in package substrates in the related art. The package substrate comprises a substrate, a connection portion and a redistribution layer. The substrate comprises a substrate body and a plurality of conductive pillars, wherein the conductive pillars penetrate at least part of the substrate body in a first direction, and the distance between any two adjacent conductive pillars is less than 15 mm; the connection portion is located on one side of the substrate in the first direction and is in contact with the conductive pillars; and the redistribution layer is located on the other side of the substrate in the first direction and is in contact with the conductive pillars. The provision of the substrate body and the plurality of conductive pillars helps improve the rigidity of the substrate, reducing warpage in the package substrate.

Description

Package substrate, method for manufacturing the same, semiconductor stack structure, and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411334014.7, filed on September 23, 2024, and entitled "Package substrate, method for manufacturing the same, semiconductor stack structure, and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The embodiments of the present application belong to the technical field of semiconductor technology, and particularly relate to a package substrate, a method for manufacturing the same, a semiconductor stack structure, and an electronic device. BACKGROUND

[0003] To further meet the miniaturization of electronic devices, higher requirements are put forward for semiconductor integration technology. In an electronic device including a semiconductor stack structure, the semiconductor stack structure includes a package substrate and a chip stacked on the package substrate. The package substrate includes a redistribution layer, and the chip is connected to the redistribution layer. However, in the related art, the package substrate may be warped and deformed, making it difficult to increase the number of chips in the semiconductor stack structure or leading to poor performance of the semiconductor stack structure, and making it difficult to continuously improve the integration level between chips. SUMMARY

[0004] Embodiments of the present application aim to provide a package substrate, a method for manufacturing the same, a semiconductor stack structure, and an electronic device, to improve the phenomenon that the warpage of the package substrate in the related art is difficult to control.

[0005] To achieve the above-mentioned purpose, the embodiments of the present application provide the following solutions.

[0006] In a first aspect, the embodiments of the present application provide a package substrate, which includes a substrate, a connecting portion, and a redistribution layer. The substrate includes a substrate body and a plurality of conductive pillars. The conductive pillars penetrate at least part of the substrate body along a first direction. The distance between any two adjacent conductive pillars is less than 15 mm. The connecting portion is located on one side of the substrate along the first direction and is in contact with the conductive pillars. The redistribution layer is located on the other side of the substrate along the first direction and is in contact with the conductive pillars.

[0007] Through the above arrangement, the conductive column connects the redistribution layer and the connecting part, so as to interconnect the redistribution layer and the connecting part. In actual application, the connecting part is connected with the circuit board, the redistribution layer is connected with the chip through the connecting part, and the packaging substrate can play the role of a conversion board, so that the chip can be connected with the circuit board. At the same time, by arranging the substrate body and the plurality of conductive columns, the rigidity of the substrate can be improved, and the warping of the packaging substrate can be reduced. Further, the distance between any two adjacent conductive columns is less than 15mm, which is less than the size of the chip, so that the chip cannot be arranged between the two adjacent conductive columns. Moreover, through the above arrangement, the rigidity of the substrate can be further improved, and the warping of the packaging substrate can be reduced.

[0008] In some embodiments including the above-mentioned embodiments, the redistribution layer includes a conductive line and a dielectric layer, the conductive line is in contact with the conductive column, and the thermal expansion coefficient of the dielectric layer is the same as or similar to that of the substrate body. Through the above arrangement, when the ambient temperature changes (for example, the ambient temperature changes suddenly cold or hot, or the temperature during the operation of the packaging substrate is relatively high), the equivalent thermal stress of the dielectric layer and the substrate body is similar, the interaction force between the dielectric layer and the substrate body is reduced, and the stress deformation between the dielectric layer and the substrate body is reduced, thereby achieving the purpose of reducing the warping degree of the packaging substrate. At the same time, when the materials of the two are the same, the adhesion effect of the substrate body and the redistribution layer is better, which is conducive to improving the connection reliability between the substrate body and the redistribution layer.

[0009] In some embodiments including the above-mentioned embodiments, the substrate body of the packaging substrate includes a first layer and a second layer arranged in a stack, and the second layer is located between the first layer and the redistribution layer. The thermal expansion coefficient of the first layer is similar to that of the second layer. Through the above arrangement, a multi-layer structure of the substrate body is realized, which is conducive to further improving the rigidity of the packaging substrate, reducing the deformation of the substrate body caused by changes in the external environment, such as pressure (for example, pressure in the process of grinding and other processes), and further controlling the warping of the packaging substrate. In addition, through the above arrangement, when the ambient temperature changes (for example, the ambient temperature changes suddenly cold or hot, or the temperature during the operation of the packaging substrate is relatively high), the equivalent thermal stress of the first layer and the second layer is similar, the interaction force between the first layer and the second layer is reduced, and the stress deformation between the first layer and the second layer is reduced, thereby achieving the purpose of reducing the warping degree of the packaging substrate. At the same time, when the materials of the two are similar, the adhesion effect of the first layer and the second layer is better than that of using materials with large differences, which is conducive to improving the connection reliability between the substrate body and the redistribution layer.

[0010] In some embodiments including the above-mentioned embodiments, the conductive pillar is disposed through the second layer, and the connecting portion is disposed through the first layer to contact the conductive pillar. Alternatively, the conductive pillar is disposed through the second layer and the first layer. Through the above-mentioned arrangement, the conductive pillar is in contact with the connecting portion, and the redistribution layer and the connecting portion are interconnected through the conductive pillar.

[0011] In some embodiments including the above-mentioned embodiments, the material of the first layer includes an organic material; and / or, the material of the second layer includes a molding material. Through the above-mentioned arrangement, the thermal expansion coefficient of the first layer is close to the thermal expansion coefficient of the dielectric layer in the redistribution layer, and the thermal expansion coefficient of the first layer is also close to the thermal expansion coefficient of the second layer, so that the equivalent thermal stress between the first layer, the second layer and the dielectric layer is close, the interaction force between the first layer and the second layer and the dielectric layer is reduced, and the stress deformation between the first layer, the second layer and the dielectric layer is reduced, thereby reducing the warpage degree of the packaging substrate.

[0012] In some embodiments including the above-mentioned embodiments, the packaging substrate further includes an electronic device, the electronic device is located between two adjacent conductive pillars, a connecting member is arranged on the side of the electronic device away from the connecting portion, and the electronic device is connected to the conductive wire through the connecting member. Through the above-mentioned arrangement, the electronic device is arranged between the two adjacent conductive pillars, which is beneficial to improve the performance of the packaging substrate while avoiding the electronic device occupying a large space of the packaging substrate, and is beneficial to improve the integration of the packaging substrate.

[0013] In the second aspect, the embodiments of the present application provide a semiconductor stack structure, which includes a chip and the packaging substrate in any of the above-mentioned embodiments. The chip and the packaging substrate are stacked, and the chip is connected to the redistribution layer of the packaging substrate. The semiconductor stack structure provided by the embodiments of the present application includes the packaging substrate as described above, and thus has all the beneficial effects described above, which will not be repeated here.

[0014] In some embodiments including the above-mentioned embodiments, the number of chips is multiple, at least one chip is flip-chip bonded to the packaging substrate, and at least one chip is wire-bonded to the packaging substrate. Through the above-mentioned arrangement, the semiconductor stack structure can realize hybrid bonding, and the performance of the semiconductor stack structure can be effectively improved by reasonably increasing the number of chips.

[0015] In the third aspect, the embodiments of the present application provide an electronic device, which includes a circuit board and the semiconductor stack structure in any of the above-mentioned embodiments. The semiconductor stack structure and the circuit board are stacked, and the circuit board is connected to the connecting portion of the semiconductor stack structure. The electronic device provided by the embodiments of the present application includes the semiconductor stack structure as described above, and thus has all the beneficial effects described above, which will not be repeated here.

[0016] In a fourth aspect, the embodiments of the present application provide a method for manufacturing a packaging substrate. The method comprises: providing a carrier plate; forming a substrate on the carrier plate, the substrate comprising a substrate body and a plurality of conductive pillars, the conductive pillars penetrating through the substrate body along a first direction, and a distance between any two adjacent conductive pillars being less than 15 mm; forming a redistribution layer on one side of the substrate, the redistribution layer being in contact with the conductive pillars; removing the carrier plate; and forming a connecting portion on the other side of the substrate, the connecting portion being in contact with the conductive pillars. The method for manufacturing a packaging substrate provided by the embodiments of the present application is used for manufacturing a packaging substrate as described above, and thus has all the beneficial effects described above, which will not be repeated here.

[0017] In some embodiments including the above-described embodiments, the forming of the substrate on the carrier plate comprises: forming a plurality of conductive pillars on the carrier plate; and filling a molding material between the plurality of conductive pillars to form the substrate body. Through the above-described arrangement, the conductive pillars are stabilized by the molding material, and the molding material has certain temperature resistance, such as not being prone to chemical or physical changes at the maximum temperature at which the packaging substrate works.

[0018] In some embodiments including the above-described embodiments, before the forming of the plurality of conductive pillars on the carrier plate, the method for manufacturing a packaging substrate further comprises: forming a first layer on the carrier plate, the material of the first layer comprising an organic material; and removing part of the first layer to form a through hole penetrating through the first layer. The forming of the plurality of conductive pillars on the carrier plate comprises: forming the conductive pillars in the through hole. Through the above-described arrangement, the substrate body can have a multi-layer structure, which slows down the deformation of the substrate body due to changes in external environment, such as being pressed (for example, being pressed in a process such as grinding), and is beneficial to further improve the rigidity of the packaging substrate and further control the warping of the packaging substrate.

[0019] In some embodiments including the above-described embodiments, before the forming of the plurality of conductive pillars on the carrier plate, the method for manufacturing a packaging substrate further comprises: forming a first layer on the carrier plate, the material of the first layer comprising an organic material. After the carrier plate is removed, before the forming of the connecting portion on the other side of the substrate, the method for manufacturing a packaging substrate further comprises: removing part of the first layer to form a through hole exposing the conductive pillars. The forming of the connecting portion on the other side of the substrate comprises: forming the connecting portion in the through hole. Through the above-described arrangement, the substrate body can have a multi-layer structure, which slows down the deformation of the substrate body due to changes in external environment, such as being pressed (for example, being pressed in a process such as grinding), and is beneficial to further improve the rigidity of the packaging substrate and further control the warping of the packaging substrate.

[0020] In some embodiments including those described above, the method for fabricating the packaging substrate further includes: after forming a plurality of conductive pillars on a carrier plate, and before filling the spaces between the conductive pillars with molding material, the method further includes: placing an electronic device between two adjacent conductive pillars, with a connector disposed on the side of the electronic device facing away from the connecting portion. After filling the spaces between the conductive pillars with molding material, the method further includes: grinding a first end face of the substrate body to expose the connector of the electronic device on the first end face, the first end face being located on the side of the substrate body facing away from the carrier plate. Through this arrangement, while placing the electronic device between two adjacent conductive pillars, the method avoids the electronic device occupying a large space on the packaging substrate, which is beneficial for improving the integration of the packaging substrate. Simultaneously, this arrangement can also improve the performance of the packaging substrate and expand its application scenarios. Attached Figure Description

[0021] Figure 1 is a structural diagram of an electronic device provided in an embodiment of this application;

[0022] Figure 2 is a structural diagram of a semiconductor stacked structure provided in an embodiment of this application;

[0023] Figure 3 is a structural diagram of a packaging substrate provided in an embodiment of this application;

[0024] Figure 4 is a structural diagram of another packaging substrate provided in an embodiment of this application;

[0025] Figure 5 is a structural diagram of another packaging substrate provided in an embodiment of this application;

[0026] Figure 6 is a structural diagram of another packaging substrate provided in an embodiment of this application;

[0027] Figure 7 is a structural diagram of another packaging substrate provided in an embodiment of this application;

[0028] Figure 8 is a structural diagram of another packaging substrate provided in an embodiment of this application;

[0029] Figure 9 is a flowchart of the steps of a method for preparing a packaging substrate according to an embodiment of this application;

[0030] Figure 10 is a structural diagram of the carrier plate provided in a method for preparing a packaging substrate according to an embodiment of this application;

[0031] Figure 11 is a structural diagram of the substrate after it has been formed in a method for preparing a packaging substrate according to an embodiment of this application;

[0032] Figure 12 is a structural diagram of a packaging substrate after the redistribution layer is formed in a method for preparing a packaging substrate according to an embodiment of this application;

[0033] FIG. 13 is a structure diagram of a connection part formed in a preparation method of a packaging substrate according to an embodiment of the present application;

[0034] FIG. 14 is a structure diagram of a substrate formed in another preparation method of a packaging substrate according to an embodiment of the present application;

[0035] FIG. 15 is a structure diagram of a substrate formed in another preparation method of a packaging substrate according to an embodiment of the present application;

[0036] FIG. 16 is a structure diagram of a connection part formed in another preparation method of a packaging substrate according to an embodiment of the present application;

[0037] FIG. 17 is a structure diagram of a substrate formed in another preparation method of a packaging substrate according to an embodiment of the present application;

[0038] FIG. 18 is a structure diagram of a connection part formed in another preparation method of a packaging substrate according to an embodiment of the present application;

[0039] FIG. 19 is a schematic diagram of cutting a packaging substrate according to an embodiment of the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application.

[0041] Hereinafter, the terms “first”, “second”, and the like are used only for description convenience, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first”, “second”, and the like can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of “a plurality of” is two or more.

[0042] In the embodiments of the present application, the words “exemplary” or “for example” are used to mean serving as an example, instance, or illustration. Any embodiment or design presented as “exemplary” or “for example” in the embodiments of the present application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of the words “exemplary” or “for example” is intended to present concepts in a concrete manner.

[0043] In describing some embodiments, the expressions “connected”, “electrically connected”, and the like may be used. For example, in describing some embodiments, the term “connected” may be used to indicate that two or more components have direct physical contact with each other, and the term “electrically connected” may be used to indicate that two or more components have electrical contact with each other.

[0044] In the context of this application, "on," "over," and "above" should be interpreted in the broadest context possible so that "on" means not only "directly on" but also includes the meaning of "on" with intervening features or layers therebetween, and "over" or "above" means not only "over" or "above" but also includes the meaning of "over" or "above" with no intervening features or layers therebetween (i.e., directly on).

[0045] Exemplary embodiments are described herein with reference to structural drawings as idealized illustrations. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the precise shapes illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched region illustrated as a rectangle will typically have curved features. Thus, the regions illustrated in the drawings are schematic and their shapes are not intended to illustrate the precise appearance of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0046] Referring to FIG. 1, FIG. 1 is a structural diagram of an electronic device 10 provided by an embodiment of the present application. The electronic device 10 can include an image sensor, a NAND flash, a high bandwidth memory, a mobile phone, a pad, a television, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, and the like. The embodiment of the present application does not specially limit the specific form of the electronic device 10.

[0047] The electronic device 10 can include a circuit board 120 and a semiconductor stack structure 110, and the semiconductor stack structure 110 is stacked with the circuit board 120, wherein the semiconductor stack structure 110 includes a packaging substrate, and the packaging substrate includes a connecting part 230. The circuit board 120 is connected with the connecting part 230.

[0048] Exemplarily, the connecting part 230 can include a pad, a bump, and the like. The shape of the bump can include a spherical shape, a columnar shape, and the like. The material of the connecting part 230 can include one or more combinations of conductive materials such as copper, nickel, gold, titanium, cobalt, tungsten, and the like, or other conductive alloy materials. By providing the connecting part 230, electrical interconnection between the circuit board 120 and the semiconductor stack structure 110 can be achieved, and the connecting part 230 can also play a role of stress buffering.

[0049] Please refer to FIG. 2, which is a structural diagram of a semiconductor stack structure 110 provided by an embodiment of the present application. The semiconductor stack structure 110 includes a packaging substrate 200 and a chip 300. The chip 300 is stacked with the packaging substrate 200, and the chip 300 is connected with the packaging substrate 200.

[0050] Please continue to refer to FIG. 2. In some embodiments, the number of chips 300 is multiple. At least one chip 300 is flip-chip bonded with the packaging substrate 200, and at least one chip 300 is wire-bonded with the packaging substrate 200.

[0051] In the embodiment of the present application, the number of chips 300 is not limited. At least one chip 300 is a first chip 310, and the first chip 310 is flip-chip bonded with the packaging substrate 200. At least one chip 300 is a second chip 320, and the second chip 320 is wire-bonded with the packaging substrate 200. Through the above arrangement, the semiconductor stack structure 110 can realize hybrid bonding, and by reasonably increasing the number of first chips 310 and second chips 320, the performance of the semiconductor stack structure 110 can be effectively improved.

[0052] For example, the number of first chips 310 can be two, and the two first chips 310 are arranged in a direction parallel to the packaging substrate 200. The first chip 310 is flip-chip bonded (FCB) with the packaging substrate 200. Here, "flip-chip bonding" can be understood as flip-chip (reversed by 180 degrees) mounting the first chip 310 on the packaging substrate 200 through bumps. For example, the bumps can include flip-chip ball grid array (FCBGA).

[0053] For example, the number of second chips 320 can be eight, and the plurality of second chips 320 are stacked in a direction perpendicular to the packaging substrate 200, and the plurality of second chips 320 are located on a side of the first chip 310 away from the packaging substrate 200. The second chip 320 is wire-bonded (WB) with the packaging substrate 200. Here, "wire bonding" can be understood as bonding the front surface of the second chip 320 with the packaging substrate 200 through a wire 400 (such as a metal wire).

[0054] In some embodiments, interconnection can also be performed between the first chip 310 and the second chip 320. For example, the first chip 310 and the second chip 320 can also be connected through through silicon via (TSV).

[0055] In some embodiments, the semiconductor stack structure 110 can include at least part of a memory. The first chip 310 can include a logic chip. The logic chip can include a central processing unit (CPU), a system on chip (SOC), or any one or more of the logic circuit chips. The second chip 320 can include a memory chip, which can include a DRAM chip.

[0056] Referring to FIG. 3, FIG. 3 is a structure diagram of a packaging substrate 200 according to an embodiment of the present application. In some embodiments, the packaging substrate 200 can include a redistribution layer 220 (RDL). The redistribution layer 220 includes a conductive line 221 and a dielectric layer 222. The conductive line 221 can re-distribute I / O (input / output) ports to a more relaxed area and form a face array arrangement. Thus, the redistribution layer 220 plays a role of re-distributing and allocating electrical signals. The first chip 310 can be connected to the conductive line 221 of the redistribution layer 220 through bumps, and the second chip 320 can be connected to the conductive line 221 of the redistribution layer 220 through a wire 400.

[0057] In order to improve the interconnection density between the chips 300 in the semiconductor stack structure 110, the line width needs to be reduced and the line density of the redistribution layer 220 in the packaging substrate 200 needs to be improved. In some embodiments, the redistribution layer 220 can be prepared in an advanced packaging production line. However, the wire bonding between the chips 300 and the packaging substrate 200 still needs to be performed in a traditional packaging production line.

[0058] In some embodiments, after the redistribution layer 220 is prepared in an advanced process production line, it needs to be cut to a suitable size and then delivered to a traditional packaging production line for wire bonding. However, since the thickness of the redistribution layer 220 is relatively thin, the redistribution layer 220 is prone to warping and deforming when it is cut, which leads to difficulty in increasing the number of chips 300 in the semiconductor stack structure 110 or poor performance of the semiconductor stack structure 110.

[0059] Therefore, referring back to FIG. 3, the packaging substrate 200 includes a substrate 210, which includes a substrate body 211 and a plurality of conductive pillars 212 penetrating at least part of the substrate body 211 along a first direction Y. The packaging substrate 200 further includes a connecting portion 230 located on one side of the substrate 210 along the first direction Y and in contact with the conductive pillars 212, and the redistribution layer 220 is located on the other side of the substrate 210 along the first direction Y and in contact with the conductive pillars 212.

[0060] Hereinafter, a direction perpendicular to the substrate body 211 is referred to as a first direction Y. The conductive pillar 212 penetrates at least part of the substrate body 211 along the first direction Y. It can be understood that the conductive pillar 212 penetrates the entire substrate body 211 along the first direction Y (as shown in FIG. 3), or the conductive pillar 212 penetrates part of the substrate body 211 along the first direction Y (as shown in FIG. 4).

[0061] Referring to FIG. 3, the substrate body 211 can have a substantially plate structure, which can be perpendicular to the first direction Y. By providing the substrate body 211, the redistribution layer 220 can be supported and carried to a certain extent. In the embodiment of the present application, the material of the substrate body 211 can include a molding material, such as an epoxy molding compound (EMC), so that the substrate body 211 has good stability and certain pressure resistance. For example, the epoxy molding compound is not easy to change chemically or physically at the highest temperature of the operation of the packaging substrate 200 or in the process of grinding and other processes.

[0062] Please continue to refer to FIG. 3. In some embodiments, the redistribution layer 220 includes a conductive line 221, and the line width of the conductive line 221 can be less than 8 μm. The present application does not limit this. By the above arrangement, the smaller the line width of the conductive line 221, the greater the line density of the conductive line 221 of the redistribution layer 220. Because the plurality of chips 300 in the semiconductor stacked structure 110 are mixedly bonded with the redistribution layer 220 of the packaging substrate 200, the line density of the conductive line 221 of the redistribution layer 220 is increased to meet the demand of high-density interconnection between the chip 300 and the packaging substrate 200 in the application of the semiconductor stacked structure 110.

[0063] Please continue to refer to FIG. 3, and in combination with FIG. 2, the shape of the conductive pillar 212 can be substantially cylindrical, and the extension direction of the conductive pillar 212 can be parallel to the first direction Y. One end of the conductive pillar 212 along the first direction Y can be connected with the conductive line 221 of the redistribution layer 220, and the other end of the conductive pillar 212 along the first direction Y can be connected with the connecting part 230. By providing the conductive pillar 212, the interconnection between the redistribution layer 220 and the connecting part 230 can be realized. In the embodiment of the present application, the material of the conductive pillar 212 can include one or a combination of copper, nickel, gold, titanium, cobalt, tungsten and other conductive materials, or other conductive alloy materials, which are not limited by the present application.

[0064] Please continue to refer to FIG. 3, the distance between any two adjacent conductive pillars 212 is less than 15 mm. For example, the distance between any two adjacent conductive pillars 212 can be 13 mm, 10 mm or 8 mm. Since the distance is less than the size of the chip 300, by limiting the distance between the two adjacent conductive pillars 212, the chip 300 cannot be placed between the two adjacent conductive pillars 212. Moreover, by the above arrangement, it is also beneficial to improve the distribution density of the conductive pillars 212 in the substrate 210, further improve the rigidity of the substrate 210, and thus reduce the warpage of the packaging substrate 200.

[0065] In summary, by the above arrangement, the conductive pillars 212 connect the redistribution layer 220 and the connecting part 230, so as to interconnect the redistribution layer 220 and the connecting part 230. In actual application, the redistribution layer 220 can be connected with the chip 300 (in combination with FIG. 2), and the connecting part 230 can be connected with the circuit board 120 (in combination with FIG. 1), so that the packaging substrate 200 can play the role of a conversion board, and thus the packaging substrate 200 can connect the chip 300 with the circuit board 120. At the same time, by arranging the substrate body 211 and the plurality of conductive pillars 212, it is beneficial to improve the rigidity of the substrate 210 and reduce the warpage of the packaging substrate 200. Further, the distance between any two adjacent conductive pillars 212 is less than 15 mm, which is less than the size of the chip 300, and the chip 300 cannot be arranged between the two adjacent conductive pillars 212. Moreover, by the above arrangement, it is also beneficial to further improve the rigidity of the substrate 210 and reduce the warpage of the packaging substrate 200. Since the packaging substrate 200 has a certain rigidity, the line width of the conductive lines 221 in the redistribution layer 220 can be reduced, so as to improve the line density and meet the demand of high-density interconnection between the chip 300 and the packaging substrate 200.

[0066] Please continue to refer to FIG. 3, in some embodiments, the thermal expansion coefficient of the dielectric layer 222 is the same as or close to that of the substrate body 211.

[0067] For example, the material of the dielectric layer 222 can include organic materials such as polyimide (PI), benzo cyclobutene (BCB), ajinomoto build-up film (ABF), etc.

[0068] In some examples, the material of the dielectric layer 222 can be the same as or similar to the material of the substrate body 211, so that the thermal expansion coefficients of the dielectric layer 222 and the substrate body 211 are the same or similar. When the ambient temperature changes (for example, the ambient temperature changes suddenly or the temperature of the packaging substrate 200 is high when the packaging substrate 200 works), the equivalent thermal stress of the dielectric layer 222 and the substrate body 211 is the same or similar, which slows down the interaction force between the dielectric layer 222 and the substrate body 211, and further reduces the stress deformation between the dielectric layer 222 and the substrate body 211, so as to slow down the warping degree of the packaging substrate 200. At the same time, when the materials of the two are the same or similar, the adhesion effect of the substrate body 211 and the redistribution layer 220 is better, which is conducive to improving the connection reliability between the substrate body 211 and the redistribution layer 220.

[0069] Here, "similar" can be understood as the difference between the thermal expansion coefficient of the dielectric layer 222 and the thermal expansion coefficient of the substrate body 211 is within 10%.

[0070] Please refer to FIG. 4, in some embodiments, the substrate body 211 can include a first layer 2111 and a second layer 2112 arranged in a stack. The second layer 2112 can be arranged between the first layer 2111 and the redistribution layer 220.

[0071] Please continue to refer to FIG. 4, as described in the above embodiment, the conductive pillar 212 penetrates at least part of the substrate body 211. For example, the conductive pillar 212 can penetrate the second layer 2112 of the substrate body 211, so that the conductive pillar 212 penetrates part of the substrate body 211. Correspondingly, the connecting portion 230 can penetrate the first layer 2111 to contact the conductive pillar 212, so that the connecting portion 230 can be connected with the conductive pillar 212. For example, the first layer 2111 can have a through hole 700, the connecting portion 230 extends into the through hole 700 and contacts the conductive pillar 212.

[0072] Please refer to FIG. 5, the conductive pillar 212 can penetrate the first layer 2111 and the second layer 2112 to be arranged, so that the conductive pillar 212 penetrates the entire substrate body 211. Correspondingly, the connecting portion 230 can be located on the side of the first layer 2111 away from the second layer 2112, and the connecting portion 230 can contact the conductive pillar 212. For example, the first layer 2111 can have a through hole 700, the conductive pillar 212 penetrates the through hole 700 and contacts the connecting portion 230.

[0073] Through the above arrangement, the multi-layer structure of the substrate body 211 is conducive to further improving the rigidity of the packaging substrate 200 and slowing down the deformation of the substrate body 211 caused by changes in the external environment, such as under pressure (for example, under pressure during grinding process), and further controlling the warping of the packaging substrate 200.

[0074] In the above embodiment, the first layer 2111 and the second layer 2112 can have similar thermal expansion coefficients. Here, the term "similar" can be understood as a difference between the thermal expansion coefficient of the first layer 2111 and the thermal expansion coefficient of the second layer 2112 being within 10%. As described in the above embodiment, when the thermal expansion coefficient of the material of the first layer 2111 is similar to the thermal expansion coefficient of the material of the second layer 2112, the equivalent thermal stress of the first layer 2111 and the second layer 2112 is similar in the case of a change in ambient temperature (e.g., a sudden change in ambient temperature or a high temperature during operation of the packaging substrate 200), which slows down the interaction force between the first layer 2111 and the second layer 2112, thereby reducing the stress deformation between the first layer 2111 and the second layer 2112, and achieving the purpose of reducing the warpage of the packaging substrate 200. At the same time, when the materials of the first layer 2111 and the second layer 2112 are similar, the adhesion effect of the first layer 2111 and the second layer 2112 is better than that of using materials with a large difference, and at the same time, it is beneficial to improve the connection reliability between the substrate body 211 and the redistribution layer 220.

[0075] In some embodiments, the material of the first layer 2111 can include an organic material, which can be, for example, polyimide (PI), ajinomoto build-up film (ABF), or the like. In some embodiments, the material of the second layer 2112 can include a molding material.

[0076] Through the above arrangement, the thermal expansion coefficient of the first layer 2111 is similar to the thermal expansion coefficient of the dielectric layer 222 in the redistribution layer 220, and the thermal expansion coefficient of the first layer 2111 is also similar to the thermal expansion coefficient of the second layer 2112, so that the equivalent thermal stress between the first layer 2111, the second layer 2112, and the dielectric layer 222 is similar, thereby slowing down the interaction force between the first layer 2111, the second layer 2112, and the dielectric layer 222, thereby reducing the stress deformation between the first layer 2111, the second layer 2112, and the dielectric layer 222, and achieving the purpose of reducing the warpage of the packaging substrate 200.

[0077] Please refer to FIG. 6. In some embodiments, the packaging substrate 200 can further include an electronic device 240 located between two adjacent conductive pillars 212. The electronic device 240 is provided with a connecting member 241 on the side away from the connecting portion 230, and the electronic device 240 can be connected to the conductive wire 221 of the redistribution layer 220 of the packaging substrate 200 through the connecting member 241. The connecting member 241 of the electronic device 240 can include, for example, the pin of the electronic device 240.

[0078] Please continue to refer to FIG. 6, in the embodiment in which the substrate body 211 includes a single layer of film, the electronic device 240 can pass through the entire substrate body 211, and the electronic device 240 can be located between two adjacent conductive pillars 212.

[0079] Please refer to FIG. 7 and FIG. 8, in the embodiment in which the substrate body 211 includes a first layer 2111 and a second layer 2112, the electronic device 240 can pass through part of the substrate body 211. For example, the electronic device 240 can be located between the first layer 2111 and the redistribution layer 220, and the electronic device 240 can pass through the second layer 2112, and the electronic device 240 is also located between two adjacent conductive pillars 212.

[0080] In some other embodiments in which the substrate body 211 includes a first layer 2111 and a second layer 2112, the electronic device 240 can also pass through the entire substrate body 211. For example, the electronic device 240 can pass through the first layer 2111 and the second layer 2112, and the electronic device 240 can be located between two adjacent conductive pillars 212.

[0081] Of course, the embodiments of the present application do not specifically limit the arrangement of the electronic device 240, and the electronic device 240 is located in the packaging substrate 200, and the electronic device 240 can be connected to the redistribution layer 220.

[0082] In some embodiments, the corresponding electronic device 240 can be set according to different application requirements. In the embodiments of the present application, the electronic device 240 can include active devices and passive devices. The active devices can include transistors, diodes, etc., and the passive devices can include capacitors, inductors, resistors, etc.

[0083] In the embodiments of the present application, the electronic device 240 can also include integrated passive devices (IPD). The number and type of electronic devices 240 are not limited in the present application.

[0084] Through the above arrangement, the electronic device 240 is arranged between two adjacent conductive pillars 212, which is conducive to improving the performance of the packaging substrate 200 while avoiding the electronic device 240 occupying a large space of the packaging substrate 200, and is conducive to improving the integration of the packaging substrate 200.

[0085] Please refer to FIG. 9, which is a step flow chart of a packaging substrate 200 preparation method provided by an embodiment of the present application. The embodiment of the present application provides a packaging substrate 200 preparation method for preparing the packaging substrate 200 in the above embodiments. The preparation method can include the following steps S101 to S105.

[0086] S101, providing a carrier plate.

[0087] Referring to FIG. 10, a carrier plate 600 is provided.

[0088] The material of the carrier plate 600 can include ceramic, glass, silicon or any other suitable material that can serve as a carrier. It can be understood that some subsequent processes need to be performed on the carrier plate 600, and therefore the temporary carrier plate 600 is provided.

[0089] In this embodiment, after the carrier plate 600 is provided, step S102 is further included.

[0090] S102, forming a substrate on the carrier plate, the substrate including a substrate body and a plurality of conductive pillars, the conductive pillars penetrating through the substrate body along a first direction, and a distance between any two adjacent conductive pillars being less than 15 mm.

[0091] Referring to FIG. 11, after the carrier plate 600 is provided, a plurality of conductive pillars 212 can be formed on the carrier plate 600.

[0092] The conductive pillars 212 can be formed on the carrier plate 600 by a through mold via (TMV) technology, and further, the conductive pillars 212 can be formed by using a layering method. The formation of the conductive pillars 212 can make the packaging substrate 200 have rigidity, and the conductive pillars 212 are arranged at intervals of no more than 15 mm, which is conducive to improving the distribution density of the conductive pillars 212 in the packaging substrate 210, further improving the rigidity of the packaging substrate 200, and controlling the warping of the packaging substrate 200.

[0093] Continuing to refer to FIG. 11, after the conductive pillars 212 are formed, a molding material can be filled between the plurality of conductive pillars 212 to form a substrate body 211.

[0094] For example, a molding process, a compression process, chemical vapor deposition (CVD), physical vapor deposition (PVD), coating, spin coating, etc. can be used. The substrate body 211 is formed around the conductive pillars 212, and the substrate body 211 is between adjacent conductive pillars 212. Through the above arrangement, the substrate body 211 can fix the conductive pillars 212, and at the same time, due to the good stability and certain pressure resistance of the substrate body 211, the performance of the packaging substrate 200 can be stabilized.

[0095] For ease of description, a side surface of the substrate body 211 away from the carrier plate 600 is referred to as a first end surface 800, and a side surface of the substrate body 211 close to the carrier plate 600 is referred to as a second end surface 900.

[0096] In some embodiments, after filling the plurality of conductive pillars 212 with the molding material, the method of manufacturing the packaging substrate 200 further comprises: grinding a first end surface 800 of the substrate body 211, the first end surface 800 being located on a side of the substrate body 211 facing away from the carrier substrate 600. By the above arrangement, the conductive pillars 212 are exposed to the first end surface 800, and meanwhile, the flatness of the first end surface 800 can be trimmed.

[0097] For example, the grinding of the first end surface 800 of the substrate body 211 can be grinding of a side of the substrate body 211 facing away from the carrier substrate 600. The grinding can include backside grinding (BG) or chemical mechanical polishing (CMP).

[0098] In the present embodiment, after the substrate 210 is formed, the method further comprises step S103.

[0099] S103, forming a redistribution layer on a side of the substrate, the redistribution layer being in contact with the conductive pillars.

[0100] Referring to FIG. 12, the redistribution layer 220 is formed on a side of the substrate 210, and the redistribution layer 220 can include conductive lines 221 and a dielectric layer 222, so that the conductive lines 221 are in contact with the conductive pillars 212. For example, forming the redistribution layer 220 includes: forming the dielectric layer 222; after the dielectric layer 222 is formed, a line pattern can be formed by a photolithography process or the like, and the conductive lines 221 can be formed by electroplating filling. The above steps can be repeated multiple times to form the redistribution layer 220.

[0101] In this way, the conductive lines 221 in the redistribution layer 220 are in contact with the conductive pillars 212, so that the conductive pillars 212 are connected to the redistribution layer 220.

[0102] In some embodiments, the line width of the conductive lines 221 is less than 8 μm, so as to improve the line density of the conductive lines 221 of the redistribution layer 220.

[0103] In the present embodiment, after the redistribution layer 220 is formed, the method further comprises step S104.

[0104] S104, removing the carrier substrate.

[0105] Referring to FIG. 12 and FIG. 13, the carrier substrate 600 is removed, and at this time, the substrate 210 has a certain rigidity and can be carried and pressed in a grinding process or the like.

[0106] In the present embodiment, after the carrier substrate 600 is removed, the method further comprises step S105.

[0107] S105, forming a connecting part on the other side of the substrate, the connecting part being in contact with the conductive column.

[0108] Please continue to refer to FIG. 13, in some embodiments, including grinding the second end surface 900, trimming the surface flatness of the substrate body 211, while exposing the conductive column 212 to the second end surface 900 of the substrate body 211.

[0109] Please continue to refer to FIG. 13, forming a connecting part 230 on the other side of the substrate 210. For example, by surface mount technology (SMT), at the position of the second end surface 900 of the substrate body 211 exposing the conductive column 212, the conductive column 212 is connected by using solder material, heating to make the solder material melt, and then forming the connecting part 230, wherein the connecting part 230 is in contact with the conductive column 212. Through the above arrangement, the conductive column 212 connects the redistribution layer 220 and the connecting part 230. Wherein, the solder material can include solder paste.

[0110] In some embodiments, the connecting part 230 can also include solder balls, which can also be prepared by a ball planting process to achieve electrical interconnection between the solder balls and the conductive column 212.

[0111] Please refer to FIG. 14, in some embodiments, after forming a plurality of conductive columns 212 on the carrier board 600, and before filling the mold material between the plurality of conductive columns 212, the preparation method of the packaging substrate 200 further includes: arranging an electronic device 240 between two adjacent conductive columns 212, the electronic device 240 being located on the carrier board 600, and the electronic device 240 being provided with a connecting piece 241 on the side away from the connecting part 230.

[0112] As described in the above embodiments, the first end surface 800 of the substrate body 211 is ground to expose the conductive column 212 to the first end surface 800. Further, the first end surface 800 of the substrate body 211 is ground to expose the connecting piece 241 of the electronic device 240 to the first end surface 800.

[0113] In this way, the electronic device 240 can be arranged in the packaging substrate 200, and the connecting piece 241 of the electronic device 240 is exposed to the first end surface 800, so that the electronic device 240 is connected with the conductive wire 221, and the electronic device 240 is connected with the redistribution layer 220 (as shown in FIG. 6).

[0114] Referring to FIG. 15, in some embodiments, before forming the plurality of conductive pillars 212 on the carrier 600, the method for manufacturing the packaging substrate 200 further comprises forming a first layer 2111 on the carrier 600. For example, the first layer 2111 can be formed by a lamination process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a coating process, a spin process, or the like. The material of the first layer 2111 comprises an organic material. The organic material of the first layer 2111 can be as described in the above embodiments, which will not be repeated here.

[0115] After forming the first layer 2111, a portion of the first layer 2111 can be removed to form a via hole 700 penetrating the first layer 2111. For example, the portion of the first layer 2111 can be removed by a laser drilling process, a lithography process, or the like.

[0116] After forming the via hole 700, the conductive pillar 212 can be formed in the via hole 700. The conductive pillar 212 can be formed by the steps as described in the above embodiments, which will not be repeated here. Further, the conductive pillar 212 not only fills in the via hole 700, but also extends from the via hole 700 to a side of the first layer 2111 away from the carrier 600, so that the dimension of the conductive pillar 212 along the first direction Y is greater than the dimension of the first layer 2111 along the first direction Y.

[0117] In some embodiments, after forming the conductive pillar 212 in the via hole 700, an electronic device 240 can be disposed between two adjacent conductive pillars 212. By the above arrangement, the electronic device 240 is located at the side of the first layer 2111 away from the carrier 600.

[0118] As described in the above embodiments, after disposing the electronic device 240, the substrate body 211 can be formed to form the substrate 210. The substrate body 211 can be formed by the steps as described in the above embodiments, which will not be repeated here.

[0119] Referring to FIG. 16, after forming the substrate 210, the redistribution layer 220 can be formed by the steps as described in the above step S103. After forming the redistribution layer 220, the carrier 600 can be removed as described in the above step S104. After removing the carrier 600, the connection portion 230 can be formed as described in the above step S105 to form the packaging substrate 200, which will not be repeated here.

[0120] Referring to FIG. 17, in some embodiments, before forming the plurality of conductive pillars 212 on the carrier substrate 600, the method for manufacturing the packaging substrate 200 further comprises: forming a first layer 2111 on the carrier substrate 600, wherein the material of the first layer 2111 comprises an organic material.

[0121] After forming the first layer 2111, the plurality of conductive pillars 212 are formed. The manufacturing process for forming the plurality of conductive pillars 212 can be as described in the above embodiments, which will not be repeated here.

[0122] In some embodiments, after forming the plurality of conductive pillars 212, the electronic device 240 can be disposed between two adjacent conductive pillars 212. Through the above arrangement, the electronic device 240 is located on the side of the first layer 2111 away from the carrier substrate 600.

[0123] After forming the plurality of conductive pillars 212 and the electronic device 240, the substrate body 211 can be formed. The formation of the substrate body 211 can be as described in the above embodiments, which will not be repeated here.

[0124] Referring to FIG. 18, the redistribution layer 220 can be formed through step S103. After forming the redistribution layer 220, the carrier substrate 600 can be removed through step S104 described above, which will not be repeated here.

[0125] After removing the carrier substrate 600, and before forming the connecting part 230 on the other side of the substrate 210, the method for manufacturing the packaging substrate 200 further comprises: removing part of the first layer 2111 to form a through hole 700 exposing the conductive pillar 212. For example, the removal method can include grinding, chemical etching, physical etching, etc.

[0126] After removing part of the first layer 2111 to form the through hole 700, the connecting part 230 can also be formed on the other side of the substrate 210. As shown in FIG. 18, the connecting part 230 is formed on the second end surface 900 of the substrate 210. Wherein, the step of forming the connecting part 230 can include: forming the connecting part 230 in the through hole 700, so that the conductive pillar 212 is connected with the connecting part 230. At this time, the conductive pillar 212 can penetrate through the second layer 2112 of the substrate body 211, and the conductive pillar 212 connects the redistribution layer 220 with the connecting part 230.

[0127] Referring to FIG. 19, in some embodiments, after step S103, the method further comprises cutting the entire packaging substrate 200. The cutting method can include laser cutting, hybrid cutting, etc., and the embodiments of the present application do not limit the cutting method.

[0128] Exemplarily, after the connection portion 230 is formed at the step S105, the whole packaging substrate 200 is firstly cut by laser, and then cut by a blade. For example, the packaging substrate 200 can be cut to have a width W of about 77.5 mm and a height L of 240 mm (as shown in FIG. 19). The size of the packaging substrate 200 after cutting is not limited in the embodiments of the present application, and the specific size can be determined according to application requirements.

[0129] Through the above setting, the packaging substrate 200 can be cut to a suitable size, so as to facilitate the packaging substrate 200 to be sent to a strip packaging processing production line for packaging operation.

[0130] Exemplarily, the packaging substrate 200 is sent to the strip packaging processing production line for packaging operation, at least one chip 300 is flip-chip bonded with the packaging substrate 200, and at least one chip 300 is wire-bonded with the packaging substrate 200, so that the semiconductor stacked structure 110 can realize hybrid bonding. Through the above preparation method of the packaging substrate 200, the warping of the packaging substrate 200 can be reduced, and the line width of the redistribution layer 220 can be further reduced, so as to further improve the line density of the redistribution layer 220, so that the packaging substrate 200 can realize high-density interconnection after hybrid bonding of the redistribution layer 220 and the chip 300, and is not restricted by the warping problem of the packaging substrate 200.

[0131] The above merely provides specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed by the present application can be easily thought by those skilled in the art, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A package substrate, characterized by, The package substrate comprises: a substrate, the substrate comprising a substrate body and a plurality of conductive pillars, the conductive pillars penetrating through at least part of the substrate body along a first direction, a distance between any two adjacent conductive pillars being less than 15 mm; a connecting portion, at least part of the connecting portion being located on one side of the substrate along the first direction, and the connecting portion being in contact with the conductive pillars; a re-distribution layer, the re-distribution layer being located on the other side of the substrate along the first direction, and the re-distribution layer being in contact with the conductive pillars.

2. The package substrate of claim 1, wherein The re-distribution layer comprises conductive lines and a dielectric layer, the conductive lines being in contact with the conductive pillars, and the dielectric layer having a thermal expansion coefficient that is the same as or similar to that of the substrate body.

3. The package substrate of claim 2, wherein, The substrate body comprises a first layer and a second layer that are stacked, and the second layer is located between the first layer and the re-distribution layer; the first layer and the second layer have similar thermal expansion coefficients.

4. The package substrate of claim 3, wherein, The conductive pillars penetrate through the second layer, and the connecting portion penetrates through the first layer to be in contact with the conductive pillars; or the conductive pillars penetrate through the second layer and the first layer.

5. The package substrate according to claim 3 or 4, wherein The material of the first layer comprises an organic material; and / or the material of the second layer comprises a molding material.

6. The package substrate of any one of claims 1-5, wherein, The package substrate further comprises an electronic device, the electronic device being located between two adjacent conductive pillars, and a connecting member being provided on the side of the electronic device that is away from the connecting portion, and the electronic device is connected to the conductive lines through the connecting member.

7. A semiconductor stack structure, characterized by, The semiconductor stack structure comprises a chip and the package substrate according to any one of claims 1-6, the chip and the package substrate are stacked, and the chip is connected to the re-distribution layer of the package substrate.

8. The semiconductor stack structure of claim 7, wherein, The number of the chips is plural.

9. An electronic device, comprising: The semiconductor stack structure comprises a circuit board and the semiconductor stack structure according to claim 7 or 8, the semiconductor stack structure and the circuit board are stacked, and the circuit board is connected to the connecting portion of the semiconductor stack structure.

10. A method for manufacturing a package substrate, comprising: providing a carrier board; forming a substrate on the carrier board, the substrate comprising a substrate body and a plurality of conductive pillars, the conductive pillars penetrating through the substrate body along a first direction, a distance between any two adjacent conductive pillars being less than 15 mm; forming a re-distribution layer on one side of the substrate, the re-distribution layer being in contact with the conductive pillars; removing the carrier board; forming a connecting portion on the other side of the substrate, the connecting portion being in contact with the conductive pillars.

11. The method of manufacturing a package substrate according to claim 10, wherein The forming of the substrate on the carrier board comprises: forming a plurality of the conductive pillars on the carrier board; filling a molding material between the plurality of the conductive pillars to form a substrate body.

12. The method of manufacturing a package substrate according to claim 11, wherein Before the forming of the plurality of the conductive pillars on the carrier board, the method further comprises: forming a first layer on the carrier board, the material of the first layer comprising an organic material; removing part of the first layer to form a through hole penetrating through the first layer; the forming of the plurality of the conductive pillars on the carrier board comprises forming the conductive pillars in the through hole.

13. The method of manufacturing a package substrate according to claim 11, wherein Before the forming of the plurality of the conductive pillars on the carrier board, the method further comprises: forming a first layer on the carrier board, the material of the first layer comprising an organic material; After removing the carrier plate, and before forming the connecting portion on the other side of the substrate, the method for preparing the packaging substrate further comprises: removing part of the first layer to form a through hole exposing the conductive column; The forming the connecting portion on the other side of the substrate comprises: forming the connecting portion in the through hole.

14. The method of manufacturing a package substrate according to claim 12 or 13, wherein After forming the plurality of conductive columns on the carrier plate, and before filling the molding material between the plurality of conductive columns, the method for preparing the packaging substrate further comprises: An electronic device is arranged between two adjacent conductive columns, and a connecting member of the electronic device is arranged on the side away from the connecting portion; After filling the molding material between the plurality of conductive columns, the method for preparing the packaging substrate further comprises: Grinding the first end surface of the substrate body to expose the connecting member of the electronic device to the first end surface, the first end surface being on the side of the substrate body away from the carrier plate.

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