Photon-counting detector

Abstract

The present description relates to a photon-counting detector comprising a plurality of electrodes each connected to a readout circuit (RDc). Each readout circuit (RDc) generates an active detection signal (evt) when charges are collected by the electrode to which this circuit is connected. Each readout circuit, referred to as the central circuit (RDc), carries out charge sharing correction by exchanging signals with readout circuits, referred to as circuits adjacent to the central circuit (RDc), connected to electrodes adjacent to the electrode to which the central circuit is connected, referred to as the central electrode. Each central circuit (RDc) selectively activates and deactivates (CSC-EN; EN) the charge sharing correction that it carries out on the basis of at least the detection signal (evt) that it generates.

Description

DESCRIPTION Photon counting detector

[0001] This application is based on, and claims priority from, French patent application FR 2410037 filed on September 20, 2024 and entitled "Photon Counting Detector", which is considered to form an integral part of this description within the limits provided by law. technical field

[0002] This description relates generally to electronic circuits, and, more specifically, to photon counting detectors (PDCs), also called, more generally, particle counting detectors. Previous technique

[0003] Many electronic systems include a photon-counting detector. This is the case, for example, with photon-counting spectral scanners, used for medical imaging. In a photon-counting spectral scanner, the detected particles are, for example, photons of X-ray radiation, that is, radiation in the wavelength range from, for example, approximately 0.01 nm to approximately 10 nm.

[0004] Figure 1 illustrates, by means of a schematic, cross-sectional and partial view, an example of a photon counting detector 1.

[0005] Detector 1 includes a layer 100 for photoconversion of photons (or particles) to be detected into charges. Layer 100 is configured so that a photon to be detected, received by layer 100, is converted into charges by layer 100, the number of charges resulting from a photon being, by For example, determined by the photon's energy. Layer 100 is generally made of a semiconductor material. For instance, to detect photons from X-rays, layer 100 contains cadmium telluride. As an illustration, in Figure 1, a photon incident on layer 100 is schematically represented by an arrow 101, and the sum of the charges generated in layer 100 by this photon 101 is schematically represented by a disk 103.

[0006] The charges are collected by electrodes 102 covering layer 100. For example, each electrode belongs to a pixel of the photon-counting detector, each pixel comprising, for example, a single electrode 102. For example, the electrodes 102 cover one of the two principal faces of layer 100, for example, the principal face of layer 100 opposite the principal face receiving the incident photons to be detected. In the example in Figure 1, the electrodes cover the lower face of layer 100.

[0007] Each electrode 102 is connected to a corresponding readout circuit RD of detector 1. For example, each RD circuit belongs to a pixel of the photon-counting detector, each pixel comprising one RD circuit. Each RD circuit receives a signal lmp representing the time evolution of the amount of charge collected by the electrode 102 to which it is connected. For example, each lmp signal is a current with a pulse each time charges resulting from a photon incident on layer 100 are collected by the electrode 102 providing that lmp signal.

[0008] Typically, each readout circuit RD is configured to provide, from the received lmp signal, an OUT signal including an indication that charges have been collected by electrode 102 connected to that RD circuit, and, in In addition, it provides information representative of the amount of charge collected. For example, this OUT signal indicates each time that a pulse of the lmp signal is received by the RD circuit, and a range of values ​​in which the maximum level of this pulse lies, this maximum level being representative of the amount of charge collected by electrode 102 during the lmp pulse, therefore of the photon energy.

[0009] Typically, the output signals OUT of the RD circuits of the pixels of detector 1 are supplied to a PROCESS processing circuit. This PROCESS circuit is configured, based on the number of photons detected by each pixel of detector 1 and their energy levels, to determine properties of an object or living being traversed by ionizing radiation before this radiation reaches detector 1. For example, the PROCESS circuit is configured to generate an image of the object or living being placed in the path of the radiation, for example, an image of the different materials or tissues that respectively compose this object or living being.

[0010] However, as schematically illustrated in Figure 1 by two arrows 104, in some cases, the charges 103 generated by a photon can be collected by two neighboring or adjacent electrodes 102. This phenomenon is called charge sharing. Each RD circuit connected to one of these two electrodes 102 then indicates, via its OUT signal, that its electrode 102 has collected charges, that is, that this RD circuit has detected a photon. Furthermore, each RD circuit connected to one of these two electrodes also provides, via its OUT signal, an indication of the amount of charge collected by its electrode, that is, an indication of the energy level of the detected photon.

[0011] To take into account charge sharing phenomena in a photon counting detector, a known solution is to implement signal exchanges between RD readout circuits connected to adjacent electrodes 102, and, in addition, to implement charge sharing correction in these RD circuits.

[0012] Charge-sharing correction, based on the signals exchanged between RD circuits connected to adjacent electrodes, detects when at least two adjacent electrodes 102 collect charges simultaneously. When adjacent electrodes 102 collect charges simultaneously, the RD readout circuits connected to these electrodes decide that all the collected charges originate from the same photon. Furthermore, based on the exchanged signals, these RD readout circuits also determine to which of these electrodes 102, and therefore to which of the circuits connected to these electrodes 102, the entire set of collected charges should be attributed. In other words, based on the signals they exchange, the RD circuits determine to which pixel affected by charge sharing the entire set of collected charges should be attributed.

[0013] Numerous readout circuits are known to implement charge-sharing correction. Such circuits are described, for example, in EP 2936208 (or US 9329283), in the article "The Medipix3RX: a high resolution, zero dead-time pixel detector readout chip allowing spectroscopic imaging" by R Ballabriga, J Alozy, G Blaj, M Campbell, M Fiederle, E Frojdh, EHM Heijne, X Llopart, M Pichotka, and S Procz, published in the Journal of Instrumentation, Volume 8, in February 2013, and also in the article "Multi-energy inter-pixel coincidence counters for charge sharing correction and compensation in photon counting detectors" by Taguchi K., published in "Med Phys." in June 2020.

[0014] Figure 2 schematically represents, in part and in block form, a photon counting detector 2 in which the readout circuits RD connected to adjacent electrodes 102 of detector 2 exchange signals with each other and implement, on the basis of the exchanged signals, a charge sharing correction.

[0015] Detector 2 includes many elements in common with detector 1, and only the differences between these two detectors are detailed here.

[0016] Figure 2 shows a top view of electrodes 102 of detector 2, with layer 100 not shown. Typically, electrodes are arranged in a matrix of rows and columns of electrodes 102. Figure 2 illustrates a matrix of nine electrodes 102 arranged in three rows and three columns. In practice, the number of rows and columns is greater, and the matrix shown in Figure 2 represents, for example, only a portion of a detector 2 electrode 102 matrix.

[0017] In Figure 2, a central electrode 102 is surrounded by eight electrodes 102 adjacent to the central electrode 102, these eight electrodes being respectively located to the north, south, east, west, northeast, northwest, southeast and southwest of the central electrode 102.

[0018] In Figure 2, the central electrode is labeled 102c, and the adjacent electrodes located to the north, south, east, west, northeast, northwest, southeast, and southwest of the central electrode 102c are respectively labeled 102n, 102s, 102e, 102w, 102ne, 102nw, 102se, and

[0019] The central electrode 102c is connected to a circuit RD called the central circuit, and each of the electrodes adjacent to the central electrode 102c is connected to a circuit RD, the circuits RD connected to the adjacent electrodes being called adjacent circuits. In Figure 2, the circuits RD connected to the respective electrodes 102c, 102n, 102s, 102e, 102w, 102ne, 102nw, 102se and 102sw are referenced respectively as RDc, RDn, RDs, RDe, RDw, RDne, RDnw, RDse and RDsw.

[0020] Although, in the example in Figure 2, the RD circuits are arranged relative to each other in the same way as the electrodes 102 to which these RD circuits are connected, this is not necessarily the case in practice.

[0021] In detector 2, each electrode 102 can be seen as a central electrode 102c surrounded (or bordered) by one or more adjacent electrodes 102, and what will be described for the example in Figure 2 can be generalized to the other electrodes 102 of detector 2. By extension, in detector 2, each circuit RD can be seen as a central circuit RDc exchanging signals with one or more adjacent circuits RD connected respectively to one or more electrodes 102 adjacent to the central electrode 102c to which the central circuit RDc is connected, and what will be described for the example in Figure 2 can be generalized to the other circuits RD of detector 2.

[0022] In the example in Figure 2, the central circuit RDc is configured to exchange signals with the adjacent circuits RDn, RDe, RDw, and RDs connected to the respective adjacent electrodes 102n, 102e, 102w, and 102s. Optionally, the central circuit RDc is further configured to exchange signals with the adjacent circuits RDse, RDsw, RDne, and RDnw connected to the respective adjacent electrodes 102se, 102sw, 102ne, and 102n, as in the example in Figure 2. In Figure 2, the signals exchanged between the central circuit and each of the adjacent circuits are represented by a double arrow 200.

[0023] Preferably, the RD circuits are identical. To this end, when the central electrode 102c is an electrode located at the edge of the matrix and there is therefore no adjacent electrode on one side of the central electrode 102, the signals 200 that the central circuit RDc would have received from one or more adjacent RD circuits connected to one or more absent adjacent electrodes are, for example, replaced by inactive or corrupted signals. For example, when a central electrode 102c has no adjacent electrode 102e, the signals that the central circuit RDc would have received from the adjacent circuit RDe are, for example, replaced by inactive or corrupted signals.

[0024] The RDc circuit is configured to implement load sharing correction from the 200 signals it exchanges with adjacent RD circuits.

[0025] Known photon counting detectors in which charge sharing correction is implemented directly at the level of the readout circuits connected to the electrodes of these detectors have various disadvantages. Summary of the invention

[0026] There is a need to overcome all or part of the drawbacks of known photon counting detectors as described above.

[0027] One embodiment overcomes all or part of the disadvantages of known photon counting detectors as described above.

[0028] One embodiment provides a photon counting detector comprising a photon-to-charge conversion layer covered with several electrodes, each connected to a readout circuit, in which: Each reading circuit is configured to generate an active detection signal when charges are collected by the electrode to which the reading circuit is connected; each reading circuit, called the central circuit, is configured to implement charge sharing correction by exchanging signals with reading circuits, called adjunct circuits of the central circuit, connected to electrodes adjunct to the electrode to which the central circuit is connected, called the central electrode; and each central circuit is configured to selectively activate and deactivate the charge sharing correction in said central circuit on the basis at least of the detection signal generated by said central circuit.

[0029] According to one embodiment: each central circuit is adapted to send the detection signal that it generates to each of the adjunct circuits of the central circuit, each of the adjunct circuits of said central circuit being adapted to send the detection signal that it generates to said central circuit.

[0030] According to one embodiment, each central circuit is configured to disable load sharing correction in said central circuit if an average number of active states of the detection signal generated by the central circuit is greater than a threshold.

[0031] According to one embodiment, each central circuit is configured to disable load sharing correction in said central circuit if an average number of active states of the detection signal generated by the central circuit and of the detection signals that the central circuit receives from adjunct circuits of the central circuit is greater than a threshold.

[0032] According to one embodiment, each central circuit is configured to disable load sharing correction in said central circuit for a duration of time delay after the end of each active state of the detection signal generated by the central circuit.

[0033] According to one embodiment, each central circuit is configured to disable load sharing correction in said central circuit if a number of active states of the detection signals that the central circuit receives from adjunct circuits of the central circuit during an active state of the detection signal generated by the central circuit is greater than a threshold.

[0034] According to one embodiment, each central circuit is configured to disable charge sharing correction in said central circuit if the central circuit and the adjunct circuit(s) of the central circuit which send active detection signals during an active state of the detection signal generated by the central circuit are connected to electrodes arranged relative to each other in a pattern corresponding to an abnormal charge sharing.

[0035] According to one embodiment, each central circuit includes a charge sharing detection circuit configured to detect that the central electrode and one or more of the electrodes adjoining the central electrode are involved in charge sharing, from the detection signal generated in the central circuit and respectively from the detection signal(s) sent to the central circuit by respectively the adjoining circuit(s) connected respectively to said one or more adjoining electrodes.

[0036] According to one embodiment: each reading circuit is configured to generate a first signal representing a quantity of charge collected by the electrode to which the reading circuit is connected; and each central circuit is adapted to send the first signal that it generates at each of the said adj acent circuits of the central circuit, each of the said adj acent circuits of the said central circuit being adapted to send the first signal that it generates to the said central circuit.

[0037] According to one embodiment, the charge sharing detection circuit of each central circuit is configured, when it detects that the central electrode and one or more of the adj electrodes are involved in charge sharing, to determine to which of the electrodes involved in charge sharing is assigned a sum of the charges collected by the electrodes involved in charge sharing.

[0038] According to one embodiment, the charge sharing detection circuit is configured to determine to which of the electrodes involved in the charge sharing is assigned the sum of the charges collected by the electrodes involved in the charge sharing from: the detection signal generated by the central circuit and the detection signal(s) sent to the central circuit by the adj acent circuit(s) connected respectively to said one or more adj acent electrodes involved in the charge sharing, or the first signal generated by the central circuit and the first signal(s) sent to the central circuit by the adj acent circuit(s) connected respectively to said one or more adj acent electrodes involved in the charge sharing.

[0039] According to one embodiment, each central circuit is configured: when the charge sharing correction is active in the central circuit, to provide an output signal representative of the sum of the charges collected by the central electrode and said one or more electrodes adjacent involved in charge sharing if this sum of charges is attributed to the central electrode, and a zero amount of charge otherwise; and when charge sharing correction is inactive in the central circuit, to provide an output signal representative of the charges collected by the central electrode only.

[0040] According to one embodiment, the reading circuits are identical. Brief description of the drawings

[0041] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the attached figures, among which:

[0042] Figure 1, described previously, represents an example of a photon counting detector;

[0043] Figure 2, described previously, represents an example of a photon counting detector in which a charge sharing correction is implemented;

[0044] Figure 3 schematically represents, in block form, an example of a photon counting detector in which a charge sharing correction is implemented;

[0045] Figure 4 schematically represents an example of a detector circuit from Figure 3;

[0046] Figure 5 schematically represents another example of a detector circuit from Figure 3; and

[0047] Figure 6 schematically represents, in block form, an embodiment of a photon counting detector in which a charge sharing correction is implemented;

[0048] Figure 7 represents, schematically and in block form, another embodiment of a detector circuit from Figure 6;

[0049] Figure 8 represents, schematically and in block form, another embodiment of a detector circuit from Figure 5;

[0050] Figure 9 represents an example of the implementation of a control circuit that is part of the circuits described in relation to Figures 6, 7 and 8;

[0051] Figure 10 shows timing diagrams illustrating the operation of the circuit in Figure 9;

[0052] Figure 11 represents another example of the implementation of a control circuit that is part of the circuits described in relation to Figures 6, 7 and 8;

[0053] Figure 12 shows timing diagrams illustrating the operation of the circuit in Figure 11. Description of the implementation methods

[0054] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0055] For the sake of clarity, only the steps and elements useful for understanding the implementation methods described have been represented and are detailed.

[0056] Unless otherwise specified, when referring to two connected elements, this means directly connected without any intermediate elements other than conductors, and when referring to two coupled elements, this means that These two elements can be connected or linked via one or more other elements.

[0057] In the description that follows, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientational qualifiers, such as the terms "horizontal", "vertical", etc., unless otherwise specified, it refers to the orientation of the figures.

[0058] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "on the order of" mean within 10% or 10°, preferably within 5% or 5°.

[0059] Figure 3 shows, in more detail, an example of the RD circuits of detector 2 in Figure 2.

[0060] In the example in Figure 3, a central circuit RDc connected to a central electrode 102c (not shown in Figure 3) only exchanges signals 200 with the adjacent circuits RDs, RDn, RDw and RDe connected to the respective adjacent electrodes 102s, 102n, 102w and 102e. In other words, in Figure 3, for a given central electrode 102c, the charge sharing correction is only implemented between this electrode 102c and its adjacent electrodes 102n, 102e, 102s and 102s.

[0061] A person skilled in the art will be able to adapt what is described in relation to the example in Figure 3 to the case of a central circuit RDc exchanging signals with adjacent circuits RDc, RDn, RDs, RDe, RDw, RDne, RDnw, RDse, and RDsw. In other words, a person skilled in the art will be able to adapt what is described in relation to the example in Figure 3 to a case where, for an electrode given central 102c, the charge sharing correction is implemented between this electrode 102c and its adjacent electrodes 102n, 102e, 102s, 102w, 102ne, 102nw, 102se and 102sw.

[0062] In the example in Figure 3, each RD circuit is configured to generate a signal evt indicating when the electrode 102 to which that RD circuit is connected is collecting charge. For example, in each RD circuit, the evt signal is active when the electrode 102 connected to that RD circuit is collecting charge, or, in other words, when the RD circuit receives an lmp pulse from that electrode 102. For example, the evt signal is a binary signal with two states. As an example, each RD circuit includes a circuit 300 configured to generate the evt signal from the lmp signal received by the RD circuit. For example, the circuit 300 is configured to provide the evt signal in the active state when the lmp signal is above a threshold, and in the inactive state otherwise.

[0063] When two RD circuits exchange signals 200 to implement a load sharing correction, each of these two RD circuits is adapted to send the evt signal it generates to the other circuit, as illustrated in Figure 3 by dashed lines in the RD circuits and solid arrows 200 between the RD circuits.

[0064] As an example, in Figure 3, the RDc circuit transmits its signal evt directly to each of the adjacent circuits RDn, RDe, RDs, and RDw, and each of the adjacent circuits RDn, RDe, RDs, and RDw transmits its signal evt directly to the central circuit RDc. Therefore, the signals 200 transmitted from the RDc circuit to the adjacent circuits RDn, RDe, RDs, and RDw contain the signal evt generated by the RDc circuit, labeled evtc in Figure 3, and the signals 200 transmitted from the adjacent circuits RDn, RDe, RDs, and RDw to the central circuit contain the signal evt generated by the RDc circuit. RDc, we therefore find the evt signals generated by the circuits RDn, RDe, RDs and RDw, referenced respectively evtn, evte, evts and evtw in figure 3.

[0065] Furthermore, although not illustrated in detail in Figure 3, each RD circuit is configured to generate a signal, for example, an internal RD circuit signal, representative of the amount of charge received by the electrode 102 to which that RD circuit is connected. For example, each RD circuit is configured, at each pulse of the lmp signal it receives, to generate a signal (not shown in Figure 3) indicating a range of values ​​within which the maximum value reached by the pulse lies.

[0066] When two RD circuits exchange signals 200 to implement a charge sharing correction, each of these two RD circuits is then adapted to send to the other of these two RD circuits the signal representative of the amount of charge received by the electrode 102 connected to this RD circuit, as illustrated in figure 3 by solid arrows 200 between the RD circuits.

[0067] As an example, in Figure 3, the RDc circuit transmits a valc signal, representing the charges collected by its electrode 102c, to each of the adjacent circuits RDn, RDe, RDs, and RDw. For instance, the RDc circuit is configured to generate a first signal (not shown in Figure 3) representing the charges collected by its electrode 102c, and is further adapted to transmit this first signal, then referenced as valc, to its adjacent circuits RDn, RDe, RDs, and RDw. In other words, the RDc circuit includes a first signal representing the charges collected by its electrode 102c, and is adapted to transmit this first signal, in the form of the valc signal, to its adjacent circuits RDn, RDe, RDs, and RDw. This first signal can be analog or digital.

[0068] As an example, conversely, the adjacent circuits RDn, RDe, RDs, and RDw transmit to the circuit RDc respective signals vain, vale, vais, and valw, representing the charges collected by the respective electrodes 102n, 102e, 102n, and 102w connected to the respective circuits RDn, RDe, RDs, and RDw. For example, each of the adjacent circuits RDn, RDe, RDs, and RDw is configured to generate a first signal (not shown in Figure 3) representative of the charges collected by the electrode 102n, 102e, 102n, 102w to which that adjacent circuit is connected, and is further adapted to transmit this first signal, then referenced respectively vain, vale, vais, and valw, to the central circuit RDc. Put another way, each adjacent circuit RDn, RDe, RDs, RDw includes a first signal representative of the charges collected by its electrode, and is adapted to transmit this first signal in the form of the respective signal vain, vale, vais, valw to the central circuit RDc.

[0069] Based on the evt signal it generates and the evtn, evte, evts and evtw signals it receives from the adjacent circuits RDn, RDe, RDs and RDw, the RDc circuit is configured to detect when a charge sharing occurs between the central electrode 102c and at least one of the adjacent electrodes 102n, 102e, 102s and 102w. For example, the RDc circuit includes a charge sharing detection circuit (not shown in Figure 3) configured to detect that the center electrode 102c and one or more adjacent electrodes 102n, 102e, 102s and 102w are involved in charge sharing, from the signal evt generated in the RDc circuit and the signals evtn, evte, evts and evtw that the RDc circuit receives from its adjacent circuits RDn, RDe, RDs and RDw.

[0070] When the central circuit RDc and one or more of its adjacent circuits RDn, RDe, RDs and RDw are involved In a charge-sharing system, these reading circuits are each configured to determine to which of the electrodes 102c, 102n, 102e, 102s, 102w connected to these circuits RDc, RDn, RDe, RDs, RDw the sum of the collected charges, or, in other words, the sum of the received energies, should be allocated. This allocation of the sum of the collected charges is, for example, implemented by the charge-sharing detection circuits of the RD circuits involved in the charge sharing.

[0071] For example, when the central circuit RDc and one or more of the adjacent circuits RDn, RDe, RDs and RDw are involved in a charge sharing, the central circuit RDc is configured to determine to which of the electrodes involved in the charge sharing is assigned the sum of the charges collected by these electrodes, based on the signal evt of the circuit RDc and the signals evt, evtn, evte, evts and evtw, for example based on the order of arrival of the active states of these signals evt, evtn, evte, evts and evtw, for example by assigning this sum to the electrode corresponding to the signal evt, evtn, evte, evts or evtw that switched to the active state first during the charge sharing.

[0072] As an alternative example, when the central circuit RDc and one or more of the adjacent circuits RDn, RDe, RDs and RDw are involved in charge sharing, the central circuit RDc is configured to determine to which of the electrodes involved in the charge sharing is assigned the sum of the charges collected by these electrodes, based on the signal representative of the charges collected by the electrode 102c that this circuit RDc generates, and the vain, vale, vais and valw signals that it receives from its adjacent circuits, for example by assigning this sum to the electrode corresponding to the highest amplitude lmp pulse.

[0073] When the RDc circuit detects a charge sharing event in which it is involved, if the RDc circuit determines that the sum of the charges collected during the charge sharing is allocated to it, the RDc circuit provides an output signal OUT (not shown in Figure 3) representing this sum. Conversely, if the RDc circuit determines that the sum of the charges collected during the charge sharing is not allocated to it, the RDc circuit provides an output signal representing zero charge.

[0074] Figure 4 schematically represents an example of the implementation of the RDc circuit of Figure 3. In this example, when the RDc circuit is involved in load sharing and the sum of the charges collected during the load sharing is allocated to the RDc circuit, the RDc circuit is configured to calculate the sum of the collected charges numerically.

[0075] The RDc circuit receives the lmp signal from electrode 102c (not shown in Figure 4). This lmp signal, for example a current, can be shaped, for example amplified, by a FE circuit within the RDc circuit. The FE circuit receives the lmp signal and provides the shaped signal Impfe.

[0076] The Impfe signal is supplied to a NUM circuit within the RDc circuit. The NUM circuit generates the evt signal of the RDc circuit from the Impfe signal it receives. For example, the NUM circuit provides the active evt signal as soon as the analog Impfe signal exceeds a threshold, and inactive otherwise. In this example, the NUM circuit corresponds to circuit 300 of the RDc circuit in Figure 3.

[0077] The NUM circuit is further configured to provide a digital sign signal from the Impfe signal. The sign signal is therefore a signal generated by the RDc circuit and is representative of the amount of charge received by the electrode. 102c. The sign signal corresponds to the first signal of the RDc circuit described in relation to figure 3.

[0078] For example, the NUM circuit is a digital discriminator configured to compare the Impfe signal it receives to several thresholds, and to provide a digital sign indicating, for each of these thresholds, whether the Impfe signal is above or below the threshold. The evt signal is, for example, derived from the sign signal, and indicates, for example, whether the Impfe signal is greater than or less than the lowest threshold of the NUM circuit.

[0079] In the example in Figure 4, the RDc circuit includes the FE circuit, and the NUM circuit therefore receives the Impfe signal. In other examples, the RDc circuit does not include an FE circuit, and the NUM circuit directly receives the lmp signal.

[0080] The sign and evt signals are provided to a load sharing detection circuit 400 of the RD circuit.

[0081] Circuit 400 is configured to transmit the evtc signal to the adjacent circuits RDn, RDe, RDs, and RDw of circuit RDc, and to receive the evtn, evte, evts, and evtw signals from the circuits adjacent to RDc. In the example in Figure 4, the evtc signal is active if the evt signal is active, and inactive otherwise. As an example, circuit 400 includes a PROC circuit configured to receive the evt, evtn, evte, evts, and evtw signals and to provide the evtc signal.

[0082] From the evt signal and the evtn, evte, evts, and evtw signals, the 400 circuit is configured to detect whether the RDc circuit is involved in load sharing with its adjacent circuits RDn, RDe, RDs, and RDw and, furthermore, when so, which of these adjacent circuits is also involved in this load sharing. In the example in Figure 4, these functions are implemented. by the PROC circuit. For example, the PROC circuit provides a sel signal indicating which adjacent circuit(s) is / are involved in load sharing.

[0083] The 400 circuit is further configured to transmit the valc signal to the adjacent circuits RDn, RDe, RDs, and RDw of the RDc circuit, and to receive the vain, vale, vais, and valw signals from the circuits adjacent to the RDc circuit. In the example in Figure 4, these vale, vain, vale, vais, and valw signals are digital signals. In the example in Figure 4, the valc signal corresponds to, for example, the digital sign signal generated by the RDc circuit and representative of the amount of charge collected by electrode 102c. As an example, the 400 circuit includes a SUM circuit configured to receive the sign, vain, vale, vais, and valw signals and to provide the valc signal from the sign signal.

[0084] The 400 circuit is configured, when a load sharing involving the RDc circuit is detected and the adjacent RDn, RDe, RDs, and RDw circuits involved in this load sharing have been determined (identified), to determine whether the sum of the charges collected during the load sharing should be allocated to the RDc circuit. In the example in Figure 4, this functionality of the 400 circuit is implemented based on the evt, evtn, evte, evts, and evtw signals by the PROC circuit, which provides an active win signal if the sum of the collected charges is allocated to the RDc circuit, and an inactive signal otherwise. As an alternative example not shown, this functionality can be implemented based on the sign, vain, vale, vais, and valw signals, for example, by the SUM circuit.

[0085] When the sum of the collected charges is allocated to the RDc circuit, the 400 circuit is configured to provide, from the sign, vain, vale, vais, and valw signals, an OUT signal representing this sum, and, conversely, when the The sum of the collected charges is assigned to one of the adjacent circuits RDn, RDe, RDs, and RDw of circuit RDc. Circuit 400 is configured to provide an OUT signal representing zero collected charges. If no charge sharing is detected, circuit 400 is configured to provide an OUT signal representing only the amount of charge received by electrode 102c, for example, from the sign signal. As an example, in Figure 4, this functionality is implemented by the SUM circuit, for example, based on the sel, win, sign, vain, vale, vais, and valw signals.

[0086] Figure 5 schematically represents another example of the implementation of the RDc circuit of Figure 3. In this example, when the RDc circuit is involved in load sharing and the sum of the charges collected during the load sharing is allocated to the RDc circuit, the RDc circuit is configured to calculate the sum of the collected charges in an analog manner.

[0087] The RDc circuit in Figure 5 includes elements in common with the RDc circuit in Figure 4, and only the differences between these two circuits are highlighted here.

[0088] The RDc circuit receives the lmp signal from electrode 102c (not shown in Figure 4). The FE circuit receives the lmp signal and provides the shaped signal Impfe.

[0089] The Impfe signal is supplied to a load-sharing detection circuit 500 of the RDc circuit. In the example in Figure 5, the RDc circuit includes the FE circuit, and therefore the 500 circuit receives the Impfe signal. In other examples, the RDc circuit does not include an FE circuit, and the 500 circuit receives the lmp signal directly.

[0090] Circuit 500 provides the valc signal from the Impfe signal. The Impfe signal (lmp if the FE circuit is omitted) is therefore a signal generated by the RDc circuit and is representative of the amount of charge received by electrode 102c. The signal Impfe (lmp if the FE circuit is omitted) corresponds to the first signal of the RDc circuit described in relation to Figure 3. In the example, the valc signal is identical to the analog signal Impfe.

[0091] The 500 circuit receives the signals vain, vale, vais and valw. In the example in Figure 5, the signals vale, vale, vain, vais and valw are analog signals.

[0092] From the Impfe signal, circuit 500 provides an analog signal sum representing the amount of charge collected by the central electrode 102c to circuit NUM. More specifically, when no charge sharing is detected, the sum signal is identical to the Impfe signal, and, when charge sharing is detected by circuit 500 and the adjacent circuit(s) RDn, RDe, RDs and RDw involved in the charge sharing have been identified by circuit 500, the sum signal represents the sum of the charges collected during the charge sharing and is, for example, equal to the sum of the Impfe signal from circuit RDc and the vain, vale, vais and valw signals from the adjacent circuits involved in the charge sharing.

[0093] As an example, the transmission of the valc signal to adjacent circuits and the provision of the sum signal is implemented by a SUMa circuit of the 500 circuit. As an example, the SUMa circuit receives the signals Impfe, vain, vale, vais and valw, and a sel signal indicating the adjacent circuit(s) involved in the load sharing when a load sharing is detected, the SUMa circuit providing the sum signal to the NUM circuit.

[0094] The NUM circuit generates the detection signal evt for the RDc circuit from the sum signal it receives. For example, the NUM circuit provides the active evt signal as soon as the signal The analog sum is greater than a threshold, and inactive otherwise. In other words, the NUM circuit corresponds, in this example, to circuit 300 of the RDc circuit in Figure 3.

[0095] The NUM circuit is further configured to provide a digital sign signal from the sum signal.

[0096] For example, the NUM circuit is a digital discriminator configured to compare the sum signal it receives to several thresholds, and to provide a digital sign indicating, for each of these thresholds, whether the sum signal is above or below the threshold. The evt signal, for example, is derived from the val signal, and indicates, for example, whether the val signal is greater than or less than the lowest threshold of the NUM circuit.

[0097] The val and evt signals are provided to the load sharing detection circuit 500 of the RD circuit.

[0098] Circuit 500 is configured to transmit the evtc signal to the adjacent circuits RDn, RDe, RDs, and RDw of circuit RDc, and to receive the evtn, evte, evts, and evtw signals from the circuits adjacent to RDc. In the example in Figure 5, the evtc signal is active if the evt signal is active, and inactive otherwise. As an example, circuit 500 includes a PROC circuit configured to receive the evt, evtn, evte, evts, and evtw signals and to provide the evtc signal.

[0099] From the evt signal and the evtn, evte, evts, and evtw signals, the 500 circuit is configured to detect whether the RDc circuit is involved in load sharing with its adjacent circuits RDn, RDe, RDs, and RDw and, furthermore, when so, which of these adjacent circuits are also involved in this load sharing. In the example in Figure 5, these functions are implemented by the PROC circuit. For example, the PROC circuit provides the signal sel indicating which adjacent circuit(s) are involved in load sharing.

[0100] The 500 circuit is configured, when a load sharing involving the RDc circuit is detected and the adjacent RDn, RDe, RDs, and RDw circuits involved in this load sharing have been determined, to determine whether the sum of the charges collected during the load sharing should be allocated to the RDc circuit. In the example in Figure 5, this functionality of the 500 circuit is implemented based on the evt, evtn, evte, evts, and evtw signals by the PROC circuit, which provides an active win signal if the sum of the collected charges is allocated to the RDc circuit, and an inactive signal otherwise. As an alternative example not shown, this functionality can be implemented based on the Impfe, vain, vale, vais, and valw signals, for example, by the SUMa circuit.

[0101] When the sum of collected charges is allocated to circuit RDc, circuit 500 is configured to provide, from the signals Impfe, win, vale, vais, and valw, an OUT signal representing this sum. Conversely, when the sum of collected charges is allocated to one of the adjacent circuits RDn, RDe, RDs, and RDw of circuit RDc, circuit 500 is configured to provide an OUT signal representing zero collected charges. If no charge sharing is detected, circuit 500 is configured to provide an OUT signal representing only the amount of charge received by electrode 102c, for example, from the Impfe signal. As an example, in Figure 5, this functionality is implemented by circuit SUMn, for example, based on the win and sign signals.

[0102] As an example, the operation of the RDc circuit in Figure 5 is as follows. The 500 circuit, for example its SUMa circuit, receives a pulse from the analog signal Impfe, and transmits it to the NUM circuit as a corresponding pulse of the sum signal. For example, when the SUMa circuit receives a pulse of the analog signal Impfe, this analog pulse is initially present in the sum signal, before the charge-sharing correction function is implemented. The NUM circuit then generates the active evt signal and the corresponding sign signal. In the first case, based on the evt, evtn, evts, evte, and evtw signals, the 500 circuit, for example its PROC circuit, determines that the RDc circuit is not involved in charge sharing (inactive win signal). The 500 circuit, for example its SUMn circuit, then provides the OUT signal representing the amount of charge collected by electrode 102c only, based on the sign signal.In a second case, based on the signals evt, evtn, evts, evte, and evtw, the 500 series circuit, for example its PROC circuit, determines that the RDc circuit is involved in load sharing and identifies the adjacent circuit(s) also involved using the sel signal. The 500 series circuit, for example its SUMa circuit, then updates the sum signal accordingly, which in turn updates the sign signal. For example, in a second step where load sharing correction is implemented, the sum signal then corresponds to the analog sum of the Impfe signal and the vain, vale, vais, and valw signals of the adjacent circuits involved. If the sum of the collected charges is assigned to the RDc circuit (win signal active), the 500 series circuit, for example its SUMn circuit, provides the OUT signal from the sign signal so that the OUT signal represents the sum of the collected charges.Conversely, if the sum of the collected charges is not allocated to the RDc circuit (inactive win signal), the 500 circuit, for example its SUMn circuit, provides the OUT signal representing a zero quantity of collected charges.

[0103] In Figures 4 and 5, although the sel and win signals are represented as separate digital signals, a person skilled in the art will understand that these two signals can be seen as two parts of a single digital signal generated by the 400 circuit in Figure 4 and by the 500 circuit in Figure 5, for example by the PROC circuits.

[0104] Examples of charge sharing correction implementations directly in the RD readout circuits of a photon counting detector have been described above in relation to Figures 2, 3, 4 and 5.

[0105] The charge-sharing corrections described above, as well as known charge-sharing corrections, suffer from a drawback. Indeed, with the charge-sharing corrections described, it is not possible to determine, or distinguish, whether the charges collected simultaneously by electrode 102c and by at least one of the electrodes adjacent to electrode 102c result from a single photon and a "true" charge-sharing, or from several photons each generating charges collected by an electrode covering the part of layer 100 in which that photon generated charges.

[0106] For example, if a first photon is received by the portion of layer 100 opposite electrode 102c, and while the charges from this first photon are being collected by electrode 102c, a second photon is received by the portion of layer 100 opposite the adjacent electrode 102n, then electrode 102n will collect at least some of the charges from the second photon while electrode 102c collects the charges from the first photon. The circuits RDc and RDn then detect that they are both involved in charge sharing and assign the sum of the collected charges to one or the other of the electrodes. Tl electrodes 102c and 102n, which degrades the operation of the photon counting detector.

[0107] To overcome this drawback, it is proposed here to add to each RD circuit the ability to selectively activate and deactivate the load sharing correction in that RD circuit.

[0108] In particular, it is planned that each RD circuit will be configured to selectively enable and disable the load sharing correction it implements based at least on the evt signal that this circuit generates.

[0109] Indeed, the active switching of the evt signal in an RD circuit is representative of the photon flux received by the pixel comprising that RD circuit. Now, when two RD circuits detect that they are involved in charge sharing, it is more likely that the charges collected by the electrodes connected to these two circuits come from a single photon than from two distinct photons when the detector receives a low flux of photons incident on the 100 layer, whereas, conversely, it is more likely that the charges collected by the electrodes connected to these two circuits come from two distinct photons than from a single photon when the detector receives a high flux of photons incident on the 100 layer.

[0110] According to one embodiment, each RD circuit is configured to deactivate the charge-sharing correction it implements if the average number of active states of its evt signal exceeds a threshold. Indeed, the average number of active states of the evt signal of an RD circuit is representative of the average flux of photons incident on the corresponding portion of layer 100, that is, the portion of layer 100 opposite the electrode to which the circuit is connected. For example, the circuit is further configured to reactivate the charge-sharing correction when this average number of active states of the signal evt falls below the threshold.

[0111] In another embodiment, each central circuit RDc is configured to disable the load-sharing correction it implements if the average number of active states of its signal evt and the signals evtn, evte, evts, evtw that it receives from its adjacent circuits exceeds a threshold. Indeed, the average number of active states of the signals evt, evtn, evte, evts, evtw is representative of the average flux of photons incident on the portion of layer 100 corresponding to that central circuit and on the portions of the layer corresponding to the adjacent circuits. As an example, the central circuit is further configured to re-enable the load-sharing correction when this average number of active states falls below the threshold.

[0112] In yet another embodiment, each RD circuit is configured, at the end of each active state of the signal evt generated by that RD circuit, to disable load sharing correction in that RD circuit for a time delay, and then, for example, to re-enable load sharing correction at the end of that time. Thus, when the frequency of the active states of the signal evt exceeds a threshold, load sharing correction remains disabled.

[0113] According to yet another embodiment, each central circuit RDc is configured to disable the load sharing correction that it implements if the number of active states of the signals evtn, evts, evte and evtw that the central circuit RDc receives from these circuits during an active state of the signal evt generated by this central circuit RDc is greater than a threshold.

[0114] According to yet another embodiment, each central circuit is configured to disable correction charge sharing is implemented if, when the RDc circuit detects charge sharing, the electrodes connected to the RDc circuit and the adjacent RD circuits involved in the detected charge sharing are arranged relative to each other in a pattern corresponding to anomalous charge sharing, or, in other words, in a pattern where charges collected simultaneously by these electrodes are more likely to originate from distinct photons than from a single photon. For example, this is the case as soon as the RD circuit detects charge sharing in which at least three electrodes from the set comprising the central electrode 102c and the adjacent electrodes 102e, 102n, 102s, and 102w are involved in the charge sharing.

[0115] Figure 6 schematically represents, in block form, an embodiment of a photon counting detector in which a charge sharing correction is implemented.

[0116] Specifically, Figure 6 illustrates a central RDc circuit of detector 2 that has been modified to add the selective deactivation function for the load sharing correction. Therefore, unless otherwise indicated, everything described for detector 2 and its RD circuits in relation to Figures 2 and 3 applies to the RDc circuit in Figure 6.

[0117] Furthermore, although Figure 6 only represents a central circuit RDc, in practice the other RD circuits of detector 2, in particular the adjacent circuits of this RDc circuit, are identical to the central RDc circuit of Figure 6.

[0118] Compared to the RDc circuit in Figure 3, the RDc circuit in Figure 6 further includes a CSC-EN control circuit configured to selectively activate and deactivate the load sharing correction implemented in that circuit. RDc, based at least on the evt signal generated by the RDc circuit, for example by its 300 circuit. The CSC-EN circuit therefore receives the evt signal.

[0119] In embodiments where the CSC-EN circuit controls the activation and deactivation of the load sharing correction on the basis of the evt signal and the evtn, evte, evts and evtw signals received by the RDc circuit, the CSC-EN circuit also receives the evtn, evte, evts and evtw signals as illustrated in the example in Figure 6.

[0120] For example, the CSC-EN circuit is configured to provide a binary EN signal that controls the activation and deactivation of load sharing correction in the RDc circuit. For example, the inactive state of the EN signal controls the deactivation of load sharing correction, and the active state of the EN signal controls the activation of load sharing correction.

[0121] In one embodiment, the CSC-EN circuit disables load sharing correction (EN inactive) if the average number of active states of the evt signal exceeds a threshold. As an example, the CSC-EN circuit is further configured to re-enable load sharing correction (EN active) when this average number of active states of the evt signal falls below the threshold.

[0122] In another embodiment, the CSC-EN circuit disables load sharing correction (EN inactive) if the average number of active states of its evt signal and the evtn, evte, evts, and evtw signals it receives exceeds a threshold. As an example, the CSC-EN circuit is further configured to re-enable load sharing correction when this average number of active states falls below the threshold.

[0123] According to yet another embodiment, the CSC-EN circuit disables the load sharing correction (EN inactive) at the end of each active state of the evt signal for a time delay period, then, for example, reactivates the load sharing correction (EN active) at the end of this time delay period, provided, of course, that another time delay period is not in progress.

[0124] In yet another embodiment, the CSC-EN circuit disables load sharing correction (EN inactive) if the number of active states of the signals evtn, evts, evte, and evtw that the central circuit RDc receives from its circuits during an active state of the signal evt exceeds a threshold. For example, the CSC-EN circuit re-enables load sharing correction at the end of this active state of the signal evt.

[0125] In yet another embodiment, the CSC-EN circuit disables the charge sharing correction (EN inactive) if, when the RDc circuit detects charge sharing, the electrodes connected to the RDc circuit and the adjacent RD circuits involved in the charge sharing are arranged relative to each other in a pattern corresponding to abnormal charge sharing. For example, the CSC-EN circuit implements this function based on the evt, evts, evte, evtw, and evtn signals it receives.

[0126] The way in which the load sharing correction in the RDc circuit is disabled by the CSC-EN circuit depends on how this load sharing correction is implemented, as will be illustrated below in relation to figures 7 and 8.

[0127] Figure 7 schematically represents, in block form, an example of an embodiment of the RDc circuit of Figure 6.

[0128] The RDc circuit in Figure 7 shares many elements with the RDc circuit in Figure 4, and only the differences between these two circuits are highlighted here.

[0129] Compared to the RDc circuit in Figure 4, the RDc circuit in Figure 7 includes the CSC-EN circuit. The CSC-EN circuit receives the evt signal, and, in the example in Figure 7, the evtw, evte, evts, and evtn signals. However, when the selective activation and deactivation of the load-sharing correction is based solely on the evt signal, the CSC-EN circuit does not receive the evtw, evte, evts, and evtn signals. The CSC-EN circuit provides the EN signal. The EN signal is supplied to the 400 circuit.

[0130] When the charge sharing correction is active (EN active), the circuit 400 operates as described in relation to Figure 4. Conversely, when the charge sharing correction is inactive (EN inactive), the circuit 400 is configured to provide an OUT signal in which the indication of the amount of charge collected by electrode 102c is determined from the sign signal only.

[0131] For example, to disable charge sharing correction when the EN signal is inactive, circuit 400 is configured to ignore the active states of the evt signal, that is, to consider the evt signal as always being inactive. For example, the PROC circuit receives the EN signal. As a result, when charge sharing correction is inactive, the evt signal is always inactive, and adjacent circuits therefore cannot involve the RDc circuit in charge sharing. Furthermore, the OUT signal provides an indication of the charges collected by electrode 102c only from the sign signal. For example, the OUT signal receives the sign signal directly. For example, the SUM circuit receives the EN signal and, when the signal EN is inactive, provides the sign signal directly to the OUT signal, without taking into account other signals it receives.

[0132] As an alternative example, to disable charge sharing correction when the EN signal is inactive, circuit 400 is configured to ignore the active states of the evte, evts, evtn, and evtw signals, and to force the evtc signal to the inactive state. Thus, circuit 400 of circuit RDc detects no charge sharing with its adjacent circuits RDs, RDe, RDw, and RDn, and conversely, circuits 400 of circuits RDs, RDe, RDw, and RDn detect no charge sharing with the central circuit RDc. As an example, the PROC circuit receives the EN signal and implements the functions described above. Furthermore, the OUT signal provides an indication of the charges collected by electrode 102c based solely on the sign signal.For example, because the PROC circuit considers the evtn, evts, evte and evtw signals to always be inactive, the sel signal does not indicate that adjacent circuits are involved in load sharing, and the SUM circuit then directly provides the sign signal to the OUT signal.

[0133] As an example, to ignore the active state of a received signal, the 400 circuit includes a multiplexer that takes as input the received signal and a signal that is always inactive, and the multiplexer is controlled by the EN signal. The signal output of the multiplexer is then the signal actually used by the 400 circuit.

[0134] As an example, to force a signal it supplies into an inactive state, the 400 circuit includes a multiplexer that takes as input the signal to be transmitted and a signal that is always inactive, and the multiplexer is controlled by the EN signal. The signal at the output of the multiplexer is then the signal actually transmitted by the 400 circuit.

[0135] Figure 8 represents, schematically and in block form, an example of an embodiment of the RDc circuit of Figure 6.

[0136] The RDc circuit in Figure 8 includes many elements in common with the RDc circuit in Figure 5, and only the differences between these two circuits are highlighted here.

[0137] Compared to the RDc circuit in Figure 5, the RDc circuit in Figure 8 includes the CSC-EN circuit. The CSC-EN circuit receives the evt signal, and, in the example in Figure 8, the evtw, evte, evts, and evtn signals. However, when the selective activation and deactivation of the load-sharing correction is based solely on the evt signal, the CSC-EN circuit does not receive the evtw, evte, evts, and evtn signals. The CSC-EN circuit provides the EN signal. The EN signal is supplied to the 500 circuit.

[0138] When the charge sharing correction is active (EN active), the circuit 500 operates as described in relation to Figure 5. Conversely, when the charge sharing correction is inactive (EN inactive), the circuit 500 is configured to provide a sum signal determined solely from the Impfe signal, so that, in the OUT signal, the indication of the amount of charge collected by electrode 102c is determined solely from the Impfe signal.

[0139] For example, to disable load sharing correction when the EN signal is inactive, the 500 circuit is configured to ignore the active states of the evt signal, that is, to consider the evt signal as always being inactive. For example, the PROC circuit receives the EN signal. As a result, when load sharing correction is inactive, the evt signal is always inactive, and therefore adjacent circuits cannot implicate the RDc circuit in charge sharing. Furthermore, the OUT signal provides an indication of the charges collected by electrode 102c solely from the Impfe signal. For example, because the evt signal is considered inactive by the PROC circuit, no charge sharing involving the RDc circuit is detected by the PROC circuit, and the sel signal does not indicate any of the adjacent readout circuits. Consequently, the sum signal, and therefore the sign signal, are determined solely by the Impfe signal, and it follows that, in the OUT signal, the indication of the amount of charge collected by electrode 102c is determined solely by the Impfe signal.

[0140] As an alternative example, to disable charge sharing correction when the EN signal is inactive, circuit 500 is configured to ignore the active states of the evte, evts, evtn, and evtw signals, and to force the evtc signal to the inactive state. Thus, circuit 500 of circuit RDc detects no charge sharing with its adjacent circuits RDs, RDe, RDw, and RDn, and conversely, circuits 400 of circuits RDs, RDe, RDw, and RDn detect no charge sharing with the central circuit RDc. As an example, the PROC circuit receives the EN signal and implements the functions described above. Furthermore, the OUT signal provides an indication of the charges collected by electrode 102c solely from the Impfe signal. For example, because the PROC circuit considers the evtn, evts, evte and evtw signals to always be inactive, the sel signal does not indicate that adjacent circuits are involved in load sharing.It follows that the sum signal, and therefore the sign signal, are determined solely by the Impfe signal, and it follows that, in the OUT signal, the indication of the quantity of charges collected by the electrode 102c is determined solely by the Impfe signal.

[0141] As an example, to ignore the active state of a received signal, the 500 circuit includes a multiplexer that takes as input the received signal and a signal that is always inactive, and the multiplexer is controlled by the EN signal. The output signal of the multiplexer is then the signal actually used by the 500 circuit.

[0142] As an example, to force a signal it supplies into an inactive state, circuit 500 includes a multiplexer that takes as input the signal to be transmitted and a signal that is always inactive, and the multiplexer is controlled by the EN signal. The signal output of the multiplexer is then the signal actually transmitted by circuit 400.

[0143] Examples of implementations described above, in relation to Figures 6, 7, and 8, are those in which, when charge sharing is detected by an RDc circuit and this RDc circuit has determined the adjacent readout circuit(s) involved in the charge sharing, the allocation in the RDc circuit of the sum of the collected charges to one or the other of the readout circuits involved in the charge sharing is based on the signals evt, evtn, evts, evte, and evtw. Those skilled in the art will be able to adapt these examples to the case where, in the RDc circuit, the allocation of the sum of the collected charges is based on the signal representing the amount of charge collected by electrode 102c, which is generated in the RDc circuit (sign in Figure 7 and Impfe in Figure 8), and the signals vale, vais, valw, and vain.

[0144] Furthermore, in the examples described in relation to figures 3 to 8, the RDc circuit exchanges signals only with the adjacent circuits RDn, RDe, RDw and RDs, so that the charge sharing correction is implemented when the charge sharing involves electrode 102c and one or more of the adjacent electrodes 102e, 102w, 102s and 102n only. A person skilled in the art will be able to adapt these examples to the case where the RDc circuit exchanges signals with the adjacent circuits RDn, RDe, RDw, RDs, RDse, RDsw, RDne and RDnw, so that the charge sharing correction is implemented when the charge sharing involves electrode 102c and one or more of the adjacent electrodes 102e, 102w, 102s, 102n, 102ne, 102nw, 102se and 102sw.

[0145] Figure 9 shows an example of the implementation of the CSC-EN circuit described in relation to Figures 6, 7 and 8. Figure 10 shows timing diagrams illustrating the operation of the CSC-EN circuit of Figure 9.

[0146] In this example, the CSC-EN circuit of the RDc circuit is configured to disable the load sharing correction implemented in the RDc circuit if the average number of active states of the evt signal generated in the RDc circuit exceeds a threshold Vth. The comparison of the average number of active states of the evt signal to the threshold Vth is, in this example, implemented with a hysteresis H on the value of the threshold Vth.

[0147] The CSC-EN circuit includes a PBF low-pass filter receiving the evt signal and providing an evtm signal having a value determined by the average number of active states of the evt signal.

[0148] The CSC-EN circuit further includes a CMP comparator receiving the evtm signal and comparing it to the threshold Vth, in this example applying a hysteresis of value H. The output of the CMP comparator provides the EN signal.

[0149] In this example, the active state of the EN signal is a high state, and the active state of the evt signal is also a high state.

[0150] Thus, as can be seen in Figure 10, when the frequency of the active states of the signal evt is relatively When the frequency of the active states of the evt signal is low (left side of Figure 10), the evtm signal is below the threshold Vth, i.e., below Vth-H in this example. The EN signal is then active (EN is high), and the correction is active. When the frequency of the active states of the evt signal is relatively high (right side of Figure 10), the evtm signal is above the threshold Vth, i.e., above the threshold Vth+H in this example. The EN signal is then inactive (EN is low), and the correction is deactivated.

[0151] A person skilled in the art will be able to adapt the above example to the case where the CSC-EN circuit determines the state of the EN signal from the average number of active states of the signals evt, evtn, evtw, evts etc...

[0152] Figure 11 shows another example of the implementation of the CSC-EN circuit described in relation to Figures 6, 7 and 8. Figure 12 shows timing diagrams illustrating the operation of the CSC-EN circuit of Figure 11.

[0153] In this example, the CSC-EN circuit of the RDc circuit is configured to disable the load sharing correction implemented in the RDc circuit for a time duration At after each end of the active state of the evt signal.

[0154] The CSC-EN circuit includes a retriggerable monostable circuit, MONO. The MONO circuit is configured to provide the EN signal in the active state by default, and to force the EN signal to the inactive state for a duration At after each end of the active state of the evt signal. Thus, the MONO circuit receives the evt signal at a control input and provides the EN signal at its output.

[0155] In this example, the active state of the EN signal is a high state, and the active state of the evt signal is also a high state.

[0156] Thus, as shown in Figure 12, when two successive active states of the signal evt are relatively far apart (on the left in Figure 12), at the end of the first of the two active states of the signal evt (time t0), the signal EN is forced into the inactive state for the duration At, then returns to the active state at the end of the duration At (time t1), before the next active state of the signal evt occurs (time t2). The load sharing correction will therefore be active for these two active states of the signal evt. On the other hand, when two successive active states of the signal evt are relatively close to each other (right in figure 12), at the end of the first of the two active states of the signal evt (time t3), the signal EN is forced into the inactive state for the duration At and the next active state of the signal evt (time t4) occurs while the duration At has not entirely elapsed.The load sharing correction will therefore be inactive for this second active state of the signal evt. Furthermore, the end of the active state occurring during the duration At re-engages the MONO circuit, and a new duration At begins (instant t5).

[0157] Two examples of CSC-EN circuit implementations have been described in relation to Figures 9 to 12. A person skilled in the art will be able to foresee other implementations of the CSC-EN circuit. For example, a person skilled in the art will be able to implement CSC-EN circuits corresponding to the different operating alternatives of the CSC-EN circuit described in relation to Figure 3.

[0158] More generally, from this description, a person skilled in the art will be able to add, in a known reading circuit implementing a load sharing correction, the function of selectively activating and deactivating the load sharing correction on the basis of at least a detection signal generated in this circuit, and, furthermore, to adapt the circuit accordingly.

[0159] For example, in each readout circuit 22 of Figure 4 of document EP 2936208 (or US 9329283), a person skilled in the art will be able to add the selective on / off function of load sharing correction based at least on the H1 signal generated in that readout circuit 22.

[0160] As another example, in the readout circuit of Figure 3 of the article "The Medipix3RX: a high resolution, zero dead-time pixel detector readout chip allowing spectroscopic imaging", a person skilled in the art will be able to add the function of selectively enabling and disabling the charge sharing correction based at least on the DiscOutLocal signal generated in this circuit.

[0161] Various embodiments and variations have been described. A person skilled in the art will understand that some features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0162] Finally, the practical implementation of the described methods and variants is within the reach of the person in the trade, based on the functional indications given above.

Claims

DEMANDS 1. Photon counting detector (1, 2) comprising a photon-to-charge conversion layer (100) covered with several electrodes (102) each connected to a readout circuit (RD), wherein: each readout circuit (RD) is configured to generate an active detection signal (evt) when charges are collected by the electrode (102) to which the readout circuit (RD) is connected; Each readout circuit, called the central circuit (RDc), is configured to implement a load-sharing correction by exchanging signals (200; evtc, evtn, evts, evte, evtw, valc, vain, vais, vale, valw) with readout circuits, called adjacent circuits (RDn, RDs, RDe, RDw) of the central circuit (RDc), connected to electrodes adjacent (102n, 102s, 102e, 102w) to the electrode to which the central circuit is connected, called the central electrode (102c); and each central circuit (RDc) is configured to selectively turn on and off (CSC-EN;EN) the load sharing correction in said central circuit on the basis at least of the detection signal (evt) generated by said central circuit.; 2. Detector according to claim 1, wherein: each central circuit (RDc) is adapted to send the detection signal (evtc) that it generates to each of the adjacent circuits (RDn, RDs, RDe, RDw) of the central circuit (RDc), each of the adjacent circuits (RDn, RDs, RDe, RDw) of said central circuit (RDc) being adapted to send the detection signal (evtn, evts, evte, evtw) that it generates to said central circuit.

3. Detector according to claim 2, wherein each central circuit (RCD) is configured to disable the load sharing correction in said central circuit (RDc) if an average number of active states of the detection signal (evt) generated by the central circuit (RDc) is greater than a threshold (Vth).

4. Detector according to claim 2, wherein each central circuit (RDc) is configured to disable load sharing correction in said central circuit (RDc) if an average number of active states of the detection signal (evt) generated by the central circuit (RDc) and of the detection signals (evtn, evts, evte, evtw) that the central circuit (RDc) receives from the adjacent circuits (RDn, RDs, RDe, RDw) of the central circuit (RDc) is greater than a threshold.

5. Detector according to claim 2, wherein each central circuit (RDc) is configured to disable load sharing correction in said central circuit (RDc) for a time delay (At) after an end of each active state of the detection signal (evt) generated by the central circuit (RDc).

6. Detector according to claim 2, wherein each central circuit (RDc) is configured to disable load sharing correction in said central circuit (RDc) if a number of active states of the detection signals (evtn, evts, evte, evtw) that the central circuit (RDc) receives from the adjacent circuits (RDn, RDs, RDe, RDw) of the central circuit (RDc) during an active state of the detection signal (evt) generated by the central circuit is greater than a threshold.

7. Detector according to claim 2, wherein each central circuit (RCD) is configured to disable load sharing correction in said central circuit (RCD) if the central circuit (RCD) and the circuit(s) adjacent (RDn, RDs, RDe, RDw) of the central circuit (RDc) which send detection signals (evtn, evts, evte, evtw) active during an active state of the detection signal (evt) generated by the central circuit (RDc) are connected to electrodes (102; 102c, 102n, 102s, 102e, 102w) arranged relative to each other in a pattern corresponding to an abnormal charge sharing.

8. Detector according to any one of claims 2 to 7, wherein: each central circuit (RDc) comprises a charge sharing detection circuit (400; 500) configured to detect that the central electrode (102c) and one or more of the electrodes adjacent (102n, 102s, 102e, 102w) to the central electrode are involved in charge sharing, from the detection signal (evt) generated in the central circuit and respectively from the detection signal(s) (evtn, evts, evte, evtw) sent to the central circuit (RDc) by respectively the adjacent circuit(s) (RDn, RDs, RDe, RDw) connected respectively to said one or more adjacent electrodes (102n, 102s, 102e, 102w).

9. Detector according to claim 8, wherein: each readout circuit (RD; RDc, RDn, RDs, RDe, RDw) is configured to generate a first signal (Impfe; sign) representative of a quantity of charge collected by the electrode (102; 102c, 102n, 102s, 102e, 102w) to which the readout circuit is connected; and each central circuit (RDc) is adapted to send the first signal (Impfe; sign; vale) that it generates to each of said adjacent circuits (RDn, RDs, RDe, RDw) of the central circuit (RDc), each of said adjacent circuits (RDn, RDs, RDe, RDw) of said central circuit (RDc) being adapted to send the first signal (Impie ; sign ; vain, vais, vale, valw) that it generates to said central circuit.

10. Detector according to claim 9, wherein the charge sharing detection circuit (400, 500) of each central circuit (RDc) is configured, when it detects that the central electrode (102c) and one or more of the adjacent electrodes (102n, 102s, 102e, 102w) are involved in charge sharing, to determine to which of the electrodes involved in charge sharing is assigned a sum of the charges collected by the electrodes involved in charge sharing. 11.Detector according to claim 9, wherein the charge-sharing detection circuit (400, 500) is configured to determine to which of the electrodes involved in charge sharing is assigned the sum of the charges collected by the electrodes involved in charge sharing from: the detection signal (evt) generated by the central circuit (RDc) and the detection signal(s) (evtn, evts, evte, evtw) sent to the central circuit (RDc) by the adjacent circuit(s) (RDn, RDs, RDe, RDw) connected respectively to said one or more adjacent electrodes (102n, 102s, 102e, 102w) involved in charge sharing, or the first signal (Impfe, sign) generated by the central circuit (RDc) and the first signal(s) (vain, vais, vale, valw) sent to the central circuit by the adjacent circuit(s) (RDn, RDs, RDe, RDw) connected respectively to said one or more adjacent electrodes (102n, 102s, 102e, 102w) involved in charge sharing.

12. Detector according to claim 10 or 11, wherein each central circuit (RDc) is configured: when the charge sharing correction is active in the central circuit, to provide an output signal (OUT) representative of the sum of the charges collected by the central electrode (102c) and said one or more adjacent electrodes (102n, 102s, 102e, 102w) involved in the charge sharing if this sum of charges is attributed to the central electrode (102c), and of a zero amount of charge otherwise; and when the charge sharing correction is inactive in the central circuit (RDc), to provide an output signal (OUT) representative of the charges collected by the central electrode (102c) only.

13. Detector according to any one of claims 1 to 12, wherein the reading circuits (RD; RDc, RDn, RDs, RDe, RDw) are identical.

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