Video processing system

Abstract

A video signal distribution device 500 according to the present disclosure divides a video signal from an imaging unit 200 that images an object at predetermined time intervals, distributes the divided video signals among a plurality of image processors 300 according to a predetermined ratio, and converts the frame rate of each of the divided video signals according to the predetermined ratio.

Description

Video processing system

[0001] The present disclosure relates to a system for processing video captured by a terminal.

[0002] The popularity of high-speed cameras that continuously capture video at very short intervals equivalent to several hundred frames per second (fps) is increasing. High-speed cameras can capture fast-moving subjects that cannot be captured by ordinary video cameras, and are thus widely used in manufacturing process inspections and sports science analysis.

[0003] On the other hand, in the case of high-speed cameras, there is a problem that it is difficult to increase the shooting time because the amount of generated data is enormous, the processing speed in the subsequent stage cannot catch up even if shooting is possible, and the storage capacity for processing is insufficient even if processing is possible.

[0004] In response to such problems, Non-Patent Document 1 proposes a technique of duplicating video data output from a camera, transmitting it to a PC, and performing取舍 selection and distributed processing of the video data on the PC side.

[0005] However, in the technique of Non-Patent Document 1, since the video signal obtained from the image sensor inside the camera is converted into a desired interface and video by the image processor and then output to the PC side, an increase in the processing of the image processor can become a bottleneck in lengthening the shooting time.

[0006] Abarde Data Co., Ltd., "Image Distribution / Parallel Processing", [Searched on August 9, 2024], Internet <URL: https: / / avadata.co.jp / products / imaging / distribution>

[0007] Therefore, an object of the present disclosure is to provide a video signal distribution device and a video processing system capable of suppressing the processing time in a terminal that captures video.

[0008] To achieve the above object, the video signal distribution device and the video processing system of the present disclosure adopt a method of dividing a video signal at a predetermined time interval and distributing it among a plurality of image processors according to a predetermined ratio.

[0009] Specifically, the video signal distribution device of this disclosure divides the video signal from a shooting unit that photographs an object at predetermined time intervals, distributes the divided video signals among a plurality of image processors according to predetermined proportions, and converts the frame rate of each of the divided video signals according to the predetermined proportions.

[0010] Alternatively, the video signal may be divided by reading out the start or end signal from the video signal and distributing it among the multiple image processors.

[0011] More specifically, the video processing system of this disclosure comprises the above-mentioned video signal distribution device, a plurality of image processors that process the divided video signals according to a predetermined ratio, and a combining processing device that combines the divided video signals in the order in which they were processed by the plurality of image processors.

[0012] The system may also further include a video distribution controller that controls the video signal distribution device to distribute the divided video signals among the plurality of image processors based on at least one of the processing capabilities of each image processor and information regarding the network between each image processor and the video signal distribution device.

[0013] The video signal distribution device, image processor, PC, and other devices disclosed herein can also be realized by a computer and a program, and the program can be recorded on a recording medium or provided via a network. The program disclosed herein is a program that causes a computer to realize each function of the device disclosed herein, and a program that causes a computer to execute each procedure of the method executed by the device disclosed herein.

[0014] Furthermore, the above disclosures can be combined as much as possible.

[0015] According to this disclosure, the processing time in the terminal that captures the video can be reduced.

[0016] This is a block diagram showing the configuration of the video processing system according to the first embodiment. This is a block diagram showing the configuration of the video signal distribution device according to the first embodiment. This is a sequence diagram showing the operation of the video signal distribution device according to the first embodiment. This is a block diagram showing a modified version of the video processing system according to the first embodiment. This is a block diagram showing a modified version of the video signal distribution device according to the first embodiment. This is a sequence diagram showing the operation of the modified version of the video signal distribution device according to the first embodiment. This is a block diagram showing the configuration of the video processing system according to the second embodiment. This is a block diagram showing the configuration of the video data merging application according to the second embodiment. This is a diagram illustrating the processing of the video data merging application according to the second embodiment. This is a block diagram showing a modified version of the video processing system according to the second embodiment. This is a diagram illustrating the processing of the video data merging application according to a modified version of the second embodiment. This is a block diagram showing the configuration of the video processing system according to the third embodiment. This is a block diagram showing the configuration of the video distribution controller according to the third embodiment. This is a diagram illustrating the operation of the video distribution controller according to the third embodiment. This is a block diagram showing the configuration of a related video processing system. This is a block diagram showing the configuration of a related video processing system.

[0017] Embodiments of this disclosure will be described in detail below with reference to the drawings. However, this disclosure is not limited to the embodiments shown below. These examples are illustrative, and this disclosure can be implemented in various modified and improved forms based on the knowledge of those skilled in the art. In this specification and in the drawings, components with the same reference numerals refer to the same components.

[0018] (First Embodiment) An image processing system 100 according to the first embodiment of the present disclosure will be described based on Figures 1 to 3.

[0019] First, the basic configuration of the image processing system 100 will be described with reference to Figure 1. As shown in Figure 1, the image processing system 100 comprises an imaging unit 200, three image processors 300A, 300B, and 300C (hereinafter sometimes collectively referred to as image processor 300), PCs (Personal Computers) 400A, 400B, and 400C (hereinafter sometimes collectively referred to as PC400), and a video signal distribution device 500. The imaging unit 200 comprises a lens 21 and an image sensor 22. The imaging unit 200 is configured to image an object to be imaged. In this embodiment, the case where there are three image processors 300 and three PCs 400 is described as an example, but the number of image processors 300 and PCs 400 can be any number.

[0020] The video processing system 100 is configured to distribute the video signals output from the image sensor 22 based on the start / end triggers of video frames, convert them into video signals of a predetermined frame rate, and output them to three image processors 300A, 300B, and 300C. This configuration allows the processing performed by the image processor 300 to be distributed, thereby avoiding processing bottlenecks and enabling higher resolution and longer recording times.

[0021] The imaging unit 200 is configured to photograph the object to be photographed, convert it into a video signal, and then output it. The lens 21 is a lens with an arbitrary focal length and is configured to focus light.

[0022] The image sensor 22 includes, for example, a PD (Photo Diode), a CMOS (Complementary Metal Oxide Semiconductor / Charge Coupled Device) circuit, a CDS (Correlated Double Sampling), and an ADC (Analog-to-digital Converter). However, the configuration of the image sensor 22 is arbitrary, and it may have other configurations or additional configurations.

[0023] The image sensor 22 outputs the video signal it generates to the video signal distribution device 500. For example, the image sensor 22 may output a video signal with 1920 x 1080 pixels. However, the output of the image sensor 22 is not limited to this, and it may output a video signal with any number of pixels. Also, for example, the image sensor 22 may output a video signal with a frame rate of 1080 fps (frames per second). However, the output of the image sensor is not limited to this, and it may output a video signal with any frame rate.

[0024] The video signal distribution device 500 distributes the video signals output from the image sensor 22 based on the start / end triggers of the video frames, converts them into video signals of a predetermined frame rate, and outputs them to three image processors 300A, 300B, and 300C. In other words, the video signal distribution device 500 reads the start or end signal from the video signal, divides the video signal, and distributes it among the multiple image processors 300. The detailed configuration and functions of the video signal distribution device 500 will be described later.

[0025] Each image processor 300 converts the video signal from the video signal distribution device 500 into a desired interface or video data and outputs it. Each image processor 300 processes the divided video signal according to a predetermined ratio. Specifically, image processor 300A outputs video data to PC 400A, image processor 300B outputs video data to PC 400B, and image processor 300C outputs video data to PC 400C.

[0026] The PC 400 includes a frame grabber 41 and an HDD / SDD (Hard Disc Drive / Solid State Drive) 42. The frame grabber 41 is configured to capture video data from the image processor 300 into the PC 400. For example, the frame grabber 41 may function based on standards that define data transmission methods for industrial cameras, such as CameraLink or CoaXPress. The HDD / SDD 42 is configured to save the video data captured by the frame grabber 41 as a video file.

[0027] Next, with reference to Figure 2, each functional part of the video signal distribution device 500 will be described. The video signal distribution device 500 comprises a video signal distribution unit 51 and three video signal rate conversion function units 52A, 52B, and 52C (hereinafter collectively referred to as video signal rate conversion function units 52). In this embodiment, the case with three video signal rate conversion function units 52 will be described as an example, but the number of video signal rate conversion function units 52 can be any number.

[0028] The video signal distribution unit 51 is a functional unit that distributes video signals to each video signal rate conversion function unit 52 based on the start / end triggers (start signal / end signal) of the video signal frames. In other words, the video signal distribution unit 51 is configured to divide the video signal from the shooting unit 200 that photographs the target object at predetermined time intervals and distribute the divided video signals among the multiple image processors 300 according to predetermined ratios. The start / end triggers are expected to be vsync (Vertical Synchronizing signal) or, in the case of MIPI (Mobile Industry Processor Interface), Frame Start / Frame End packets. However, the start / end triggers are not limited to these, and video signals may be distributed based on any start / end trigger.

[0029] The video signal rate conversion function unit 52 is a function unit that converts the distributed video signals into video signals with a reduced frame rate according to the number of distributions. In other words, the video signal rate conversion function unit 52 is configured to convert the frame rate of each divided video signal according to a predetermined ratio. In this embodiment, the case in which the video signal is distributed equally to three video signal rate conversion function units 52 (number of distributions = 3) is shown. Specifically, each video signal rate conversion function unit 52 reduces the frame rate to 360 fps, which is 1 / 3 of 1080 fps. Here, the number of distributions is an example of a predetermined ratio.

[0030] Here, there are various methods for changing the frame rate. For example, the frame rate may be changed by rewriting the data in a specific area of ​​the packet (such as the header).

[0031] Next, the processing sequence of the video signal distribution device 500 will be described with reference to Figure 3. The video signal distribution unit 51 receives video signals of a predetermined frame rate and number of frames sequentially. Each video signal is provided with a start signal and an end signal as start / end triggers.

[0032] Figure 3 shows an example in which video signals (1) to (4), divided by time, are sequentially input to the video signal distribution unit 51. Note that video signals (1) to (4) include cases where there is one frame, as well as cases where there are multiple frames. Video signals (1) to (4) are video signals with a frame rate of 1080 fps. Each video signal is distributed to the respective video signal rate conversion function unit 52 in the order in which it is input to the video signal distribution unit 51. Specifically, the video signal distribution unit 51 inputs video signal (1) to the video signal rate conversion function unit 52A, video signal (2) to the video signal rate conversion function unit 52B, and video signal (3) to the video signal rate conversion function unit 52C.

[0033] Subsequently, the video signal distribution unit 51 inputs the video signal (4) to the video signal rate conversion function unit 52A, and the same process is repeated thereafter.

[0034] The video signal rate conversion function unit 52A outputs a video signal (1)' in which the frame rate of video signal (1) is reduced to 360 fps. Similarly, the video signal rate conversion function unit 52B outputs a video signal (2)' in which the frame rate of video signal (2) is reduced to 360 fps. Similarly, the video signal rate conversion function unit 52C outputs a video signal (3)' in which the frame rate of video signal (3) is reduced to 360 fps.

[0035] Furthermore, the video signal rate conversion function unit 52A outputs video signal (4)' with the frame rate of video signal (4) reduced to 360 fps after outputting video signal (1)', and then repeats the same process. The video signal rate conversion function units 52B and 52C also repeat the same process.

[0036] (Comparison with related video processing systems) The effects of the video processing system 100 will be explained in comparison with the related video processing systems shown in Figures 15 and 16.

[0037] Figure 15 shows a configuration in which the associated video processing system 100A includes a camera 20A and a PC 40A. The camera 20A includes a buffer 31A and a processing unit 32A. The PC 40A includes a frame grabber 41A and an HDD / SSD 42A.

[0038] The video signal from the image sensor is stored in the buffer 31A and then sent to the processing unit 32A for processing. The video signal processed by the processing unit 32A is then captured by the frame grabber 41A and stored in the PC 40A and then stored in the HDD / SSD 42A.

[0039] However, with the configuration shown in Figure 15, the amount of data generated is enormous, and even if image capture is possible, the processing speed of the subsequent stages (processing unit 32A, frame grabber 41A) cannot keep up. Furthermore, even if processing is possible, the storage capacity of the buffer 31A and HDD / SSD 42A is insufficient, making it difficult to extend the image capture time.

[0040] In response to this, a video processing system 100B, as shown in Figure 16, has been proposed. In the video processing system 100B, a video copy device 50A is used to duplicate the video signal and transmit it to multiple PCs 40A, where the PCs 40A select which video signals to process (see Non-Patent Literature 1). The video processing system 100B makes it possible to eliminate bottlenecks in processing speed and storage capacity on the PC side that processes the camera image.

[0041] However, even with the configuration of FIG. 16, inside the camera 20A, since the video signal obtained from the image sensor is converted into a desired interface or video by the image processor 30A and then output externally, the bottleneck inside the camera 20A cannot be eliminated. Also, since the frame number (ID) in an external interface such as CoaXPress is not assigned to the signals inside the camera 20A, it is impossible to select and process the frames that should recognize and process the frame number (ID).

[0042] In contrast, according to the present embodiment, since the processing performed by the image processor 300 can be decentralized using the video signal distribution device 500, it is possible to avoid the bottleneck of the processing and perform shooting with a higher resolution and long-time high-speed camera.

[0043] (Modification of the First Embodiment) A video processing system 101 according to a modification of the first embodiment will be described based on FIGS. 4 to 6. The video processing system 101 has the same configuration as the video processing system 100, but its processing is different.

[0044] Specifically, as shown in FIG. 5, the video signal distribution device 500 distributes the video signal unevenly inside it (video signal distribution unit 51) and inputs it to the video signal rate conversion function unit 52. Then, as shown in FIGS. 4 and 5, the video signal distribution device 500 (video signal rate conversion function unit 52) converts the distributed video signal into a video signal with a reduced frame rate according to the number of distributions and transmits it to the corresponding image processor 300.

[0045] In this embodiment, an example is shown in which the video signal is distributed to the video signal rate conversion functional units 52A, 52B, and 52C at a ratio of 2:1:1. Therefore, in this embodiment, the video signal rate conversion functional unit 52A transmits a video signal with its frame rate reduced to 540 fps, which is 2 / 4 of 1080 fps, to the image processor 300A. Also, the video signal rate conversion functional unit 52B transmits a video signal with its frame rate reduced to 270 fps, which is 1 / 4 of 1080 fps, to the image processor 300B. Further, the video signal rate conversion functional unit 52C transmits a video signal with its frame rate reduced to 270 fps, which is 1 / 4 of 1080 fps, to the image processor 300C.

[0046] Next, the processing sequence of the video signal distribution device 500 will be described while referring to FIG. 6. Similar to FIG. 3, FIG. 6 shows an example in which video signals (1)-(4) are sequentially input to the video signal distribution unit 51. The video signals (1)-(4) are video signals with a frame rate of 1080 fps.

[0047] The video signal distribution unit 51 inputs the video signal (1) to the video signal rate conversion functional unit 52A and inputs the video signal (2) to the video signal rate conversion functional unit 52B. Thereafter, the video signal distribution unit 51 inputs the video signal (3) to the video signal rate conversion functional unit 52A and inputs the video signal (4) to the video signal rate conversion functional unit 52C. The video signal distribution unit 51 repeats the same processing thereafter.

[0048] The video signal rate conversion functional unit 52A outputs a video signal (1)' with the frame rate of the video signal (1) reduced to 540 fps, and then outputs a video signal (3)' with the frame rate of the video signal (3) reduced to 540 fps. The video signal rate conversion functional unit 52B outputs a video signal (2)' with the frame rate of the video signal (2) reduced to 270 fps. Similarly, the video signal rate conversion functional unit 52C outputs a video signal (4)' with the frame rate of the video signal (4) reduced to 270 fps. The video signal rate conversion functional unit 52 repeats the same processing thereafter.

[0049] However, the scope of this disclosure is not limited to the above, and the proportion to which the video signal is distributed unbalanced to the video signal rate conversion function units 52A, 52B, and 52C is arbitrary.

[0050] Furthermore, the scope of this disclosure is not limited to the case where the video signal rate conversion function unit 52 (video signal rate conversion function unit 52A in the above example) is input to the video signal rate conversion function unit 52A with a large distribution ratio at intervals as described above (every other signal in the above example), but multiple video signals may be input consecutively to the video signal rate conversion function unit 52A with a large distribution ratio.

[0051] According to this modified example, the processing performed by the image processor 300 can be distributed using the video signal distribution device 500, thereby avoiding processing bottlenecks and enabling high-resolution, long-duration high-speed camera shooting.

[0052] (Second Embodiment) A video processing system 102 according to a second embodiment of the present disclosure will be described based on Figures 7 to 9. In addition to the configuration of the video processing system in the above embodiment, the video processing system 102 includes a coupling processing device 600. In this embodiment, the case is shown in which the video signal is evenly distributed to the three video signal rate conversion function units 52 of the video signal distribution device 500 (number of distributions = 3). That is, each video signal rate conversion function unit 52 of the video signal distribution device 500 transmits a video signal with a frame rate reduced to 360 fps, which is 1 / 3 of 1080 fps, to the corresponding image processor 300.

[0053] The merging processing device 600 comprises a video data merging application 61 and an HDD / SSD 62. The video data merging application 61 is a functional unit that merges video data processed in a distributed manner on each PC 400. Specifically, as shown in Figure 8, the video data merging application 61 comprises three video data reading units 63A, 63B, and 63C (hereinafter collectively referred to as video data reading units 63) and a video data merging processing unit 64.

[0054] The video data reading unit 63A reads video data from the HDD / SSD 42 of PC400A. The video data reading unit 63B reads video data from the HDD / SSD 42 of PC400B. The video data reading unit 63C reads video data from the HDD / SSD 42 of PC400C. Each video data reading unit 63 sends the read video data to the video data merging processing unit 64.

[0055] The video data merging processing unit 64 merges the video data from each video data reading unit 63. The video data merging processing unit 64 merges the divided video signals (video data) in the order in which they were processed by the multiple image processors 300. Specifically, it merges three 360fps video data into one 1080fps video data while converting the frame rate. The video data merging processing unit 64 saves the merged video data as a video file to the HDD / SSD 62.

[0056] Next, the processing of the video data merging application 61 will be explained with reference to Figure 9. The video data reading unit 63 reads video data (frames) based on the processing in the preceding stage, that is, the order in which the corresponding video signals were distributed in the video signal distribution device 500. In this embodiment, in the preceding stage of each PC 400, the video signals are evenly distributed in the order of video signal rate conversion function units 52A, 52B, and 52C (number of distributions = 3). As a result, video data is repeatedly saved in the order of PC400A's HDD / SSD 42, PC400B's HDD / SSD 42, PC400C's HDD / SSD 42, and so on. For this reason, the video data reading unit 63A, video data reading unit 63B, video data reading unit 63C, and so on read video data from the corresponding HDD / SSD and send it to the video data merging processing unit 64.

[0057] The video data merging processing unit 64 merges the video data from the video data reading unit 63 in the order in which it was received, while converting the frame rate.

[0058] If the divided video signal consists of multiple frames, the video data may be read from the HDD / SSD42 of each PC400 for each of these multiple frames and then combined.

[0059] According to this embodiment, the processing performed by the image processor 300 can be distributed using the video signal distribution device 500, thereby avoiding processing bottlenecks and enabling high-resolution, long-duration high-speed camera shooting.

[0060] Furthermore, according to this embodiment, by combining the video signal distribution device 500 and the coupling processing device 600, it becomes possible to acquire high-resolution, long-duration high-speed camera video data.

[0061] (Modification of the Second Embodiment) Based on Figures 10 and 11, a modified image processing system 103 according to the second embodiment will be described. The image processing system 103 has the same configuration as the image processing system 102, but its processing is different. Specifically, this modification shows an example in which the video signal is distributed to the video signal rate conversion function units 52A, 52B, and 52C of the video signal distribution device 500 in a ratio of 4:1:1. That is, the video signal distribution device 500 transmits a video signal with a reduced frame rate to 720 fps, which is 4 / 6 of 1080 fps, to the image processor 300A, and transmits a video signal with a reduced frame rate to 180 fps, which is 1 / 6 of 1080 fps, to the image processors 300B and 300C.

[0062] As described above, the video data reading unit 63 reads video data (frames) based on the processing in the preceding stage, that is, the order in which the corresponding video signals were distributed in the video signal distribution device 500. In this modified example, in the preceding stage of each PC 400, the video signals are distributed unbalanced among the video signal rate conversion function units 52A, 52B, and 52C. As a result, the video data is repeatedly saved in the order of PC400A's HDD / SSD42, PC400B's HDD / SSD42, PC400A's HDD / SSD42, PC400C's HDD / SSD42, and so on.

[0063] Therefore, as shown in Figure 11, the video data reading unit 63A, the video data reading unit 63B, the video data reading unit 63A, the video data reading unit 63C, and so on read video data from the corresponding HDD / SSD and send it to the video data merging processing unit 64.

[0064] The video data merging processing unit 64 merges the video data from the video data reading unit 63 in the order in which it was received, while converting the frame rate.

[0065] According to this modified example, the processing performed by the image processor 300 can be distributed using the video signal distribution device 500, thereby avoiding processing bottlenecks and enabling high-resolution, long-duration high-speed camera shooting.

[0066] Furthermore, according to this embodiment, by combining the video signal distribution device 500 and the coupling processing device 600, it becomes possible to acquire high-resolution, long-duration high-speed camera video data.

[0067] (Third Embodiment) A video processing system 104 according to the third embodiment will be described based on Figures 12 to 14. The video processing system 104 has the same configuration as the video processing system in the embodiments described above. The video processing system 104 also includes a video distribution controller 700. In this embodiment, an example is shown in which the video signal is distributed to the video signal rate conversion function units 52A, 52B, and 52C in a ratio of 2:1:1. Specifically, the video signal distribution device 500 transmits a video signal with a reduced frame rate to 540 fps, which is 2 / 4 of 1080 fps, to the image processor 300A, and transmits a video signal with a reduced frame rate to 270 fps, which is 1 / 4 of 1080 fps, to the image processors 300B and 300C.

[0068] The video distribution controller 700 controls the video signal distribution device 500 based on the bandwidth of networks 900A, 900B, and 900C (hereinafter sometimes collectively referred to as network 900) and the processing capacity of the image processor 300. In other words, the video distribution controller 700 controls the video signal distribution device 500 to distribute the divided video signals among the multiple image processors 300 based on at least one of the processing capacity of each image processor 300 and information about the network 900 between each image processor 300 and the video signal distribution device 500. The video distribution controller 700 also controls the operation of the video signal distribution device 500 and the video data merging application 61 based on the determined distribution configuration.

[0069] Specifically, as shown in Figure 13, the video distribution controller 700 comprises a distribution determination unit 71, a network information collection unit 72, and a processor information collection unit 73. The network information collection unit 72 is configured to collect information (such as bandwidth) related to the network 900 (network 900A between the video signal distribution device 500 and the image processor 300A, network 900B between the video signal distribution device 500 and the image processor 300B, and network 900C between the video signal distribution device 500 and the image processor 300C). The processor information collection unit 73 is configured to collect information (such as processing capability) related to the image processor 300.

[0070] The distribution determination unit 71 controls the video signal distribution device 500 and the video data merging application 61 based on the information collected by the network information collection unit 72 and the processor information collection unit 73. Specifically, the distribution determination unit 71 controls the distribution ratio of video signals by the video signal distribution device 500 based on the bandwidth of the network 900. For example, if the distance between each image processor 300 and the video signal distribution device 500 is different, the distribution determination unit 71 allocates more video signals to the location where the largest possible bandwidth can be secured.

[0071] Furthermore, the distribution determination unit 71 controls the distribution ratio of video signals by the video signal distribution device 500 based on the processing power of the image processor 300. For example, the distribution determination unit 71 allocates more video signals to the image processor 300, which has higher processing power. In addition, the distribution determination unit 71 controls the operation of the video signal distribution device 500 and the video data merging application 61 based on the determined distribution pattern (distribution ratio).

[0072] Figure 14 shows an example of distribution by the distribution determination unit 71. The table on the left shows the information collected by the network information collection unit 72 and the processor information collection unit 73, and the table on the right shows the distribution result based on that information. In path #1 (for example, the path processed by image processor 300A), the allocatable network capacity is 2 wavelengths and the processing power of the image processor is high. In path #2 (for example, the path processed by image processor 300B), the allocatable network capacity is 1 wavelength and the processing power of the image processor is low. In path #3 (for example, the path processed by image processor 300C), the allocatable network capacity is 1 wavelength and the processing power of the image processor is low. Therefore, the distribution determination unit 71 compares all paths and allocates more video signals to path #1, which has a large allocatable network capacity and high image processor processing power.

[0073] However, the scope of this disclosure is not limited thereto, and the distribution determination unit 71 can determine the distribution ratio based on any information. For example, the distribution determination unit 71 may determine the distribution ratio based on the buffer amount, the number of frames that can be processed, etc.

[0074] According to this embodiment, the processing performed by the image processor 300 can be distributed using the video signal distribution device 500, thereby avoiding processing bottlenecks and enabling high-resolution, long-duration high-speed camera shooting.

[0075] Furthermore, according to this embodiment, by combining the video signal distribution device 500 and the coupling processing device 600, it becomes possible to acquire high-resolution, long-duration high-speed camera video data.

[0076] Furthermore, according to this embodiment, by combining the video signal distribution device 500 and the coupling processing device 600 with the video distribution controller 700, it becomes possible to perform distributed processing in accordance with the processing capacity of the image processor 300 and the performance of the network 900, thereby avoiding bottlenecks.

[0077] The video signal distribution device, image processor, PC, and other devices disclosed herein can also be realized by a computer and a program, and the program can be recorded on a recording medium or provided via a network. The program disclosed herein is a program that causes a computer to realize each function of the device disclosed herein, and a program that causes a computer to execute each procedure of the method executed by the device disclosed herein.

[0078] The video processing system disclosed herein can be applied to the information and communication industry.

[0079] 100, 101, 102, 103, 104: Video processing system 21: Lens 22: Image sensor 200: Shooting unit 300, 300A, 300B, 300C: Image processor 41: Frame grabber 42: HDD / SSD 400A, 400B, 400C: PC 51: Video signal distribution unit 52A, 52B, 52C: Video signal rate conversion function unit 500: Video signal distribution device 61: Video data merging application 62: HDD / SSD 63A, 63B, 63C: Video data reading unit 64: Video data merging processing unit 600: Merging processing unit 71: Distribution judgment unit 72: Network information collection unit 73: Processor information collection unit 700: Video distribution controller 900, 900A, 900B, 900C: Network 100A, 100B: Video processing system 20A: Camera 30A: Image processor 31A: Buffer 32A: Processing unit 40A: PC 41A: Frame grabber 42A: HDD / SSD

Claims

1. A video signal distribution device that divides a video signal from a camera unit that photographs an object at predetermined time intervals, distributes the divided video signals among multiple image processors according to predetermined ratios, and converts the frame rate of each of the divided video signals according to the predetermined ratios.

2. The video signal distribution device according to claim 1, which reads out a start signal or an end signal from the video signal, divides the video signal, and distributes it among the plurality of image processors.

3. A video processing system comprising: a video signal distribution device according to claim 1 or 2; a plurality of image processors that process the divided video signals according to a predetermined ratio; and a combining device that combines the divided video signals in the order in which the plurality of image processors processed them.

4. The video processing system according to claim 3, further comprising a video distribution controller that controls the video signal distribution device to distribute the divided video signals among the plurality of image processors based on at least one of the processing capacity of each image processor and information relating to the network between each image processor and the video signal distribution device.

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