Electronic device and method for supporting single affinity setting

Abstract

The present disclosure provides an electronic device for supporting a single affinity setting. The electronic device may: queue a first task to a first processor core; identify, by using information about an affinity setting, whether the first task is a single affinity task in which an affinity is set to the first processor core; on the basis of identifying that the first task is the single affinity task, acquire information about a waiting time of a second task that is waiting in the first processor core; and change at least one setting associated with the affinity setting on the basis of identifying that the waiting time is greater than a reference waiting time.

Description

Electronic device and method supporting a single affinity setting

[0001] The present disclosure relates to an electronic device and method that support a single affinity setting.

[0002] Recent computing systems optimize performance by utilizing multi-core processors to process multiple tasks simultaneously. Since multiple processor cores in multi-core processors can handle tasks in parallel, processing speed and efficiency are significantly improved. However, in systems using multi-core processors, managing which core executes each task is critical, and this has a major impact on system performance.

[0003] Generally, operating systems (OS) do not assign tasks to specific cores but rather distribute them evenly across all available cores. However, when tasks are distributed across multiple cores, the utilization of cache memory between cores can become inefficient. Consequently, if cache misses occur frequently, task processing performance may degrade and the system's response speed may slow down.

[0004] To address this, affinity settings can be utilized. Through these affinity settings, tasks with applied affinity settings are consistently executed on the specified core(s), thereby maximizing cache utilization and preventing performance degradation.

[0005] The information described above may be provided as related art for the purpose of aiding understanding of the present disclosure. No claim or determination is made as to whether any of the foregoing may be applied as prior art related to the present disclosure.

[0006] According to one embodiment, an electronic device may be provided. The electronic device may include a processor comprising a plurality of processor cores and a memory comprising at least one storage medium for storing instructions. Each processor core includes a processing circuit, and the plurality of processor cores may include a first processor core and a second processor core having different performance. The instructions may cause the electronic device to perform at least one operation when executed individually or collectively by the at least one processor. The at least one operation may include an operation of enqueuing a first task to the first processor core. The at least one operation may include an operation of identifying whether the first task is a single affinity task using information regarding affinity settings. The at least one operation may include an operation of obtaining information regarding the waiting time of a second task waiting at the first processor core based on the identification that the first task is the single affinity task. The above at least one operation may include an operation to change at least one setting associated with the affinity setting based on identifying that the waiting time is greater than the reference waiting time. The single affinity task may be configured to run on the first processor core rather than on another processor core.

[0007] According to one embodiment, a method of operation of an electronic device may be provided. The method of operation of the electronic device may include at least one operation. The at least one operation may include queuing a first task to the first processor core. The at least one operation may include identifying whether the first task is a single affinity task using information regarding an affinity setting. The at least one operation may include obtaining information regarding the waiting time of a second task waiting on the first processor core based on the identification that the first task is the single affinity task. The at least one operation may include changing at least one setting associated with the affinity setting based on the identification that the waiting time is greater than a reference waiting time. The single affinity task may be configured to be executed on the first processor core rather than on another processor core.

[0008] According to one embodiment, a storage medium may be provided for storing at least one instruction readable by a computer. The at least one instruction may cause the electronic device to perform at least one operation when executed by at least a part of at least one processor of the electronic device. The at least one operation may include queuing a first task to the first processor core. The at least one operation may include identifying whether the first task is a single affinity task using information regarding an affinity setting. The at least one operation may include obtaining information regarding the waiting time of a second task waiting at the first processor core based on the identification that the first task is the single affinity task. The at least one operation may include changing at least one setting associated with the affinity setting based on the identification that the waiting time is greater than a reference waiting time. The single affinity task may be configured to be executed on the first processor core rather than on another processor core.

[0009] In relation to the description of the drawings, the same or similar reference numerals may be used for identical or similar components.

[0010] FIG. 1 is a block diagram of an electronic device in a network environment according to various embodiments of the present disclosure.

[0011] FIG. 2a is a block diagram illustrating the configuration of a processor according to one embodiment of the present disclosure.

[0012] FIG. 2b is a diagram illustrating the hierarchical structure of a computing system according to one embodiment of the present disclosure.

[0013] FIG. 3 is a diagram illustrating a method for an electronic device to schedule a task according to one embodiment of the present disclosure.

[0014] FIG. 4 is a flowchart illustrating an operation for an electronic device to change at least one setting associated with a single affinity setting, according to one embodiment of the present disclosure.

[0015] FIG. 5 is a flowchart illustrating an operation for an electronic device to change at least one setting associated with a single affinity setting, according to one embodiment of the present disclosure.

[0016] FIG. 6 is a diagram illustrating an operation for changing at least one setting associated with a single affinity setting according to one embodiment of the present disclosure.

[0017] FIG. 7 is a flowchart illustrating the operation of an electronic device dequeuing a task according to one embodiment of the present disclosure.

[0018] FIG. 8 is a flowchart illustrating the operation of an electronic device applying a single affinity setting based on processor temperature information according to one embodiment of the present disclosure.

[0019] Hereinafter, embodiments of the present disclosure are described in detail with reference to the drawings so that those skilled in the art can easily practice them. However, the present disclosure may be embodied in various different forms and is not limited to the embodiments described herein. In relation to the description of the drawings, the same or similar reference numerals may be used for identical or similar components. Furthermore, in the drawings and related descriptions, descriptions of well-known functions and configurations may be omitted for clarity and brevity.

[0020] FIG. 1 is a block diagram of an electronic device in a network environment according to various embodiments of the present disclosure.

[0021] Referring to FIG. 1, in a network environment (100), an electronic device (101) may communicate with an electronic device (102) through a first network (198) (e.g., a short-range wireless communication network) or with an electronic device (104) or a server (108) through a second network (199) (e.g., a long-range wireless communication network). According to one embodiment, the electronic device (101) may communicate with the electronic device (104) through a server (108). According to one embodiment, the electronic device (101) may include a processor (120), memory (130), input module (150), sound output module (155), display module (160), audio module (170), sensor module (176), interface (177), connection terminal (178), haptic module (179), camera module (180), power management module (188), battery (189), communication module (190), subscriber identification module (196), or antenna module (197). In some embodiments, at least one of these components (e.g., connection terminal (178)) may be omitted from the electronic device (101), or one or more other components may be added. In some embodiments, some of these components (e.g., sensor module (176), camera module (180), or antenna module (197)) may be integrated into a single component (e.g., display module (160)).

[0022] The processor (120) can control at least one other component (e.g., hardware or software component) of the electronic device (101) connected to the processor (120) by executing software (e.g., program (140)), for example, and can perform various data processing or operations. According to one embodiment, as at least part of the data processing or operations, the processor (120) can store commands or data received from other components (e.g., sensor module (176) or communication module (190)) in volatile memory (132), process the commands or data stored in volatile memory (132), and store the resulting data in non-volatile memory (134). According to one embodiment, the processor (120) may include a main processor (121) (e.g., central processing unit or application processor) or an auxiliary processor (123) that can operate independently or together with it (e.g., graphics processing unit, neural processing unit (NPU), image signal processor, sensor hub processor, or communication processor). For example, if the electronic device (101) includes a main processor (121) and an auxiliary processor (123), the auxiliary processor (123) may be configured to use less power than the main processor (121) or to be specialized for a designated function. The auxiliary processor (123) may be implemented separately from the main processor (121) or as part thereof.

[0023] The auxiliary processor (123) may control at least some of the functions or states associated with at least one component of the electronic device (101) (e.g., display module (160), sensor module (176), or communication module (190)) on behalf of the main processor (121) while the main processor (121) is in an inactive (e.g., sleep) state, or together with the main processor (121) while the main processor (121) is in an active (e.g., application execution) state. According to one embodiment, the auxiliary processor (123) (e.g., image signal processor or communication processor) may be implemented as part of another functionally related component (e.g., camera module (180) or communication module (190)). According to one embodiment, the auxiliary processor (123) (e.g., neural network processing unit) may include a hardware structure specialized for processing an artificial intelligence model. The artificial intelligence model may be generated through machine learning. Such learning may be performed, for example, on the electronic device (101) itself where the artificial intelligence is performed, or through a separate server (e.g., server (108)). The learning algorithm may include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model may include a plurality of artificial neural network layers.An artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to the hardware structure, the artificial intelligence model may include a software structure, either additionally or substantially.

[0024] The memory (130) can store various data used by at least one component of the electronic device (101) (e.g., processor (120) or sensor module (176)). The data may include, for example, input data or output data for software (e.g., program (140)) and related commands. The memory (130) may include volatile memory (132) or non-volatile memory (134).

[0025] The program (140) may be stored as software in memory (130) and may include, for example, an operating system (142), middleware (144), or an application (146).

[0026] The input module (150) can receive commands or data to be used for a component of the electronic device (101) (e.g., processor (120)) from outside the electronic device (101) (e.g., user). The input module (150) may include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0027] The sound output module (155) can output a sound signal to the outside of the electronic device (101). The sound output module (155) may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as multimedia playback or recording playback. The receiver may be used to receive incoming calls. According to one embodiment, the receiver may be implemented separately from the speaker or as part thereof.

[0028] The display module (160) can visually provide information to an external (e.g., user) of the electronic device (101). The display module (160) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling said device. According to one embodiment, the display module (160) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of the force generated by said touch.

[0029] The audio module (170) can convert sound into an electrical signal or, conversely, convert an electrical signal into sound. According to one embodiment, the audio module (170) can acquire sound through the input module (150) or output sound through the sound output module (155) or an external electronic device (e.g., electronic device (102)) (e.g., speaker or headphones) connected directly or wirelessly to the electronic device (101).

[0030] The sensor module (176) can detect the operating state of the electronic device (101) (e.g., power or temperature) or the external environmental state (e.g., user state) and generate an electrical signal or data value corresponding to the detected state. According to one embodiment, the sensor module (176) may include, for example, a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0031] The interface (177) may support one or more specified protocols that can be used for the electronic device (101) to be connected directly or wirelessly to an external electronic device (e.g., electronic device (102)). According to one embodiment, the interface (177) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0032] The connection terminal (178) may include a connector through which the electronic device (101) can be physically connected to an external electronic device (e.g., electronic device (102)). According to one embodiment, the connection terminal (178) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0033] The haptic module (179) can convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus that the user can perceive through tactile or kinesthetic senses. According to one embodiment, the haptic module (179) may include, for example, a motor, a piezoelectric element, or an electric stimulation device.

[0034] The camera module (180) can capture still images and video. According to one embodiment, the camera module (180) may include one or more lenses, image sensors, image signal processors, or flashes.

[0035] The power management module (188) can manage the power supplied to the electronic device (101). According to one embodiment, the power management module (188) can be implemented, for example, as at least part of a power management integrated circuit (PMIC).

[0036] The battery (189) can supply power to at least one component of the electronic device (101). According to one embodiment, the battery (189) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0037] The communication module (190) can support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between an electronic device (101) and an external electronic device (e.g., electronic device (102), electronic device (104), or server (108)), and the performance of communication through the established communication channel. The communication module (190) may include one or more communication processors that operate independently of the processor (120) (e.g., application processor) and support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (190) may include a communication module (192) (e.g., cellular communication module, short-range communication module, or GNSS (global navigation satellite system) communication module) or a wired communication module (194) (e.g., LAN (local area network) communication module, or power line communication module). The corresponding communication module among these communication modules can communicate with an external electronic device (104) through a first network (198) (e.g., a short-range communication network such as Bluetooth, WiFi (wireless fidelity) direct, or IrDA (infrared data association)) or a second network (199) (e.g., a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules may be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The communication module (192) can identify or authenticate the electronic device (101) within a communication network such as the first network (198) or the second network (199) using subscriber information (e.g., International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module (196).

[0038] The communication module (192) can support 5G networks and next-generation communication technologies following 4G networks, for example, new radio access technology. NR access technology can support high-speed transmission of high-capacity data (enhanced mobile broadband (eMBB)), minimization of terminal power and connection of multiple terminals (massive machine type communications (mMTC)), or high reliability and low latency (ultra-reliable and low-latency communications (URLLC)). The communication module (192) can support a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate, for example. The communication module (192) can support various technologies for securing performance in the high-frequency band, such as beamforming, massive MIMO (multiple-input and multiple-output), full-dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large-scale antenna. The communication module (192) can support various requirements specified in the electronic device (101), external electronic device (e.g., electronic device (104)), or network system (e.g., second network (199)). According to one embodiment, the communication module (192) can support a Peak data rate (e.g., 20 Gbps or more) for eMBB realization, loss coverage (e.g., 164 dB or less) for mMTC realization, or U-plane latency (e.g., downlink (DL) and uplink (UL) each 0.5 ms or less, or round trip 1 ms or less) for URLLC realization.

[0039] An antenna module (197) can transmit a signal or power to or from an external source (e.g., an external electronic device). According to one embodiment, the antenna module (197) may include an antenna comprising a radiator made of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). According to one embodiment, the antenna module (197) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as a first network (198) or a second network (199), may be selected from the plurality of antennas, for example, by a communication module (190). A signal or power may be transmitted or received between the communication module (190) and an external electronic device through the selected at least one antenna. According to some embodiments, in addition to the radiator, other components (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as part of the antenna module (197).

[0040] According to various embodiments, the antenna module (197) may form a mmWave antenna module. According to one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent to a first surface (e.g., bottom surface) of the printed circuit board and capable of supporting a specified high frequency band (e.g., mmWave band), and a plurality of antennas (e.g., array antennas) disposed on or adjacent to a second surface (e.g., top surface or side surface) of the printed circuit board and capable of transmitting or receiving a signal of the specified high frequency band.

[0041] At least some of the above components can be connected to each other via a communication method between peripheral devices (e.g., bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface) and exchange signals (e.g., commands or data) with each other.

[0042] According to one embodiment, commands or data may be transmitted or received between the electronic device (101) and an external electronic device (104) through a server (108) connected to a second network (199). Each of the external electronic devices (102, or 104) may be the same or different type of device as the electronic device (101). According to one embodiment, all or part of the operations performed on the electronic device (101) may be performed on one or more of the external electronic devices (102, 104, or 108). For example, if the electronic device (101) needs to perform a function or service automatically or in response to a request from a user or another device, the electronic device (101) may request one or more external electronic devices to perform at least part of the function or service instead of performing the function or service itself or additionally. One or more external electronic devices that receive the above request may execute at least part of the requested function or service, or additional function or service related to the request, and transmit the result of the execution to the electronic device (101). The electronic device (101) may provide the result as is or additionally processed as at least part of the response to the request. For this purpose, for example, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used. The electronic device (101) may provide ultra-low latency services using, for example, distributed computing or mobile edge computing. In one embodiment, the external electronic device (104) may include an Internet of Things (IoT) device. The server (108) may be an intelligent server using machine learning and / or neural networks. According to one embodiment, the external electronic device (104) or the server (108) may be included within a second network (199).The electronic device (101) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0043] FIG. 2a is a block diagram illustrating the configuration of a processor according to one embodiment of the present disclosure. FIG. 2b is a diagram illustrating the hierarchical structure of a computing system according to one embodiment of the present disclosure.

[0044] The components and operations of the components described with reference to FIG. 2a and 2b may be, in part or in whole, identical to the components and operations of the components described with reference to FIG. 1. The components and operations of the components described with reference to FIG. 2a and 2b may be, in part or in whole, identical to the components and operations of the components described with reference to FIG. 3 through 8, which will be described later.

[0045] Referring to FIG. 2a, the electronic device (101) may include at least one processor (200) (e.g., the processor (120) of FIG. 1).

[0046] According to one embodiment, at least one processor (200) can control the overall operation of the electronic device (101) and perform at least one operation of the electronic device (101) (e.g., at least one of the operations described above in FIGS. 1 to 8). The processor (200) can perform operations or data processing regarding the control and / or communication of at least one other component of the electronic device (101). The processor (200) may include at least one processing circuit that executes instructions stored in memory (e.g., memory (130) of FIG. 1). For example, when instructions stored in memory (e.g., memory (130) of FIG. 1) are executed individually and / or collectively by at least one processor (200), they may cause the electronic device (101) to perform at least one operation (e.g., at least one of the operations described above in FIGS. 1 to 8).

[0047] According to one embodiment, at least one processor (200) may include various processing circuits and / or multiple processors. One or more of the at least one processor (200) may be configured to perform various functions described in this disclosure individually and / or collectively. Where in this disclosure, "processor," "at least one processor," and "one or more processors" are described as being configured to perform various functions, these terms may cover, for example, a situation in which one processor performs some of the cited functions and other processor(s) perform other parts of the cited functions, and may also cover, but are not limited to, a situation in which a single processor can perform all of the cited functions. Additionally, at least one processor (200) may include a combination of processors performing the cited / disclosed various functions, for example, in a distributed manner. At least one processor (200) may execute program instructions to achieve or perform various functions.

[0048] According to one embodiment, at least one processor (200) may include at least one of a CPU (central processing unit), NPU (graphics processing unit), MPU (micro processing unit), MCU (micro controller unit), AP (application processor), CP (communication processor), SoC (system on chip), or IC (integrated circuit) sensor hub, supplementary processor, ASIC (application specific integrated circuit), or FPGA (field programmable gate arrays), and may have multiple cores.

[0049] According to one embodiment, at least one processor (200) (e.g., CPU) may be a multicore processor comprising a plurality of processor cores (e.g., CPU cores). For example, at least one processor (200) may be a multicore processor comprising eight processor cores (e.g., processor core #0 (e.g., CPU0) to processor core #7 (e.g., CPU7) of FIG. 2a). Each processor core may include processing circuits and / or memory.

[0050] According to one embodiment, a multicore processor can process multiple tasks simultaneously. A task may be a unit of a job (or function) that can be executed in a computing system. A task may consist of a series of instructions that a processor (or processor core) must process to perform a specific purpose. A task may be associated with a process or a thread. A task may be implemented, for example, as a process and / or a thread. A process may be an instance of a running program (or application). A process may be, for example, a unit of execution that performs a single task. When a program (or application) is executed, the operating system (OS) allocates resources such as memory and a processor to the program and may create a process, which is an independent unit of execution. A thread may be a unit of execution for tasks that are executed in parallel within a process. A process may be divided into multiple threads to process multiple tasks in parallel. Each process may have an independent memory space. Each thread within a process may share the same memory space. In this disclosure, a processor core may be abbreviated as a core.

[0051] According to one embodiment, at least some of the processor cores of the processor (200) may provide different performance (e.g., maximum performance). For example, the first processor core of the processor (200) (e.g., processor core #7 in FIG. 2a) may be a big core, which is a high-performance core, and the second processor core (e.g., processor core #0 in FIG. 2a) may be a little core, which is a low-power core. The big core may be a core suitable for handling tasks requiring high computational performance (e.g., processes or threads requiring high performance). Although the big core consumes more power than the little core, it may include a higher clock speed and a larger cache memory. The little core is a core that consumes less power than the big core and may be used, for example, to handle low-load tasks (e.g., processes or threads that do not require fast processing).

[0052] According to one embodiment, at least some of the processor cores of the processor (200) may provide the same performance (e.g., maximum performance). For example, the first processor core (e.g., processor core #7 in FIG. 2a) and the third processor core (e.g., processor core #6 in FIG. 2a) of the processor (200) may be big cores providing the same performance. For example, the second processor core (e.g., processor core #0 in FIG. 2a) and the fourth processor core (e.g., processor core #1 in FIG. 2a) of the processor (200) may be little cores providing the same performance.

[0053] According to one embodiment, the processor (200) can determine which processor core to assign a process to based on affinity settings, the priority of the process, the attributes (or characteristics) and / or load of the process through a kernel layer scheduler (e.g., the kernel scheduler (220) of FIG. 2b).

[0054] Meanwhile, in the embodiment of FIG. 2a, the processor (200) is described as an octa-core having eight processor cores, but the embodiments of the present disclosure are not limited thereto. For example, the processor (200) may be composed of any one of a dual core, triple core, quad core, hexa core, or octa core.

[0055] Referring to FIG. 2b, an electronic device (101) (or a computing system of the electronic device (101)) may include an application layer (201), a kernel layer (202), and / or a hardware layer (203). The hardware layer (203) may be included in a platform that provides an environment in which an OS runs. The platform may include hardware such as a processor and memory, as well as software such as a framework and an API (application programming interface) (e.g., a system call API). In the embodiment of FIG. 2b, for convenience of explanation, the processor (230) located in the hardware layer (203) (e.g., the processor (120) of FIG. 1 or the processor (200) of FIG. 2a) is described as an example of a CPU system including a plurality of CPUs or a plurality of CPU cores (e.g., CPU0 to CPU7). However, the embodiment is not limited thereto, and the same description may apply even if a different type of processor (e.g., an NPU, a GPU) including a plurality of processor cores is located in the hardware layer (203).

[0056] According to one embodiment, the application layer (201) may be a layer where an application (210) (e.g., the application (146) of FIG. 1) (or a program) that the user interacts with directly is located. The application layer (201) may allow the application (210) to interact with the OS or hardware through various software frameworks and APIs.

[0057] According to one embodiment, the application (210) may include, for example, a program executed by the user's selection. The application (210) may be executed based on an OS. The application (210) may provide various services, such as games, text editing, and media playback. In the present disclosure, the application (210) may be referred to as an app.

[0058] According to one embodiment, the kernel layer (202) is the center of the OS and can act as an intermediary between the application layer (201) and the hardware layer (203). The kernel layer (202) can forward requests from the application layer (201) to the hardware layer (203). The kernel layer (202) can manage hardware resources such as the processor (230) and memory. For example, the kernel layer (202) can perform management functions such as memory management, process management, file system management, and network management.

[0059] According to one embodiment, the kernel layer (202) may include a kernel scheduler (220). The kernel scheduler (220) may manage the state of a process (or task) and allocate resources of the processor (230), such as CPU time, to the process (or task). The kernel scheduler (220) may determine which process or thread (or task) to execute on a processor core (e.g., CPU core) based on at least one setting (e.g., affinity setting). In the present disclosure, the kernel scheduler (220) may be abbreviated as a scheduler.

[0060] According to one embodiment, the kernel scheduler (220) may use various scheduling methods so that the management of processor resources (e.g., CPU resources) is performed efficiently. For example, a real-time scheduling method (hereinafter referred to as RT (real-time) scheduling method) and a completely fair scheduler (CFS) scheduling method may be used for scheduling.

[0061] According to one embodiment, the RT scheduling method is based on a real-time scheduler and can preempt processor resources based on high priority. The CFS scheduling method is based on a CFS scheduler and can be used to allocate processor resources fairly. The CFS scheduling method can be used to allocate processor resources to processes included in a control group based on processor resource usage determined per control group.

[0062] According to one embodiment, the kernel scheduler (220) may include a runnable check module (221), an affinity control module (222), a load balancer control module (223) and / or a priority control module (224).

[0063] According to one embodiment, a runnable check module (221) can monitor the state of a processor (230) to obtain state information of the processor (230). The state information may include, for example, information regarding a runnable delay or a delay time for a task(s) in a runnable state. A runnable state may correspond to a state in which a task is executable. A delay time may correspond to the time until a task in a runnable state transitions to a running state. The runnable check module (221) may periodically obtain state information of each processor core (e.g., CPU core). The runnable check module (221) may transmit the obtained information to an affinity control module (222), a load balancer control module (223), and / or a priority control module (224).

[0064] According to one embodiment, the affinity control module (222) can control the affinity setting. For example, the affinity control module (222) can process a request for an affinity setting (an affinity request) from an application (210) via a system call. The affinity setting may be set by a developer, for example, during the design of the application (210) (or program). The set affinity setting may be included in the data (or code) of the application (210). The affinity setting included in the data (or code) of the application (210) may be transmitted to an electronic device (101) via a communication circuit (e.g., the communication module (190) of FIG. 1) during the distribution of the application (210). When an application (210) in an electronic device (101) is installed, an affinity setting may be enabled, and when the application (210) is executed, an affinity request may be transmitted to an affinity control module (222) through the invocation of a system call for the affinity setting, so that the affinity setting may be applied. While the affinity setting is applied, information regarding the affinity setting may be stored in the affinity control module (222). Based on the fact that the affinity request is a request for a single affinity setting, the affinity control module (222) may process the task so that it is executed only on a designated (or fixed) single processor core (e.g., CPU7). For example, the affinity control module (222) may disable the affinity setting upon request or upon the occurrence of a designated event. The affinity control module (222) may contain (or store) information regarding the affinity setting. Information about the affinity setting may include, for example, information about the tasks and processor cores bound by the affinity setting (e.g., task ID (or process ID), processor core ID).

[0065] According to one embodiment, the load balancer control module (223) can control the load balancer (or load balancer function). The load balancer function may be a function that distributes tasks waiting on a specific processor core (e.g., CPU7) in a multi-core processor to at least one other processor core (e.g., CPU6). For example, the load balancer control module (223) can monitor the status of each CPU core and assign tasks to the most suitable CPU core. For example, the load balancer control module (223) can monitor the status of the CPU core to which a task is assigned and redistribute the task to another CPU core based on whether the CPU core is in an overloaded state. Through this, the load on each CPU core is maintained evenly, and tasks are prevented from being concentrated on a specific CPU core, thereby improving the performance of the entire system.

[0066] According to one embodiment, the priority control module (224) can set the priority of a task (e.g., scheduling priority) and schedule the task based on the priority. For example, the priority control module (224) can process a request for setting the priority of a task from an application (210) via a system call. The priority setting may be a setting of how much scheduling a task can be allocated. The priority control module (224) can set the priority within the RT priority or CFS range. The RT priority can always have a higher priority than the CFS. In the case of the CFS, the priority can be determined by a nice value (e.g., set within the range of -20 to 19). For example, the lower the nice value, the higher the priority. Through the operation of this priority control module (224), the electronic device can optimize processor resources and process necessary tasks quickly.

[0067] According to one embodiment, the hardware layer (203) may include at least one hardware configuration (e.g., a processor) of the electronic device (101). For example, the hardware layer (203) may include a processor (230) including a plurality of CPU cores (e.g., CPU0 to CPU8).

[0068] Hereinafter, with reference to FIG. 2b, the operation for setting affinity is described. For convenience of explanation, the single affinity setting is applied to CPU7, which corresponds to the big core, as an example. However, the embodiment is not limited thereto, and the single affinity setting may also be applied to other CPU cores (e.g., CPU0, which corresponds to the little core).

[0069] According to one embodiment, an affinity or affinity setting may be a setting that specifies at least one processor core (e.g., CPU core) on which a process or thread corresponding to a task can be executed. A task with affinity set for a specific processor core(s) may be bound to that processor core(s). In other words, a task with affinity set for a specific processor core(s) may be executed only on that processor core(s). Through such an affinity setting, the performance of the processor can be optimized and resource contention between processes can be reduced.

[0070] According to one embodiment, a single affinity or a single affinity setting may be a setting that designates a processor core (e.g., a CPU core) on which a process or thread corresponding to a task can be executed as a single processor core. A task with affinity set for a single processor core may be bound only to that processor core. In other words, a task with a single affinity set may be executed only on a single processor core. In the present disclosure, a task with a single affinity set may be defined and referred to as a single affinity task. Meanwhile, when a single affinity is set, the designated processor core may be monopolized for the execution of the task. In this case, a delay (e.g., scheduling delay) may occur for other task(s) waiting to be executed on that processor core.

[0071] According to one embodiment, the electronic device (101) can select and use a high-performance CPU or a low-performance CPU through an affinity setting depending on performance. For example, if it is desired to run a thread running in a process only on a specific CPU, the electronic device (101) can use an affinity system call to set the affinity to a high-performance CPU for a thread requiring high performance and to set the affinity to a power-efficient CPU for a low-performance thread to run.

[0072] Referring to FIG. 2b, according to one embodiment, an application (210) may transmit an affinity request (21) (an affinity setting request) for CPU7 to a kernel scheduler (220) via a system call (e.g., an affinity system call). Based on the affinity request (21), the kernel scheduler (220) may designate CPU7 as the CPU core for the execution of the corresponding task via an affinity control module (222). The kernel scheduler (220) may assign (22) a process ID (PID) of the process corresponding to the task and transmit the assigned PID to CPU7. Through this single affinity setting process, the process may be executed only on the designated CPU7. Meanwhile, according to the method described above, the affinity setting (e.g., a single affinity setting) set via a system call is not always guaranteed to operate as intended and may change depending on the system's situation and policy.

[0073] FIG. 3 is a diagram illustrating a method for an electronic device to schedule a task according to one embodiment of the present disclosure.

[0074] The components and operations of the components described with reference to FIG. 3 may be, in part or in whole, identical to the components and operations of the components described with reference to FIG. 1 to 2b. The components and operations of the components described with reference to FIG. 3 may be, in part or in whole, identical to the components and operations of the components described with reference to FIG. 4 to 8, which will be described later.

[0075] In the embodiment of FIG. 3, for convenience of explanation, the first task (301) and the second task (302) are assigned to one processor core (hereinafter, the first processor core) (e.g., CPU7 or CPU0 in FIG. 2b), and the first task (301) corresponds to a single affinity task with a single affinity set for the first processor core and has a higher priority (e.g., schedule priority) than the second task (302). However, the embodiment is not limited thereto. For example, the second task (302) may have a higher priority than the first task (301). For example, at least one other task (e.g., a third task) may be additionally assigned to the first processor core. In this case as well, the same description as FIG. 3 may apply to the example.

[0076] Referring to FIG. 3, an electronic device (e.g., the electronic device (101) of FIG. 1) can enqueue a first task (301) corresponding to a single affinity task at a first time point (t1). By doing so, the first task (301) can be added to the queue of a first processor core. The electronic device can execute the first task by allocating resources (e.g., CPU time) of the first processor core to the first task (301) at a second time point (t2). During the period from the first time point (t1) to the second time point (t2), the first task may be in a waiting state (or, runnable state), and after the second time point (t2), the first task may be in an execution state.

[0077] According to one embodiment, the electronic device may queue the second task (302) at a third time point (t3). For example, the electronic device may queue the second task (302) while the first task (301) is being executed. This allows the second task (302) to be added to the queue along with the first task (301). As illustrated in FIG. 3, the third time point (t3) may be a time point after the second time point, but is not limited thereto. For example, the third time point (t3) may be a time point between the first time point (t1) and the second time point (t2), or a time point before the first time point (t1).

[0078] According to one embodiment, the electronic device can keep the second task (302) added to the queue of the first processor core in a waiting state because the resources of the first processor core are allocated to the first task (301), that is, because the first task (301) is scheduled. Meanwhile, the first task (301) is a single affinity task and because the priority of the first task (301) is high, the first task (301) can monopolize the resources of the first processor core. In this case, the second task (302) may remain in a waiting state. For example, as illustrated in FIG. 3, the second task (302) may remain in a waiting state for a waiting time (320) (e.g., t5-t3, where the current time (t5) may be the time at which the waiting time (320) of the second task is measured) longer than the reference waiting time (321) (e.g., t4-43). This can delay the entire system and compromise system stability. For example, if a third-party application (app) indiscriminately sets a single affinity and high priority for task(s), this can hinder the processing of essential tasks, causing phenomena such as panic or watchdog, which may compromise system stability. For example, if the second task (302) is a task that needs to be processed, the delay in processing the essential task due to the monopolization of processor resources by the first task (301) can compromise system stability. Therefore, to stabilize the system, a solution is required to resolve the monopolization of processor resources by tasks with a single affinity set.

[0079] FIG. 4 is a flowchart illustrating an operation for an electronic device to change at least one setting associated with a single affinity setting, according to one embodiment of the present disclosure.

[0080] The components and operations of the components described with reference to FIG. 4 may be, in part or in whole, identical to the components and operations of the components described with reference to FIG. 1 to 3. The components and operations of the components described with reference to FIG. 4 may be, in part or in whole, identical to the components and operations of the components described with reference to FIG. 5 to 8, which will be described later.

[0081] According to one embodiment, at least one of the operations of FIG. 4 may be performed by a scheduler (e.g., kernel scheduler (220) of FIG. 2b) of an electronic device (e.g., electronic device (101) of FIG. 1).

[0082] Referring to FIG. 4, according to one embodiment, in operation 410, the electronic device may queue a first task (e.g., the first task (301) of FIG. 3) to a first processor core (e.g., processor core #7 of FIG. 2a or CPU7 of FIG. 2b). By doing so, the first task may be added to the queue of the first processor core.

[0083] According to one embodiment, in operation 420, the electronic device may identify (or determine) whether the first task is a single affinity task for which affinity (single affinity) is set for a first processor core within a processor (e.g., processor (200) of FIG. 2a or processor (230) of FIG. 2b), based on the identification that the first task is queued. For example, when the electronic device identifies that the first task is queued, it may identify whether the first task is a single affinity task for the first processor core based on information regarding the affinity setting.

[0084] According to one embodiment, when it is identified that a first task is queued, the electronic device can identify whether the first task is a single affinity task for the first processor core based on information regarding an affinity setting (hereinafter referred to as affinity setting information). For example, in response to the identification that the first task is queued, the electronic device can identify that the first task is a single affinity task for the first processor core by identifying that an affinity setting is applied to the first task based on the affinity setting information and that the affinity setting is a single affinity setting for the first processor core. For example, in response to the identification that the first task is queued, the electronic device can identify that the first task is not a single affinity task for the first processor core by identifying that an affinity setting is applied to the first task based on the affinity setting information and that the affinity setting is not a single affinity setting for the first processor core. For example, in response to the identification that the first task is queued, the electronic device can identify that the first task is not a single affinity task for the first processor core by identifying that no affinity setting is applied to the first task based on the affinity setting information.

[0085] According to one embodiment, in operation 430, the electronic device may change at least one setting associated with an affinity setting based on the identification that the first task is a single affinity task for the first processor core. For example, the electronic device may perform an operation of releasing the affinity setting of the first task for a specified time in response to the identification that the first task is a single affinity task for the first processor core. For example, the electronic device may perform an operation of lowering the priority of the first task to a specified priority (base priority) or lower for a specified time in response to the identification that the first task is a single affinity task for the first processor core. In this way, the delay caused by the single affinity setting may be resolved for a specified period.

[0086] According to one embodiment, in operation 440, the electronic device may schedule the first task to the first processor core using at least one setting for the first task based on the identification that the first task is not a single affinity task for the first processor core. The at least one setting for the first task may include, for example, an affinity setting for the first task, a setting related to the attribute (or characteristic) of the first task, a priority setting for the first task, and / or a type setting for the first task. The operation of scheduling the first task to the first processor core may include, for example, an operation of allocating a resource (e.g., time) of the first processor core to the first task.

[0087] In the embodiment of FIG. 4 described above, when a first task with single affinity is identified without considering the waiting time of other task(s) added to the queue of the first processor core along with the first task, which is a single affinity task, the single affinity setting of the first task can be immediately released or the priority of the first task can be lowered. Through this, delays caused by the single affinity setting can be eliminated. However, this method may result in ignoring system call situations associated with the single affinity setting by the developer of the application (e.g., the application (210) of FIG. 2b) without considering circumstances such as the occurrence of delays.

[0088] FIG. 5 is a flowchart illustrating an operation for an electronic device to change at least one setting associated with a single affinity setting, according to one embodiment of the present disclosure.

[0089] FIG. 6 is a diagram illustrating an operation for changing at least one setting associated with a single affinity setting according to one embodiment of the present disclosure.

[0090] The components and operations of the components described with reference to FIGS. 5 and 6 may be, in part or in whole, identical to the components and operations of the components described with reference to FIGS. 1 and 4. The components and operations of the components described with reference to FIGS. 5 and 6 may be, in part or in whole, identical to the components and operations of the components described with reference to FIGS. 7 and 8, which will be described later.

[0091] According to one embodiment, at least one of the operations of FIG. 5 may be performed by a scheduler of an electronic device (e.g., the electronic device (101) of FIG. 1) (e.g., the kernel scheduler (220) of FIG. 2b).

[0092] Referring to FIG. 5, according to one embodiment, in operation 510, the electronic device may queue a first task (e.g., the first task (301) of FIG. 3) to a first processor core (e.g., processor core #7 of FIG. 2a or CPU7 of FIG. 2b). Operation 510 of FIG. 5 may include, for example, operation 410 of FIG. 4.

[0093] According to one embodiment, in operation 520, the electronic device may identify (or determine) whether the first task is a single affinity task for which affinity (single affinity) for the first processor core in the processor is set, based on the identification that the first task is queued. Operation 520 of FIG. 5 may include, for example, operation 420 of FIG. 4. If it is identified that the first task is a single affinity task for the first processor core, operation 530 may be performed. If it is identified that the first task is not a single affinity task for the first processor core, operation 560 may be performed.

[0094] According to one embodiment, in operation 530, the electronic device may obtain (or monitor) information regarding the waiting time (e.g., waiting time (320) of FIG. 3) of a second task waiting on the first processor core (e.g., second task (302) of FIG. 3) based on the identification that the first task is a single affinity task for the first processor core. The waiting time of the second task may correspond, for example, to the period during which the second task is in a waiting state. The second task may be in a waiting state, for example, until it is transitioned from a runnable state to a running state. In the present disclosure, the waiting time may be referred to as a delay time, a runnable delay, or a runnable delay time.

[0095] According to one embodiment, the second task may be a task queued to the first processor core after the first task has been queued to the first processor core. In other words, the second task may be a task added to the queue after the first task has been added to the queue of the first processor core. For example, the second task may be a task added to the queue of the first processor core while, for instance, the first task is in execution. However, the timing of the queuing of the second task is not limited thereto, and the embodiments of the present disclosure may also apply, for example, even when the second task is queued before the first task and is in a waiting state due to the execution of the first task.

[0096] According to one embodiment, the electronic device can obtain information about the waiting time of the second task while the first task is running. For example, while the first task is running, the electronic device can obtain information about the waiting time of the second task by using a runnable check module (e.g., the runnable check module (221) of FIG. 2b).

[0097] According to one embodiment, the electronic device may periodically obtain information regarding the waiting time of a second task. For example, the electronic device may periodically obtain information regarding the waiting time of a second task according to a specified period (e.g., a scheduled tick period (e.g., 8ms)). The electronic device may update a delayed task list according to the scheduled tick period and obtain information regarding the waiting time (delay time) of the delayed task(s) included in the delayed task list.

[0098] According to one embodiment, in operation 540, the electronic device can identify whether the waiting time is longer than a reference waiting time (e.g., reference waiting time (321) of FIG. 3). According to one embodiment, the reference waiting time can be set in various ways by considering factors such as the properties (or characteristics) of the process and the performance of the processor. If the waiting time is not longer than the reference waiting time, operation 530 may be performed again. For example, if the waiting time is not longer than the reference waiting time (e.g., a short runnable delay case), the electronic device may wait for a specified time (e.g., a time corresponding to a schedule tick period (e.g., 8ms)) and perform operation 530 again after that time has elapsed. Through this, information regarding the waiting time of the second task waiting on the first processor core can be obtained again at a specified period. If the waiting time is longer than the reference waiting time, operation 550 may be performed.

[0099] According to one embodiment, in operation 550, the electronic device may change at least one setting associated with an affinity setting (or affinity) based on the identification that the waiting time is longer than the reference waiting time (e.g., a long runnable delay case). The at least one setting associated with the affinity setting (or affinity) may include, for example, at least one setting for a first task with a single affinity set and / or at least one setting for a delay task (e.g., a second task) in which a delay occurs due to the first task with a single affinity set. The operation of changing at least one setting may be performed for the execution of a task (e.g., a second task) in which the waiting time is longer than the reference waiting time. Through this operation, the delay caused by the single affinity setting is resolved, and system stability may be maintained. Examples of the operation of changing at least one setting associated with the affinity setting (or affinity) of operation 550 are described below with reference to FIG. 6.

[0100] According to one embodiment, in operation 560, the electronic device may schedule the first task to the first processor core using at least one setting for the first task based on the identification that the first task is not a single affinity task for the first processor core. Operation 560 of FIG. 5 may include, for example, operation 440 of FIG. 4.

[0101] Referring to FIG. 6, according to one embodiment, an operation to change at least one setting (e.g., operation 430 of FIG. 4 or operation 550 of FIG. 5) may include at least one of the following operations:

[0102] - An operation (610) to release the affinity setting of the first task. For example, the electronic device may perform an operation to release the affinity setting of the first task (e.g., a single affinity setting) for a specified time. Through this method of operation 610, the excess of processor resources caused by the single affinity setting is released for a specified time, and the delay for the waiting task can be resolved.

[0103] - An action (620) of changing at least one setting to immediately execute a specified task running within a limited resource (e.g., a task associated with a kernel task (e.g., Bounded Kworker)). For example, the electronic device may perform an action of changing at least one setting associated with an affinity setting so that the second task is immediately executed based on the identification that the second task is a task associated with a kernel thread running within a limited resource. For example, to immediately execute the second task, the electronic device may set the priority of the second task to the highest priority, disable the single affinity setting of the first task, and set the priority of the first task to a lower priority than that of the second task. Through this method of action 620, an essential task (or critical task) among the waiting tasks may be immediately executed, thereby resolving the processing delay of the essential task (e.g., kernel task) caused by the single affinity setting.

[0104] - An action (630) to lower the priority of the first task. For example, the electronic device may perform an action to lower the priority of the first task (e.g., schedule priority) to a specified priority (base priority) or lower for a specified period of time. The base priority may be set, for example, to a priority corresponding to a specified value (e.g., a priority corresponding to a value of 0 among nice values ​​that can be set from -20 to 19), the priority of the second task, or a priority lower than the priority of the second task. The action 630 may be performed, for example, when the priority of the first task is set higher than the specified priority. Meanwhile, according to an embodiment, the electronic device may set the priority of the first task (e.g., schedule priority) to the lowest priority among the priorities that can be set for a specified period of time. Through this method of action 630, more processor resources may be allocated to waiting tasks, and delays caused by a single affinity setting may be eliminated.

[0105] - An operation (640) of adjusting a threshold value at which the load balancer operates to distribute the second task to another processor core. For example, the electronic device may use a load balancer control module (e.g., the load balancer control module (223) of FIG. 2b) to perform an operation of adjusting a threshold value (e.g., an imbalance value) at which the load balancer operates to distribute the second task to at least one other process core different from the first processor core. For example, the electronic device may use a load balancer control module (e.g., the load balancer control module (223) of FIG. 2b) to start the operation of the load balancer (e.g., trigger the operation of the load balancer) to distribute the second task to at least one other process core different from the first processor core. At least one other processor core may be a processor core (e.g., processor core #6 of FIG. 2a) having the same performance as the first processor core (e.g., processor core #7 of FIG. 2a), or a processor core (e.g., processor core #0 of FIG. 2a) having different performance (e.g., lower performance than the first processor core). The performance of the processor core may be determined based, for example, on information regarding the clock speed of the processor core, information regarding instructions per cycle (IPC) indicating the number of instructions that the processor core can process during one clock cycle, and / or information regarding the number of threads that the processor core can process simultaneously. The performance of the processor core may be verified, for example, by accessing a specific file. For example, the CPU architecture used may be verified by accessing the " / proc / cpuinfo" file. For example, the maximum frequency at which the CPU core can operate may be verified by accessing the " / sys / devices / system / cpu / cpu0 / cpufreq / scaling_max_freq" file.Through this method of operation 640, it is possible to determine which CPU can achieve the highest performance in the system. Through the method of operation 640 described above, waiting tasks are distributed and processed through other processor cores, so that even if the first processor core is monopolized by the first task due to a single affinity setting, delays for other tasks can be eliminated.

[0106] - An action (650) to raise the priority of the second or third task. For example, the electronic device may perform an action to raise the priority of the second or third task (e.g., schedule priority). The second and third tasks may be tasks added to the queue of the first processor core along with the first task, for example, and may be delayed tasks with a waiting time longer than the reference waiting time. The electronic device may raise the priority of the delayed task with the longest waiting time to a value higher than the specified priority (e.g., priority of the first task). For example, if the waiting time of the third task is longer than the waiting time of the second task, the electronic device may set the priority of the third task to a value higher than the priority of the first task. The electronic device may set the priority of the delayed task with the longest waiting time to the highest priority among the settable priorities. Through this method of action 650, more processor resources may be allocated to the task that has been waiting for the longest period, so that the delay for that task caused by a single affinity setting may be resolved.

[0107] - If the first task is a task related to rendering, or if the first task is a task related to rendering and the affinity (e.g., single affinity) is set to a low-performance CPU (e.g., little CPU), an action (660) to disable the affinity setting of the first task so that the first task is executed on a second processor core having higher performance than the first processor core based on FPS (frames per second). For example, the electronic device may include, when the first task is a task related to rendering, or when the first task is a task related to rendering and the affinity is set to a low-performance CPU (e.g., little CPU), obtaining information about the FPS, and based on identifying that the FPS is lower than the reference FPS, an operation to disable the affinity setting so that the first task is executed on a second processor core (e.g., processor core #7, the big core in FIG. 2b) having higher performance than the first processor core (e.g., processor core #0, the little core in FIG. 2a), and / or an operation to apply the affinity setting to the second processor core. The operation 660 may be performed, for example, when the first task is set to a single affinity on a processor core with performance below the reference performance (e.g., processor core #0, the little core in FIG. 2b). Through this method of operation 660, even if a rendering-related task is set to a single affinity on a low-performance processor core, it is possible to prevent the image quality from degrading because the FPS of the video processed by the task is lower than the reference FPS, which is the expected FPS.

[0108] - An operation (670) of changing a single affinity setting for a first processor core of a first task to a single affinity setting for a second processor core having the same performance as the first processor core. For example, the electronic device may, through a system call, release the single affinity setting for the first processor core of the first task (e.g., processor core #7 in FIG. 2a) and apply a single affinity setting to a second processor core having the same performance as the first processor core (e.g., processor core #6 in FIG. 2a). Through this method of operation 670, the first task can continue to be executed through the second processor core having the same performance as the first processor core, and other delayed tasks can be executed through the first processor core. Through this, delays caused by the single affinity setting can be resolved.

[0109] Meanwhile, the embodiments of the present disclosure are not limited to the operations of FIG. 6 described above. For example, various configuration changes may be applied to the embodiments of the present disclosure to execute delay task(s) (e.g., second task) for which the waiting time is longer than the reference waiting time due to a single affinity setting, or to maintain system stability.

[0110] In the embodiment of FIG. 5 described above, unlike the embodiment of FIG. 4, at least one setting associated with the affinity setting can be changed by considering the waiting time of other task(s) added to the queue of the first processor core along with the first task, which is a single affinity task, only when the waiting time is longer than the reference waiting time, for example, only when the delay time of the waiting task is long enough to impair the stability of the system. Additionally, in the embodiment of FIG. 5, unlike the embodiment of FIG. 4, when the waiting time of the delayed task is shorter than the reference time, for example, when the delay time of the waiting task is not long enough to impair the stability of the system, the single affinity setting can be maintained as intended by the developer of the application (e.g., the application (210) of FIG. 2b).

[0111] FIG. 7 is a flowchart illustrating the operation of an electronic device de-queuing a task according to one embodiment of the present disclosure.

[0112] The components and operations of the components described with reference to FIG. 7 may be, in part or in whole, identical to the components and operations of the components described with reference to FIG. 1 through 6. The components and operations of the components described with reference to FIG. 7 may be, in part or in whole, identical to the components and operations of the components described with reference to FIG. 8, which will be described later.

[0113] According to one embodiment, at least one of the operations of FIG. 7 may be performed by a scheduler (e.g., kernel scheduler (220) of FIG. 2b) of an electronic device (e.g., electronic device (101) of FIG. 1).

[0114] Referring to FIG. 7, according to one embodiment, in operation 710, the electronic device may initiate an operation (hereinafter referred to as a dequeuing operation) for dequeuing a first task (e.g., the first task (301) of FIG. 3) from a first processor core (e.g., processor core #7 of FIG. 2a or CPU7 of FIG. 2b). For example, the electronic device may initiate an operation for dequeuing the first task from the first processor core in response to the completion of the execution of the first task.

[0115] According to one embodiment, in operation 720, the electronic device can identify whether the first task corresponds to a single affinity task for which affinity is set on the first processor core. Operation 720 of FIG. 7 may include operation 420 of FIG. 4 or operation 520 of FIG. 5. As illustrated in FIG. 5, if the first task is a single affinity task for the first processor core, an operation to obtain (or monitor) information regarding the waiting time of at least one other task waiting on the first processor core (e.g., the second task (302) of FIG. 3) is applied. Therefore, it is necessary to terminate the operation during de-queuing so that it is necessary to identify whether the first task is a single affinity task for the first processor core.

[0116] According to one embodiment, in operation 730, the electronic device may terminate the operation of obtaining information about the runnable delay time of a second task waiting on the first processor core based on the identification that the first task is a single affinity task for the first processor core.

[0117] According to one embodiment, in operation 740, the electronic device may complete a de-queuing operation based on the identification that the first task is not a single affinity task for the first processor core or after operation 730 is performed. This allows the first task to be completely removed from the queue of the first processor core.

[0118] FIG. 8 is a flowchart illustrating the operation of an electronic device applying a single affinity setting based on processor temperature information according to one embodiment of the present disclosure.

[0119] The components and operations of the components described with reference to FIG. 8 may be all or partly the same as the components and operations of the components described with reference to FIG. 1 to 7.

[0120] According to one embodiment, at least one of the operations of FIG. 8 may be performed by a scheduler of an electronic device (e.g., the electronic device (101) of FIG. 1) (e.g., the kernel scheduler (220) of FIG. 2b).

[0121] Referring to FIG. 8, according to one embodiment, in operation 810, the electronic device may queue a first task (e.g., the first task (301) of FIG. 3) to a first processor core (e.g., processor core #7 of FIG. 2a or CPU7 of FIG. 2b). Operation 810 of FIG. 8 may include, for example, operation 410 of FIG. 4 or operation 510 of FIG. 5.

[0122] According to one embodiment, in operation 820, the electronic device may identify (or determine) whether the first task is a single affinity task with affinity set to a first processor core in the processor, based on the identification that the first task is queued. Operation 820 of FIG. 8 may include, for example, operation 420 of FIG. 4 or operation 520 of FIG. 5. If the first task is a single affinity task for the first processor core, operation 830 may be performed. If the first task is not a single affinity task for the first processor core, operation 870 may be performed.

[0123] According to one embodiment, in operation 830, the electronic device may obtain information about the processor temperature (hereinafter, processor temperature information). The processor temperature information may include information about the temperature of the first processor core to which the first task is queued. The processor temperature information may further include information about the overall temperature of the processor to which the first processor core belongs (e.g., the processor (200) of FIG. 2), and / or information about the respective temperatures of other processor core(s) within the processor to which the first processor core belongs. The electronic device may obtain the processor temperature information periodically or when a specified event is satisfied.

[0124] According to one embodiment, in operation 840, the electronic device can identify whether the processor temperature is lower than a reference temperature based on processor temperature information. For example, the electronic device can identify whether the temperature of the first processor core to which the first task is queued is lower than a reference temperature based on processor temperature information. For example, the electronic device can identify whether the overall temperature of the processor to which the first processor core belongs is lower than a reference temperature based on processor temperature information.

[0125] According to one embodiment, in operation 850, the electronic device may maintain a single affinity setting based on the identification that the processor temperature is lower than a reference temperature. Thus, when the processor temperature is not high, the single affinity setting may be maintained so that the first task can continue to be executed by the first processor core.

[0126] According to one embodiment, in operation 860, the electronic device may disable (e.g., temporarily disable) the single affinity setting based on the identification that the processor temperature is not lower than a reference temperature. Thus, when the processor temperature is too high, the single affinity setting may be temporarily disabled for heat control to prevent damage to system stability caused by heat.

[0127] According to one embodiment, the electronic device may re-acquire processor temperature information after the single affinity setting has been released. In this case, the electronic device may identify whether the processor temperature is lower than a specified temperature based on the processor temperature information. Based on the identification that the processor temperature is lower than the specified temperature, the electronic device may reapply the single affinity setting. In this manner, after the single affinity setting has been temporarily released for heat control, if the heat is dissipated, the single affinity setting may be reapplied for the execution of the first task.

[0128] According to one embodiment, the electronic device can reapply the single affinity setting without verifying processor temperature information after releasing the single affinity setting for a specified period of time. Through this method, the single affinity setting can be automatically reapplied without a procedure to re-acquire processor temperature information.

[0129] According to one embodiment, in operation 870, the electronic device may execute the first task on the first processor core (e.g., schedule it on the first processor core) using at least one setting for the first task based on the identification that the first task is not a single affinity task for the first processor core. Operation 870 of FIG. 8 may include, for example, operation 440 of FIG. 4.

[0130] According to one embodiment of the present disclosure, a single affinity setting may be applied to a specific task so that the specific task is executed only by a single processor core (e.g., CPU). Such a single affinity setting may impair the stability of the system depending on the circumstances. Therefore, the electronic device needs to support an operation to prevent the system stability resulting from the single affinity setting from being compromised in a specific situation (e.g., a situation where the delay of delayed tasks is large) and / or at a specific level (e.g., at the level of a scheduler (e.g., kernel scheduler (220) of FIG. 2b)).

[0131] According to one embodiment, an electronic device may include a processor (e.g., CPU) comprising a plurality of processor cores (e.g., CPU cores) and a memory comprising at least one storage medium for storing instructions. Each processor core includes a processing circuit, and the plurality of processor cores may include a first processor core and a second processor core having different performance capabilities.

[0132] According to one embodiment, an electronic device may queue a first task (e.g., the first task (301) of FIG. 3) to the first processor core. The electronic device may identify whether the first task is a single affinity task by using information regarding an affinity setting. Based on the identification that the first task is a single affinity task, the electronic device may obtain information regarding the waiting time of a second task (e.g., the second task (302) of FIG. 3) waiting on the first processor core. Based on the identification that the waiting time is greater than a reference waiting time, the electronic device may change at least one setting associated with the affinity setting. The single affinity task may be configured to run on the first processor core rather than on another processor core.

[0133] According to one embodiment, the second task is a task queued after the first task has been queued, and information regarding the waiting time of the second task can be obtained while the first task is running.

[0134] The operation of changing at least one setting may include an operation of changing an affinity setting for the first task, an operation of changing the priority of the first task, or an operation of changing the priority of the second task, which is performed to resolve the delay of the second task caused by the setting of the single affinity of the first task.

[0135] According to one embodiment, the operation of changing the at least one setting may include the operation of releasing the affinity setting for the first task for a specified time.

[0136] According to one embodiment, the operation of changing the at least one setting may include the operation of changing the at least one setting associated with the affinity setting so that the second task is executed based on the identification that the second task is a task associated with a kernel operation executed within a limited resource.

[0137] According to one embodiment, the operation of changing at least one setting may include the operation of lowering the schedule priority of the first task to a reference priority or lower for a specified period of time.

[0138] According to one embodiment, the operation of changing the at least one setting may include the operation of adjusting a threshold value at which a load balancer operates to distribute the second task to at least one core different from the first processor core.

[0139] According to one embodiment, the operation of changing at least one setting may include the operation of increasing the schedule priority of the second task.

[0140] According to one embodiment, the second task is a task related to rendering, and the operation of changing the at least one setting may include: an operation of obtaining information about FPS (frames per second); and an operation of disabling the affinity setting so that the first task is executed on the second processor core having higher performance than the first processor core, based on the identification that the FPS is lower than a reference FPS.

[0141] According to one embodiment, the operation of changing the at least one setting may include: an operation of obtaining information about the temperature of the first processor core or the processor; and an operation of releasing the affinity setting based on the identification that the temperature is lower than a reference temperature.

[0142] According to one embodiment, information regarding the waiting time of the second task can be obtained periodically according to a schedule tick period.

[0143] According to one embodiment, the affinity setting may be applied by calling a system call for the affinity setting by the application when the application associated with the first task is installed or executed.

[0144] The embodiments of this document and the terms used therein are not intended to limit the technical features described in this document to specific embodiments, and should be understood to include various modifications, equivalents, or substitutions of said embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of said items unless the relevant context clearly indicates otherwise. In this document, phrases such as "A or B," "at least one of A and B," "at least one of A or B," "A, B or C," "at least one of A, B and C," and "at least one of A, B, or C" each may include any one of the items listed together in the corresponding phrase, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used simply to distinguish said components from other said components and do not limit said components in any other aspect (e.g., importance or order). Where any (e.g., 1st) component is referred to as “coupled” or “connected” to another (e.g., 2nd) component, with or without the terms “functionally” or “communicationly,” it means that said any component may be connected to said other component directly (e.g., via a wire), wirelessly, or through a third component.

[0145] The term “module” as used in the embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit, for example. A module may be a component formed integrally, or a minimum unit of said component or a part thereof that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0146] One embodiment of the present document may be implemented as software (e.g., program (140) of FIG. 1) comprising one or more instructions stored in a storage medium (e.g., internal memory (136) of FIG. 1 or external memory (138) of FIG. 1) that is readable by a machine (e.g., electronic device (101) of FIG. 1). For example, a processor (e.g., processor (120) of FIG. 1) of the machine (e.g., electronic device (101) of FIG. 1) may call at least one of the one or more instructions stored from the storage medium and execute it. This enables the machine to be operated to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code that can be executed by an interpreter. The storage medium readable by the machine may be provided in the form of a non-transitory storage medium. Here, 'non-temporary' simply means that the storage medium is a tangible device and does not contain a signal (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently and cases where it is stored temporarily.

[0147] According to one embodiment, the method according to the embodiments disclosed herein may be provided by being included in a computer program product. The computer program product may be traded between a seller and a buyer as a product. The computer program product may be distributed in the form of a device-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or distributed online (e.g., download or upload) through an application store (e.g., Play Store™) or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created on a device-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or a relay server.

[0148] According to one embodiment, each component (e.g., module or program) of the components described above may include a singular or multiple entities, and some of the multiple entities may be separated and placed in other components. According to one embodiment, one or more of the components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Generally or additionally, multiple components (e.g., module or program) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in the same or similar manner as those performed by the corresponding component among the multiple components prior to integration. According to one embodiment, operations performed by the module, program, or other components may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Claims

1. In an electronic device, A processor comprising a plurality of processor cores - each processor core comprises a processing circuit, and the plurality of processor cores comprises a first processor core and a second processor core having different performance -; and It includes memory comprising at least one storage medium for storing instructions, and When executed by the processor, the above instructions cause the electronic device: Enqueue the first task to the first processor core, and Using information regarding the affinity setting, identify whether the first task is a single affinity task, and Based on the identification that the first task is the single affinity task, information regarding the waiting time of the second task waiting on the first processor core is obtained, and Based on the identification that the above waiting time is greater than the reference waiting time, it causes at least one setting associated with the affinity setting to be changed, and An electronic device configured to execute the single affinity task on the first processor core, rather than on another processor core.

2. In Paragraph 1, The above second task is a task queued after the above first task has been queued, and An electronic device for which information regarding the waiting time of the second task is obtained while the first task is running.

3. In Paragraph 1 or 2, The operation of changing at least one of the above settings is: An electronic device comprising an operation to change an affinity setting for the first task, an operation to change the priority of the first task, or an operation to change the priority of the second task, which are performed to resolve a delay of the second task caused by the setting of the single affinity of the first task.

4. In any one of paragraphs 1 through 3, The operation of changing at least one of the above settings is: An electronic device comprising an operation to release the affinity setting for the first task for a specified period of time.

5. In any one of paragraphs 1 through 4, The operation of changing at least one of the above settings is: An electronic device comprising an operation to change at least one setting associated with the affinity setting so that the second task is executed, based on the identification that the second task is a task associated with a kernel operation executed within a limited resource.

6. In any one of paragraphs 1 through 5, The operation of changing at least one of the above settings is: An electronic device comprising an operation to lower the schedule priority of the first task to a reference priority or lower for a specified period of time.

7. In any one of paragraphs 1 through 6, The operation of changing at least one of the above settings is: An electronic device comprising an operation to adjust a threshold value at which a load balancer operates in order to distribute the second task to at least one processor core different from the first processor core.

8. In any one of paragraphs 1 through 7, The operation of changing at least one of the above settings is: An electronic device comprising an operation to increase the schedule priority of the second task.

9. In any one of paragraphs 1 through 8, The above second task is a task related to rendering, and The operation of changing at least one of the above settings is: An operation to obtain information about FPS (frames per second); and An electronic device comprising an operation to disable the affinity setting so that the first task is executed on the second processor core having higher performance than the first processor core, based on the identification that the above FPS is lower than the reference FPS.

10. In any one of paragraphs 1 through 9, The operation of changing at least one of the above settings is: An operation to obtain information regarding the temperature of the first processor core or the processor; and An electronic device comprising an operation to disable the affinity setting based on identifying that the above temperature is lower than a reference temperature.

11. In any one of paragraphs 1 through 10, An electronic device in which information regarding the waiting time of the second task is periodically acquired according to a schedule tick period.

12. In any one of paragraphs 1 through 11, An electronic device in which the affinity setting is applied through the invocation of a system call for the affinity setting by the application, based on the installation or execution of an application associated with the first task.

13. A method of an electronic device, wherein the electronic device comprises a processor including a plurality of processor cores, each processor core comprising a processing circuit, and wherein the plurality of processor cores comprises a first processor core and a second processor core having different performance, and the method comprises: The operation of enqueuing the first task to the first processor core; An operation to identify whether the first task is a single affinity task using information regarding the affinity setting; An operation to obtain information about the waiting time of a second task waiting on the first processor core based on the identification that the first task is the single affinity task; Based on the identification that the above waiting time is greater than the reference waiting time, the method includes changing at least one setting associated with the affinity setting, and A method in which the single affinity task is configured to be executed on the first processor core, rather than on another processor core.

14. In Paragraph 13, The above second task is a task queued after the above first task has been queued, and A method in which information regarding the waiting time of the second task is obtained while the first task is running.

15. A storage medium storing at least one instruction readable by a computer, wherein the at least one instruction causes the electronic device to perform at least one operation when executed by at least one processor of the electronic device, and The electronic device comprises a processor including a plurality of processor cores, each processor core including a processing circuit, and the plurality of processor cores include a first processor core and a second processor core having different performance. The above at least one operation is: The operation of enqueuing the first task to the first processor core; An operation to identify whether the first task is a single affinity task using information regarding the affinity setting; An operation to obtain information about the waiting time of a second task waiting on the first processor core based on the identification that the first task is the single affinity task; and Based on the identification that the above waiting time is greater than the reference waiting time, the method includes changing at least one setting associated with the affinity setting, and A storage medium configured to execute the single affinity task on the first processor core, rather than on another processor core.

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