Display substrate and display device

Abstract

Provided is a display substrate, comprising: a base substrate; a driving circuit layer; a light-emitting device layer located on the side of the driving circuit layer distant from the base substrate; a packaging layer located on the side of the light-emitting device layer distant from the base substrate; a touch layer located on the side of the packaging layer distant from the base substrate, wherein the touch layer comprises a touch electrode and a touch line, and at least part of the touch line is located in a peripheral region; and a color film layer located on the side of the touch layer distant from the base substrate. The touch layer comprises a first touch metal layer and a second touch metal layer located on the first touch metal layer. At least part of the touch line comprises a first sub-line and a second sub-line, the first sub-line is electrically connected to the second sub-line, the first sub-line is located in the first touch metal layer, and the second sub-line is located in the second touch metal layer. The color film layer comprises a protective portion located in the peripheral region, and the orthographic projection of the protective portion on the base substrate at least partially overlaps the orthographic projection of the second sub-line on the base substrate.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] An organic light emitting diode (OLED) is an active light emitting display device, which has the advantages of self-emission, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, a display device with an OLED as a light emitting device and a signal controlled by a thin film transistor (TFT) has become the mainstream product in the current display field. FMLOC (Flexible Multi-Layer On Cell) is an advanced touch technology, which allows the metal and inorganic film layer pattern to be made on the packaging layer of the display substrate, thereby realizing the touch function. This technology is particularly suitable for flexible and foldable OLED display screens.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure, and therefore, the above information can contain information that does not constitute the prior art.

[0004] SUMMARY

[0005] In one aspect, a display substrate is provided, the display substrate includes a display area and a peripheral area located at a periphery of the display area, and the display substrate includes:

[0006] a substrate substrate;

[0007] a driving circuit layer located on the substrate substrate;

[0008] a light emitting device layer located on a side of the driving circuit layer away from the substrate substrate, the light emitting device layer including a plurality of light emitting devices, the plurality of light emitting devices being arranged at intervals along a first direction and a second direction;

[0009] a packaging layer located on a side of the light emitting device layer away from the substrate substrate;

[0010] a touch layer located on a side of the packaging layer away from the substrate substrate, the touch layer including a touch electrode and a touch trace, the touch electrode being located in the display area, the touch trace being electrically connected with the touch electrode, and at least a part of the touch trace being located in the peripheral area; and

[0011] a color film layer located on a side of the touch layer away from the substrate substrate;

[0012] The touch control layer comprises a first touch control metal layer and a second touch control metal layer located on a side of the first touch control metal layer away from the substrate;

[0013] At least a part of the touch control trace comprises a first sub-trace and a second sub-trace, the first sub-trace is electrically connected with the second sub-trace, the first sub-trace is located on the first touch control metal layer, and the second sub-trace is located on the second touch control metal layer; and

[0014] The color filter layer comprises a protection portion located on the peripheral region, and a projection of the protection portion on the substrate at least partially overlaps with a projection of the second sub-trace on the substrate.

[0015] According to some exemplary embodiments, the peripheral region comprises a bending region located on a side of the display region along the second direction and spaced apart from the display region;

[0016] The touch control trace comprises a first trace portion, a second trace portion and a third trace portion electrically connected in sequence, the first trace portion is located on a side of the bending region close to the display region, the second trace portion is located on the bending region, and the third trace portion is located on a side of the bending region away from the display region;

[0017] The first trace portion comprises a first sub-portion and a second sub-portion electrically connected, the first sub-portion is located on the first touch control metal layer, and the second sub-portion is located on the second touch control metal layer; and

[0018] The protection portion comprises a first protection portion located on a side of the bending region close to the display region, and a projection of the first protection portion on the substrate at least partially overlaps with a projection of the second sub-portion on the substrate.

[0019] According to some exemplary embodiments, the encapsulation layer comprises a barrier wall and an organic encapsulation layer, the barrier wall is arranged around the display region and located on a side of the bending region close to the display region, and the organic encapsulation layer is located on a side of the barrier wall close to the display region;

[0020] The first sub-portion continuously extends from a side of the barrier wall close to the display region to a side of the barrier wall away from the display region, and a projection of the second sub-portion on the substrate is spaced apart from a projection of the barrier wall on the substrate; and

[0021] A projection of the first protection portion on the substrate is spaced apart from a projection of the barrier wall on the substrate, and the projection of the first protection portion on the substrate covers the projection of the second sub-portion on the substrate.

[0022] According to some exemplary embodiments, the second sub-portion is located on a side of the barrier wall close to the display area.

[0023] According to some exemplary embodiments, a part of the second sub-portion is located on a side of the barrier wall close to the display area, and another part of the second sub-portion is located on a side of the barrier wall away from the display area.

[0024] According to some exemplary embodiments, the third trace portion includes a third sub-portion, the third sub-portion being located on the first touch metal layer; and

[0025] The touch layer includes a touch insulating layer located between the first touch metal layer and the second touch metal layer, a projection of the touch insulating layer on the substrate substrate at least partially overlaps with a projection of the third sub-portion on the substrate substrate.

[0026] According to some exemplary embodiments, the third trace portion further includes a fourth sub-portion, the fourth sub-portion being electrically connected with the third sub-portion, the fourth sub-portion being located on the driving circuit layer.

[0027] According to some exemplary embodiments, the driving circuit layer includes a first source-drain metal layer, a second source-drain metal layer located on a side of the first source-drain metal layer away from the substrate substrate, and a third source-drain metal layer located on a side of the second source-drain metal layer away from the substrate substrate, the fourth sub-portion being located on the third source-drain metal layer.

[0028] According to some exemplary embodiments, the driving circuit layer includes a first source-drain metal layer, a second source-drain metal layer located on a side of the first source-drain metal layer away from the substrate substrate, and a third source-drain metal layer located on a side of the second source-drain metal layer away from the substrate substrate, the fourth sub-portion being located on the third source-drain metal layer and the second source-drain metal layer.

[0029] According to some exemplary embodiments, the third trace portion includes a fifth sub-portion, the fifth sub-portion being located on the second touch metal layer;

[0030] The protection portion includes a second protection portion located on a side of the bending area away from the display area, a projection of the second protection portion on the substrate substrate at least partially overlaps with a projection of the fifth sub-portion on the substrate substrate.

[0031] According to some exemplary embodiments, the third trace portion is located on the driving circuit layer.

[0032] According to some exemplary embodiments, the driving circuit layer comprises a first source-drain metal layer, a second source-drain metal layer located on a side of the first source-drain metal layer away from the substrate, and a third source-drain metal layer located on a side of the second source-drain metal layer away from the substrate; and

[0033] The third trace portion is located on the third source-drain metal layer, or the third trace portion is located on the third source-drain metal layer and the second source-drain metal layer.

[0034] According to some exemplary embodiments, the driving circuit layer comprises a power supply trace, the power supply trace comprises a power supply trace sub-portion located on a side of the bending region away from the display region; and

[0035] The power supply trace sub-portion and the third trace portion at least partially overlap on the substrate, and the power supply trace sub-portion is located on a side of the third trace portion close to the substrate.

[0036] According to some exemplary embodiments, the second trace portion is located on the driving circuit layer.

[0037] According to some exemplary embodiments, the touch control trace further comprises a switching portion, one end of the switching portion is directly connected with the first trace portion and the other end is connected with the second trace portion, and the switching portion is located on the second touch control metal layer.

[0038] According to some exemplary embodiments, the color film layer comprises a first sub-color film layer, a second sub-color film layer and a third sub-color film layer, and the light emitting device layer comprises a first light emitting device, a second light emitting device and a third light emitting device;

[0039] The first sub-color film layer covers the first light emitting device on the substrate, the second sub-color film layer covers the second light emitting device on the substrate, and the third sub-color film layer covers the third light emitting device on the substrate; and

[0040] At least two of the first sub-color film layer, the second sub-color film layer and the third sub-color film layer comprise a part located on the spacing region of the light emitting device, and / or the protection portion is located on at least one of the first sub-color film layer, the second sub-color film layer and the third sub-color film layer.

[0041] In yet another aspect, a display device is provided, comprising the display substrate as claimed in any one of the above. BRIEF DESCRIPTION OF DRAWINGS

[0042] The features and advantages of the present disclosure will become more apparent from the detailed description of example embodiments of the present disclosure with reference to the accompanying drawings.

[0043] FIG. 1 schematically illustrates a cross-sectional view of a display substrate in the related art.

[0044] FIG. 2 schematically illustrates a cross-sectional view of a color filter layer in a display substrate in the related art.

[0045] FIG. 3 schematically illustrates a plan view of a display substrate according to some embodiments of the present disclosure.

[0046] FIG. 4 schematically illustrates a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0047] FIG. 5 schematically illustrates a cross-sectional view of a combination of a color filter layer and a pixel definition layer in a display substrate according to some embodiments of the present disclosure.

[0048] FIG. 6 schematically illustrates a graph of transmittance curves of different color filters.

[0049] FIG. 7 schematically illustrates a plan view of a combination of a color filter layer and a pixel definition layer in a display substrate according to some embodiments of the present disclosure.

[0050] FIG. 8 schematically illustrates a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0051] FIG. 9 schematically illustrates a cross-sectional view taken along line NN’ in FIG. 3.

[0052] FIG. 10 schematically illustrates an enlarged view of region A1 in FIG. 3.

[0053] FIG. 11 schematically illustrates an enlarged view of region A1 in FIG. 3.

[0054] FIG. 12 schematically illustrates a cross-sectional view of a driving circuit layer in a display substrate according to some embodiments of the present disclosure.

[0055] FIG. 13 schematically illustrates an enlarged view of region A2 in FIG. 3.

[0056] FIG. 14A schematically illustrates an enlarged view of region A3 in FIG. 13.

[0057] FIG. 14B schematically illustrates a cross-sectional view taken along line HH’ in FIG. 14A.

[0058] FIG. 15A schematically illustrates another enlarged view of region A3 in FIG. 13.

[0059] FIG. 15B schematically illustrates a cross-sectional view taken along line JJ’ in FIG. 15A.

[0060] FIG. 16 schematically illustrates a magnified view of the area A4 in FIG. 3.

[0061] FIG. 17 schematically illustrates a cross-sectional view taken along the line FF’ in FIG. 16.

[0062] FIG. 18 schematically illustrates a magnified view of the area A5 in FIG. 3.

[0063] FIG. 19 schematically illustrates a cross-sectional view taken along the line GG’ in FIG. 18.

[0064] FIG. 20 schematically illustrates another cross-sectional view taken along the line GG’ in FIG. 18.

[0065] FIG. 21 schematically illustrates yet another cross-sectional view taken along the line GG’ in FIG. 18.

[0066] FIG. 22 schematically illustrates still another cross-sectional view taken along the line GG’ in FIG. 18.

[0067] FIG. 23 schematically illustrates a flowchart of a method for manufacturing a display substrate according to some embodiments of the present disclosure.

[0068] It should be noted that, in the drawings used to describe the embodiments of the present disclosure, the size of a layer, a structure, or an area can be exaggerated or reduced for clarity, i.e., the drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0069] In order to make the objects, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the protection scope of the present disclosure.

[0070] It should be noted that, in the drawings, the size and relative size of elements can be exaggerated for clarity and / or descriptive purposes. Thus, the size and relative size of the elements in the drawings are not necessarily drawn to scale. In the description and drawings, identical or similar reference numerals indicate identical or similar components.

[0071] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, it can be directly on, directly connected to, or directly coupled to the other element, or intervening elements can be present. In contrast, when an element is described as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. Other terms of relationship between elements are to be interpreted in a like fashion, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connected" can refer to physical or electrical connection, communication connection, and / or fluid connection. In addition, the X-axis, Y-axis and Z-axis are not limited to three axes of a rectangular coordinate system, and can be interpreted in a wider sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to one another, or can represent different directions that are not perpendicular to one another. For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to include only X, only Y, only Z, or any combination of any two or more of X, Y and Z, such as XYZ, XY, YZ and XZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated items.

[0072] It should be noted that, although the terms "first," "second," etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer and / or section from another element, component, region, layer and / or section. Thus, a first element, component, region, layer and / or section discussed below could be termed a second element, component, region, layer and / or section without departing from the teachings of the present disclosure.

[0073] Spatially relative terms, such as "upper," "lower," "left," "right," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device described is turned over in the figure, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. The device can be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0074] In this document, the terms“substantially,”“approximately,”“about,”“largely,” and other similar terms are used as terms of approximation, and not as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. Considering factors such as process variations, measurement inaccuracies, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system),“about” or“approximately” as used herein includes the stated value and indicates that a particular value as determined by one of ordinary skill in the art is within an acceptable range of deviation. For example,“about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0075] It should be noted that, in this document, the term“same layer” refers to a layer structure formed by using the same film formation process to form a film layer for forming a specific pattern, and then patterning the film layer by a one-time patterning process using the same mask plate. Depending on the specific pattern, the one-time patterning process can include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, the plurality of elements, components, structures, and / or parts located in the“same layer” are composed of the same material and are formed by the same patterning process. Generally, the plurality of elements, components, structures, and / or parts located in the“same layer” have approximately the same thickness.

[0076] Those skilled in the art should understand that, in this document, unless otherwise specified, the expression“height” or“thickness” refers to the dimension along the surface of each film layer disposed perpendicular to the display substrate, i.e., the dimension along the light-emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0077] FIG. 1 schematically shows a cross-sectional view of a display substrate in the related art. FIG. 2 schematically shows a cross-sectional view of a color film layer in a display substrate in the related art.

[0078] Referring to FIG. 1, the display substrate includes a substrate 100, a driving circuit layer 200 located on the substrate 100, a light-emitting device layer 300 located on the driving circuit layer 200 away from the substrate 100, an encapsulation layer 400 located on the light-emitting device layer 300 away from the substrate 100, a touch layer 500 located on the encapsulation layer 400 away from the substrate 100, a first organic protective layer OC1 located on the touch layer 500 away from the substrate 100, a color film layer 600 located on the first organic protective layer OC1 away from the substrate 100, and a second organic protective layer OC2 located on the color film layer 600 away from the substrate 100.

[0079] With reference to FIGS. 1 and 2, the color film layer 600 includes a first sub-color film layer CF1, a second sub-color film layer CF2, a third sub-color film layer CF3, and a black matrix layer BM. The first sub-color film layer CF1 is located in the first sub-pixel region, the second sub-color film layer CF2 is located in the second sub-pixel region, the third sub-color film layer CF3 is located in the third sub-pixel region, and the black matrix layer BM covers the interval regions of the first sub-color film layer CF1, the second sub-color film layer CF2, and the third sub-color film layer CF3. The color film layer 600 can replace the polarizing plate structure, thereby reducing light loss and reducing the power consumption of the display substrate. In addition, the color film layer 600 can also provide a wider color gamut and more accurate color performance, thereby improving the visual experience.

[0080] However, the first sub-color film layer CF1, the second sub-color film layer CF2, the third sub-color film layer CF3, and the black matrix layer BM in the color film layer 600 need to be manufactured by four exposure processes using four mask plates, which increases the cost of manufacturing the display substrate.

[0081] FIG. 3 schematically shows a plan view of a display substrate according to some embodiments of the present disclosure. FIG. 4 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure. FIG. 5 schematically shows a cross-sectional view of a combination of a color film layer and a pixel definition layer in a display substrate according to some embodiments of the present disclosure.

[0082] With reference to FIGS. 3 and 4, the display substrate includes a substrate 100, a driving circuit layer 200 on the substrate 100, a light emitting device layer 300 on a side of the driving circuit layer 200 away from the substrate 100, an encapsulation layer 400 on a side of the light emitting device layer 300 away from the substrate 100, a first organic protective layer OC1 on a side of the encapsulation layer 400 away from the substrate 100, a color film layer 600 on a side of the first organic protective layer OC1 away from the substrate 100, and a second organic protective layer OC2 on a side of the color film layer 600 away from the substrate 100. The display substrate includes a display region AA and a peripheral region NA located at a periphery of the display region AA. The light emitting device layer 300 includes a plurality of light emitting devices 310 distributed at intervals. The plurality of light emitting devices 310 are located in the display region AA and are arranged in an array along a first direction X and a second direction Y. The plurality of light emitting devices 310 are electrically connected to the driving circuit layer 200, and the driving circuit layer 200 independently drives each light emitting device 310 to realize picture display.

[0083] With reference to FIGS. 4 and 5, the color filter layer 600 includes a first sub-color filter layer CF1, a second sub-color filter layer CF2, and a third sub-color filter layer CF3, the light emitting device layer 300 includes a first light emitting device 311, a second light emitting device 312, and a third light emitting device 313, a normal projection of the first sub-color filter layer CF1 on the substrate substrate 100 covers a normal projection of the first light emitting device 311 on the substrate substrate 100, a normal projection of the second sub-color filter layer CF2 on the substrate substrate 100 covers a normal projection of the second light emitting device 312 on the substrate substrate 100, and a normal projection of the third sub-color filter layer CF3 on the substrate substrate 100 covers a normal projection of the third light emitting device 313 on the substrate substrate 100. At least two of the first sub-color filter layer CF1, the second sub-color filter layer CF2, and the third sub-color filter layer CF3 include a portion located in the spacing region of the light emitting device 310.

[0084] The inventor has found that, by superimposing at least two of the first sub-color filter layer CF1, the second sub-color filter layer CF2, and the third sub-color filter layer CF3 in the spacing region of the light emitting device 310, an effect similar to that of a black matrix can be achieved, that is, the color filter layer 600 only includes the first sub-color filter layer CF1, the second sub-color filter layer CF2, and the third sub-color filter layer CF3, and a black matrix layer does not need to be additionally provided, thereby saving a mask and reducing the manufacturing cost of the display substrate.

[0085] FIG. 6 schematically shows a transmittance curve of different color filters.

[0086] Referring to FIG. 6, the abscissa represents wavelength (nm), and the ordinate represents light transmittance (%). The graph shows the transmittance of a black matrix layer (BM), a red color filter, a blue color filter, and a green color filter (R+G+B), a red color filter and a green color filter (R+G), a red color filter and a blue color filter (R+B), and a blue color filter and a green color filter (B+G) in a wavelength range of 300 nm to 1300 nm. As can be seen from the graph, the transmittance curve of the red color filter, the blue color filter, and the green color filter in the visible light wavelength range is basically coincident with the transmittance curve of the black matrix layer in the visible light wavelength range. The transmittance curve of the red color filter and the blue color filter (R+B) in the visible light wavelength range only has two small peaks of increased transmittance in the visible light wavelength range, and is relatively close to the transmittance curve of the black matrix layer (BM). The transmittance curve of the blue color filter and the green color filter (B+G) and the transmittance curve of the red color filter and the green color filter (R+G) both have more obvious peaks of increased transmittance in the visible light wavelength range, and the transmittance curves of the blue color filter and the green color filter (B+G) and the red color filter and the green color filter (R+G) are quite different from the transmittance curve of the black matrix layer (BM).

[0087] From the transmittance data, the red color filter, blue color filter and green color filter stacked film layer and the red color filter and blue color filter stacked film layer can be used as a scheme to replace the black matrix layer.

[0088] The inventors further carried out reflectivity and hue tests. The reflectivity and hue data of the red color filter and blue color filter stacked film layer (R+B) in the visible light band are close to those of the black matrix layer (BM). From the comprehensive transmittance, reflectivity and hue data, replacing the black matrix layer (BM) with the red color filter and blue color filter stacked film layer (R+B) can meet the optical requirements of the display substrate.

[0089] FIG. 7 schematically shows a plan view of a color filter layer and a pixel definition layer combination in a display substrate according to some embodiments of the present disclosure, wherein the cross-sectional view shown in FIG. 5 is a cross-sectional structure along the cutting line MM’ in FIG. 7.

[0090] With reference to FIGS. 4, 5 and 7, the light emitting device layer 300 includes a pixel definition layer PDL, which includes a first sub-pixel opening PK1, a second sub-pixel opening PK2 and a third sub-pixel opening PK3. At least a portion of the first light emitting device 311 is located within the first sub-pixel opening PK1, at least a portion of the second light emitting device 312 is located within the second sub-pixel opening PK2, and at least a portion of the third light emitting device 313 is located within the third sub-pixel opening PK3.

[0091] For example, the light emitting device 310 includes an anode, a light emitting functional layer located away from the substrate 100 on a side of the anode, and a cathode located away from the substrate 100 on a side of the light emitting functional layer. The anode is formed before the pixel definition layer PDL, the light emitting functional layer is formed after the pixel definition layer PDL, the anode is located on a side of the pixel definition layer PDL close to the substrate 100, and at least a portion of the light emitting functional layer and the cathode are located in the sub-pixel openings of the pixel definition layer PDL and in contact with the anode.

[0092] It should be noted that only the first sub-pixel opening PK1, the second sub-pixel opening PK2 and the third sub-pixel opening PK3 in the pixel definition layer PDL are shown in FIG. 7. The areas outside the first sub-pixel opening PK1, the second sub-pixel opening PK2 and the third sub-pixel opening PK3 all have film layer materials of the pixel definition layer PDL. In order to more clearly show the structure of the pixel definition layer PDL and the color filter layer CF, the filling pattern of the pixel definition layer PDL is omitted in FIG. 7.

[0093] With reference to FIGS. 3, 5 and 7, the first sub-color filter layer CF1 has a first opening KK1 and a second opening KK2, a normal projection of the first opening KK1 on the substrate 100 covers a normal projection of the second sub-pixel opening PK2 on the substrate 100, and a normal projection of the second opening KK2 on the substrate 100 covers a normal projection of the third sub-pixel opening PK3 on the substrate 100, that is, the first sub-color filter layer CF1 covers most of the display area AA, and only has the first opening KK1 and the second opening KK2 at positions corresponding to the second sub-pixel opening PK2 and the third sub-pixel opening PK3.

[0094] It should be noted that only the first opening KK1 and the second opening KK2 in the first sub-color filter layer CF1 are shown in FIG. 7, and the regions other than the first opening KK1 and the second opening KK2 have the film layer material of the first sub-color filter layer CF1. In order to more clearly show the structure of the pixel definition layer PDL and the color filter layer CF, the filling pattern of the first sub-color filter layer CF1 is omitted in FIG. 7. With reference to FIGS. 3, 5 and 7, the second sub-color filter layer CF2 has a plurality of second sub-color filter portions CF2a arranged at intervals, and a normal projection of the second sub-color filter portion CF2a on the substrate 100 covers a normal projection of the second sub-pixel opening PK2 on the substrate 100.

[0095] With reference to FIGS. 3, 5 and 7, the third sub-color filter layer CF3 has a third opening KK3 and a fourth opening KK4, a normal projection of the third opening KK3 on the substrate 100 covers a normal projection of the first sub-pixel opening PK1 on the substrate 100, and a normal projection of the fourth opening KK4 on the substrate 100 covers a normal projection of the second sub-pixel opening PK2 on the substrate 100, that is, the third sub-color filter layer CF3 covers most of the display area AA, and only has the third opening KK3 and the fourth opening KK4 at positions corresponding to the first sub-pixel opening PK1 and the second sub-pixel opening PK2.

[0096] It should be noted that only the third opening KK3 and the fourth opening KK4 in the third sub-color filter layer CF3 are shown in FIG. 7, and the regions other than the third opening KK3 and the fourth opening KK4 have the film layer material of the third sub-color filter layer CF3. In order to more clearly show the structure of the pixel definition layer PDL and the color filter layer CF, the filling pattern of the third sub-color filter layer CF3 is omitted in FIG. 7.

[0097] In this way, in the interval regions of the first sub-pixel opening PK1, the second sub-pixel opening PK2 and the third sub-pixel opening PK3, at least the laminated film layer formed by the first sub-color filter layer CF1 and the third sub-color filter layer CF3 is arranged, which can replace the black matrix layer to avoid the light color crosstalk problem between adjacent light emitting devices.

[0098] For example, the first light emitting device 311 emits red light, and the color of the first sub-color film layer CF1 is red; the second light emitting device 312 emits green light, and the color of the second sub-color film layer CF2 is green; and the third light emitting device 313 emits blue light, and the color of the third sub-color film layer CF3 is blue. That is, in the interval region of the light emitting device, there is a laminated film layer formed by stacking the red color film and the blue color film.

[0099] It should be noted that FIG. 7 schematically shows the shape and arrangement of a sub-pixel opening, and the embodiments of the present disclosure are not limited thereto. The shape of the sub-pixel opening can also be rectangular, rhombic, pentagonal, hexagonal, etc., and the three sub-pixel openings can be arranged in a horizontal parallel, vertical parallel, or triangular manner, etc. According to some exemplary embodiments, in combination with reference to FIGS. 5 and 7, the orthographic projection of the first opening KK1 on the substrate substrate 100 covers the orthographic projection of the second sub-pixel opening PK2 on the substrate substrate, the orthographic projection of the fourth opening KK4 on the substrate substrate 100 covers the orthographic projection of the first opening KK1 on the substrate substrate, and the orthographic projection of the second sub-color film layer CF2 on the substrate substrate covers the orthographic projection of the fourth opening KK4 on the substrate substrate.

[0100] Alternatively, the first opening KK1 can also be set to be slightly larger than the fourth opening KK4, that is, the orthographic projection of the first opening KK1 on the substrate substrate covers the orthographic projection of the fourth opening KK4 on the substrate substrate.

[0101] For example, the distance D1 between the edge of the orthographic projection of the first opening KK1 on the substrate substrate and the edge of the orthographic projection of the second sub-pixel opening PK2 on the substrate substrate is about 4 microns.

[0102] For example, the distance D2 between the edge of the orthographic projection of the second sub-color film part CF2a on the substrate substrate 100 and the edge of the orthographic projection of the first opening KK1 on the substrate substrate 100 is about 4.5 microns, and the distance D3 between the edge of the orthographic projection of the second sub-color film part CF2a on the substrate substrate 100 and the edge of the orthographic projection of the fourth opening KK4 on the substrate substrate 100 is about 1 micron.

[0103] For example, referring to FIGS. 5 and 7, the distance D4 between the edge of the orthographic projection of the second opening KK2 on the substrate substrate 100 and the edge of the orthographic projection of the third sub-pixel opening PK3 on the substrate substrate 100 is about 4 microns, and the distance D5 between the edge of the orthographic projection of the third opening KK3 on the substrate substrate 100 and the edge of the orthographic projection of the first sub-pixel opening PK1 on the substrate substrate 100 is about 4 microns.

[0104] FIG. 8 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0105] Referring to FIG. 8, the touch layer 500 is directly in contact with the color film layer 600 away from the surface of the substrate 100, that is, the first organic protective layer between the touch layer 500 and the color film layer 600 is removed, and meanwhile, the second organic protective layer on the side of the color film layer 600 away from the substrate 100 is also removed. By removing the first organic protective layer and the second organic protective layer, the number of exposure processes can be reduced, that is, the number of masks can be reduced, thereby reducing the manufacturing cost of the display substrate.

[0106] It should be noted that in some display substrates provided with the first organic protective layer and the second organic protective layer, the patterns of the first organic protective layer and the second organic protective layer are the same, and the first organic protective layer and the second organic protective layer can be formed by using the same mask through the exposure process, that is, the film layer provided with the bonding pad area is removed to expose the bonding pad, so as to facilitate the bonding of the circuit board.

[0107] In addition, according to actual process requirements, the first organic protective layer OC1 and the second organic protective layer OC2 can be removed at the same time, and at least two of the first sub-color film layer CF1, the second sub-color film layer CF2 and the third sub-color film layer CF3 are used to replace the black matrix layer BM, that is, the color film layer 600 in FIG. 8 adopts the structure shown in FIG. 5, thereby saving two masks. Alternatively, only the first organic protective layer OC1 and the second organic protective layer OC2 can be removed, but the black matrix layer BM is still retained, that is, the color film layer 600 in FIG. 8 adopts the structure shown in FIG. 2. Alternatively, only at least two of the first sub-color film layer CF1, the second sub-color film layer CF2 and the third sub-color film layer CF3 can be used to replace the black matrix layer BM, but the first organic protective layer OC1 and the second organic protective layer OC2 are still retained.

[0108] According to some exemplary embodiments, in combination with reference to FIG. 3 and FIG. 8, the touch layer 500 includes a touch buffer layer TBL located away from the substrate 100 on the side of the encapsulation layer 400, a first touch metal layer TMA located away from the substrate 100 on the side of the touch buffer layer TBL, a touch insulating layer TLD located away from the substrate 100 on the side of the first touch metal layer TMA, and a second touch metal layer TMB located away from the substrate 100 on the side of the touch insulating layer TLD. The first touch metal layer TMA and the second touch metal layer TMB include a plurality of touch electrodes 510 and a plurality of touch wires 520. The touch electrodes 510 are located in the display area AA, and at least part of the touch wires 520 are located in the peripheral area NA. One end of the touch wire 520 is electrically connected to the touch electrode 510, and the other end is electrically connected to the bonding pad BP located in the bonding area NA2.

[0109] The touch electrode 510 includes a plurality of touch driving electrodes 511 and a plurality of touch sensing electrodes 512, and the touch wire 520 includes a plurality of touch driving wires 520T and a plurality of touch sensing wires 520R. The plurality of touch driving electrodes 511 arranged at intervals along the first direction X are sequentially electrically connected by a plurality of first connecting portions 513 and electrically connected to at least one touch driving wire 520T. The plurality of touch sensing electrodes 512 arranged at intervals along the second direction Y are sequentially electrically connected by a plurality of second connecting portions 514 and electrically connected to at least one touch sensing wire 520R. For example, the touch driving electrode 511, the touch sensing electrode 512, and the first connecting portion 513 can be located in the first touch metal layer TMA, and the second connecting portion 514 can be located in the second touch metal layer TMB. For another example, the touch driving electrode 511, the touch sensing electrode 512, and the first connecting portion 513 can be located in the second touch metal layer TMB, and the second connecting portion 514 can be located in the first touch metal layer TMA. Based on the working principle of mutual capacitance detection, the touch integrated circuit realizes touch action by detecting the mutual capacitance between the touch driving electrode 511 and the touch sensing electrode 512.

[0110] FIG. 9 schematically shows a cross-sectional view taken along the line NN' in FIG. 3, wherein FIG. 9 only schematically shows the structures of the touch layer and the color filter layer.

[0111] With reference to FIGS. 3, 8, and 9, in order to reduce the resistance of the touch wire 520, at least a portion of the touch wire 520 can be provided as a double-layer wire structure. The at least a portion of the touch wire 520 includes a first sub-wire 520A and a second sub-wire 520B. The first sub-wire 520A is electrically connected to the second sub-wire 520B. The first sub-wire 520A is located in the first touch metal layer TMA, and the second sub-wire 520B is located in the second touch metal layer TMB. The orthographic projection of the first sub-wire 520A on the substrate 100 at least partially overlaps the orthographic projection of the second sub-wire 520B on the substrate 100. The second sub-wire 520B is electrically connected to the first sub-wire 520A through at least one via in the touch insulating layer TLD.

[0112] However, the inventors have found through research that, after the first organic protective layer and the second organic protective layer are removed, the second sub-wire 520B is not protected by other film layers. In subsequent manufacturing processes or during use of the display substrate, there is a risk that the second sub-wire 520B will be corroded, resulting in touch failure.

[0113] To avoid the problem, the inventors have found that the second sub-wiring 520B can be covered by the color filter layer 600, i.e., the color filter layer 600 includes a protection portion 610 located in the peripheral area NA, a normal projection of the protection portion 610 on the substrate 100 at least partially overlaps a normal projection of the second sub-wiring 520B on the substrate 100, and the second sub-wiring 520B is covered by the protection portion 610, so that the problem of corrosion of the second sub-wiring 520B due to exposure of the second sub-wiring 520B can be effectively avoided.

[0114] According to some exemplary embodiments, with reference to FIGS. 3, 7 and 9, the protection portion 610 can be located in at least one of the first sub-color filter layer CF1, the second sub-color filter layer CF2 and the third sub-color filter layer CF3.

[0115] For example, the protection portion 610 can be located in the first sub-color filter layer CF1 (the protection portion 610 is formed together in a process of forming the first sub-color filter layer CF1), i.e., the protection portion 610 is formed at a corresponding position according to a pattern of the second sub-wiring 520B to be covered, and according to a position of the protection portion 610, the protection portion 610 located in the peripheral area and a portion of the first sub-color filter layer CF1 located in the display area for filtering light can be spaced apart or connected as an integral structure.

[0116] For another example, the protection portion 610 can be located in the second sub-color filter layer CF2 (the protection portion 610 is formed together in a process of forming the second sub-color filter layer CF2), and a portion of the second sub-color filter layer CF2 (i.e., the protection portion 610) covering the second sub-wiring 520B is spaced apart from the second sub-color filter portion CF2a located in the display area AA.

[0117] For yet another example, the protection portion 610 can be located in the third sub-color filter layer CF3 (the protection portion 610 is formed together in a process of forming the third sub-color filter layer CF3), i.e., the protection portion 610 is formed at a corresponding position according to a pattern of the second sub-wiring 520B to be covered, and according to a position of the protection portion 610, the protection portion 610 located in the peripheral area and a portion of the third sub-color filter layer CF3 located in the display area for filtering light can be spaced apart or connected as an integral structure.

[0118] It should be noted that the touch electrode 510 located in the display area AA is completely covered by the color filter layer 600, and even if the first organic protection layer and the second organic protection layer are removed, the touch electrode 510 is still protected by the color filter layer 600.

[0119] According to some exemplary embodiments, referring to FIG. 3, the peripheral area NA includes a bending area NA1 and a binding area NA2, the bending area NA1 is located at one side of the display area AA along the second direction Y and is spaced apart from the display area AA, the binding area NA2 is located at one side of the bending area NA1 away from the display area AA and is spaced apart from the bending area NA1, one end of the touch wire 520 is electrically connected with the touch electrode 510, and the other end extends along the edge of the display area AA to the bending area NA1 until extending to the binding area NA2 and being electrically connected with the binding pad BP located in the binding area NA2.

[0120] The touch wire 520 includes a first wire part 521, a second wire part 522 and a third wire part 523 which are electrically connected in sequence, the first wire part 521 is located at one side of the bending area NA1 close to the display area AA, the second wire part 522 is located in the bending area NA1, and the third wire part 523 is located at one side of the bending area NA1 away from the display area AA, one end of the first wire part 521 is electrically connected with the touch electrode 510 and the other end is electrically connected with the second wire part 522, one end of the second wire part 522 away from the first wire part 521 is electrically connected with the third wire part 523, and one end of the third wire part 523 away from the second wire part 522 is electrically connected with the binding pad BP.

[0121] It should be noted that considering that there is a certain deviation between the actually bent area and the designed bending area in the process of bending the bending area NA1 of the display substrate due to factors such as process precision, in order to avoid damaging the structure located in the binding area NA2 in the bending process, a certain gap needs to be left between the bending area NA1 and the binding area NA2. In the interval area between the bending area NA1 and the binding area NA2, the relevant signal wire continuously extends from the bending area NA1 to the binding area NA2 until being electrically connected with the binding pad BP located in the binding area NA2.

[0122] Referring to FIGS. 3, 8 and 9, the first wire part 521 located inside the bending area NA1 can be arranged in a double-layer wire manner and covered by the color film layer 600, that is, the first wire part 521 includes a first sub-part 5211 and a second sub-part 5212 which are electrically connected, the first sub-part 5211 is located in the first touch metal layer TMA, and the second sub-part 5212 is located in the second touch metal layer TMB, the protection part 610 includes a first protection part 611 located at one side of the bending area NA1 close to the display area AA, and the orthographic projection of the first protection part 611 on the substrate 100 at least partially overlaps with the orthographic projection of the second sub-part 5212 on the substrate 100.

[0123] FIG. 10 schematically shows an enlarged view of the area A1 in FIG. 3. FIG. 10 only schematically shows the touch layer and the barrier structure located in the area.

[0124] According to some exemplary embodiments, in combination with reference to FIG. 3, FIG. 8, FIG. 9 and FIG. 10, the encapsulation layer 400 includes the dam D AM, the first inorganic encapsulation layer CVD1, the organic encapsulation layer IJP located on the side of the first inorganic encapsulation layer CVD1 away from the substrate base plate 100, and the second inorganic encapsulation layer CVD2 located on the side of the organic encapsulation layer IJP away from the substrate base plate 100, the dam D AM is arranged around the display area AA and located on the side of the bending area NA1 close to the display area AA, the organic encapsulation layer IJP is located on the side of the dam D AM close to the display area AA, and the dam D AM is used to define the boundary of the organic encapsulation layer IJP in the process of forming the organic encapsulation layer IJP.

[0125] The dam D AM can be formed by a multi-layer film layer stack, for example, the dam D AM can include a part of the driving circuit layer 200, and the dam D AM can also include a part of the pixel definition layer PDL. The inventors have found through research that due to the high height of the dam D AM, the material of the color film layer 600 includes organic material, and the color film layer 600 will have a leveling process when it is formed, so that the color film layer 600 can not completely cover the second sub-part 5212 in the part above the dam D AM. In order to avoid the exposure of the second sub-part 5212 above the dam D AM, the second sub-part 5212 can be discontinuously arranged at the dam D AM, and the first sub-part 5211 continuously extends from the side of the dam D AM close to the display area AA to the side of the dam D AM close to the bending area NA1, so as to ensure the transmission of the touch signal.

[0126] That is, the first sub-part 5211 continuously extends from the side of the dam D AM close to the display area AA to the side of the dam D AM close to the bending area NA1, the touch insulation layer TLD covers the first sub-part 5211, the second sub-part 5212 is spaced apart from the dam D AM on the substrate base plate, the first protection part 611 is spaced apart from the dam D AM on the substrate base plate, and the first protection part 611 on the substrate base plate covers the second sub-part 5212 on the substrate base plate.

[0127] According to some exemplary embodiments, in combination with reference to FIG. 3 and FIG. 10, the second sub-part 5212 is located on the side of the dam D AM close to the display area AA away from the display area AA, the second sub-part 5212 is spaced apart from the side of the dam D AM close to the display area AA by a predetermined distance, and the end of the first protection part 611 close to the dam D AM is closer to the dam D AM than the end of the second sub-part 5212 close to the dam D AM, so that the first protection part 611 can better cover the second sub-part 5212.

[0128] FIG. 11 schematically shows an enlarged view of the region A1 in FIG. 3. FIG. 10 schematically shows the touch layer and the barrier structure in the region.

[0129] According to some exemplary embodiments, with reference to FIGS. 3 and 11, a part of the second sub-portion 5212 is located on the side of the barrier DAM close to the display region AA, and another part of the second sub-portion 5212 is located on the side of the barrier DAM away from the display region AA, that is, the second sub-portion 5212 has a break at the barrier DAM. A part of the first protective portion 611 is located on the side of the barrier DAM close to the display region AA and covers the part of the second sub-portion 5212 on the side of the barrier DAM close to the display region AA, and a part of the first protective portion 611 is located on the side of the barrier DAM away from the display region AA and covers the part of the second sub-portion 5212 on the side of the barrier DAM away from the display region AA.

[0130] It should be noted that FIG. 10 and FIG. 11 both schematically show the structure of the first wiring portion 521 at the barrier DAM between the bending region NA1 and the display region AA, at the barrier DAM on both sides of the display region AA along the first direction X, and at the barrier DAM on the side of the display region AA away from the bending region NA1. If the first wiring portion 521 crosses the barrier DAM, the structure can be set according to the structure schematically shown in FIG. 10 or FIG. 11.

[0131] According to some exemplary embodiments, with reference to FIGS. 3, 8 and 11, the part of the first wiring portion 521 on the side of the barrier DAM close to the display region AA can include a transverse wiring portion 521a extending along the first direction X and a vertical wiring portion 521b extending along the second direction Y, and one end of the vertical wiring portion 521b extends in the direction towards the barrier DAM. In the plurality of transverse wiring portions 521a arranged along the second direction Y, the first touch metal layer TMA and the second touch metal layer TMB can be used to alternatively wire, that is, in two adjacent transverse wiring portions 521a, one transverse wiring portion 521a is located on the first touch metal layer TMA, and the other transverse wiring portion 521a is located on the second touch metal layer TMB. In this way, the orthogonal projection of the two adjacent transverse wiring portions on the substrate 100 can be tangent or partially overlapped, so as to reduce the total width of the plurality of transverse wiring portions 521a along the second direction Y, and facilitate the realization of narrow frame display.

[0132] It should be noted that the tangent of the orthogonal projection of the two structures means that the orthogonal projection of one structure does not overlap the orthogonal projection of the other structure, and the edge of the orthogonal projection of one structure partially overlaps the edge of the orthogonal projection of the other structure.

[0133] According to some exemplary embodiments, referring to FIGS. 8 and 11, the vertical wire portion 521b is arranged in a double-layer wire structure of the first touch metal layer TMA and the second touch metal layer TMB, and the orthogonal projections of adjacent vertical wire portions 521b on the substrate are spaced apart.

[0134] According to some exemplary embodiments, referring to FIGS. 2 and 9, the color filter layer 600 includes a first sub-color filter layer CF1, a second sub-color filter layer CF2, a third sub-color filter layer CF3, and a black matrix layer BM (i.e., the structure shown in FIG. 2), and the protection portion 610 can be located in at least one of the first sub-color filter layer CF1, the second sub-color filter layer CF2, the third sub-color filter layer CF3, and the black matrix layer BM.

[0135] According to some exemplary embodiments, referring to FIGS. 5 and 9, the color filter layer 600 includes a first sub-color filter layer CF1, a second sub-color filter layer CF2, and a third sub-color filter layer CF3, and the protection portion 610 can be located in at least one of the first sub-color filter layer CF1, the second sub-color filter layer CF2, and the third sub-color filter layer CF3.

[0136] It should be noted that the layers in the color filter layer 600 are sequentially formed in a predetermined order, and the protection portion 610 can be located in the layer that is formed first in the color filter layer 600, so as to avoid the problem that the exposed part of the touch wire is corroded by the developing solution in the process of forming at least one layer in the color filter layer 600, for example, the first sub-color filter layer CF1 is formed first, and the protection portion 610 can be located in the first sub-color filter layer CF1, or the black matrix layer BM is formed first, and the protection portion 610 can be located in the black matrix layer BM.

[0137] For example, the first sub-color filter layer CF1 can be a red color filter, that is, the red color filter is formed first, and the protection portion 610 is formed together in the process of forming the red color filter.

[0138] According to some exemplary embodiments, referring to FIGS. 3 and 8, the part of the touch wire 520 located in the bending area NA1 is at risk of being broken, and the inventors have found through research that arranging the part of the touch wire 520 located in the bending area NA1 in the driving circuit layer 200 can greatly reduce the risk of the part of the wire being broken in the bending process. That is, the second wire portion 522 is located in the driving circuit layer 200, the driving circuit layer 200 includes multiple metal layers, and the second wire portion 522 can be located in one of the metal layers, thereby effectively avoiding the problem of the second wire portion 522 being broken when bending.

[0139] FIG. 12 schematically shows a cross-sectional view of a driving circuit layer in a display substrate according to some embodiments of the present disclosure.

[0140] According to some exemplary embodiments, in combination with reference to FIG. 3 and FIG. 12, the driving circuit layer 200 can include a buffer layer buffer on the substrate 100, an active layer Poly on the side of the buffer layer buffer away from the substrate 100, a first gate insulating layer GI1 on the side of the active layer Poly away from the substrate 100, a first gate metal layer Gate1 on the side of the first gate insulating layer GI1 away from the substrate 100, a second gate insulating layer GI2 on the side of the first gate metal layer Gate1 away from the substrate 100, a second gate metal layer Gate2 on the side of the second gate insulating layer GI2 away from the substrate 100, an interlayer dielectric layer ILD on the side of the second gate metal layer Gate2 away from the substrate 100, a first source-drain metal layer SD1 on the side of the interlayer dielectric layer ILD away from the substrate 100, a passivation layer PVX on the side of the first source-drain metal layer SD1 away from the substrate 100, a first planarization layer PLN1 on the side of the passivation layer PVX away from the substrate 100, a second source-drain metal layer SD2 on the side of the first planarization layer PLN1 away from the substrate 100, a second planarization layer PLN2 on the side of the second source-drain metal layer SD2 away from the substrate 100, a third source-drain metal layer SD3 on the side of the second planarization layer PLN2 away from the substrate 100, and a third planarization layer PLN3 on the side of the third source-drain metal layer SD3 away from the substrate 100.

[0141] For example, in the driving circuit layer 200 shown in FIG. 12, the second wiring part 522 can be located in at least one of the first source-drain metal layer SD1, the second source-drain metal layer SD2, and the third source-drain metal layer SD3.

[0142] For another example, the second wiring part 522 can be located in the second source-drain metal layer SD2. The inventors have found through research that among the metal film layers located in the bending area, the second source-drain metal layer SD2 is closest to the neutral layer and is subjected to the least bending stress when bending. Therefore, locating the second wiring part 522 in the second source-drain metal layer SD2 can further reduce the risk of breakage of the second wiring part 522 when bending.

[0143] According to some exemplary embodiments, the driving circuit layer includes a plurality of pixel driving circuits, and each pixel driving circuit can include a plurality of transistors and at least one capacitor. For example, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Among them, T in the above circuit structure refers to a thin-film transistor, C refers to a capacitor, and the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0144] According to some exemplary embodiments, the plurality of transistors in the pixel driving circuit can employ low temperature poly-silicon thin film transistors, or can employ oxide thin film transistors, or can employ both low temperature poly-silicon thin film transistors and oxide thin film transistors. The active layer of the low temperature poly-silicon thin film transistor employs low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor employs oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. By integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display panel, i.e., an LTPS+Oxide (LTPO for short) display panel, the advantages of both can be utilized, low frequency driving can be achieved, power consumption can be reduced, and display quality can be improved.

[0145] FIG. 13 schematically shows an enlarged view of region A2 in FIG. 3. FIG. 14A schematically shows an enlarged view of region A3 in FIG. 13. FIG. 14B schematically shows a cross-sectional view taken along line HH’ in FIG. 14A.

[0146] According to some exemplary embodiments, in combination with reference to FIGS. 10, 12, 13, 14A and 14B, the first wiring portion 521 includes a first sub-portion 5211 and a second sub-portion 5212, the second wiring portion 522 is located in the second source-drain metal layer SD2, the first sub-portion 5211 is electrically connected to the third connection portion 210 located in the third source-drain metal layer SD3 through the first via V1 located in the touch buffer layer TBL and the second via V2 located in the third planarization layer PLN3, and the third connection portion 210 is electrically connected to the second wiring portion 522 through the third via V3 located in the second planarization layer PLN2, so that the first wiring portion 521 is electrically connected to the second wiring portion 522.

[0147] In addition, the third planarization layer PLN3 and the touch buffer layer TBL also have a first inorganic encapsulation layer CVD1 and a second inorganic encapsulation layer CVD2 therebetween. In the process of etching the first via V1, the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 are etched together until the third connection portion 210 is exposed.

[0148] It should be noted that FIGS. 14A and 14B schematically show the case where the driving circuit layer has the second source-drain metal layer SD2 and the third source-drain metal layer SD3. Alternatively, when the driving circuit layer only includes the second source-drain metal layer SD2 and the first source-drain metal layer, the first sub-portion 5211 can be directly connected to the second wiring portion 522.

[0149] It should be noted that in order to more clearly show the distribution position and connection relationship of some wires in the region, a part of the gap between the wires is omitted in FIG. 13, for example, the plurality of first wire portions 521 and the plurality of second wire portions 522 are connected into a block structure, but in the actual display substrate, there is a gap between adjacent first wire portions 521, and there is also a gap between adjacent second wire portions 522.

[0150] FIG. 15A schematically shows another enlarged view of the region A3 in FIG. 13. FIG. 15B schematically shows a cross-sectional view taken along line JJ' in FIG. 15A. According to some exemplary embodiments, in combination with reference to FIGS. 8, 10, 12, 13 and 15A, the first wire portion 521 includes a first sub-portion 5211 and a second sub-portion 5212, the second wire portion 522 is located in the second source-drain metal layer SD2, the touch wire 520 further includes a transfer portion 524 located in the second touch metal layer TMB, one end of the transfer portion 524 away from the second wire portion 522 is electrically connected with the first sub-portion 5211 through a fourth via V4 located in the touch insulation layer TLD, the other end of the transfer portion 524 is electrically connected with the third connection portion 210 through a fifth via V5 located in the touch insulation layer TLD and a sixth via V6 located in the third planarization layer PLN3, the third connection portion 210 is located in the third source-drain metal layer SD3, and the third connection portion 210 is further electrically connected with the second wire portion 522 through a third via V3 located in the second planarization layer PLN2, so that the first wire portion 521 is electrically connected with the second wire portion 522. This scheme of using the transfer portion 524 to electrically connect the first wire portion 521 with the second wire portion 522 makes the touch buffer layer TBL not need to be exposed using Mask, which is beneficial to further reduce the manufacturing cost of the display substrate.

[0151] It should be noted that FIGS. 15A and 15B schematically show the case that the drive circuit layer has the second source-drain metal layer SD2 and the third source-drain metal layer SD3. Alternatively, when the drive circuit layer only includes the second source-drain metal layer SD2 and the first source-drain metal layer, the transfer portion 524 can be directly connected with the second wire portion 522.

[0152] It should be noted that the third planarization layer PLN3 and the touch insulation layer TLD also have a touch buffer layer TBL, a first inorganic packaging layer CVD1 and a second inorganic packaging layer CVD2, and in the process of etching the fifth via V5, the touch buffer layer TBL, the first inorganic packaging layer CVD1 and the second inorganic packaging layer CVD2 are etched together until the third connecting portion 210 is exposed. That is, the fifth via V5 connecting the adapter portion 524 and the third connecting portion 210 is formed in the patterning process of the touch insulation layer TLD, and the via in the touch buffer layer TBL is a via etched together in the patterning process of the touch insulation layer TLD. There is no other via in the touch buffer layer TBL that needs to be formed by a separate patterning process, so the touch buffer layer TBL does not need to use a mask for patterning process.

[0153] It should be noted that, in combination with reference to FIG. 11 and FIG. 15A, when the first wiring portion 521 adopts the structure shown in FIG. 11, the adapter portion 524 is connected to the second sub-portion 5212 as an integral structure.

[0154] According to some exemplary embodiments, in combination with reference to FIG. 3 and FIG. 15B, the color film layer 600 further includes a third protection portion 613 located in the peripheral area NA, and a projection of the third protection portion 613 on the substrate substrate covers a projection of the adapter portion 524 on the substrate substrate 100. By covering the adapter portion 524 through the third protection portion 613, the problem of connection failure between the first wiring portion 521 and the second wiring portion 522 due to corrosion of the adapter portion 524 can be effectively avoided.

[0155] Optionally, the display substrate further includes a protective adhesive layer covering the surface of the bending area, and the third protection portion can also be located in the protective adhesive layer, that is, the third protection portion is formed at the same time as the protective adhesive layer located in the bending area is formed.

[0156] FIG. 16 schematically shows an enlarged view of the area A4 in FIG. 3. FIG. 17 schematically shows a cross-sectional view taken along the line FF' in FIG. 16.

[0157] According to some exemplary embodiments, in combination with reference to FIG. 3, FIG. 8, FIG. 16 and FIG. 17, the third wiring portion 523 can adopt a similar wiring scheme as the first wiring portion 521, adopt double-layer wiring of the first touch metal layer TMA and the second touch metal layer TMB, and be protected by the color film layer 600.

[0158] With reference to FIGS. 16 and 17, the third trace portion 523 includes a third sub-portion 5231 and a fifth sub-portion 5233, the third sub-portion 5231 is located in the first touch metal layer TMA, and the fifth sub-portion 5233 is located in the second touch metal layer TMB, and the third sub-portion 5231 and the fifth sub-portion 5233 are electrically connected by at least one via in the touch insulating layer TLD. The protection portion 610 includes a second protection portion 612 located away from the display area AA side of the bending area NA1, and a projection of the second protection portion 612 on the substrate substrate at least partially overlaps a projection of the fifth sub-portion 5233 on the substrate substrate.

[0159] According to some exemplary embodiments, with reference to FIG. 16, the second protection portion 612 is a block-shaped whole structure, and an edge of the second protection portion 612 can be extended and arranged along an edge of the third trace portion 523 located on the outer side. On both sides of the plurality of third trace portions 523 along the row direction (i.e., the first direction shown in FIG. 3) and the side of the third trace portion 523 away from the bonding pad BP, the second protection portion 612 completely covers the edge of the plurality of third trace portions 523, and the exceeding distance is greater than or equal to 8 microns, so as to ensure the coverage of the second protection portion 612 to the third trace portion 523.

[0160] In addition, the projection of the second protection portion 612 on the substrate substrate is spaced apart from the projection of the bonding pad BP on the substrate substrate, so that the bonding pad BP can be electrically connected with the circuit board. Therefore, at the end of the plurality of third trace portions 523 connected with the bonding pad BP, there is a part of the third trace portion 523 not covered by the second protection portion 612.

[0161] It should be noted that, due to the too dense arrangement of the third trace portion 523, FIG. 16 only schematically shows the gap between part of the adjacent third trace portions 523, and in actual products, there is a gap between any adjacent third trace portions 523.

[0162] According to some exemplary embodiments, the connection mode of the third trace portion 523 and the second trace portion 522 can be set by referring to the connection mode of the first trace portion 521 and the second trace portion 522 described above, which will not be described herein again.

[0163] FIG. 18 schematically shows an enlarged view of the area A5 in FIG. 3. FIG. 19 schematically shows a cross-sectional view taken along the line GG' in FIG. 18.

[0164] The inventors have found that, in the module segment preparation process of the display substrate (for example, a process of binding the circuit board to the binding pads of the binding area), the second protection portion 612 located away from the display area AA in the bending area NA1 has a risk of peeling off the third trace portion 523, thereby exposing the third trace portion 523 and causing reliability problems. In order to avoid this problem, the inventors have further designed the structure of the third trace portion 523.

[0165] Referring to FIGS. 18 and 19, the third trace portion 523 includes a third sub-portion 5231 located in the first touch metal layer TMA, and a projection of the touch insulating layer TLD on the substrate substrate at least partially overlaps with a projection of the third sub-portion 5231 on the substrate substrate. The third trace portion 523 can only include the third sub-portion 5231 located in the first touch metal layer TMA, the third sub-portion 5231 can be covered by the touch insulating layer TLD, and the adhesion between the touch insulating layer TLD and the third sub-portion 5231 is relatively close, and the touch insulating layer TLD is not easy to peel off from the third sub-portion 5231.

[0166] According to some exemplary embodiments, referring to FIGS. 3, 12, 13 and 19, the driving circuit layer 200 includes a power supply trace PL, the power supply trace PL includes a power supply trace sub-portion PL1 located away from the display area AA in the bending area NA1, the projection of the power supply trace sub-portion PL1 on the substrate substrate at least partially overlaps with the projection of the third trace portion 523 on the substrate substrate, and the power supply trace sub-portion PL1 is located on the side of the third trace portion 523 close to the substrate substrate. Since the third trace portion 523 only includes the third sub-portion 5231 located in the first touch metal layer TMA, the power supply trace sub-portion PL1 can be located in the first source-drain metal layer SD1, the second source-drain metal layer SD2 and the third source-drain metal layer SD3, and the power supply trace sub-portion PL1 has a three-layer trace structure, so that the resistance of the power supply trace sub-portion PL1 is low.

[0167] For example, the power supply trace PL can be used to input a voltage signal to the cathode or anode of the light emitting device, one end of the power supply trace PL is electrically connected to the binding pad BP located in the binding area NA2, and the other end extends into the display area AA and is electrically connected to the pixel driving circuit.

[0168] It should be noted that when the third trace portion 523 only includes the third sub-portion 5231 located in the first touch metal layer TMA, the third trace portion 523 can be electrically connected to the second trace portion 522 directly through the via in the touch buffer layer TBL (for example, the connection mode shown in FIGS. 14A and 14B), or can be electrically connected to the second trace portion 522 through the adapter in the second touch metal layer TMB (for example, the connection mode shown in FIGS. 15A and 15B).

[0169] Optionally, the third trace portion 523 can also not include the third sub-portion 5231 located at the first touch metal layer TMA, and only include the fifth sub-portion of the second touch metal layer, which is also covered by the second protection portion. For details, refer to the structure shown in FIG. 17. When the third trace portion 523 only includes the fifth sub-portion of the second touch metal layer, the fifth sub-portion of the second touch metal layer can be connected to the connection portion of the third source-drain metal layer through the via in the touch buffer layer, and then connected to the second trace portion of the second source-drain metal layer, so as to realize the signal transmission between the third trace portion and the second trace portion.

[0170] FIG. 20 schematically shows another cross-sectional view taken along the line GG' in FIG. 18.

[0171] According to some exemplary embodiments, in combination with reference to FIGS. 8, 18 and 20, in order to further reduce the resistance of the third trace portion 523, the third trace portion 523 can further include a fourth sub-portion 5232, which is electrically connected to the third sub-portion 5231, and the fourth sub-portion 5232 is located at the driving circuit layer 200, i.e., a part of the metal layer at the driving circuit layer 200 is electrically connected to the third trace portion 523, so as to effectively reduce the resistance of the third trace portion 523, and further reduce the signal attenuation generated by the third trace portion 523 when transmitting the touch signal.

[0172] According to some exemplary embodiments, in combination with reference to FIGS. 12, 18 and 20, the driving circuit layer 200 can include a first source-drain metal layer SD1, a second source-drain metal layer SD2 located away from the substrate 100 on one side of the first source-drain metal layer SD1, and a third source-drain metal layer SD3 located away from the substrate 100 on one side of the second source-drain metal layer SD2, and the fourth sub-portion 5232 is located at the third source-drain metal layer SD3. The third sub-portion 5231 is electrically connected to the fourth sub-portion 5232 through a seventh via V7 located in the touch buffer layer TBL and an eighth via V8 located in the third planarization layer PLN3. The third planarization layer PLN3 and the touch buffer layer TBL further have a first inorganic encapsulation layer CVD1 and a second inorganic encapsulation layer CVD2 therebetween. In the process of etching to form the seventh via V7, the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 are etched at the same time until the fourth sub-portion 5232 is exposed.

[0173] With reference to FIGS. 12, 13 and 20, when the third trace portion 523 includes the third sub-portion 5231 and the fourth sub-portion 5232 located at the third source-drain metal layer SD3, the power supply trace sub-portion PL1 can be located at the first source-drain metal layer SD1 and the second source-drain metal layer SD2, the power supply trace sub-portion PL1 has a double-layer trace structure, compared to the scheme that the power supply trace sub-portion PL1 can be located at the first source-drain metal layer SD1, the second source-drain metal layer SD2 and the third source-drain metal layer SD3, through voltage drop (IR Drop) simulation analysis, the amount of power supply voltage drop does not appear obvious increase.

[0174] According to some exemplary embodiments, with reference to FIGS. 12, 18 and 20, the third trace portion 523 includes the third sub-portion 5231 and the fourth sub-portion 5232 located at the third source-drain metal layer SD3, the fourth sub-portion 5232 can be electrically connected with the second trace portion 522 through the via located in the second planarization layer PLN2, so as to realize the electrical connection between the third trace portion 523 and the second trace portion 522.

[0175] FIG. 21 schematically shows another cross-sectional view taken along the line GG' in FIG. 18.

[0176] According to some exemplary embodiments, with reference to FIGS. 12, 18 and 21, the driving circuit layer 200 can include the first source-drain metal layer SD1, the second source-drain metal layer SD2 located at the side of the first source-drain metal layer SD1 away from the substrate substrate 100, and the third source-drain metal layer SD3 located at the side of the second source-drain metal layer SD2 away from the substrate substrate 100, and the fourth sub-portion 5232 is located at the third source-drain metal layer SD3 and the second source-drain metal layer SD2. That is, the third trace portion 523 is located at the first touch metal layer TMA, the third source-drain metal layer SD3 and the second source-drain metal layer SD2, and the third trace portion 523 has a three-layer trace structure, so that the resistance of the third trace portion 523 is further reduced.

[0177] The third sub-portion 5231 is electrically connected with the fourth sub-portion 5232 through the seventh via V7 located in the touch buffer layer TBL and the eighth via V8 located in the third planarization layer PLN3, and the part of the fourth sub-portion 5232 located at the third source-drain metal layer SD3 is electrically connected with the part located at the second source-drain metal layer SD2 through the ninth via V9 in the second planarization layer PLN2.

[0178] With reference to FIGS. 12, 13 and 21, when the third trace portion 523 includes the third sub-portion 5231 and the fourth sub-portion 5232 located at the third source-drain metal layer SD3 and the second source-drain metal layer SD2, the power supply trace sub-portion PL1 can be located at the first source-drain metal layer SD1.

[0179] According to some exemplary embodiments, in combination with reference to FIGS. 12, 18 and 21, the third wiring portion 523 includes a third sub-portion 5231 and a fourth sub-portion 5232 located at the second source-drain metal layer SD2 and the third source-drain metal layer SD3. The fourth sub-portion 5232 located at the part of the second source-drain metal layer SD2 can be connected to the second wiring portion 522 as an integral structure, so as to realize the electrical connection between the third wiring portion 523 and the second wiring portion 522.

[0180] According to some exemplary embodiments, the third wiring portion 523 can be located only at the driving circuit layer 200. Compared with the scheme that the third wiring portion 523 is located at the driving circuit layer 200 and the first touch metal layer TMA, the touch buffer layer TBL does not need to use Mask exposure, and the manufacturing cost is lower.

[0181] FIG. 22 schematically shows another cross-sectional view taken along the line GG' in FIG. 18.

[0182] According to some exemplary embodiments, in combination with reference to FIGS. 12, 18 and 22, the driving circuit layer 200 includes the first source-drain metal layer SD1, the second source-drain metal layer SD2 located at the side of the first source-drain metal layer SD1 away from the substrate 100, and the third source-drain metal layer SD3 located at the side of the second source-drain metal layer SD2 away from the substrate 100. The third wiring portion 523 is located at the third source-drain metal layer SD3, and the third planarization layer PLN3 can protect the third wiring portion 523.

[0183] In combination with reference to FIGS. 12, 13 and 22, when the third wiring portion 523 is located at the third source-drain metal layer SD3, the power supply wiring sub-portion PL1 can be located at the first source-drain metal layer SD1 and the second source-drain metal layer SD2.

[0184] Of course, according to actual process requirements, the third wiring portion 523 can also be located at the third source-drain metal layer SD3 and the second source-drain metal layer SD2, and the power supply wiring sub-portion PL1 can be located at the first source-drain metal layer SD1.

[0185] FIG. 23 schematically shows a flowchart of a preparation method of a display substrate according to some embodiments of the present disclosure.

[0186] At least some embodiments of the present disclosure also provide a preparation method of a display substrate. With reference to FIG. 23, the preparation method includes the following steps.

[0187] In step S10, a driving circuit layer is formed on a substrate.

[0188] In step S20, a light emitting device layer is formed at the side of the driving circuit layer away from the substrate. The light emitting device layer includes a plurality of light emitting devices, and the plurality of light emitting devices are arranged at intervals along a first direction and a second direction.

[0189] In step S30, a packaging layer is formed on a side of the light-emitting device layer away from the substrate.

[0190] In step S40, a touch layer is formed on a side of the packaging layer away from the substrate, the touch layer including a touch electrode and a touch trace, the touch electrode being located in the display area, the touch trace being electrically connected with the touch electrode, at least a part of the touch trace being located in the peripheral area, the touch layer including a first touch metal layer and a second touch metal layer located on a side of the first touch metal layer away from the substrate; at least a part of the touch trace including a first sub-trace and a second sub-trace, the first sub-trace being electrically connected with the second sub-trace, the first sub-trace being located in the first touch metal layer, the second sub-trace being located in the second touch metal layer.

[0191] In step S50, a color filter layer is formed on a side of the touch layer away from the substrate, the color filter layer including a protection portion located in the peripheral area, a normal projection of the protection portion on the substrate at least partially overlapping a normal projection of the second sub-trace on the substrate.

[0192] In the preparation method, by forming the protection portion covering the second sub-trace in the process of forming the color filter layer, the problem of corrosion of the second sub-trace due to exposure can be effectively avoided without increasing the preparation process of the display substrate.

[0193] At least some embodiments of the present disclosure also provide a display device including the display substrate as described above. The display device can include any device or product having a display function. For example, the display device can be a smart phone, a mobile phone, an electronic book reader, a desktop PC (personal computer), a laptop PC, a netbook PC, a PDA (personal digital assistant), a PMP (portable multimedia player), a digital audio player, a mobile medical device, a camera, a wearable device (e.g., a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, electronic accessories, electronic tattoos, or a smart watch), a television, etc.

[0194] It should be understood that the display panel and the display device according to the embodiments of the present disclosure have all the features and advantages of the display substrate described above, and specific details can be referred to the description above, which will not be repeated here. Although some embodiments of the general inventive concept of the present disclosure have been shown and described, it would be understood by those skilled in the art that changes can be made in these embodiments without departing from the principles and spirit of the general inventive concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, The display substrate comprises a display area and a peripheral area located at the periphery of the display area, and the display substrate comprises: a substrate substrate; a driving circuit layer located on the substrate substrate; a light emitting device layer located on the side of the driving circuit layer away from the substrate substrate, the light emitting device layer comprising a plurality of light emitting devices, the plurality of light emitting devices being arranged at intervals along a first direction and a second direction; an encapsulation layer located on the side of the light emitting device layer away from the substrate substrate; a touch layer located on the side of the encapsulation layer away from the substrate substrate, the touch layer comprising a touch electrode and a touch trace, the touch electrode being located in the display area, the touch trace being electrically connected with the touch electrode, and at least a part of the touch trace being located in the peripheral area; and a color film layer located on the side of the touch layer away from the substrate substrate, wherein the touch layer comprises a first touch metal layer and a second touch metal layer located on the side of the first touch metal layer away from the substrate substrate; at least a part of the touch trace comprises a first sub-trace and a second sub-trace, the first sub-trace being electrically connected with the second sub-trace, the first sub-trace being located in the first touch metal layer, and the second sub-trace being located in the second touch metal layer; and the color film layer comprises a protection portion located in the peripheral area, and the orthographic projection of the protection portion on the substrate substrate at least partially overlaps the orthographic projection of the second sub-trace on the substrate substrate. 2.The display substrate of claim 1, wherein, The peripheral area comprises a bending area located on one side of the display area along the second direction and arranged at intervals with the display area; the touch trace comprises a first trace portion, a second trace portion and a third trace portion electrically connected in sequence, the first trace portion being located on the side of the bending area close to the display area, the second trace portion being located in the bending area, and the third trace portion being located on the side of the bending area away from the display area; the first trace portion comprises a first sub-portion and a second sub-portion electrically connected, the first sub-portion being located in the first touch metal layer, and the second sub-portion being located in the second touch metal layer; and the protection portion comprises a first protection portion located on the side of the bending area close to the display area, and the orthographic projection of the first protection portion on the substrate substrate at least partially overlaps the orthographic projection of the second sub-portion on the substrate substrate. The encapsulation layer comprises a barrier wall and an organic encapsulation layer, the barrier wall being arranged around the display area and located on the side of the bending area close to the display area, and the organic encapsulation layer being located on the side of the barrier wall close to the display area; 3.The display substrate of claim 2, wherein, the first sub-portion continuously extends from the side of the barrier wall close to the display area to the side of the barrier wall away from the display area, and the orthographic projection of the second sub-portion on the substrate substrate is spaced apart from the orthographic projection of the barrier wall on the substrate substrate; and the orthographic projection of the first protection portion on the substrate substrate is spaced apart from the orthographic projection of the barrier wall on the substrate substrate, and the orthographic projection of the first protection portion on the substrate substrate covers the orthographic projection of the second sub-portion on the substrate substrate. ​ ​ 4.The display substrate of claim 3, wherein, The second sub-portion is located on the side of the barrier wall close to the display area. 5.The display substrate of claim 3, wherein, The second sub-portion is located on the side of the barrier wall close to the display area. 6.The display substrate according to any one of claims 2-5, wherein, The third trace portion includes a third sub-portion, which is located on the first touch metal layer. The touch layer includes a touch insulating layer between the first touch metal layer and the second touch metal layer, and a projection of the touch insulating layer on the substrate substrate at least partially overlaps with a projection of the third sub-portion on the substrate substrate. 7.The display substrate of claim 6, wherein, The third trace portion further includes a fourth sub-portion, which is electrically connected with the third sub-portion, and the fourth sub-portion is located on the driving circuit layer. 8.The display substrate of claim 7, wherein, The driving circuit layer includes a first source-drain metal layer, a second source-drain metal layer located on the side of the first source-drain metal layer away from the substrate substrate, and a third source-drain metal layer located on the side of the second source-drain metal layer away from the substrate substrate, and the fourth sub-portion is located on the third source-drain metal layer. 9.The display substrate of claim 7, wherein, The driving circuit layer includes a first source-drain metal layer, a second source-drain metal layer located on the side of the first source-drain metal layer away from the substrate substrate, and a third source-drain metal layer located on the side of the second source-drain metal layer away from the substrate substrate, and the fourth sub-portion is located on the third source-drain metal layer and the second source-drain metal layer. 10.The display substrate of any one of claims 2-9, wherein, The third trace portion includes a fifth sub-portion, which is located on the second touch metal layer. The protection portion includes a second protection portion located on the side of the bending area away from the display area, and a projection of the second protection portion on the substrate substrate at least partially overlaps with a projection of the fifth sub-portion on the substrate substrate. 11.The display substrate of any one of claims 2-5, wherein, The third trace portion is located on the driving circuit layer. 12.The display substrate of claim 11, wherein, The driving circuit layer includes a first source-drain metal layer, a second source-drain metal layer located on the side of the first source-drain metal layer away from the substrate substrate, and a third source-drain metal layer located on the side of the second source-drain metal layer away from the substrate substrate. The third trace portion is located on the third source-drain metal layer, or the third trace portion is located on the third source-drain metal layer and the second source-drain metal layer. The driving circuit layer includes a power supply trace, and the power supply trace includes a power supply trace sub-portion located on the side of the bending area away from the display area. 13.The display substrate of any one of claims 2-12, wherein, The projection of the power supply trace sub-portion on the substrate substrate at least partially overlaps with the projection of the third trace portion on the substrate substrate, and the power supply trace sub-portion is located on the side of the third trace portion close to the substrate substrate. The second trace portion is located on the driving circuit layer. The touch trace further includes a switching portion, one end of the switching portion is directly connected with the first trace portion and the other end is connected with the second trace portion, and the switching portion is located on the second touch metal layer. 14.The display substrate according to any one of claims 2-13, wherein, The color film layer includes a first sub-color film layer, a second sub-color film layer, and a third sub-color film layer, and the light emitting device layer includes a first light emitting device, a second light emitting device, and a third light emitting device. 15.The display substrate of claim 14, wherein, ​ 16.The display substrate according to any one of claims 1-15, wherein, ​ A normal projection of the first sub-color filter layer on the substrate substrate covers a normal projection of the first light emitting device on the substrate substrate, a normal projection of the second sub-color filter layer on the substrate substrate covers a normal projection of the second light emitting device on the substrate substrate, and a normal projection of the third sub-color filter layer on the substrate substrate covers a normal projection of the third light emitting device on the substrate substrate; and At least two of the first sub-color filter layer, the second sub-color filter layer, and the third sub-color filter layer include a portion located in a spacing region of the light emitting device; and / or, The protection portion is located in at least one of the first sub-color filter layer, the second sub-color filter layer, and the third sub-color filter layer.

17. A display device, wherein, The display device includes the display substrate according to any one of claims 1-16.

Images