Display apparatus and driving method therefor

Abstract

Provided in the present application are a display apparatus and a driving method therefor. The display apparatus comprises a display panel and a control circuit, wherein the control circuit generates a ramp signal and inputs same into pixel units in N regions of the display panel, which N regions are delimited in a scanning direction, and the control circuit sequentially controls, within one frame, the pixel units of the regions to write data and emit light. The ramp signal comprises N pulse periods in each frame, and driving periods of the pixel units comprise a data writing sub-period and a light-emission sub-period, the data writing sub-period occupying one pulse period, and the light-emission sub-period occupying N -1 pulse periods. The present solution solves the problem of the brightness regulation range of existing display apparatuses being limited.

Description

Display device and driving method thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device and a driving method thereof. BACKGROUND

[0002] Micro LED display technology mainly has two ways of pulse width modulation (PWM) and pulse amplitude modulation (PAM) in circuit architecture, each with advantages and disadvantages. Corresponding light emitting methods have global light emission and progressive light emission.

[0003] In the scheme of global light emission, since the entire display panel emits light at the same time after data writing, a high instantaneous current is generated. This situation is particularly evident in the PWM circuit architecture, and a high instantaneous current is generated at different gray scales. This has an adverse effect on the power consumption and internal voltage drop (IR drop) of the display panel.

[0004] On the other hand, micro LED display technology also needs to be compatible with ultra-high brightness and ultra-low brightness at the same time, which requires the light emitting time to be adjusted in a larger range.

[0005] The traditional PWM driving method is difficult to meet the needs of low power consumption and wide brightness range. While the pure progressive light emission can reduce the instantaneous current, it needs to input the ramp signal row by row and shift row by row, which increases the circuit complexity and cost.

[0006] Therefore, how to realize a wider brightness adjustment range in micro LED display technology, while reducing power consumption, improving gray scale accuracy, and improving the impact of flicker, has become a technical problem that needs to be solved at present. SUMMARY

[0007] Embodiments of the present application provide a display device and a driving method thereof, aiming to solve the technical problem of limited brightness adjustment range in the existing display device.

[0008] Embodiments of the present application provide a display device, comprising: a display panel, the display panel comprising N regions divided along a scanning direction, each region comprising a plurality of pixel units, N being an integer greater than 1; and a control circuit electrically connected to the plurality of pixel units, the control circuit being configured to generate a ramp signal and input the ramp signal to the plurality of pixel units, and to sequentially control the pixel units of each of the N regions to perform data writing and light emission in a driving period of a frame of picture; wherein the ramp signal comprises N pulse periods in the driving period of the frame of picture, the driving period of the pixel units of each region comprises a data writing sub-period and a light emission sub-period, the data writing sub-period precedes the light emission sub-period, the data writing sub-period comprises one pulse period of the ramp signal, and the light emission sub-period comprises N-1 pulse periods of the ramp signal.

[0009] Embodiments of the present application also provide a driving method of a display device, a display panel of the display device comprising N regions divided along a scanning direction, each region comprising a plurality of pixel units, N being an integer greater than 1, the driving method comprising: generating a ramp signal, the ramp signal comprising N pulse periods in a driving period of a frame of picture; inputting the ramp signal to the plurality of pixel units; and sequentially controlling the pixel units of each of the N regions to perform data writing and light emission in the driving period of the frame of picture; wherein the driving period of the pixel units of each region comprises a data writing sub-period and a light emission sub-period, the data writing sub-period precedes the light emission sub-period, the data writing sub-period comprises one pulse period of the ramp signal, and the light emission sub-period comprises N-1 pulse periods of the ramp signal. Advantages

[0010] Embodiments of the present application effectively solve the technical problems of limited brightness adjustment range, high power consumption, insufficient gray scale accuracy, and obvious flicker phenomenon in the prior art by adopting a pulse width modulation driving mode combining a global ramp signal with multi-pulse and realizing progressive light emission. Specifically, embodiments of the present application adopt a global ramp signal to ensure that all pixel units receive the same ramp signal, thereby improving display consistency. In addition, embodiments of the present application introduce multi-pulse light emission technology. In the driving period of a frame of picture, the ramp signal contains multiple pulse periods, so that the pixel units in each region can emit light multiple times, thereby expanding the brightness adjustment range. In particular, when displaying in low gray scale, the flicker phenomenon can be effectively improved. By adjusting the number of pulses and the light emission time of each pulse, the light emission duty cycle can be flexibly controlled to meet the wide display requirements from ultra-low brightness to ultra-high brightness. In addition, embodiments of the present application adopt a progressive light emission mode to divide the display panel into multiple regions. The pixel units in each region sequentially complete data writing and multiple light emission in the driving period of a frame of picture, thereby not only improving the display effect but also significantly reducing the instantaneous current to effectively solve the problem of high power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0011] FIG. 1 is a schematic diagram of a display device according to an embodiment of the present application.

[0012] FIG. 2 is a schematic diagram of region division of a display device according to an embodiment of the present application.

[0013] FIG. 3 is a circuit diagram of a pixel unit of a display device according to an embodiment of the present application.

[0014] FIG. 4 is a waveform diagram of various signals in the display device shown in FIG. 3. Embodiments of the present application

[0015] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0016] The terms "first", "second", and similar terms do not denote any order, quantity, or importance, but are only used to distinguish different technical features. The term "multiple" and similar terms mean two or more, unless otherwise explicitly limited.

[0017] Embodiments of the present application can be combined with each other.

[0018] As shown in FIG. 1, the display device provided by embodiments of the present application may, for example, be a Micro-LED display device. Of course, the display device can also be a Mini-LED display device or an OLED display device. Embodiments of the present application are described with reference to a Micro-LED display device.

[0019] The display device comprises a source driving circuit, a gate driving circuit, a timing controller, a light emitting controller, a power management chip, a substrate, a data line DATA, a scanning line SCAN, a power line (VDD, VSS), a light emitting control signal line EM, a pixel array, a packaging layer, a polarizer, a color filter, and the like.

[0020] The substrate may be, for example, a glass substrate, a flexible substrate (for example, a polyimide substrate), or the like. The pixel array is formed by a plurality of pixel units PX arranged in rows and columns, each pixel unit PX comprising a light emitting device and a driving circuit. The driving circuit comprises a TFT device for controlling the brightness of each light emitting device of the display device, the TFT device comprising low temperature polysilicon (LTPS) and metal oxide TFT, the light emitting device being electrically connected to the driving circuit, the light emitting device comprising a light emitting layer, an electron transport layer, a hole transport layer, a cathode, an anode, and the like. Each stage of the gate driving unit in the gate driving circuit corresponds to control a row of pixel units PX, for realizing the selection of the pixel units PX. Each stage of the gate driving unit is composed of a thin film transistor (TFT) and a capacitor. The source driving circuit is used to provide data signals to the pixel units PX. The timing controller is used to receive externally input image data and synchronization signals, and to generate signals required by the gate driving circuit and the source driving circuit. The power management chip is used to provide the required operating voltage for each part of the display device.

[0021] In addition, the display device of the present application can also integrate an embedded touch circuit, which is electrically connected to the display driving circuit, and realizes the touch function and the display function in a time division multiplexing manner.

[0022] Embodiments of the present application provide a display device and a driving method thereof. The display device comprises a display panel and a control circuit. As shown in FIG. 2, the display panel comprises N regions (R1-RN) divided along a scanning direction SD, each region comprising a plurality of pixel units PX, and N is an integer greater than 1. The control circuit is electrically connected to the plurality of pixel units PX, used to generate a ramp signal Sweep, input the ramp signal Sweep to the plurality of pixel units PX, and sequentially control the pixel units PX in each region of the N regions (R1-RN) to perform data writing and light emitting in a driving period of a frame of picture.

[0023] The ramp signal Sweep in the display device and the driving method thereof provided by the embodiments of the present application is a global multi-pulse signal. Global means that one ramp signal Sweep is provided to all pixel units PX of the entire display panel, that is, one ramp signal output terminal is electrically connected to all pixel units PX of the entire display panel. Multi-pulse means that the ramp signal Sweep has a plurality of pulse periods in the driving period of a frame of picture. In the embodiments of the present application, the number of pulse periods is the same as the number of regions of the display panel.

[0024] The display device and the driving method thereof provided by the embodiments of the present application include N pulse periods in a sweep signal Sweep in a driving period of a frame picture, and the driving period of the pixel unit PX of each region includes a data writing sub-period and a light emitting sub-period, the data writing sub-period precedes the light emitting sub-period, the data writing sub-period includes one pulse period of the sweep signal Sweep, and the light emitting sub-period includes N-1 pulse periods of the sweep signal Sweep.

[0025] The display panel is divided into N regions (R1-RN) from top to bottom (along the scanning direction SD), and the pixel unit PX of each region enters a light emitting stage after data writing is completed. Due to the combination of the multi-pulse sweep signal Sweep, the pixel unit PX needs to be restarted constantly, and therefore, the pixel unit PX is reset once in each pulse period of the light emitting stage to ensure that the pixel unit PX compares the sweep signal Sweep with the data signal and then emits light in the pulse period.

[0026] As shown in FIGS. 3 and 4, the pixel unit PX in the display device provided by the embodiments of the present application includes a light emitting device 204 and a driving circuit. The driving circuit includes a pulse width modulation module 201, a pulse amplitude modulation module 203, and a reset module 202. The pulse width modulation module 201 is electrically connected with the reset module 202, the reset module 202 is electrically connected with the pulse amplitude modulation module 203, and the pulse amplitude modulation module 203 is electrically connected with the light emitting device 204.

[0027] The control circuit is configured to generate a sweep signal Sweep, a first reset control signal, and a light emitting control signal. The first reset control signal is configured to control the reset module 202 in the pixel unit PX to reset, and the light emitting control signal is configured to control the pixel unit PX to emit light.

[0028] In the embodiments of the present application, each of the N regions (R1-RN) includes M rows of pixel units PX, and M is an integer greater than 1. The control circuit provides M scanning signals to the M rows of pixel units PX in each region in a data writing stage of the data writing sub-period.

[0029] Specifically, the scanning signal of the Kth region (K is greater than or equal to 1 and less than or equal to N) is represented as S(K). The first region has M scanning signals, which are S1-SM, the second region has M scanning signals, which are SM+1-S2M, and the Nth region has M scanning signals, which are S(N-1)*M+1-SN*M.

[0030] In the embodiments of the present application, the data writing sub-period includes one pulse period, and the data writing sub-period includes one first reset stage and one data writing stage, and each first reset stage is followed by one data writing stage.

[0031] In the first reset stage, the control circuit inputs a first reset control signal RST to the reset module 202 of the pixel unit PX. The emission control signal EM(K) is a high-level signal, so that the first transistor T1, the sixth transistor T6, and the fourteenth transistor T14 in the pulse width modulation module 201 and the pulse amplitude modulation module 203 are turned off, and the second reset control signal EMi(K) is a low-level signal, so that the fifth transistor T5 and the thirteenth transistor T13 are turned on, and a low-level signal Vss is written to the first node A and the fifth node E, so that the potentials of the nodes are reset.

[0032] In the data writing stage, the scanning signal S(K) is sequentially changed to a low-level signal, so that the second transistor T2, the third transistor T3, the tenth transistor T10, and the eleventh transistor T11 are turned on, and the data signal (including the first data signal Data_PWM(K) and the second data signal Data_PAM(K)) is written to the pixel unit PX.

[0033] In the embodiment of the present application, the light-emitting sub-period includes a plurality of pulse periods, specifically, the light-emitting sub-period includes N-1 second reset stages and N-1 light-emitting stages, and each second reset stage is followed by a light-emitting stage.

[0034] In the second reset stage, the control circuit inputs a first reset control signal RST to the reset module 202 of the pixel unit PX. Specifically, the first reset control signal RST is a low-level signal, so that the eighth transistor T8 and the ninth transistor T9 in the reset module 202 are turned on, and the reset voltage is written to the third node C and the fourth node D. At the same time, the emission control signal EM(K) is a low-level signal, so that the first transistor T1, the sixth transistor T6, and the fourteenth transistor T14 in the pulse width modulation module 201 and the pulse amplitude modulation module 203 are turned on, and the slope signal Sweep is a high-level signal, and the high potential is coupled to the first node A.

[0035] In the light-emitting stage, the control circuit inputs the slope signal Sweep and the data signal (including the first data signal Data_PWM(K) and the second data signal Data_PAM(K)) to the pulse width modulation module 201 and the pulse amplitude modulation module 203 of the pixel unit PX, so that the pixel unit PX controls the light-emitting device 204 to emit light according to the slope signal Sweep and the data signal. Specifically, as the potential of the slope signal Sweep decreases, the potential of the first node A gradually decreases until the fourth transistor T4 is turned on, the fourth node D is pulled down to the Vdd potential, and the third node C is coupled to the seventh transistor T7 to be turned on. The seventh transistor T7, the twelfth transistor T12, and the fourteenth transistor T14 in the light-emitting channel are all turned on, and the light-emitting device 204 starts to emit light.

[0036] Through the multi-pulse light emitting mode, the display device of the embodiment of the present application can emit light multiple times in the driving period of a frame of picture, thereby improving the display effect, and especially in low gray scale display, the flicker phenomenon can be effectively improved, and the large range controllability of the light emitting duty cycle is realized.

[0037] As shown in FIG. 4, the driving period of the pixel unit PX of the Kth region includes stage 1, stage 2, stage 3, stage 4, stage 5, stage 6, etc.

[0038] In the driving period of the pixel unit PX of the Kth region, the data writing operation is performed first, and then the light emitting operation is performed, the data writing operation includes the first reset stage (stage 1) and the data writing stage (stage 2), and the light emitting operation includes the second reset stage (stage 3, stage 5, stage 7) and the light emitting stage (stage 4, stage 6, stage 8).

[0039] Stage 1: Enter the first reset stage in the data writing sub-period, the plurality of scan signals S(K) input to the Kth region are all high level signals, the global ramp signal Sweep is a high level signal, the first reset control signal RST is a low level signal, the light emitting control signal EM(K) is a high level signal, and the second reset control signal EMi(K) is a low level signal. In the first reset stage, for the pulse width modulation module 201 and the pulse amplitude modulation module 203, the light emitting control signal EM(K) of the region is a high level signal, the first transistor T1, the sixth transistor T6, and the fourteenth transistor T14 are closed, the second reset control signal EMi(K) is a low level signal, the fifth transistor T5 and the thirteenth transistor T13 are opened, and the low level signal Vss is written to the first node A and the fifth node E to reset the potentials of the first node A and the fifth node E. The fourth transistor T4 and the twelfth transistor T12 are opened to ensure that the pixel units PX of all rows of the region are compensated for threshold voltage Vth when being written with data signals in the following stage. The fourth transistor T4 compensates for the threshold voltage Vth using Vdd, and the twelfth transistor T12 compensates for the threshold voltage Vth using the data signal (the second data signal Data_PAM(K)). The second reset control signal EMi(K) is a reset control signal of a frame of picture.

[0040] In the reset module 202, the global first reset control signal RST is a low level signal (the first reset control signal RST is a reset control signal corresponding to one pulse period, the global first reset control signal RST refers to that the first reset control signal input end is electrically connected with all pixel units PX of the whole display panel, one first reset control signal RST is provided to all pixel units PX of the whole display panel), the eighth transistor T8 and the ninth transistor T9 are turned on, the third node C and the fourth node D write the first reset signal Vref and the second reset signal VH respectively (the first reset signal Vref may be, for example, a high potential voltage, and the second reset signal VH may be a high potential voltage or a low potential voltage. When the fourth transistor T4 and the sixth transistor T6 are turned on, the voltage of the third node C is equal to Vref+Vdd-VH). The first reset signal Vref is used to turn off the seventh transistor T7.

[0041] Stage 2: enter the data writing stage, the ramp signal Sweep is a signal linearly decreasing in level, the first reset control signal RST is a high level signal, the second reset control signal EMi(K) is a high level signal, and the emission control signal EM(K) is a high level signal. The plurality of scan signals S(K) input to the plurality of row pixel units PX of the Kth region in turn are low level signals, the second transistor T2, the third transistor T3, the tenth transistor T10 and the eleventh transistor T11 are turned on, the second reset control signal EMi(K) is a high level signal, the fifth transistor T5 and the thirteenth transistor T13 are turned off, the fourth transistor T4 and the twelfth transistor T12 are both turned on, the first node A and the fifth node E write data for compensating the threshold voltage Vth of the fourth transistor T4 and the twelfth transistor T12 in turn until all row pixel units PX of the region are written. In stage 1 and stage 2, the emission control signal EM(K) is a high level signal, and since the first transistor T1 is turned off by the emission control signal EM(K), the ramp signal Sweep is not used to compare with the data signal (the first data signal Data_PWM(K)) in the pulse period (stage 1 and stage 2).

[0042] Stage 3: entering the second reset stage in the light emitting sub-period, the plurality of scan signals S(K) input to the plurality of pixel units PX in the Kth region are all high level signals, the second reset control signal EMi(K) is a high level signal, the first reset control signal RST is a low level signal, the ramp signal Sweep is a high level signal, and the light emitting control signal EM(K) is a low level signal. The first transistor T1, the sixth transistor T6, and the fourteenth transistor T14 are all turned on, the global ramp signal Sweep is a high level signal, the first node A is coupled to a high potential, and the fourth transistor T4 is turned off. The global first reset control signal RST is a low level signal, the eighth transistor T8 and the ninth transistor T9 are turned on, the fourth node D writes the potential of the second reset signal VH, and the seventh transistor T7 is turned off. The fourth transistor T4 is turned off, and the sixth transistor T6 is turned on. The seventh transistor T7 on the light emitting path is turned off, and the twelfth transistor T12 and the fourteenth transistor T14 are turned on.

[0043] Stage 4: in the light emitting stage in the light emitting sub-period, the plurality of scan signals S(K) input to the Kth region are all high level signals, the second reset control signal EMi(K) is a high level signal, the first reset control signal RST is a high level signal, the ramp signal Sweep is a linearly decreasing ramp signal, and the light emitting control signal EM(K) is a low level signal. As the potential of the ramp signal Sweep decreases, the potential of the coupled first node A gradually decreases until the fourth transistor T4 is turned on, the fourth node D is pulled down to the Vdd potential, the third node C is coupled to turn on the seventh transistor T7, the seventh transistor T7, the twelfth transistor T12, and the fourteenth transistor T14 on the light emitting path are all turned on, and the light emitting device 204 starts to emit light.

[0044] Stage 5: entering the second reset stage in the next light emitting sub-period, the global first reset control signal RST is a low level signal, and the seventh transistor T7 is turned off. The light emitting device 204 stops emitting light, the potentials of the third node C and the fourth node D are reset, the ramp signal Sweep jumps to a high potential, the first node A is coupled to a high potential, and the fourth transistor T4 is turned off. In stage 5, the levels (potentials) of various signals are the same as those in stage 3.

[0045] Stage 6: entering the light emitting stage in the next light emitting sub-period. As the potential of the ramp signal Sweep decreases, the fourth transistor T4 is turned on again, the seventh transistor T7 is turned on in turn, and the light emitting device 204 emits light again. In stage 6, the levels (potentials) of various signals are the same as those in stage 4.

[0046] Repeat the above steps to complete the multi-pulse light emission.

[0047] The display device and the driving method thereof provided by the embodiments of the present application realize the combination effect of pulse width modulation and multi-pulse and progressive light emission by adopting a global multi-pulse ramp signal Sweep. Specifically, by dividing the display panel into multiple regions, the pixel units PX of each region complete data writing and multiple light emission in the driving period of one frame of picture, which not only improves the display effect, but also reduces the instantaneous current. In addition, the embodiments of the application improve the low gray scale flicker performance and realize large range controllability of the light emission duty cycle. Through the multi-pulse light emission mode, short time light emission can be performed multiple times during low gray scale display, effectively improving the flicker phenomenon.

[0048] Table 1

[0049] Phase Phase 1 Phase 2 Phase 3 Phase 4 Phase 5 Phase 6 T1 / T6 / T14 Off Off On On On On T2 / T3 / T10 / T11 Off On Off Off Off Off T4 On On Off Off Off Off T5 / T13 On Off Off Off Off Off T7 Off Off Off Off On Off T8 / T9 On Off On Off On On T12 On On On On On On Voltage of Node A VSS Vdd+Vth1 Vdd+Vth1+Sweep_H-Data_PWM Vdd+Vth1+Sweep(t)-Data_PWM Vdd+Vth1+Sweep_H-Data_PWM Vdd+Vth1+Sweep(t)-Data_PWM Voltage of Node B Sweep_H Data_PWM Sweep_H Sweep(t) Sweep_H Sweep(t) Voltage of Node C Vref Vref Vref Vref→Vref+vdd-VH Vref Vref→Vref+vdd-VH Voltage of Node D VHVHVHVH→Vdd VHVH→Vdd Voltage of Node E Vss Data_PAM+Vth2 Data_PAM+Vth2 Data_PAM+Vth2 Data_PAM+Vth2 Data_PAM+Vth2 Remark At the beginning of the driving period of the pixel unit PX in the Kth region, the control circuit first performs the reset operation before data writing. In this phase, the control circuit inputs a reset signal to the pixel unit PX in the Kth region, so that the related transistors in the pulse width modulation module 201, the pulse amplitude modulation module 203 and the reset module 202 are reset to the initial state. In the data writing phase, the control circuit writes a data signal to the pixel unit PX in the Kth region and performs threshold voltage compensation. At the same time, the pixel units PX in other regions enter the corresponding light emitting phase. The progressive light emission of the display panel is realized, which effectively reduces the instantaneous current. After the Kth region completes data writing, the control circuit starts to reset the pixel unit PX in the K+1th region. At the same time, the control circuit also resets the reset module 202 in the pixel unit PX in all regions, and resets the global ramp signal Sweep. The control circuit performs data writing and threshold voltage compensation on the pixel unit PX in the K+1th region, while the pixel units PX in other regions enter the light emitting phase. For the pixel units PX in the non-K+1th region, as the potential of the ramp signal Sweep decreases, the voltage of the first node A gradually decreases. When the voltage of the first node A decreases to the threshold voltage of the fourth transistor T4, the fourth transistor T4 is turned on. Subsequently, the voltage of the fourth node D changes from VH to Vdd, and the voltage of the third node C changes from Vref to Vref+Vdd-VH, causing the seventh transistor T7 to change from the off state to the on state, and the pixel unit PX starts to emit light.When the K+1th region completes data writing, the control circuit starts to perform a reset operation on the pixel unit PX of the K+2th region. At the same time, the control circuit resets the reset module 202 in the pixel unit PX of all regions again, and resets the global sweep signal. In this stage, the control circuit performs data writing and threshold voltage compensation on the pixel unit PX of the K+2th region, while the pixel units PX of other regions enter the light-emitting stage. For the pixel unit PX of the non-K+2th region, the light-emitting process is the same as the process described in Remark 4. With the decrease of the sweep signal Sweep potential, the voltage of the first node A gradually decreases until the fourth transistor T4 is triggered to be turned on, and then the seventh transistor T7 is turned on, and the pixel unit PX starts to emit light.

[0050] As shown in Table 1 above, the working states of the plurality of transistors (T1-T14) and the plurality of nodes (A, B, C, D, E) in the driving circuit in different stages are as follows:

[0051] Stage 1 (first reset stage before data writing): T1 / T6 / T14, T2 / T3 / T10 / T11 are closed, T4, T5 / T13, T8 / T9, T12 are turned on; the voltage of node A is VSS, the voltage of node B is Sweep_H, the voltage of node C is Vref, the voltage of node D is VH, and the voltage of node E is Vss.

[0052] Stage 2 (data writing stage): T1 / T6 / T14 are closed, T2 / T3 / T10 / T11, T4, T12 are turned on, T5 / T13, T7, T8 / T9 are closed; the voltage of node A is Vdd+Vth1, the voltage of node B is Data_PWM, the voltage of node C is Vref, the voltage of node D is VH, and the voltage of node E is Data_PAM+Vth2.

[0053] Stage 3 (second reset stage): T1 / T6 / T14, T8 / T9, T12 are turned on, and other transistors are closed; the voltage of node A is Vdd+Vth1+Sweep_H-Data_PWM, the voltage of node B is Sweep_H, the voltage of node C is Vref, the voltage of node D is VH, and the voltage of node E is Data_PAM+Vth2.

[0054] Phase 4 (light emitting phase): T1 / T6 / T14, T12 remain open, T4 and T7 change from the closed state to the open state, and other transistors are closed; the voltage of node A changes from Vdd+Vth1+Sweep_H-Data_PWM to Vdd+Vth1+Sweep(t)-Data_PWM, the voltage of node B is Sweep(t), the voltage of node C changes from Vref to Vref+vdd-VH, the voltage of node D changes from VH to Vdd, and the voltage of node E remains Data_PAM+Vth2.

[0055] Phase 5 (next reset phase): similar to phase 3.

[0056] Phase 6 (next light emitting phase): similar to phase 4.

[0057] In a driving cycle of a frame of picture, the six phases are performed in sequence to realize the processes of reset, data writing and multiple light emitting. After completing data writing, the pixel units PX of each region will perform multiple light emitting, thereby improving the display effect.

[0058] By adopting the global multi-pulse ramp signal Sweep, the pixel units PX of each region of the display panel complete data writing and multiple light emitting in a driving cycle of a frame of picture, so that the display device of the embodiment of the present application can perform light emitting multiple times in a driving cycle of a frame of picture, thereby improving the display effect, reducing the instantaneous current, and effectively improving the flicker phenomenon, especially in low gray scale display, and realizing wide-range controllability of the light emitting duty cycle.

[0059] The embodiment of the present application provides a display device, which comprises a display panel and a control circuit. The display panel is electrically connected with the control circuit. The control circuit can comprise a source electrode driving circuit, a gate electrode driving circuit, a timing controller, a light emitting controller and a power management chip.

[0060] As shown in FIG. 2, the display panel comprises N regions (R1-RN) divided along a scanning direction SD, each region comprises a plurality of pixel units PX, and N is an integer greater than 1.

[0061] The control circuit is electrically connected with the plurality of pixel units PX, and the control circuit is configured to generate a ramp signal Sweep and input the ramp signal Sweep to the plurality of pixel units PX, and to sequentially control the pixel units PX of each region in the N regions (R1-RN) to perform data writing and light emitting in a driving cycle of a frame of picture.

[0062] The sweep signal Sweep includes N pulse periods in a driving period of a frame picture, and the driving period of each pixel unit PX includes a data writing sub-period and a light emitting sub-period. The data writing sub-period precedes the light emitting sub-period, and the data writing sub-period includes one pulse period of the sweep signal Sweep, and the light emitting sub-period includes N-1 pulse periods of the sweep signal Sweep.

[0063] As an improvement, the control circuit is further configured to dynamically adjust the number of partitions according to the complexity of the display content. The control circuit first analyzes the image complexity of the current frame, for example, by calculating the frequency components or dynamic range of the image, and then dynamically adjusts the number of partitions N according to the analysis result. For example, for a complex scene with high dynamic range, the number of partitions is increased to improve the control accuracy; for a simple scene with low dynamic range, the number of partitions is reduced to reduce power consumption.

[0064] As shown in FIGS. 3 and 4, the pixel unit PX includes a light emitting device 204 and a driving circuit. The driving circuit is electrically connected with the light emitting device 204, and is configured to control the light emitting of the light emitting device 204.

[0065] The driving circuit includes a pulse width modulation module 201, a pulse amplitude modulation module 203, and a reset module 202. The pulse width modulation module 201 is electrically connected with the reset module 202, the reset module 202 is electrically connected with the pulse amplitude modulation module 203, and the pulse amplitude modulation module 203 is electrically connected with the light emitting device 204.

[0066] The pulse width modulation module 201 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a first capacitor C1.

[0067] The gate of the first transistor T1 is electrically connected with an emission control signal input terminal EM(K), one of the source and the drain of the first transistor T1 is electrically connected with a sweep signal input terminal Sweep, and the other of the source and the drain of the first transistor T1 is electrically connected with a first node A.

[0068] The gate of the second transistor T2 is electrically connected with a scan signal input terminal S(K), one of the source and the drain of the second transistor T2 is electrically connected with a first data signal input terminal Data_PWM(K), and the other of the source and the drain of the second transistor T2 is electrically connected with the first node A.

[0069] One end of the first capacitor C1 is electrically connected with the first node A, and the other end of the first capacitor C1 is electrically connected with a second node B.

[0070] The gate of the third transistor T3 is electrically connected with the scan signal input terminal S(K), and one of the source and the drain of the third transistor T3 is electrically connected with the second node B.

[0071] The gate of the fourth transistor T4 is electrically connected to the second node B. One of the source and drain of the fourth transistor T4 is electrically connected to the first power supply signal input terminal Vdd. The other of the source and drain of the fourth transistor T4 is electrically connected to the other of the source and drain of the third transistor T3.

[0072] The gate of the fifth transistor T5 is electrically connected to the second reset control signal input terminal EMi(K), one of the source and drain of the fifth transistor T5 is electrically connected to the second power supply signal input terminal Vss, and the other of the source and drain of the fifth transistor T5 is electrically connected to the second node B.

[0073] The gate of the sixth transistor T6 is electrically connected to the light-emitting control signal input terminal EM(K), one of the source and drain of the sixth transistor T6 is electrically connected to the drain of the fourth transistor T4, and the other of the source and drain of the sixth transistor T6 is electrically connected to the third node C of the reset module 202.

[0074] The reset module 202 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a second capacitor C2.

[0075] The gate of the seventh transistor T7 is electrically connected to the third node C, and one of the source and drain of the seventh transistor T7 is electrically connected to the first power supply signal input terminal Vdd.

[0076] The gate of the eighth transistor T8 is electrically connected to the first reset control signal input terminal RST, one of the source and drain of the eighth transistor T8 is electrically connected to the second reset signal input terminal VH, and the other of the source and drain of the eighth transistor T8 is electrically connected to the fourth node D.

[0077] The gate of the ninth transistor T9 is electrically connected to the first reset control signal input terminal RST, one of the source and drain of the ninth transistor T9 is electrically connected to the first reset signal input terminal Vref, and the other of the source and drain of the ninth transistor T9 is electrically connected to the third node C.

[0078] One end of the second capacitor C2 is electrically connected to the third node C, and the other end of the second capacitor C2 is electrically connected to the fourth node D.

[0079] The pulse amplitude modulation module 203 includes a third capacitor C3, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14.

[0080] One end of the third capacitor C3 is electrically connected to the first power signal input terminal Vdd, and the other end of the third capacitor C3 is electrically connected to the fifth node E.

[0081] The gate of the tenth transistor T10 is electrically connected with the scan signal input end S(K), and one of the source and the drain of the tenth transistor T10 is electrically connected with the fifth node E.

[0082] The gate of the eleventh transistor T11 is electrically connected with the scan signal input end S(K), one of the source and the drain of the eleventh transistor T11 is electrically connected with the second data signal input end Data_PAM(K), and the other of the source and the drain of the eleventh transistor T11 of the pulse amplitude modulation module 203 is electrically connected with the other of the source and the drain of the seventh transistor T7.

[0083] The gate of the twelfth transistor T12 is electrically connected with the fifth node E, one of the source and the drain of the twelfth transistor T12 is electrically connected with the other of the source and the drain of the eleventh transistor T11, and the other of the source and the drain of the twelfth transistor T12 is electrically connected with the other of the source and the drain of the tenth transistor T10.

[0084] The gate of the thirteenth transistor T13 is electrically connected with the second reset control signal input end EMi(K), one of the source and the drain of the thirteenth transistor T13 is electrically connected with the second power signal input end Vss, and the other of the source and the drain of the thirteenth transistor T13 is electrically connected with the fifth node E.

[0085] The gate of the fourteenth transistor T14 is electrically connected with the light-emitting control signal input end EM(K), one of the source and the drain of the fourteenth transistor T14 is electrically connected with the drain of the twelfth transistor T12, and the other of the source and the drain of the fourteenth transistor T14 is electrically connected with the anode of the light-emitting device 204.

[0086] As shown in FIG. 4, the data writing sub-period includes a first reset stage and a data writing stage, and the control circuit is configured to input the first reset control signal RST to the reset module 202 of the pixel unit PX in the first reset stage, and write the data signal (including the first data signal Data_PWM(K) and the second data signal Data_PAM(K)) to the pulse width modulation module 201 and the pulse amplitude modulation module 203 of the pixel unit PX in the data writing stage after the first reset stage.

[0087] The light-emitting sub-period includes N-1 second reset stages and N-1 light-emitting stages, and the control circuit is configured to input the first reset control signal RST to the reset module 202 of the pixel unit PX in the second reset stage, and input the ramp signal Sweep and the data signal to the pulse width modulation module 201 and the pulse amplitude modulation module 203 of the pixel unit PX in the light-emitting stage after the second reset stage, so that the pixel unit PX controls the light-emitting device 204 to emit light according to the ramp signal Sweep and the data signal.

[0088] The control circuit is further configured to generate a first reset control signal RST for controlling the reset module 202 in the pixel unit PX to perform a reset and a light emission control signal EM(K) for controlling the pixel unit PX to emit light.

[0089] As an improvement, the control circuit is further configured to dynamically adjust the duration of each light emission stage according to the image content of the current frame. For example, for high brightness regions, the control circuit prolongs the light emission time; for low brightness regions, the control circuit shortens the light emission time. The control circuit is configured to analyze the input image data in real time, calculate the average brightness or brightness distribution of each region, and then generate light emission control parameters. These light emission control parameters are used to adjust the pulse width of the light emission control signal EM(K), thereby dynamically adjusting the light emission time.

[0090] As an improvement, the control circuit is further configured to dynamically adjust the rising and falling edges of the first reset control signal RST according to the current display content. For example, for high-contrast image regions, a first reset control signal RST with a steeper slope is generated to improve the response speed; for low-contrast regions, a first reset control signal RST with a slower slope is generated to reduce overcharging. The control circuit can include a digital-to-analog converter (DAC) and a variable current source. The DAC sets the output of the current source according to the instructions of the control circuit, thereby controlling the slope of the first reset control signal RST.

[0091] The first reset control signal RST is a low-level signal in the first reset stage of the data write sub-period and a high-level signal in the data write stage of the data write sub-period, and the light emission control signal EM(K) is a high-level signal in the data write sub-period and a low-level signal in the light emission sub-period; or

[0092] The first reset control signal RST is a high-level signal in the first reset stage and a low-level signal in the data write stage, and the light emission control signal EM(K) is a low-level signal in the data write sub-period and a high-level signal in the light emission sub-period.

[0093] The first reset control signal RST is a low-level signal in the second reset stage of the light emission sub-period and a high-level signal in the light emission stage of the light emission sub-period, and the light emission control signal EM(K) is a low-level signal in the light emission sub-period; or

[0094] The first reset control signal RST is a high-level signal in the second reset stage of the light emission sub-period and a low-level signal in the light emission stage of the light emission sub-period, and the light emission control signal EM(K) is a high-level signal in the light emission sub-period.

[0095] The control circuit comprises a ramp signal generation unit, an output terminal of the ramp signal generation unit is electrically connected with a plurality of pixel units PX of the display panel, and the ramp signal generation unit is configured to generate a ramp signal Sweep and provide the ramp signal Sweep to the plurality of pixel units PX.

[0096] As an improvement, the control circuit is further configured to adjust the distribution and duration of the pulses of the ramp signal Sweep within a driving period of a frame. Specifically, the control circuit can configure more light-emitting pulses in the middle part of the frame, and reduce the number of pulses in the beginning and end part of the frame.

[0097] As an improvement, the ramp signal generation unit of the control circuit comprises a programmable current source. The programmable current source is configured to dynamically adjust the slope of the ramp signal Sweep according to the brightness distribution of the current display content. Specifically, the programmable current source changes its output current according to the control signal provided by the control circuit, thereby changing the charging rate of the ramp signal Sweep. For example, for high brightness areas, a larger current is used to generate a steeper slope to improve contrast; for low brightness areas, a smaller current is used to generate a slower slope to increase gray scale performance. Such dynamic adjustment can be performed multiple times during each frame to adapt to the brightness requirements of different areas.

[0098] Each of the N regions (R1~RN) comprises M rows of pixel units PX, and M is an integer greater than 1. The control circuit is further configured to provide M scanning signals S(K) to the M rows of pixel units PX of each region in the data writing stage of the data writing sub-period.

[0099] As an improvement, the control circuit is further configured to generate an interleaved scanning signal, so that the same rows of different partitions are scanned in turn. For example, the 1st row of the first region, the 1st row of the second region, the 1st row of the third region, the 1st row of the fourth region are scanned in turn, and then the 2nd row of the first region, the 2nd row of the second region, and so on. In this way, the instantaneous power consumption can be further reduced, and the power consumption distribution of the large-size display panel can be improved.

[0100] As an improvement, the control circuit is further configured to dynamically adjust the pulse width of the scanning signal S(K) according to the data complexity of the current row. Specifically, the control circuit first analyzes the degree of data change of each row. For rows with large data changes, the control circuit prolongs the pulse width of the scanning signal S(K) to give more time for data writing; for rows with small data changes, the control circuit shortens the pulse width of the scanning signal S(K).

[0101] As an improvement, the control circuit is further configured to pre-charge the first capacitor C1 of the pixel unit PX to a level close to the target voltage during the data writing stage. Specifically, before actually writing the data signal, the control circuit first applies a preset voltage to the first capacitor C1, which is close to the target voltage to be finally written. This pre-charging manner can significantly shorten the data writing time and improve the writing efficiency.

[0102] All the transistors in the display device provided by the embodiments of the present application are P-type transistors, and of course, can also be N-type transistors.

[0103] The embodiments of the present application further provide a driving method of a display device, and the driving method comprises:

[0104] A ramp signal Sweep is generated, and the ramp signal Sweep comprises N pulse periods within a driving period of a frame of pictures.

[0105] The ramp signal Sweep is input to the plurality of pixel units PX.

[0106] Within the driving period of the frame of pictures, the pixel units PX in each of the N regions (R1-RN) are sequentially controlled to perform data writing and light emission.

[0107] The driving period of the pixel units PX in each region comprises a data writing sub-period and a light emission sub-period, the data writing sub-period precedes the light emission sub-period, the data writing sub-period comprises one pulse period of the ramp signal Sweep, and the light emission sub-period comprises N-1 pulse periods of the ramp signal Sweep.

[0108] The data writing sub-period comprises a first reset stage and a data writing stage, and the driving method further comprises:

[0109] In the first reset stage, a first reset control signal RST is input to the reset module 202 of the pixel unit PX;

[0110] In the data writing stage after the first reset stage, a data signal is written to the pulse width modulation module 201 and the pulse amplitude modulation module 203 of the pixel unit PX in the current region.

[0111] The light emission sub-period comprises N-1 second reset stages and N-1 light emission stages, and the driving method further comprises:

[0112] In the second reset stage, a first reset control signal RST is input to the reset module 202 of the pixel unit PX in the current region to reset the pixel unit PX;

[0113] In the light emitting stage after the second reset stage, the pulse width modulation module 201 and the pulse amplitude modulation module 203 of the pixel unit PX are inputted with the sweep signal Sweep and the data signal, so that the pixel unit PX controls the light emitting device 204 to emit light according to the sweep signal Sweep and the data signal.

[0114] The driving method further comprises:

[0115] generating a first reset control signal RST and a light emitting control signal EM(K), wherein the first reset control signal RST is used to control the reset module 202 in the pixel unit PX to reset, and the light emitting control signal EM(K) is used to control the pixel unit PX to emit light.

[0116] In the first reset stage of the data writing sub-period, the first reset control signal RST is a low-level signal.

[0117] In the data writing stage of the data writing sub-period, the first reset control signal RST is a high-level signal.

[0118] In the data writing sub-period, the light emitting control signal EM(K) is a high-level signal.

[0119] In the light emitting sub-period, the light emitting control signal EM(K) is a low-level signal.

[0120] In the second reset stage of the light emitting sub-period, the first reset control signal RST is a low-level signal;

[0121] In the light emitting stage of the light emitting sub-period, the first reset control signal RST is a high-level signal;

[0122] In the light emitting sub-period, the light emitting control signal EM(K) is a low-level signal.

[0123] Each of the N regions (R1~RN) comprises M rows of pixel units PX, and M is an integer greater than 1, and the driving method further comprises:

[0124] In the data writing stage of the data writing sub-period, M scan signals S(K) are provided to the M rows of pixel units PX in each region.

[0125] The driving method further comprises the following steps:

[0126] Under the control of the light emitting control signal EM(K), the sweep signal Sweep is written to the first node A through the first transistor T1;

[0127] Under the control of the scan signal S(K), the data signal is written to the first node A through the second transistor T2;

[0128] The voltage between the first node A and the second node B is stored through the first capacitor C1.

[0129] The threshold voltage of the first transistor T1 is compensated by the third transistor T3 and the fourth transistor T4 under the control of the scanning signal S(K);

[0130] The second node B is initialized by the fifth transistor T5 under the control of the second reset control signal EMi(K);

[0131] The first power signal Vdd output by the fourth transistor T4 is output to the reset module 202 by the sixth transistor T6 under the control of the light emission control signal EM(K).

[0132] The driving method further comprises the following steps:

[0133] The first power signal Vdd is selectively provided to the pulse amplitude modulation module 203 by the seventh transistor T7 under the control of the voltage of the third node C;

[0134] The second reset signal VH is written to the fourth node D by the eighth transistor T8 under the control of the first reset control signal RST;

[0135] The first reset signal Vref is written to the third node C by the ninth transistor T9 under the control of the first reset control signal RST;

[0136] The voltage of the third node C is coupled to change when the voltage of the fourth node D changes by the second capacitor C2.

[0137] The driving method further comprises the following steps:

[0138] The tenth transistor T10 and the eleventh transistor T11 are turned on simultaneously under the control of the scanning signal S(K). The turning on of T10 causes the voltage of the fifth node E to be transmitted; the turning on of T11 causes the second data signal Data_PAM(K) to be transmitted to the source of T12.

[0139] The twelfth transistor T12 is selectively turned on under the control of the voltage of the fifth node E. Specifically, the gate of T12 is connected to node E, and the on-off state of T12 depends on the voltage level of node E.

[0140] The thirteenth transistor T13 is turned on to transmit the level of the second power signal Vss to the fifth node E, thereby initializing the fifth node E, under the control of the second reset control signal EMi(K).

[0141] In the light emission stage, the light emission control signal EM(K) controls the fourteenth transistor T14 to be turned on to connect the drain of T12 to the anode of the light emitting device 204.

[0142] The third capacitor C3 is connected between the first power signal input end Vdd and the fifth node E, and is used for storing a control voltage.

[0143] The embodiments of the present application effectively solve the technical problems of limited brightness adjustment range, high power consumption, insufficient gray scale accuracy, and obvious flickering phenomenon in the prior art by adopting the pulse width modulation driving mode combined with the global ramp signal Sweep and multi-pulse, and realizing progressive light emission. Specifically, the embodiments of the present application adopt the global ramp signal Sweep, which ensures that all pixel units receive the same ramp signal Sweep, thereby improving the consistency of display. In addition, the embodiments of the present application introduce multi-pulse light emission technology. In the driving period of a frame of picture, the ramp signal Sweep contains multiple pulse periods, so that the pixel units in each region can emit light multiple times, thereby expanding the brightness adjustment range. In particular, when displaying in low gray scale, the embodiments of the present application can effectively improve the flickering phenomenon. By adjusting the number of pulses and the light emission time of each pulse, the light emission duty cycle can be flexibly controlled to meet the wide display requirements from ultra-low brightness to ultra-high brightness. In addition, the embodiments of the present application adopt the progressive light emission mode, divide the display panel into multiple regions, and sequentially complete data writing and multiple light emission of the pixel units in each region in the driving period of a frame of picture, thereby not only improving the display effect, but also significantly reducing the instantaneous current, and effectively solving the problem of high power consumption.

[0144] The embodiments of the present application are described in detail above, and the content of the specification should not be understood as limiting the protection scope of the present application.

Claims

1. A display device comprising: a display panel comprising N regions divided along a scanning direction, each region comprising a plurality of pixel units, N being an integer greater than 1; and a control circuit electrically connected to the plurality of pixel units, the control circuit being configured to generate a ramp signal and input the ramp signal to the plurality of pixel units, and being configured to sequentially control the pixel units of each of the N regions to perform data writing and light emission in a driving period of a frame; wherein the ramp signal comprises N pulse periods in the driving period of the frame, the driving period of the pixel units of each region comprises a data writing sub-period and a light emission sub-period, the data writing sub-period precedes the light emission sub-period, the data writing sub-period comprises one pulse period of the ramp signal, and the light emission sub-period comprises N-1 pulse periods of the ramp signal. The pixel unit comprises:

2. The display device according to claim 1, wherein a light emitting device; and a driving circuit electrically connected to the light emitting device and configured to control light emission of the light emitting device; wherein the driving circuit comprises a pulse width modulation module, a pulse amplitude modulation module, and a reset module, the pulse width modulation module is electrically connected to the reset module, the reset module is electrically connected to the pulse amplitude modulation module, and the pulse amplitude modulation module is electrically connected to the light emitting device. The pulse width modulation module comprises:

3. The display device according to claim 2, wherein a first transistor having a gate electrically connected to a light emission control signal input terminal, one of a source and a drain of the first transistor electrically connected to a ramp signal input terminal, and the other of the source and the drain of the first transistor electrically connected to a first node; a second transistor having a gate electrically connected to a scanning signal input terminal, one of a source and a drain of the second transistor electrically connected to a first data signal input terminal, and the other of the source and the drain of the second transistor electrically connected to the first node; a first capacitor having one end electrically connected to the first node and the other end electrically connected to a second node; a third transistor having a gate electrically connected to the scanning signal input terminal, one of a source and a drain of the third transistor electrically connected to the second node; a fourth transistor having a gate electrically connected to the second node, one of a source and a drain of the fourth transistor electrically connected to a first power signal input terminal, and the other of the source and the drain of the fourth transistor electrically connected to the other of the source and the drain of the third transistor; a fifth transistor having a gate electrically connected to a second reset control signal input terminal, one of a source and a drain of the fifth transistor electrically connected to a second power signal input terminal, and the other of the source and the drain of the fifth transistor electrically connected to the second node. ​ A sixth transistor, one of a source and a drain of the sixth transistor is electrically connected with the fourth transistor, and the other of the source and the drain of the sixth transistor is electrically connected with a third node of the reset module.

4. The display device according to claim 2, wherein The reset module comprises: A seventh transistor, a gate of the seventh transistor is electrically connected with the third node, one of a source and a drain of the seventh transistor is electrically connected with the first power signal input end; An eighth transistor, a gate of the eighth transistor is electrically connected with the first reset control signal input end, one of a source and a drain of the eighth transistor is electrically connected with the second reset signal input end, and the other of the source and the drain of the eighth transistor is electrically connected with the fourth node; A ninth transistor, a gate of the ninth transistor is electrically connected with the first reset control signal input end, one of a source and a drain of the ninth transistor is electrically connected with the first reset signal input end, and the other of the source and the drain of the ninth transistor is electrically connected with the third node; A second capacitor, one end of the second capacitor is electrically connected with the third node, and the other end of the second capacitor is electrically connected with the fourth node.

5. The display device according to claim 2, wherein The pulse amplitude modulation module comprises: A third capacitor, one end of the third capacitor is electrically connected with the first power signal input end, and the other end of the third capacitor is electrically connected with a fifth node; A tenth transistor, a gate of the tenth transistor is electrically connected with the scan signal input end, one of a source and a drain of the tenth transistor is electrically connected with the fifth node; An eleventh transistor, a gate of the eleventh transistor is electrically connected with the scan signal input end, one of a source and a drain of the eleventh transistor is electrically connected with the second data signal input end, and the other of the source and the drain of the eleventh transistor of the pulse amplitude modulation module is electrically connected with the other of the source and the drain of the seventh transistor; A twelfth transistor, a gate of the twelfth transistor is electrically connected with the fifth node, one of a source and a drain of the twelfth transistor is electrically connected with the other of the source and the drain of the eleventh transistor, and the other of the source and the drain of the twelfth transistor is electrically connected with the other of the source and the drain of the tenth transistor; A thirteenth transistor, a gate of the thirteenth transistor is electrically connected with the second reset control signal input end, one of a source and a drain of the thirteenth transistor is electrically connected with the second power signal input end, and the other of the source and the drain of the thirteenth transistor is electrically connected with the fifth node; A fourteenth transistor, a gate of the fourteenth transistor is electrically connected with the light-emitting control signal input end, one of a source and a drain of the fourteenth transistor is electrically connected with the drain of the twelfth transistor, and the other of the source and the drain of the fourteenth transistor is electrically connected with an anode of the light-emitting device.

6. The display device according to claim 2, wherein The data writing sub-period comprises a first reset stage and a data writing stage, and the control circuit is configured to input a first reset control signal to a reset module of the pixel unit in the first reset stage, and write a data signal to a pulse width modulation module and a pulse amplitude modulation module of the pixel unit in the data writing stage after the first reset stage; The light emitting sub-period comprises N-1 second reset stages and N-1 light emitting stages, and the control circuit is configured to input a first reset control signal to a reset module of the pixel unit in the second reset stage, and input the ramp signal and the data signal to the pulse width modulation module and the pulse amplitude modulation module of the pixel unit in the light emitting stage after the second reset stage, so that the pixel unit controls the light emitting device to emit light according to the ramp signal and the data signal.

7. The display device of claim 6, wherein, The control circuit is further configured to generate a first reset control signal and a light emitting control signal, the first reset control signal being used to control the reset module in the pixel unit to reset, and the light emitting control signal being used to control the pixel unit to emit light.

8. The display device of claim 7, wherein, The first reset control signal is a low-level signal in the first reset stage of the data writing sub-period, and is a high-level signal in the data writing stage of the data writing sub-period, and the light emitting control signal is a high-level signal in the data writing sub-period, and is a low-level signal in the light emitting sub-period; or The first reset control signal is a high-level signal in the first reset stage, and is a low-level signal in the data writing stage, and the light emitting control signal is a low-level signal in the data writing sub-period, and is a high-level signal in the light emitting sub-period.

9. The display device of claim 8, wherein, The first reset control signal is a low-level signal in the second reset stage of the light emitting sub-period, and is a high-level signal in the light emitting stage of the light emitting sub-period, and the light emitting control signal is a low-level signal in the light emitting sub-period; or The first reset control signal is a high-level signal in the second reset stage of the light emitting sub-period, and is a low-level signal in the light emitting stage of the light emitting sub-period, and the light emitting control signal is a high-level signal in the light emitting sub-period.

10. The display device according to claim 1, wherein The control circuit comprises a ramp signal generation unit, an output end of the ramp signal generation unit being electrically connected with a plurality of the pixel units of the display panel, and the ramp signal generation unit being configured to generate the ramp signal and provide the ramp signal to the plurality of the pixel units.

11. The display device according to claim 1, wherein Each of the N regions comprises M rows of pixel units, M being an integer greater than 1, and the control circuit is further configured to provide M scanning signals to M rows of the pixel units in each of the regions in the data writing stage of the data writing sub-period.

12. The display device of claim 1, wherein, The control circuit is further configured to dynamically adjust the duration of each light emitting stage according to the image content of a current frame.

13. A driving method of a display device, wherein, The display panel of the display device comprises N regions divided along a scanning direction, each region comprising a plurality of pixel units, N being an integer greater than 1, and the driving method comprises: generating a ramp signal, the ramp signal comprising N pulse periods in a driving period of a frame of picture; inputting the ramp signal to a plurality of the pixel units; and The pixel units in each of the N regions are sequentially controlled for data writing and light emission in a driving period of a frame of picture; The driving period of the pixel units in each of the regions comprises a data writing sub-period and a light emission sub-period, the data writing sub-period precedes the light emission sub-period, the data writing sub-period comprises one pulse period of the ramp signal, and the light emission sub-period comprises N-1 pulse periods of the ramp signal.

14. The driving method according to claim 13, wherein The data writing sub-period comprises a first reset stage and a data writing stage, and the driving method further comprises: In the first reset stage, a first reset control signal is input to the reset module of the pixel units; In the data writing stage after the first reset stage, data signals are written to the pulse width modulation module and the pulse amplitude modulation module of the pixel units.

15. The driving method according to claim 13, wherein The light emission sub-period comprises N-1 second reset stages and N-1 light emission stages, and the driving method further comprises: In the second reset stage, a first reset control signal is input to the reset module of the pixel units; In the light emission stage after the second reset stage, the ramp signal and the data signals are input to the pulse width modulation module and the pulse amplitude modulation module of the pixel units, so that the pixel units control the light emitting device to emit light according to the ramp signal and the data signals.

16. The driving method according to claim 13, wherein The driving method further comprises: generating a first reset control signal and a light emission control signal, wherein the first reset control signal is used to control the reset module in the pixel units to reset, and the light emission control signal is used to control the pixel units to emit light.

17. The driving method according to claim 16, wherein In the first reset stage of the data writing sub-period, the first reset control signal is a low-level signal; In the data writing stage of the data writing sub-period, the first reset control signal is a high-level signal; In the data writing sub-period, the light emission control signal is a high-level signal; In the light emission sub-period, the light emission control signal is a low-level signal.

18. The driving method according to claim 17, wherein In the second reset stage of the light emission sub-period, the first reset control signal is a low-level signal; In the light emission stage of the light emission sub-period, the first reset control signal is a high-level signal; In the light emission sub-period, the light emission control signal is a low-level signal.

19. The driving method according to claim 13, wherein Each of the N regions comprises M rows of pixel units, and M is an integer greater than 1, and the driving method further comprises: In the data writing stage of the data writing sub-period, M scanning signals are provided to the M rows of pixel units in each of the regions.

20. The driving method according to claim 13, wherein The driving method further comprises: dynamically adjusting the duration of each light emission stage according to the image content of the current frame.

Images