Display panel and display apparatus

Abstract

The present application provides a display panel and a display apparatus. The display panel comprises a plurality of repeating units, wherein each repeating unit comprises at least two sub-pixels, and each sub-pixel comprises a light-emitting device, a driving transistor, and a switching transistor. At least one sub-pixel comprises a multiplexing transistor for controlling signal transmission between a plurality of driving transistors and a multiplexing signal line on the basis of a multiplexing control signal. In a same repeating unit, the number of multiplexing transistors electrically connected to a same multiplexing signal line is less than the number of sub-pixels.

Description

Display panel and display device

[0001] This application claims priority to Chinese Patent Application No. 202411364555.4, filed on September 27, 2024, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] In order to realize the display of sub-pixels in the display area, the sub-pixels need to include pixel driving circuits. The sub-pixels are arranged in the display area, so that the pixel driving circuits included in the sub-pixels are also arranged in the display area. However, the pixel driving circuits include a large number of transistors, which will occupy a large layout space, resulting in a decrease in the number of sub-pixels that can be arranged in the display area, which is not conducive to the high-resolution design of the display panel. SUMMARY

[0004] Embodiments of the present application provide a display panel and a display device, which can support the display panel to realize high-resolution design.

[0005] Embodiments of the present application provide a display panel, which includes a plurality of repeating units, each of the repeating units including at least two sub-pixels, each of the sub-pixels including a light-emitting device, a driving transistor configured to drive the light-emitting device to emit light, and a switch transistor configured to control signal transmission between the light-emitting device and the driving transistor according to a first light-emitting control signal. At least one of the sub-pixels includes a multiplexing transistor configured to control signal transmission between a plurality of the driving transistors and a multiplexing signal line according to a multiplexing control signal. In the same repeating unit, the number of the multiplexing transistors electrically connected to the same multiplexing signal line is less than the number of the sub-pixels.

[0006] The present application provides a display device, which includes any of the above-mentioned display panels. BRIEF DESCRIPTION OF DRAWINGS

[0007] FIGS. 1A-1B are structural schematic diagrams of a display panel according to embodiments of the present application;

[0008] FIGS. 2A-2C are circuit structural schematic diagrams of a repeating unit according to embodiments of the present application;

[0009] FIGS. 3A-3B are timing diagrams corresponding to sub-pixels according to embodiments of the present application;

[0010] FIGS. 4A-4L are wiring structural schematic diagrams corresponding to the repeating unit shown in FIG. 2A;

[0011] FIGS. 5A-5L are schematic diagrams of wiring structures of the repeating unit shown in FIG. 2B;

[0012] FIG. 6 is a schematic diagram of a structure of a display device according to an embodiment of the present application. Embodiments of the present application

[0013] For the purpose of making the present application, technical solutions and effects more clear and explicit, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application, and each embodiment can be combined with each other but not described one by one. The ordinal numbers such as first / second, the word "comprising" is not exclusive, the computer non-volatile storage medium storing instructions / code for executing the method steps of the method, any combination of the embodiments can be used, etc. Those skilled in the art should understand that the embodiments of the present application can be modified or replaced equivalently without departing from the spirit and scope of the present application, and such modifications or equivalent replacements should be covered in the scope of the present application.

[0014] The present application provides a display panel and a display device, which include a plurality of repeating units, each of the repeating units including at least two sub-pixels, each of the sub-pixels including a light emitting device, a driving transistor configured to drive the light emitting device to emit light, and a switch transistor configured to control signal transmission between the light emitting device and the driving transistor according to a first light emitting control signal. At least one of the sub-pixels includes a multiplexing transistor configured to control signal transmission between a plurality of driving transistors and a multiplexing signal line according to a multiplexing control signal. In the same repeating unit, the number of multiplexing transistors electrically connected to the same multiplexing signal line is less than the number of sub-pixels. By connecting the driving transistors of the plurality of sub-pixels to the multiplexing signal line through the multiplexing transistors, the number of transistors included in the display panel is reduced, thereby facilitating high-resolution design of the display panel.

[0015] Specifically, as shown in FIGS. 1A-1B are schematic diagrams of a structure of a display panel according to an embodiment of the present application, the present application provides a display panel, which includes a plurality of repeating units RU.

[0016] Each of the repeating units RU includes at least two sub-pixels Spi, each of the sub-pixels Spi including a light emitting device LD and a pixel driving circuit.

[0017] Optionally, the light emitting colors of the plurality of sub-pixels Spi included in the same repeating unit RU can be the same or different.

[0018] Optionally, the light emitting device LD includes an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, etc.

[0019] FIGS. 2A-2C are schematic diagrams of a circuit structure of a repeating unit, the pixel driving circuit includes a driving module and a switch control module.

[0020] The driving module is electrically connected with the light emitting device LD, and the driving module is configured to drive the light emitting device LD to emit light. The driving module includes a driving transistor Tdr configured to generate a driving current to drive the light emitting device LD to emit light.

[0021] The switch control module is electrically connected with the driving transistor Tdr and the light emitting device LD, and the switch control module is configured to control the on-off of the driving current flow path according to a light emitting control signal. The switch control module includes a switch transistor Ts configured to control the signal transmission between the light emitting device LD and the driving transistor Tdr according to a first light emitting control signal EM1.

[0022] Please continue to refer to FIGS. 1A-1B and 2A-2C. At least one sub-pixel Spi includes a multiplexing transistor Tm configured to control the signal transmission between a plurality of driving transistors Tdr and a multiplexing signal line according to a multiplexing control signal. In the same repeating unit RU, the number of multiplexing transistors Tm electrically connected to the same multiplexing signal line is less than the number of sub-pixels Spi, so that the driving transistors Tdr of a plurality of sub-pixels Spi are connected to the multiplexing signal line through the multiplexing transistors Tm, thereby reducing the number of transistors included in the display panel, thereby facilitating the display panel to achieve high-resolution design.

[0023] Optionally, in the same repeating unit RU, different sub-pixels Spi can include a plurality of multiplexing transistors Tm with different functions, to further reduce the number of transistors included in the display panel. As shown in FIGS. 1A and 2A-2C, in the same repeating unit RU, the multiplexing signal lines electrically connected to the multiplexing transistors Tm included in different sub-pixels Spi transmit different signals, and the multiplexing control signals corresponding to the multiplexing transistors Tm included in different sub-pixels Spi are different, so that different sub-pixels Spi in the same repeating unit RU include multiplexing transistors Tm with different functions, thereby allowing a plurality of sub-pixels Spi included in the same repeating unit RU to share multiplexing transistors Tm with different functions, to further reduce the number of transistors included in the display panel.

[0024] That is, the same repeating unit RU can include X sub-pixels Spi and Y multiplexing transistors Tm. Wherein, X≥2, and X≥Y. That is, the same repeating unit RU can include only one multiplexing transistor Tm, or can include a plurality of multiplexing transistors Tm.

[0025] As in a same repeating unit RU, the sub-pixel Spi includes a first multiplexing transistor Tm1, a control terminal of the first multiplexing transistor Tm1 receives a multiplexing control signal which is a second light-emitting control signal EM2, a first source-drain terminal of the first multiplexing transistor Tm1 is electrically connected to a multiplexing signal line which is a first power supply line VDL electrically connected to the first voltage terminal VDD, and a second source-drain terminal of the first multiplexing transistor Tm1 is electrically connected to a first source-drain terminal of the driving transistor Tdr of a plurality of sub-pixels Spi in the same repeating unit RU, so that the plurality of sub-pixels Spi in the same repeating unit RU share the first multiplexing transistor Tm1, and the driving transistor Tdr of the plurality of sub-pixels Spi is electrically connected to the first voltage terminal VDD according to the second light-emitting control signal EM2 transmitted by the same multiplexing signal line. The multiplexing transistor Tm includes the first multiplexing transistor Tm1.

[0026] Alternatively, as in a same repeating unit RU, the sub-pixel Spi includes a second multiplexing transistor Tm2, a control terminal of the second multiplexing transistor Tm2 receives a multiplexing control signal which is a first gate control signal Pscan1, a first source-drain terminal of the second multiplexing transistor Tm2 is electrically connected to a multiplexing signal line which is a first reset line VL1, and a second source-drain terminal of the second multiplexing transistor Tm2 is electrically connected to a first source-drain terminal of the driving transistor Tdr of a plurality of sub-pixels Spi in the same repeating unit RU, so that the plurality of sub-pixels Spi in the same repeating unit RU share the second multiplexing transistor Tm2, and the driving transistor Tdr of the plurality of sub-pixels Spi is electrically connected to the first reset line VL1 according to the first gate control signal Pscan1 transmitted by the same multiplexing signal line. The multiplexing transistor Tm includes the second multiplexing transistor Tm2.

[0027] Alternatively, as in a same repeating unit RU, the sub-pixel Spi includes a first multiplexing transistor Tm1, and another sub-pixel Spi can include a second multiplexing transistor Tm2.

[0028] It should be noted that, for each sub-pixel Spi, the working principle corresponding to sharing the multiplexing transistor Tm is the same as the working principle corresponding to not sharing the multiplexing transistor Tm, so that the working principle of each sub-pixel Spi is not affected while reducing the number of transistors included in the display panel. Thus, in some embodiments, the multiplexing transistor Tm can not be limited to the first multiplexing transistor Tm1 and the second multiplexing transistor Tm2 described above, but can also be other transistors in the pixel driving circuit (such as the reset transistor Tr described below). The multiplexing transistor Tm not shared refers to the multiplexing transistor Tm being independently arranged in each sub-pixel Spi.

[0029] Please continue to refer to FIG. 2A~FIG. 2C. In order to make the luminous intensity of the light emitting device LD meet the design requirements, the sub-pixel Spi includes a data transistor Tda, the data transistor Tda includes a control terminal configured to receive a first scan signal Nscan1, a first source-drain terminal electrically connected with a data line DL, and a second source-drain terminal.

[0030] In addition, the sub-pixel Spi can further include an initial transistor Ti, a first capacitor C1 and a second capacitor C2, the initial transistor Ti includes a control terminal configured to receive a second scan signal Nscan2, a first source-drain terminal electrically connected with a first initial line VIL, and a second source-drain terminal electrically connected with the second source-drain terminal of the data transistor Tda.

[0031] The first capacitor C1 is connected in series between the second source-drain terminal of the data transistor Tda and the control terminal of the driving transistor Tdr, and the second capacitor C2 is connected in series between the first voltage terminal VDD and the second source-drain terminal of the data transistor Tda.

[0032] Optionally, in order to compensate for the influence of the threshold voltage of the driving transistor Tdr on the driving current, the sub-pixel Spi further includes a compensation transistor Tc, the compensation transistor Tc includes a control terminal configured to receive the second scan signal Nscan2, a first source-drain terminal electrically connected with the first source-drain terminal of the switch transistor Ts and the second source-drain terminal of the driving transistor Tdr, and a second source-drain terminal electrically connected with the control terminal of the driving transistor Tdr.

[0033] Optionally, in order to reset the anode potential of the light emitting device LD, the sub-pixel Spi can include a reset transistor Tr, the reset transistor Tr includes a control terminal configured to receive a second gate control signal Pscan2, a first source-drain terminal electrically connected with a second reset line VL2, and a second source-drain terminal electrically connected with the anode of the light emitting device LD and the second source-drain terminal of the switch transistor Ts.

[0034] Since the switch transistor Ts and the first multiplexing transistor Tm1 can both control the on-off of the driving current flow path, the switch control module can include the first multiplexing transistor Tm1.

[0035] Optionally, in order to reset the potential of the control terminal of the driving transistor Tdr, the sub-pixel Spi further includes a reset transistor Tre, as shown in FIG. 2C. The reset transistor Tre includes a control terminal configured to receive a third scan signal, a first source-drain terminal electrically connected with a third reset line VL3, and a second source-drain terminal electrically connected with the control terminal of the driving transistor Tdr. The third scan signal corresponding to the reset transistor Tre can be the same as the second scan signal Pscan2, and when the reset transistor Tre is turned on, the switch transistor Ts can be in an off state.

[0036] Further, the reset transistor Tr can be used to reset the anode potential of the light emitting device LD and the control terminal potential of the drive transistor Tdr at the same time, so that the reset transistor Tre can be omitted, and the number of transistors included in the display panel can be reduced. Accordingly, when the reset transistor Tr electrically connects the second reset line VL2 and the anode of the light emitting device LD according to the second gate control signal Pscan2, the switch transistor Ts can be configured to be turned on according to the first light emitting control signal EM1, so as to reset the anode potential of the light emitting device LD and the control terminal potential of the drive transistor Tdr at the same time.

[0037] When the anode potential of the light emitting device LD and the control terminal potential of the drive transistor Tdr are reset at the same time, in order to avoid the light emitting device LD from emitting light by mistake, when the reset transistor Tr electrically connects the second reset line VL2 and the anode of the light emitting device LD according to the second gate control signal Pscan2, the switch transistor Ts can be turned on according to the first light emitting control signal EM1, and the first multiplexing transistor Tm1 can be configured to be turned off according to the second light emitting control signal EM2.

[0038] Optionally, in order to save the width of the frame of the display panel, the display panel includes a gate driving circuit, and the gate driving circuit includes a plurality of gate driving sub-circuits. The control terminals of the second multiplexing transistor Tm2 and the reset transistor Tr are electrically connected to gate driving sub-circuits of different stages, so that the second multiplexing transistor Tm2 and the reset transistor Tr can be controlled by signals generated by the same gate driving circuit. For example, the control terminal of the second multiplexing transistor Tm2 receives a gate control signal generated by an n-mth gate driving sub-circuit, and the control terminal of the reset transistor Tr receives a gate control signal generated by an nth gate driving sub-circuit. Wherein, n > m, and m ≥ 1.

[0039] Optionally, the drive transistor Tdr, the switch transistor Ts, the first multiplexing transistor Tm1, the second multiplexing transistor Tm2, the reset transistor Tr, the data transistor Tda, the compensation transistor Tc, and the initial transistor Ti can be P-type transistors or N-type transistors. The drive transistor Tdr, the switch transistor Ts, the first multiplexing transistor Tm1, the second multiplexing transistor Tm2, the reset transistor Tr, the data transistor Tda, the compensation transistor Tc, and the initial transistor Ti can be silicon transistors or oxide transistors. The oxide transistor includes an oxide semiconductor material such as indium gallium zinc oxide.

[0040] FIGS. 3A-3B are timing diagrams of corresponding sub-pixels, provided by an embodiment of the present application, to drive the transistor Tdr, the switch transistor Ts, the first multiplexing transistor Tm1, the second multiplexing transistor Tm2, and the reset transistor Tr as P-type transistors, and the data transistor Tda, the compensation transistor Tc, and the initial transistor Ti as N-type transistors, for example, to illustrate the working principle of the sub-pixel Spi shown in FIGS. 2A-2B.

[0041] The first stage t1: the first emission control signal EM1, the second emission control signal EM2, and the second gate control signal Pscan2 are high, and the first scan signal Nscan1, the second scan signal Nscan2, and the first gate control signal Pscan1 are low. The second multiplexing transistor Tm2 is turned on, and the first reset signal transmitted by the first reset line VL1 is transmitted to the first source-drain end of the plurality of drive transistors Tdr.

[0042] The second stage t2: the second emission control signal EM2, the second scan signal Nscan2, and the first gate control signal Pscan1 are high, and the first emission control signal EM1, the first scan signal Nscan1, and the second gate control signal Pscan2 are low. The switch transistor Ts, the initial transistor Ti, the compensation transistor Tc, and the reset transistor Tr are turned on, the first initial signal transmitted by the first initial line VIL is transmitted to one end of the first capacitor C1 and the second capacitor C2, and the second reset signal transmitted by the second reset line VL2 is transmitted to the anode of the light-emitting device LD and resets the potential of the control end of the drive transistor Tdr.

[0043] The third stage t3: the first emission control signal EM1, the second scan signal Nscan2, the first gate control signal Pscan1, and the second gate control signal Pscan2 are high, and the second emission control signal EM2 and the first scan signal Nscan1 are low. The first multiplexing transistor Tm1, the initial transistor Ti, and the compensation transistor Tc are turned on, the supply voltage of the first voltage end VDD is transmitted to the first source-drain end of the drive transistor Tdr, and the first initial signal transmitted by the first initial line VIL is transmitted to one end of the first capacitor C1 and the second capacitor C2, so that the first capacitor C1 stores the threshold voltage information of the drive transistor Tdr.

[0044] The fourth stage t4: the first light-emitting control signal EM1, the second light-emitting control signal EM2, the first scan signal Nscan1, the first gate control signal Pscan1 and the second gate control signal Pscan2 are high level, and the second scan signal Nscan2 is low level. The data transistor Tda in the first sub-pixel Spi1 and the second sub-pixel Spi2 is turned on, and the data signal transmitted by the data line DL is coupled to the control end of the driving transistor Tdr through the first capacitor C1.

[0045] The fifth stage t5: the first light-emitting control signal EM1, the second light-emitting control signal EM2 and the second gate control signal Pscan2 are high level, and the first scan signal Nscan1, the second scan signal Nscan2 and the first gate control signal Pscan1 are low level. The second multiplexing transistor Tm2 is turned on, and the first reset signal transmitted by the first reset line VL1 is transmitted to the first source-drain end of the plurality of driving transistors Tdr.

[0046] The sixth stage t6: the first light-emitting control signal EM1 and the first gate control signal Pscan1 are high level, and the first scan signal Nscan1, the second scan signal Nscan2, the second light-emitting control signal EM2 and the second gate control signal Pscan2 are low level. The reset transistor Tr is turned on, and the second reset signal transmitted by the second reset line VL2 is transmitted to the anode of the light-emitting device LD.

[0047] The seventh stage t7: the first gate control signal Pscan1 and the second gate control signal Pscan2 are high level, and the first light-emitting control signal EM1, the second light-emitting control signal EM2, the first scan signal Nscan1 and the second scan signal Nscan2 are low level. The switch transistor Ts and the second multiplexing transistor Tm2 are turned on, and the driving transistor Tdr generates a driving current to control the light-emitting device LD to emit light.

[0048] Optionally, the same first light emitting control signal EM1 can control the on and off of the switch transistor Ts of multiple rows of sub-pixels Spi at the same time. The same second light emitting control signal EM2 can control the on and off of the first multiplexing transistor Tm1 of multiple rows of sub-pixels Spi at the same time, and the same first gate control signal Pscan1 can control the on and off of the second multiplexing transistor Tm2 of multiple rows of sub-pixels Spi at the same time. A first scan signal Nscan1 can correspond to control the on and off of the data transistor Tda of a row of sub-pixels Spi, and a second scan signal Nscan2 can correspond to control the on and off of the initial transistor Ti and the compensation transistor Tc of a row of sub-pixels Spi. Thus, the time period corresponding to the execution of the fourth stage t4 of two adjacent rows of sub-pixels Spi can correspond to the time period of the invalid level of the same second light emitting control signal EM2. As shown in FIG. 2B and FIG. 3B, the first scan signal received by the control end of the data transistor Tda of the first sub-pixel Spi1 and the second sub-pixel Spi2 is the nth level scan signal Nscan1(n) generated by the nth level gate driving sub-circuit of another gate driving circuit in the display panel, the first scan signal received by the control end of the data transistor Tda of the third sub-pixel Spi3 and the fourth sub-pixel Spi4 is the nth+1 level scan signal Nscan1(n+1) generated by the nth+1 level gate driving sub-circuit of the another gate driving circuit, and the time period corresponding to the execution of the fourth stage t4 of the first sub-pixel Spi1 and the second sub-pixel Spi2 and the time period corresponding to the execution of the fourth stage t4 of the third sub-pixel Spi3 and the fourth sub-pixel Spi4 correspond to the time period of the invalid level of the same second light emitting control signal EM2.

[0049] It should be noted that the circuit structure of the sub-pixel Spi is not limited to the design form shown in FIG. 2A~FIG. 2C. For example, in some embodiments, the second source-drain end of the data transistor Tda can be connected to the first source-drain end of the driving transistor Tdr, the second source-drain end of the initial transistor Ti and the control end of the driving transistor Tdr are electrically connected, the first capacitor C1 is connected in series between the first voltage end VDD and the control end of the driving transistor Tdr, and the second capacitor C2 is connected in series between the control end of the driving transistor Tdr and the control end of the data transistor Tda. The connection mode of the first multiplexing transistor Tm1, the second multiplexing transistor Tm2, the reset transistor Tr, the switch transistor Ts, the driving transistor Tdr and the light emitting device LD is set with reference to FIG. 2A~FIG. 2C.

[0050] It should be noted that the control end of the transistor can correspond to the gate, and the first source-drain end and the second source-drain end of the transistor can correspond to the source and the drain, respectively.

[0051] Optionally, in order to make the multiple sub-pixels Spi in the same repeating unit RU share the multiplexing transistor Tm, so as to save the layout space, the multiple sub-pixels Spi in the same repeating unit RU can be symmetrically arranged based on the design of the multiplexing transistor Tm.

[0052] Figures 4A-4L are schematic diagrams of the wiring structure of the repeating unit shown in Figure 2A, and Figures 5A-5L are schematic diagrams of the wiring structure of the repeating unit shown in Figure 2B. Taking the example of the same repeating unit RU including the first multiplexing transistor Tm1 and the second multiplexing transistor Tm2, the description is as follows.

[0053] The repeating unit RU includes the first sub-pixel Spi1 and the second sub-pixel Spi2 which are symmetrically arranged. The first sub-pixel Spi1 includes the first multiplexing transistor Tm1, and the second sub-pixel Spi2 includes the second multiplexing transistor Tm2, as shown in Figures 1A, 2A-2B, 4A-4B, and 5A-5B.

[0054] Since the first sub-pixel Spi1 and the second sub-pixel Spi2 share the first multiplexing transistor Tm1 and the second multiplexing transistor Tm2, when the first sub-pixel Spi1 and the second sub-pixel Spi2 correspondingly adopt the structure design shown in Figure 2A, they include a total of 14 transistors, which is two less than the design in which the first sub-pixel Spi1 and the second sub-pixel Spi2 respectively include the first multiplexing transistor Tm1 and the second multiplexing transistor Tm2. Therefore, it is beneficial to reduce the number of transistors included in the display panel.

[0055] In addition, the repeating unit RU can further include the third sub-pixel Spi3 and the fourth sub-pixel Spi4 which are symmetrically arranged. The third sub-pixel Spi3 is symmetric to the first sub-pixel Spi1 about the first multiplexing transistor Tm1, and the fourth sub-pixel Spi4 is symmetric to the second sub-pixel Spi2 about the second multiplexing transistor Tm2. The second source / drain terminal of the first multiplexing transistor Tm1 and the second multiplexing transistor Tm2 is electrically connected to the first source / drain terminal of the driving transistor Tdr of the third sub-pixel Spi3 and the fourth sub-pixel Spi4, as shown in Figures 1A, 2B, 4B, and 5B.

[0056] Since the first sub-pixel Spi1 to the fourth sub-pixel Spi4 share the first multiplexing transistor Tm1 and the second multiplexing transistor Tm2, when the first sub-pixel Spi1 and the second sub-pixel Spi2 correspondingly adopt the structure design shown in Figure 2B, they include a total of 26 transistors, which is six less than the design in which the first sub-pixel Spi1 to the fourth sub-pixel Spi4 respectively include the first multiplexing transistor Tm1 and the second multiplexing transistor Tm2. Therefore, it is beneficial to reduce the number of transistors included in the display panel.

[0057] Optionally, the first sub-pixel Spi1 and the second sub-pixel Spi2 have different light-emitting colors, so that the sub-pixels Spi of different light-emitting colors share the multiplexing transistor Tm. Optionally, the light-emitting colors of the first sub-pixel Spi1 to the fourth sub-pixel Spi4 include red, green, blue, and the like. For example, the light-emitting color of the first sub-pixel Spi1 is red, the light-emitting color of the second sub-pixel Spi2 is green, the light-emitting color of the third sub-pixel Spi3 is blue, and the light-emitting color of the fourth sub-pixel Spi4 is green.

[0058] Please continue to refer to FIG. 1B, FIG. 4A to FIG. 4L, and FIG. 5A to FIG. 5L. The layout space-saving wiring structure of the sub-pixel Spi is described by taking the example of a repeating unit RU including two sub-pixels Spi or four sub-pixels Spi.

[0059] The display panel includes a substrate 100, a first active layer 201, a first metal layer 301, a second metal layer 302, a first source-drain layer 401, and a second source-drain layer 402.

[0060] Optionally, the substrate 100 can include glass, polyimide, and the like.

[0061] Optionally, the substrate 100 can include a substrate 1001, a barrier layer 1002 located on the substrate 1001, and a buffer layer 1003 located on the barrier layer 1002.

[0062] Optionally, the substrate 100 further includes a light-blocking layer 101 located between the buffer layer 1003 and the barrier layer 1002.

[0063] Please continue to refer to FIG. 1B, FIG. 4C, and FIG. 5C. The first active layer 201 is located on the substrate 100, and the first active layer 201 includes a first connection part Ca, a first active pattern P1 of a driving transistor Tdr, a second active pattern P2 of a switching transistor Ts, a third active pattern P3 of a first multiplexing transistor Tm1, and a fourth active pattern P4 of a second multiplexing transistor Tm2. In the same repeating unit RU, the first connection part Ca is connected between the first doped parts of the plurality of first active patterns P1, the second active pattern P2 is connected to the first active pattern P1 corresponding to the second doped part away from the first connection part Ca (i.e., the second active pattern P2 is connected to the second doped part of the first active pattern P1 corresponding), and the third active pattern P3 and the fourth active pattern P4 are connected to the first connection part Ca, so as to realize the connection of the plurality of first active patterns P1, the third active pattern P3, and the fourth active pattern P4 through the first connection part Ca, thereby providing a basis for the plurality of sub-pixels Spi sharing the multiplexing transistor Tm.

[0064] Please continue to refer to FIG. 1B, FIG. 4D and FIG. 5D, the first metal layer 301 is located on the first active layer 201, and the first metal layer 301 includes a first electrode C1a, a first light-emitting control wire EML1a, a first light-emitting control connecting wire EML2a and a first gate control wire Pscan1a. The first electrode C1a corresponds to the channel part of the first active pattern P1 to serve as the gate of the driving transistor Tdr. The channel part of the first active pattern P1 is located between the first doped part and the second doped part of the first active pattern P1. Part of the first light-emitting control wire EML1a overlaps the channel part of the second active pattern P2 to serve as the gate of the switching transistor Ts. Part of the first light-emitting control connecting wire EML2a overlaps the channel part of the third active pattern P3 to serve as the gate of the first multiplexing transistor Tm1. Part of the first gate control wire Pscan1a overlaps the channel part of the fourth active pattern P4 to serve as the gate of the second multiplexing transistor Tm2.

[0065] Please continue to refer to FIG. 1B, FIG. 4E and FIG. 5E, the second metal layer 302 is located on the first metal layer 301, and the second metal layer 302 includes a second electrode C12b, part of the second electrode C12b overlaps the first electrode C1a. The first electrode C1a and the second electrode C12b can serve as the two electrodes of the first capacitor C1.

[0066] Please continue to refer to FIG. 1B, FIG. 4H and FIG. 5H, the first source-drain layer 401 is located on the second metal layer 302, and the first source-drain layer 401 includes a first power supply connecting part VDa and a second light-emitting control connecting wire EML2b. The first power supply connecting part VDa is connected between the third active pattern P3 and the first voltage terminal VDD to realize electrical connection between the first multiplexing transistor Tm1 and the first voltage terminal VDD. The second light-emitting control connecting wire EML2b is connected to the first light-emitting control connecting wire EML2a to transmit the second light-emitting control signal EM2 to the gate of the first multiplexing transistor Tm1 through the first light-emitting control connecting wire EML2a and the second light-emitting control connecting wire EML2b.

[0067] Please continue to refer to FIG. 1B, FIG. 4I and FIG. 5I, the second source-drain layer 402 is located on the first source-drain layer 401, and the second source-drain layer 402 includes a first power supply line VDL, which is electrically connected between the first power supply connecting part VDa and the first voltage terminal VDD to realize electrical connection between the first power supply connecting part VDa and the first voltage terminal VDD.

[0068] Optionally, the first active layer 201 includes a silicon semiconductor material, and the first metal layer 301, the second metal layer 302, the first source-drain layer 401 and the second source-drain layer 402 can include at least one of silver, copper, molybdenum and titanium.

[0069] Since the data transistor Tda, the compensation transistor Tc and the initial transistor Ti can be oxide transistors, the display panel can further include a second active layer 202. As shown in FIG. 1B, FIGS. 4A-4B, FIG. 4F, FIGS. 5A-5B and FIG. 5F, the display panel includes the second active layer 202 located on the second metal layer 302, and the second active layer 202 includes a sixth active pattern I1 of the data transistor Tda, a seventh active pattern I2 of the compensation transistor Tc and an eighth active pattern I3 of the initial transistor Ti.

[0070] To enhance the driving capability of the data transistor Tda, the compensation transistor Tc and the initial transistor Ti, a gate can be disposed on both sides of the channel portion of the sixth active pattern I1, the seventh active pattern I2 and the eighth active pattern I3. Accordingly, as shown in FIG. 1B, FIGS. 4A-4B, FIGS. 4E-4G, FIGS. 5A-5B and FIGS. 5E-5G, the second metal layer 302 can include a first scan wire Nscan1a and a first scan connection line Nscan2a. The display panel includes a third metal layer 303 located between the second active layer 202 and the first source-drain layer 401, and the third metal layer 303 includes a second scan wire Nscan1b and a second scan connection line Nscan2b. Part of the first scan wire Nscan1a and part of the second scan wire Nscan1b overlap with the channel portion of the sixth active pattern I1 to form two gates of the data transistor Tda, respectively. Part of the first scan connection line Nscan2a and part of the second scan connection line Nscan2b overlap with the channel portion of the seventh active pattern I2 and the channel portion of the eighth active pattern I3 to form two gates of the compensation transistor Tc and the initial transistor Ti, respectively. The first scan wire Nscan1a and the second scan wire Nscan1b are configured to transmit a first scan signal Nscan1, and the first scan connection line Nscan2a and the second scan connection line Nscan2b are configured to transmit a second scan signal Nscan2.

[0071] As shown in FIG. 1B, FIGS. 4A-4L and FIGS. 5A-5L, the display panel includes a first gate insulating layer 501, a second gate insulating layer 502, a third gate insulating layer 503, a first interlayer dielectric layer 601, a second interlayer dielectric layer 602, a first planarization layer 701 and a second planarization layer 702.

[0072] The first gate insulating layer 501 is located between the first active layer 201 and the first metal layer 301, the second gate insulating layer 502 is located between the first metal layer 301 and the second metal layer 302, the first interlayer dielectric layer 601 is located between the second metal layer 302 and the second active layer 202, the third gate insulating layer 503 is located between the second active layer 202 and the third metal layer 303, the second interlayer dielectric layer 602 is located between the third metal layer 303 and the first source-drain layer 401, the first planar layer 701 is located between the first source-drain layer 401 and the second source-drain layer 402, and the second planar layer 702 is located on the second source-drain layer 402.

[0073] Please continue to refer to FIGS. 4A-4L and 5A-5L. To form the second capacitor C2, the first metal layer 301 includes a third electrode C2a, the third electrode C2a is located between two first electrodes C1a, and the third electrode C2a partially overlaps with two second electrodes C12b. The first source-drain layer 401 includes a second power supply connection portion VDb, the second power supply connection portion VDb partially overlaps with the third electrode C2a, and the second power supply connection portion VDb is electrically connected between the first power supply line VDL and the third electrode C2a, so as to realize the power supply connection between the third electrode C2a and the first voltage end VDD through the second power supply connection portion VDb and the first power supply line VDL. Moreover, the same third electrode C2a forms two sub-pixel Spi second capacitors C2 with two second electrodes C12b. Since the relative distance between the third electrode C2a and the second electrode C12b is relatively close, the third electrode C2a and the second electrode C12b are used to form the second capacitor C2, which is also beneficial to improve the capacitance value of the second capacitor C2. The second power supply connection portion VDb can be connected with the third electrode C2a through the first connection hole HoA penetrating through the first planar layer 701, the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, and the second gate insulating layer 502, as shown in FIGS. 4J and 5J.

[0074] Please continue to refer to FIGS. 4A-4H and 5A-5H. To realize the electrical connection between the second source-drain end of the compensation transistor Tc and the control end of the driving transistor Tdr, the first source-drain layer 401 includes a first electrode connection portion Ce1 connected between the seventh active pattern I2 and the first electrode C1a. The first electrode connection portion Ce1 is connected with the first electrode C1a through the first via hole Ho1 penetrating through the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, and the second gate insulating layer 502, as shown in FIGS. 4J and 5J. The first electrode connection portion Ce1 is connected with the seventh active pattern I2 through the second via hole Ho2 penetrating through the second interlayer dielectric layer 602 and the third gate insulating layer 503, as shown in FIGS. 4K and 5K.

[0075] To realize the connection between the second source-drain end of the data transistor Tda and the first capacitor C1 and the second capacitor C2, the first source-drain layer 401 further comprises a second electrode connecting part Ce2 connected between the sixth active pattern I1 and the second electrode C12b. Since the second electrode C12b corresponds to an electrode of the first capacitor C1 and the second capacitor C2, the sixth active pattern I1 is connected with the second electrode C12b through the second electrode connecting part Ce2, so as to realize the connection between the second source-drain end of the data transistor Tda and the first capacitor C1 and the second capacitor C2. The second electrode connecting part Ce2 is connected with the second electrode C12b through the third via hole Ho3 penetrating through the second interlayer dielectric layer 602, the third gate insulating layer 503 and the first interlayer dielectric layer 601, as shown in FIG. 4J and FIG. 5J. The second electrode connecting part Ce2 is connected with the sixth active pattern I1 through the fourth via hole Ho4 penetrating through the second interlayer dielectric layer 602 and the third gate insulating layer 503, as shown in FIG. 4K and FIG. 5K.

[0076] To realize the connection between the first source-drain end of the data transistor Tda and the data line DL, the first source-drain layer 401 comprises a third electrode connecting part Ce3 connected between the sixth active pattern I1 and the data line DL. The second source-drain layer 402 comprises the data line DL. The third electrode connecting part Ce3 is connected with the sixth active pattern I1 through the fifth via hole Ho5 penetrating through the second interlayer dielectric layer 602 and the third gate insulating layer 503, as shown in FIG. 4K and FIG. 5K. The third electrode connecting part Ce3 is connected with the data line DL through the sixth via hole Ho6 penetrating through the first planar layer 701, as shown in FIG. 4L and FIG. 5L.

[0077] To realize the electrical connection between the first source-drain end of the compensation transistor Tc and the first source-drain end of the switch transistor Ts and the second source-drain end of the drive transistor Tdr, the first source-drain layer 401 comprises a fourth electrode connecting part Ce4 connected between the seventh active pattern I2 and the first active pattern P1 and the second active pattern P2. The fourth electrode connecting part Ce4 is connected with the first active pattern P1 and the second active pattern P2 through the seventh via hole Ho7 penetrating through the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, the second gate insulating layer 502 and the first gate insulating layer 501, as shown in FIG. 4J and FIG. 5J. The fourth electrode connecting part Ce4 is connected with the seventh active pattern I2 through the eighth via hole Ho8 penetrating through the second interlayer dielectric layer 602 and the third gate insulating layer 503, as shown in FIG. 4K and FIG. 5K.

[0078] Please continue to refer to FIGS. 4A-4L and 5A-5L, to provide the first initial signal to the initial transistor Ti, the first metal layer 301 further comprises a first initial line VIL. To realize the electrical connection between the first initial line VIL and the initial transistor Ti, the first source-drain layer 401 comprises a fifth electrode connecting part Ce5 connected between the eighth active pattern I3 and the first initial line VIL. Wherein, the fifth electrode connecting part Ce5 is connected with the first initial line VIL through a ninth via hole Ho9 penetrating through the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, and the second gate insulating layer 502, as shown in FIGS. 4J and 5J. The fifth electrode connecting part Ce5 is connected with the eighth active pattern I3 through a tenth via hole Ho10 penetrating through the second interlayer dielectric layer 602 and the third gate insulating layer 503, as shown in FIGS. 4K and 5K.

[0079] Please continue to refer to FIGS. 4A-4L and 5A-5L, the first active layer 201 comprises a fifth active pattern P5 of the reset transistor Tr, and the fifth active pattern P5 is connected with the second active pattern P2 away from one end of the first active pattern P1. Optionally, the first source-drain layer 401 further comprises a sixth electrode connecting part Ce6 connected between the anode of the light emitting device LD and the second active pattern P2 and the fifth active pattern P5. Wherein, the sixth electrode connecting part Ce6 is connected with the second active pattern P2 and the fifth active pattern P5 through a second connecting hole HoB penetrating through the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, the second gate insulating layer 502, and the first gate insulating layer 501, as shown in FIGS. 4J and 5J.

[0080] The following describes the difference design existing in the wiring structure of the two sub-pixel Spi multiplexing transistors Tm and the four sub-pixel Spi multiplexing transistors Tm.

[0081] Please continue to refer to FIG. 1B and FIGS. 4A-4L, the first connecting part Ca extends along a first direction, and the second active pattern P2, the third active pattern P3, and the fourth active pattern P4 extend along a second direction intersecting the first direction. Wherein, the third active pattern P3 and the fourth active pattern P4 are located between the first connecting part Ca and the first light emitting control wire EML1a, so that two sub-pixels Spi can share the multiplexing transistor Tm. Wherein, the first direction can correspond to one of the horizontal direction and the vertical direction, and the second direction can correspond to the other of the horizontal direction and the vertical direction.

[0082] Please continue to refer to FIG. 1B and FIG. 4H, the second light-emitting control connection line EML2b includes a first sub-connection line EML2b1 and a second sub-connection line EML2b2, the first sub-connection line EML2b1 is connected to the first light-emitting control connection line EML2a and the second sub-connection line EML2b2, and the second sub-connection line EML2b2 is located on the side of the first light-emitting control wire EML1a away from the third active pattern P3 and the fourth active pattern P4. Wherein, the second sub-connection line EML2b2 is connected between the two first sub-connection lines EML2b1. The first sub-connection line EML2b1 is connected to the first light-emitting control connection line EML2a through the eleventh via hole Ho11 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, and the second gate insulating layer 502, as shown in FIG. 4J.

[0083] Please continue to refer to FIG. 1B and FIG. 4G~FIG. 4H, the third metal layer 303 includes a second gate control wire Pscan1b, the first source-drain layer 401 includes a third gate control wire Pscan1c, and the third gate control wire Pscan1c is connected between the first gate control wire Pscan1a and the second gate control wire Pscan1b to transmit the first gate control signal Pscan1 through the first gate control wire Pscan1a~the third gate control wire Pscan1c. Wherein, the third gate control wire Pscan1c is connected to the first gate control wire Pscan1a through the twelfth via hole Ho12 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, and the second gate insulating layer 502, as shown in FIG. 4J. The third gate control wire Pscan1c is connected to the second gate control wire Pscan1b through the thirteenth via hole Ho13 penetrating the second interlayer dielectric layer 602, as shown in FIG. 4K.

[0084] Please continue to refer to FIG. 1B and FIG. 4A~FIG. 4L, the first metal layer 301 includes a second gate control line PL transmitting a second gate control signal Pscan2, and a part of the second gate control line PL overlaps with the channel part of the fifth active pattern P5 to form the gate of the reset transistor Tr. While the second gate control line PL is located on the side of the first light-emitting control wire EML1a away from the third active pattern P3 and the fourth active pattern P4.

[0085] Please continue to refer to FIG. 1B and FIG. 4A-4L, the second metal layer 302 includes a first reset wire VL1a and a first reset connection line VL2a. The first source-drain layer 401 includes a second reset wire VL1b and a second reset connection line VL2b, the second reset wire VL1b is connected between the first reset wire VL1a and the fourth active pattern P4, and the second reset connection line VL2b is connected between the first reset connection line VL2a and the fifth active pattern P5. The first reset line VL1 includes the first reset wire VL1a and the second reset wire VL1b, and the second reset line VL2 includes the first reset connection line VL2a and the second reset connection line VL2b.

[0086] The second reset wire VL1b is connected to the fourth active pattern P4 through a fourteenth via hole Ho14 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, the second gate insulating layer 502, and the first gate insulating layer 501, as shown in FIG. 4J. The second reset wire VL1b is connected to the first reset wire VL1a through a fifteenth via hole Ho15 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, and the first interlayer dielectric layer 601, as shown in FIG. 4J. The second reset connection line VL2b is connected to the fifth active pattern P5 through a sixteenth via hole Ho16 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, the second gate insulating layer 502, and the first gate insulating layer 501, as shown in FIG. 4J. The second reset connection line VL2b is connected to the first reset connection line VL2a through a seventeenth via hole Ho17 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, and the first interlayer dielectric layer 601, as shown in FIG. 4J.

[0087] The sixth electrode connection part Ce6 can be electrically connected to the anode of the light emitting device LD through a third connection hole HoC penetrating the second planar layer 702, as shown in FIG. 4L.

[0088] Please continue to refer to FIG. 1B and FIG. 5A-5L, the first connection part Ca includes a first connection sub-part Ca1 and a second connection sub-part Ca2, the first connection sub-part Ca1 extends along a first direction, and the second connection sub-part Ca2 extends along a second direction intersecting the first direction. The first connection sub-part Ca1 is connected between the first doped parts of two first active patterns P1 adjacent along the first direction, and the second connection sub-part Ca2 is connected between two first connection sub-parts Ca1 adjacent along the second direction. The second active pattern P2 extends along the second direction, and the second active pattern P2 is electrically connected to the first active pattern P1 away from one end of the first connection sub-part Ca1. The third active pattern P3 and the fourth active pattern P4 extend along the first direction, and the third active pattern P3 and the fourth active pattern P4 are located on opposite sides of the second connection sub-part, so that the four sub-pixels Spi can share the multiplexing transistor Tm.

[0089] The first light-emitting control wire EML1a is located between the first active pattern P1 and the third active pattern P3 and the fourth active pattern P4, so that the first light-emitting control wire EML1a and the corresponding second active pattern P2 partially overlap.

[0090] Please continue to refer to FIG. 1B, FIG. 5A-5B and FIG. 5G-5H, the third metal layer 303 includes a first reset wire VL1a, the first source-drain layer 401 includes a second reset wire VL1b, and the second reset wire VL1b is connected between the first reset wire VL1a and the fourth active pattern P4. The first reset line VL1 includes the second reset wire VL1b and the first reset wire VL1a.

[0091] Wherein, the second reset wire VL1b is connected with the fourth active pattern P4 through the eighteenth via hole Ho18 penetrating through the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, the second gate insulating layer 502 and the first gate insulating layer 501, and the second reset wire VL1b is connected with the first reset wire VL1a through the nineteenth via hole Ho19 penetrating through the second interlayer dielectric layer 602, as shown in FIG. 5J.

[0092] Please continue to refer to FIG. 1B, FIG. 5A-5B and FIG. 5D, the first metal layer 301 includes a first gate control connection line Pscan2 for transmitting a second gate control signal Pscan2, and a part of the first gate control connection line Pscan2a overlaps with the channel part of the fifth active pattern P5 to form the gate of the reset transistor Tr. While the first gate control connection line Pscan2a is located between the first light-emitting control wire EML1a and the third active pattern P3 and the fourth active pattern P4.

[0093] Please continue to refer to FIG. 1B, FIG. 5A-5B and FIG. 5G-5H, the third metal layer 303 includes a first reset connection line VL2a. The first source-drain layer 401 includes a second emission control trace EML1b, a second emission control connection line EML2b, a second gate control trace Pscan1b, a second gate control connection line Pscan2b and a second reset connection line VL2b, the second emission control trace EML1b is electrically connected with the first emission control trace EML1a, the second emission control connection line EML2b is electrically connected with the first emission control connection line EML2a, the second gate control trace Pscan1b is connected with the first gate control trace Pscan1a, the second gate control connection line Pscan2b is connected between two first gate control connection lines Pscan2a, the second reset connection line VL2b is connected between the first reset connection line VL2a and the fifth active pattern P5. The second emission control trace EML1b and the first emission control trace EML1a are configured to transmit a first emission control signal EM1, the second emission control connection line EML2b and the first emission control connection line EML2a are configured to transmit a second emission control signal EM2. The second gate control trace Pscan1b and the first gate control trace Pscan1a are configured to transmit a first gate control signal Pscan1. The second gate control connection line Pscan2b and the first gate control connection line Pscan2a are configured to transmit a second gate control signal Pscan2. The second reset line VL2 includes the second reset connection line VL2b and the first reset connection line VL2a.

[0094] The second light-emitting control wire EML1b is connected with the first light-emitting control wire EML1a through the twentieth via hole Ho20 penetrating through the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601 and the second gate insulating layer 502. The second light-emitting control connection wire EML2b is connected with the first light-emitting control connection wire EML2a through the twenty-first via hole Ho21 penetrating through the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601 and the second gate insulating layer 502. The second gate control wire Pscan1b is connected with the first gate control wire Pscan1a through the twenty-second via hole Ho22 penetrating through the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601 and the second gate insulating layer 502. The second gate control connection wire Pscan2b is connected with the first gate control connection wire Pscan2a through the twenty-third via hole Ho23 penetrating through the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601 and the second gate insulating layer 502. The second reset connection wire VL2b is connected with the fifth active pattern P5 through the twenty-fourth via hole Ho24 penetrating through the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, the second gate insulating layer 502 and the first gate insulating layer 501. The second reset connection wire VL2b is connected with the first reset connection wire VL2a through the twenty-fifth via hole Ho25 penetrating through the second interlayer dielectric layer 602, as shown in FIG. 5J.

[0095] The first power connection part VDa can be connected with the first power line VDL through the twenty-sixth via hole Ho26 penetrating through the first flat layer 701, as shown in FIG. 5L.

[0096] Optionally, the first source-drain layer 401 further comprises a second power line VSa electrically connected with the second voltage terminal VSS, and the second source-drain layer 402 comprises a third power connection part VSb connected with the second power line VSa. The third power connection part VSb is connected with the second power line VSa through the fourth connection hole HoD penetrating through the second flat layer 702. The first power line VDL is connected with the second power connection part through the fifth connection hole HoE penetrating through the second flat layer 702, as shown in FIG. 4L and FIG. 5L.

[0097] In addition, the first metal layer 301 is further provided with a connection wire LA, which can be configured to transmit one of a data signal, a power signal and the like, so as to improve the resistance of the wire in the display panel and thus improve the display quality.

[0098] As shown in the sub-pixel Spi wiring structure in FIG. 4A, the first sub-pixel Spi1 includes a first multiplexing transistor Tm1, the second sub-pixel Spi2 includes a second multiplexing transistor Tm2, and the first sub-pixel Spi1 and the second sub-pixel Spi2 are mirror-symmetrical. The first multiplexing transistor Tm1 and the second multiplexing transistor Tm2 are arranged between two second active patterns P2, which is conducive to realizing multiplexing transistors Tm of the first sub-pixel Spi1 and the second sub-pixel Spi2, so as to reduce the design of the number of transistors included in the display panel.

[0099] As shown in the sub-pixel Spi wiring structure in FIG. 5A, the first sub-pixel Spi1 includes a first multiplexing transistor Tm1, the second sub-pixel Spi2 includes a second multiplexing transistor Tm2, the first sub-pixel Spi1 and the second sub-pixel Spi2 are mirror-symmetrical, the first sub-pixel Spi1 and the third sub-pixel Spi3 are mirror-symmetrical about the first multiplexing transistor Tm1, and the second sub-pixel Spi2 and the fourth sub-pixel Spi4 are mirror-symmetrical about the second multiplexing transistor Tm2. The first multiplexing transistor Tm1 and the second multiplexing transistor Tm2 are arranged between the fifth active pattern P5 and the first active pattern P1 of the four sub-pixels Spi, which is conducive to realizing multiplexing transistors Tm of the first sub-pixel Spi1 to the fourth sub-pixel Spi4, so as to reduce the design of the number of transistors included in the display panel.

[0100] It can be understood that the present application only takes the example of the repeat unit RU including two sub-pixels Spi or four sub-pixels Spi, but in actual application, the repeat unit RU can include a design form of more than 4 sub-pixels Spi.

[0101] Please continue to refer to FIG. 1B, the display panel can further include a third source-drain layer 403, a third planar layer 703, and a pixel definition layer 800. The third source-drain layer 403 is located between the second planar layer 702 and the third planar layer 703, and the anode 901 of the light-emitting device LD is located between the pixel definition layer 800 and the third planar layer 703. It can be understood that the display panel further includes a light-emitting layer, a cathode, and other unshown parts of the light-emitting device LD.

[0102] FIG. 6 is a structural schematic diagram of a display device provided by an embodiment of the present application. The present application further provides a display device including any of the above-mentioned display panels.

[0103] It can be understood that the display device includes a television, a computer, a virtual display device, and the like.

[0104] The principles and implementation manners of the present application are described by using specific examples in the present application, and the above examples are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will have changes, and the above description should not be understood as the limitation of the present application.

Claims

1. A display panel, wherein, It includes multiple repeating units, each repeating unit including at least two sub-pixels, each sub-pixel including a light-emitting device, a driving transistor configured to drive the light-emitting device to emit light, and a switching transistor configured to control the signal transmission between the light-emitting device and the driving transistor according to a first light emission control signal; In this embodiment, at least one sub-pixel includes a multiplexing transistor configured to control signal transmission between a plurality of driving transistors and a multiplexing signal line according to a multiplexing control signal; in the same repeating unit, the number of multiplexing transistors electrically connected to the same multiplexing signal line is less than the number of sub-pixels.

2. The display panel of claim 1, wherein, In the same repeating unit, the signals transmitted by the multiplexing signal lines electrically connected to the multiplexing transistors included in different sub-pixels are different, and the multiplexing control signals corresponding to the multiplexing transistors included in different sub-pixels are different.

3. The display panel of claim 2, wherein, The repeating unit includes a first sub-pixel and a second sub-pixel that are mirrored, the first sub-pixel including a first multiplexed transistor, and the second sub-pixel including a second multiplexed transistor; The multiplexing control signal received by the control terminal of the first multiplexing transistor is a second light emission control signal. The multiplexing signal line electrically connected to the first source-drain terminal of the first multiplexing transistor is a first power supply line electrically connected to the first voltage terminal. The second source-drain terminal of the first multiplexing transistor is electrically connected to the first source-drain terminal of the driving transistor of the first sub-pixel and the second sub-pixel. The multiplexing control signal received by the control terminal of the second multiplexing transistor is a first gate control signal; the multiplexing signal line electrically connected to the first source-drain terminal of the second multiplexing transistor is a first reset line; and the second source-drain terminal of the second multiplexing transistor is electrically connected to the first source-drain terminal of the driving transistor of the first sub-pixel and the second sub-pixel.

4. The display panel of claim 3, wherein, The repeating unit includes a third sub-pixel and a fourth sub-pixel that are mirrored. The third sub-pixel is symmetrical to the first sub-pixel about the first multiplexing transistor, and the fourth sub-pixel is symmetrical to the second sub-pixel about the second multiplexing transistor. The second source / drain terminals of the first multiplexed transistor and the second multiplexed transistor are electrically connected to the first source / drain terminals of the driving transistors of the third sub-pixel and the fourth sub-pixel.

5. The display panel of claim 3 or 4, wherein, The display panel includes a gate driving circuit, which includes a plurality of gate driving sub-circuits; the sub-pixel includes: The data transistor includes a control terminal configured to receive a first scan signal, a first source-drain terminal electrically connected to a data line, and a second source-drain terminal; The compensation transistor includes a control terminal for receiving a second scan signal, a first source-drain terminal electrically connected to the first source-drain terminal of the switching transistor and the second source-drain terminal of the driving transistor, and a second source-drain terminal electrically connected to the control terminal of the driving transistor. The initial transistor includes a control terminal for receiving the second scan signal, a first source-drain terminal electrically connected to the first initial line, and a second source-drain terminal electrically connected to the second source-drain terminal of the data transistor; a reset transistor, comprising a control terminal receiving a second gate control signal, a first source-drain terminal electrically connected with a second reset line, and a second source-drain terminal electrically connected with an anode of the light emitting device and a second source-drain terminal of the switch transistor; a first capacitor connected in series between the second source-drain terminal of the data transistor and the control terminal of the drive transistor; and a second capacitor connected in series between the first voltage terminal and the second source-drain terminal of the data transistor; wherein the control terminals of the second multiplex transistor and the reset transistor are electrically connected with different stages of the gate drive sub-circuit; when the reset transistor electrically connects the second reset line and the anode of the light emitting device according to the second gate control signal, the switch transistor is configured to be turned on according to the first light emitting control signal, and the first multiplex transistor is configured to be turned off according to the second light emitting control signal.

6. The display panel of claim 5, wherein, comprising: a first active layer, comprising a first connection part, a first active pattern of the drive transistor, a second active pattern of the switch transistor, a third active pattern of the first multiplex transistor, and a fourth active pattern of the second multiplex transistor; wherein in the same repeating unit, the first connection part is connected between first doped parts of a plurality of the first active patterns, the second active pattern is connected with a corresponding first active pattern away from one end of the first connection part, and the third active pattern and the fourth active pattern are connected with the first connection part; a first metal layer on the first active layer, comprising a first electrode, a first light emitting control wire, a first light emitting control connection line, and a first gate control wire; a part of the first light emitting control wire overlaps with a channel part of the second active pattern, a part of the first light emitting control connection line overlaps with a channel part of the third active pattern, and a part of the first gate control wire overlaps with a channel part of the fourth active pattern; a second metal layer on the first metal layer, comprising a second electrode, a part of the second electrode overlaps with the first electrode; a first source-drain layer on the second metal layer, comprising a first power supply connection part and a second light emitting control connection line; the first power supply connection part is connected between the third active pattern and the first voltage terminal, and the second light emitting control connection line is connected with the first light emitting control connection line; and a second source-drain layer on the first source-drain layer, comprising a first power supply line electrically connected between the first power supply connection part and the first voltage terminal.

7. The display panel of claim 6, wherein, The first connection part extends along a first direction, and the second active pattern, the third active pattern, and the fourth active pattern extend along a second direction intersecting the first direction. The third active pattern and the fourth active pattern are located between the first connection part and the first light-emitting control wire, the second light-emitting control connection wire includes a first sub-connection wire and a second sub-connection wire, the first sub-connection wire is connected to the first light-emitting control connection wire and the second sub-connection wire, and the second sub-connection wire is located on a side of the first light-emitting control wire away from the third active pattern and the fourth active pattern.

8. The display panel of claim 7, wherein, Comprise: The third metal layer is located between the second metal layer and the first source-drain layer and includes a second gate control wire; The first source-drain layer includes a third gate control wire, and the third gate control wire is connected between the first gate control wire and the second gate control wire.

9. The display panel of claim 7, wherein, The first active layer includes a fifth active pattern of the reset transistor, and the fifth active pattern is connected to an end of the second active pattern away from the first active pattern; The first metal layer includes a second gate control line for transmitting the second gate control signal, a part of the second gate control line overlaps a channel part of the fifth active pattern, and the second gate control line is located on a side of the first light-emitting control wire away from the third active pattern and the fourth active pattern; The second metal layer includes a first reset wire and a first reset connection wire; The first source-drain layer includes a second reset wire and a second reset connection wire, the second reset wire is connected between the first reset wire and the fourth active pattern, and the second reset connection wire is connected between the first reset connection wire and the fifth active pattern.

10. The display panel of claim 6, wherein, The first connection part includes a first connection sub-part and a second connection sub-part, the first connection sub-part extends along a first direction, the second connection sub-part extends along a second direction intersecting the first direction, the first connection sub-part is connected between the first doped parts of two first active patterns adjacent along the first direction, and the second connection sub-part is connected between two first connection sub-parts adjacent along the second direction; The second active pattern extends along the second direction, and the second active pattern is electrically connected to an end of the first active pattern away from the first connection sub-part; The third active pattern and the fourth active pattern extend along the first direction, and the third active pattern and the fourth active pattern are located on opposite sides of the second connection sub-part; The first light-emitting control wire is located between the first active pattern and the third active pattern and the fourth active pattern.

11. The display panel of claim 10, wherein, Comprise: The third metal layer is located between the second metal layer and the first source-drain layer and includes a first reset wire; The first source-drain layer includes a second reset wire, and the second reset wire is connected between the first reset wire and the fourth active pattern.

12. The display panel of claim 11, wherein, The first active layer comprises a fifth active pattern of the reset transistor, and the fifth active pattern is connected with the second active pattern away from one end of the first active pattern. The first metal layer comprises a first gate control connection line for transmitting the second gate control signal, and a part of the first gate control connection line overlaps a channel portion of the fifth active pattern, and the first gate control connection line is located between the first light-emitting control trace and the third active pattern and the fourth active pattern. The third metal layer comprises a first reset connection line. The first source-drain layer comprises a second light-emitting control trace, a second light-emitting control connection line, a second gate control trace, a second gate control connection line and a second reset connection line, the second light-emitting control trace is electrically connected with the first light-emitting control trace, the second light-emitting control connection line is electrically connected with the first light-emitting control connection line, the second gate control trace is connected with the first gate control trace, the second gate control trace is connected between the two first gate control connection lines, and the second reset connection line is connected between the first reset connection line and the fifth active pattern.

13. The display panel of claim 6, wherein, The second metal layer comprises a first scan trace and a first scan connection line; and the display panel comprises: A second active layer located on the second metal layer, comprising a sixth active pattern of the data transistor, a seventh active pattern of the compensation transistor and an eighth active pattern of the initial transistor; A third metal layer located between the second active layer and the first source-drain layer, comprising a second scan trace and a second scan connection line; Part of the first scan trace and part of the second scan trace overlap a channel portion of the sixth active pattern, and part of the first scan connection line and part of the second scan connection line overlap channel portions of the seventh active pattern and the eighth active pattern.

14. The display panel of claim 13, wherein, The first metal layer comprises the first initial line, and the second source-drain layer comprises a data line; and the first source-drain layer comprises: A first electrode connection portion connected between the seventh active pattern and the first electrode; A second electrode connection portion connected between the sixth active pattern and the second electrode; A third electrode connection portion connected between the sixth active pattern and the data line; A fourth electrode connection portion connected between the seventh active pattern and the first active pattern and the second active pattern; A fifth electrode connection portion connected between the eighth active pattern and the first initial line.

15. The display panel of claim 6, wherein The first metal layer comprises a third electrode located between the two first electrodes, and the third electrode partially overlaps the two second electrodes; The first source-drain layer comprises a second power supply connection portion, the second power supply connection portion partially overlaps the third electrode, and the second power supply connection portion is electrically connected between the first power supply line and the third electrode.

16. The display panel of claim 3, wherein, The first sub-pixel and the second sub-pixel have different light-emitting colors.

17. A display device, wherein, The display panel comprises any one of claims 1-16.

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