Memory and access control method therefor, and electronic device

Abstract

A memory and an access control method therefor, and an electronic device. The memory comprises: a plurality of memory arrays distributed on a substrate in the direction parallel to the substrate, a plurality of first word line gating sub-circuits (21), and a plurality of first word line gating control lines (HB_MAT_S); each memory array comprises a plurality of layers of memory cell arrays and a plurality of common word lines (CWLs), each memory cell array comprises a plurality of word lines extending in parallel, and the CWLs are connected to at least one word line; each CWL is connected to a corresponding word line driving terminal (HB_SWD) by means of the corresponding first word line gating sub-circuit (21); and a same word line driving terminal (HB_SWD) is separately connected to at least two CWLs of different memory arrays, and each first word line gating sub-circuit (21) is configured to electrically connect the corresponding word line driving terminal (HB_SWD) to the corresponding CWL or disconnect the corresponding word line driving terminal (HB_SWD) from the corresponding CWL under the control of the corresponding first word line gating control line (HB_MAT_S), wherein different CWLs of a same memory array are connected to different word line driving terminals (HB_SWD).

Description

Memory, access control method thereof and electronic device

[0001] The present application claims priority from the Chinese patent application No. 2024113374868, filed on September 24, 2024, and entitled "Memory, access control method thereof and electronic device", the contents of which are to be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, in particular to a memory, an access control method thereof and an electronic device. BACKGROUND

[0003] With the development of integrated circuit technology, the critical dimension of devices is increasingly shrinking, and the types and number of devices contained in a single chip are increasing, so that any slight difference in process production can affect the performance of the device.

[0004] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0005] SUMMARY

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] The present application provides a memory, comprising: a plurality of storage arrays distributed along a direction parallel to a substrate on the substrate, a plurality of first word line gating sub-circuits, and a plurality of first word line gating control lines; the storage array comprises a plurality of layers of storage unit arrays stacked along a direction perpendicular to the substrate and a plurality of common word lines, the storage unit array comprises a plurality of storage units, a plurality of word lines extending along a direction parallel to the substrate, and the common word line is connected to at least one word line; the common word line is connected to one word line driving end through the first word line gating sub-circuit; the same word line driving end is connected to at least two common word lines through different first word line gating sub-circuits, and the common word lines connected to the same word line driving end belong to different storage arrays respectively; the first word line gating sub-circuit is further connected to the first word line gating control line; the first word line gating sub-circuit is configured to electrically connect or disconnect the word line driving end and the common word line under the control of the first word line gating control line; wherein different common word lines of the same storage array are connected to different word line driving ends.

[0008] In some embodiments, the first word line gating sub-circuits connected to the common word lines of the same memory cell array are connected to the same first word line gating control line, and the first word line gating sub-circuits connected to the common word lines of different memory cell arrays are connected to different first word line gating control lines.

[0009] In some embodiments, the first word line gating sub-circuits connected to the common word lines of the same memory cell array are connected to the same first word line gating control line, and the first word line gating sub-circuits connected to the common word lines of different memory cell arrays are connected to different first word line gating control lines.

[0010] In some embodiments, the memory further comprises a plurality of second word line gating sub-circuits and a plurality of second word line gating control lines, the common word lines are further connected to the second word line gating sub-circuits, the second word line gating sub-circuits are further connected to a first preset voltage terminal and the second word line gating control lines, and the second word line gating sub-circuits are configured to electrically connect or disconnect the common word lines and the first preset voltage terminal under the control of the second word line gating control lines.

[0011] In some embodiments, the second word line gating sub-circuits connected to the common word lines of the same memory cell array are connected to the same second word line gating control line, and the second word line gating sub-circuits connected to the common word lines of different memory cell arrays are connected to different second word line gating control lines.

[0012] In some embodiments, the signals of the first word line gating control lines connected to the first word line gating sub-circuits connected to the same common word line and the second word line gating control lines connected to the second word line gating sub-circuits connected to the same common word line are not simultaneously valid level signals; the signals of the two first word line gating control lines connected to the two first word line gating sub-circuits connected to the same word line driving terminal are not simultaneously valid level signals.

[0013] When the signal of the first word line gating control line connected to one of the memory cell arrays of the plurality of memory cell arrays of the same memory array is a valid level signal, the signals of the first word line gating control lines connected to the remaining memory cell arrays of the memory array are invalid level signals, and the signals of the first word line gating control lines connected to the remaining memory arrays of the memory array connected to the same word line driving terminal are invalid level signals.

[0014] In some embodiments, the memory further comprises a plurality of first bit line gating sub-circuits and a plurality of first bit line gating control lines.

[0015] The memory array further comprises: a plurality of bit lines extending in a direction perpendicular to the substrate, a plurality of common bit lines, the common bit lines being connected to at least one bit line, and the common bit lines and the bit lines being connected by the first bit line gating sub-circuit; the first bit line gating sub-circuit is further connected to the first bit line gating control line; the first bit line gating sub-circuit is configured to electrically connect or disconnect the common bit lines and the bit lines under the control of the first bit line gating control line.

[0016] In some embodiments, the memory further comprises: a plurality of second bit line gating sub-circuits, a plurality of second bit line gating control lines;

[0017] The bit lines are further connected to the second bit line gating sub-circuit, the second bit line gating sub-circuit is further connected to a second preset voltage terminal and a second bit line gating control line; the second bit line gating sub-circuit is configured to electrically connect or disconnect the bit lines and the second preset voltage terminal under the control of the second bit line gating control line.

[0018] In some embodiments, the memory cell array comprises a plurality of memory cells arranged in a first direction and a second direction parallel to the substrate, the word lines extending in the first direction; the word lines are connected to a row of memory cells arranged in the first direction;

[0019] Each column of bit lines arranged in the second direction corresponds to L common bit lines, and each L consecutive bit lines in the same column of bit lines are divided into a bit line group; the bit lines in the same bit line group are connected to different common bit lines corresponding to the column of bit lines; the plurality of first bit line gating sub-circuits connected to the bit lines in the same bit line group are connected to the same first bit line gating control line, and the plurality of second bit line gating sub-circuits connected to the bit lines in the same bit line group are connected to the same second bit line gating control line.

[0020] In some embodiments, the first bit line gating control line connected to the first bit line gating sub-circuit connected to the same bit line and the second bit line gating control line connected to the second bit line gating sub-circuit are not simultaneously valid level signals;

[0021] When the first bit line gating control line connected to the plurality of first bit line gating sub-circuits connected to the bit lines in the same bit line group of the same memory array is a valid level signal, the first bit line gating control lines connected to the remaining bit line groups of the memory array are all invalid level signals.

[0022] The embodiments of the present disclosure provide an access control method, applied to the above-mentioned memory, comprising:

[0023] In the data access phase, a valid level signal is loaded on a first word line gate control line connected to a first word line connected to a common word line to which a target memory cell to be operated is connected, an invalid level signal is loaded on a first word line gate control line connected to a first word line connected to a memory cell array to which a memory cell array to which the target memory cell is connected is connected, and an invalid level signal is loaded on a first word line gate control line connected to a first word line gate sub-circuit connected to all other memory arrays connected to the same word line driving end as the memory array to which the target memory cell is connected.

[0024] In some embodiments, the method further comprises loading an invalid level signal on a second word line gate control line connected to a second word line gate sub-circuit connected to a common word line to which the target memory cell is connected, loading a valid level signal on a second word line gate control line connected to a second word line connected to a memory cell array to which a memory cell array to which the target memory cell is connected is connected, and loading a valid level signal on a second word line gate control line connected to a second word line gate sub-circuit connected to all other memory arrays connected to the same word line driving end as the memory array to which the target memory cell is connected.

[0025] In some embodiments, the method further comprises:

[0026] loading a valid level signal on a first bit line gate control line connected to a first bit line gate sub-circuit connected to a bit line group to which a bit line connected to the target memory cell belongs; loading an invalid level signal on a second bit line gate control line connected to a second bit line gate sub-circuit connected to the bit line group to which the bit line connected to the target memory cell belongs; and loading an invalid level signal on a first bit line gate control line connected to a first bit line gate sub-circuit connected to other bit line groups of the memory array to which the target memory cell is connected; and loading a valid level signal on a second bit line gate control line connected to a second bit line gate sub-circuit connected to the other bit line groups.

[0027] The electronic device provided by the embodiments of the present disclosure includes the memory as described in any of the above embodiments.

[0028] In some embodiments, the electronic device further includes a control circuit configured to access the memory according to the access control method as described in any of the above embodiments.

[0029] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the present application. Other advantages of the present application can be realized and attained by means of the instrumentalities and combinations particularly pointed out in the following description.

[0030] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.

[0031] SUMMARY

[0032] The accompanying drawings are intended to provide a better understanding of the technical scheme of the present application, and constitute a part of the specification. The drawings, together with the embodiments of the present application, are used to explain the technical scheme of the present application, and do not constitute a limitation on the technical scheme of the present application.

[0033] FIG. 1 is a structural schematic diagram of a memory according to some embodiments;

[0034] FIG. 2 is a partial equivalent circuit diagram of a word line gating circuit according to some embodiments;

[0035] FIG. 3 is a schematic diagram of a common bit line and a bit line connection according to some embodiments;

[0036] FIG. 4 is an equivalent circuit diagram of a bit line gating circuit according to some embodiments;

[0037] FIG. 5 is a block diagram of an electronic device according to some embodiments.

[0038] DETAILED DESCRIPTION

[0039] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The features of the embodiments of the present disclosure and the embodiments can be combined with each other as long as they do not conflict.

[0040] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as the common meaning understood by a person having ordinary skill in the art to which the present disclosure belongs.

[0041] The embodiments of the present disclosure are not necessarily limited to the sizes shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the actual proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0042] In the present disclosure, ordinal numbers such as "first", "second", "third" and the like are set in order to avoid confusion of the components, and do not represent any order, number or importance.

[0043] In the present disclosure, for the convenience of description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.

[0044] In this disclosure, unless clearly specified and limited otherwise, the terms "mount", "connect", and "join" should be interpreted broadly. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or a connection within two elements. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0045] In this disclosure, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to a region through which current mainly flows.

[0046] In this disclosure, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using a transistor with opposite polarity, or in the case of changing the direction of current in circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this disclosure, "source electrode" and "drain electrode" can be exchanged with each other.

[0047] In this disclosure, "connection" includes the case where the constituent elements are connected together through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected constituent elements. Examples of the element having a certain electrical action include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0048] In this disclosure, "parallel" means approximately parallel or almost parallel, such as a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0049] FIG. 1 is a top view of a memory according to an embodiment of the present disclosure. FIG. 2 is an equivalent circuit diagram of part of a word line selection circuit 100 according to some embodiments.

[0050] As shown in FIG. 1 and FIG. 2, the memory provided by the embodiments of the present disclosure can include a plurality of memory arrays (such as the first memory array MATk and the second memory array MATk+1 shown in FIG. 1, only two memory arrays are shown in FIG. 1, but the embodiments of the present disclosure are not limited thereto, and there can be more memory arrays) distributed along a direction parallel to a substrate, and a word line gating circuit 100, which can include a plurality of first word line gating sub-circuits 21 and a plurality of first word line gating control lines HB_MAT_S. The memory array can include a plurality of layers of memory cell arrays stacked along a direction perpendicular to the substrate, a plurality of common word lines CWL, the memory cell array can include a plurality of memory cells, a plurality of word lines WL extending along a direction parallel to the substrate, and the common word line CWL is connected to at least one word line WL; each common word line CWL is connected to a word line driving end HB_SWD through a first word line gating sub-circuit 21, and the word line driving end HB_SWD can be connected to an external word line driver to load a signal generated by the word line driver to the common word line CWL. The same word line driving end HB_SWD can be connected to at least two common word lines CWL (each common word line CWL is connected to one first word line gating sub-circuit 21) through different first word line gating sub-circuits 21, respectively, and the common word lines CWL connected to the same word line driving end HB_SWD belong to different memory arrays, respectively. The first word line gating sub-circuit 21 is further connected to the first word line gating control line HB_MAT_S; the first word line gating sub-circuit 21 is configured to electrically connect or disconnect the word line driving end HB_SWD and the common word line CWL under the control of the first word line gating control line HB_MAT_S; wherein different common word lines CWL in the same memory array are connected to different word line driving ends HB_SWD.

[0051] The scheme provided by the embodiments of the present disclosure can share the word line driver by different memory arrays, can reduce the number of hybrid bonding pads used for connecting a plurality of memory arrays and a word line driver, reduce the area occupied by the hybrid bonding pads, reduce the device area, and improve the device density.

[0052] In some embodiments, the memory cell can be a 1T1C structure memory cell including one transistor and one capacitor. However, the embodiments of the present disclosure are not limited thereto, and other structures of memory cells can also be used.

[0053] In some embodiments, the array of memory cells can include a plurality of memory cells arrayed along a first direction X parallel to the substrate and a second direction Y parallel to the substrate, the word lines WL can extend along the first direction X, and one word line WL connects a row of memory cells arrayed along the first direction X. The first direction X and the second direction Y can be perpendicular.

[0054] In some embodiments, the memory array can further include a plurality of bit lines BL extending along a direction perpendicular to the substrate arrayed along the first direction X and the second direction Y, a plurality of common bit lines CBL, and each common bit line CBL connects at least one bit line BL.

[0055] In some embodiments, the same word line driving end HB_SWD can connect two common word lines CWL through different first word line gating sub-circuits 21 respectively, and the two common word lines CWL connected to the same word line driving end HB_SWD belong to two adjacent memory arrays respectively. The two adjacent memory arrays can be, for example, two memory arrays adjacent along the first direction X. For example, as shown in FIG. 1 and FIG. 2, the first memory array MATk and the second memory array MATk+1 are two adjacent memory arrays, the first common word line CWL1_k of the first memory array MATk is connected to the first word line driving end HB_SWD1 through a first word line gating sub-circuit 21, and the first common word line CWL1_k+1 of the second memory array MATk+1 is connected to the first word line driving end HB_SWD1 through a first word line gating sub-circuit 21; the second common word line CWL2_k of the first memory array MATk is connected to the second word line driving end HB_SWD2 through a first word line gating sub-circuit 21, and the second common word line CWL2_k+1 of the second memory array MATk+1 is connected to the second word line driving end HB_SWD2 through a first word line gating sub-circuit 21; the third common word line CWL3_k of the first memory array MATk is connected to the third word line driving end HB_SWD3 through a first word line gating sub-circuit 21, and the third common word line CWL3_k+1 of the second memory array MATk+1 is connected to the third word line driving end HB_SWD3 through a first word line gating sub-circuit 21; and so on.

[0056] In some embodiments, the first word line gating sub-circuits 21 connected with the multiple common word lines CWL of the same storage cell array can be connected with the same first word line gating control line HB_MAT_S, and the first word line gating sub-circuits 21 connected with the common word lines CWL of different storage cell arrays can be connected with different first word line gating control lines HB_MAT_S. FIG. 2 shows two storage cell arrays connected with the first word line gating sub-circuits 21 and the first word line gating control lines HB_MAT_S belonging to different storage arrays. The multiple first word line gating sub-circuits 21 connected with one storage cell array are connected with the first first word line gating control line HB_MAT_S1, and the multiple first word line gating sub-circuits 21 connected with the other storage cell array are connected with the second first word line gating control line HB_MAT_S2.

[0057] In some embodiments, the word line gating circuit 100 can further include multiple second word line gating sub-circuits 22 and multiple second word line gating control lines HB_MAT_Sb. The common word line CWL is further connected with the second word line gating sub-circuits 22. The second word line gating sub-circuits 22 are further connected with the first preset voltage terminal VSS and the second word line gating control lines HB_MAT_Sb. The second word line gating sub-circuits 22 are configured to electrically connect or disconnect the common word line CWL and the first preset voltage terminal VSS under the control of the second word line gating control lines HB_MAT_Sb. In some embodiments, the voltage of the first preset voltage terminal VSS can be a low voltage, such as zero voltage or negative voltage. The scheme provided by the embodiments of the present disclosure can connect the common word line with the first preset voltage terminal VSS when the first word line gating sub-circuit 21 connected with the common word line CWL is disconnected, so as to avoid the common word line CWL in a floating state.

[0058] In some embodiments, the multiple second word line gating sub-circuits 22 connected with the multiple common word lines CWL of the same storage cell array can be connected with the same second word line gating control line HB_MAT_Sb, and the second word line gating sub-circuits 22 connected with the common word lines CWL of different storage cell arrays can be connected with different second word line gating control lines HB_MAT_Sb. As shown in FIG. 2, the multiple second word line gating sub-circuits 22 connected with one storage cell array are connected with the first second word line gating control line HB_MAT_Sb1, and the multiple second word line gating sub-circuits 22 connected with the other storage cell array are connected with the second second word line gating control line HB_MAT_Sb2.

[0059] In some embodiments, one common word line CWL can be connected to W word lines WL which are continuously distributed along the second direction Y. W can be 2, 3, 4, etc. In FIG. 1, one common word line CWL is connected to 4 continuously distributed word lines WL. However, embodiments of the present disclosure are not limited thereto, and one common word line CWL can be connected to multiple word lines WL which are spaced along the second direction Y.

[0060] In some embodiments, the common word line CWL can be connected to the first word line selection sub-circuit 21 and the second word line selection sub-circuit 22 through a stepped electrode.

[0061] In some embodiments, each column of bit lines BL distributed along the second direction Y can correspond to L common bit lines CBL. In the same column, every L continuously distributed bit lines BL are divided into one bit line group, and the bit lines BL in the same bit line group are respectively connected to different common bit lines CBL corresponding to the column of bit lines BL. L can be 2, 3, 4, etc. For example, as shown in FIG. 3, one column of bit lines BL can correspond to 4 common bit lines CBL, i.e., 4 common bit lines CBL can be arranged in the region where the column of storage units is located, every 4 continuously distributed bit lines BL are divided into one bit line group, and the 4 bit lines BL in the same bit line group are respectively connected to the first common bit line CBL1, the second common bit line CBL2, the third common bit line CBL3, and the fourth common bit line CBL4. The bit lines BL in adjacent bit line groups which are connected to the same common bit line CBL are spaced by 3 bit lines BL. The connection mode shown in FIG. 3 is only an example, and other connection modes can be used.

[0062] In some embodiments, L can be equal to W. However, L can not be equal to W. For example, two word lines WL which are spaced along the second direction Y can be connected to the same common word line CWL, and every 4 continuously distributed bit lines BL are respectively connected to 4 common bit lines CBL, etc.

[0063] In some embodiments, the word lines WL connected to the storage units of the bit lines BL in the same bit line group in the same layer are connected to the same common word line CWL. As shown in FIG. 3, the storage units in the first row and the first column connected to the bit line BL1 to the bit line BL4 to the storage units in the fourth row and the first column (connected to the first word line WL to the fourth word line WL) are connected to the same common word line CWL.

[0064] In other embodiments, as shown in FIG. 4, one column of bit lines BL can correspond to 2 common bit lines CBL, i.e., 2 common bit lines CBL can be arranged in the region where the column of storage units is located, every 2 continuously distributed bit lines BL are divided into one bit line group, and the 2 bit lines BL in the same bit line group are respectively connected to the first common bit line CBL1 and the second common bit line CBL2.

[0065] In some embodiments, the memory can further include: a plurality of first bit line gating sub-circuits 31, a plurality of first bit line gating control lines SL; and the common bit line CBL and the bit lines BL are connected through the first bit line gating sub-circuits 31; the first bit line gating sub-circuits 31 are further connected to the first bit line gating control lines SL; and the first bit line gating sub-circuits 31 are configured to electrically connect or disconnect the common bit line CBL and the bit lines BL under the control of the first bit line gating control lines SL. The scheme provided in this embodiment can connect only the BL to be operated to the CBL, and disconnect the remaining BLs, thereby reducing the capacitive reactance of the CBL, reducing power consumption, and improving operation speed. When the capacitive reactance of the CBL is smaller, the voltage change ΔVBL on the BL is larger after the BL and the storage unit perform charge sharing. Therefore, the CBL can be connected to more bit lines, and the corresponding memory can use fewer CBLs. In addition, since the CBL is connected to the sense amplifier, the number of CBLs is reduced, and the number of sense amplifiers connected to the CBLs can be reduced accordingly; that is, one CBL can be connected to more BLs, the number of CBLs is reduced, and the number of sense amplifiers is reduced.

[0066] In some embodiments, the plurality of first bit line gating sub-circuits 31 connected to the plurality of bit lines BL of the same bit line group can be connected to the same first bit line gating control line SL, and the plurality of first bit line gating sub-circuits 31 connected to the plurality of bit lines BL of different bit line groups can be connected to different first bit line gating control lines SL. For example, as shown in FIG. 4, the first bit line BL1 and the second bit line BL2 form a bit line group, the first bit line gating sub-circuits 31 connected to the bit lines BL of this bit line group are connected to the first first bit line gating control line SL1; the third bit line BL3 and the fourth bit line BL4 form a bit line group, the first bit line gating sub-circuits 31 connected to the bit lines BL of this bit line group are connected to the second first bit line gating control line SL2; and the fifth bit line BL5 and the sixth bit line BL6 form a bit line group, the first bit line gating sub-circuits 31 connected to the bit lines BL of this bit line group are connected to the third first bit line gating control line SL3.

[0067] In some embodiments, the memory can further include: a plurality of second bit line gating sub-circuits 32, a plurality of second bit line gating control lines PreC;

[0068] The bit line BL is also connected to the second bit line gating sub-circuit 32, and the second bit line gating sub-circuit 32 is also connected to a second preset voltage terminal Vpre and a second bit line gating control line PreC; the second bit line gating sub-circuit 32 is configured to electrically connect or disconnect the bit line BL and the second preset voltage terminal Vpre under the control of the second bit line gating control line PreC. The scheme provided in this embodiment can avoid the non-target bit line floating when the first bit line gating sub-circuit 31 is turned off, and facilitate the connection of the non-target bit line to the second preset voltage terminal Vpre, so as to avoid the voltage change of the non-target bit line and the interference on the target bit line. However, the embodiments of the present disclosure are not limited thereto, and in other embodiments, the second bit line gating sub-circuit 32 can not be provided.

[0069] In some embodiments, the voltage of the second preset voltage terminal Vpre can be a value between the voltage corresponding to the logic data "0" (such as zero voltage) and the voltage VDD corresponding to the logic data "1", such as 1 / 2VDD, etc.

[0070] In some embodiments, the plurality of second bit line gating sub-circuits 32 connected by the plurality of bit lines in the same bit line group can be connected to the same second bit line gating control line PreC, and the plurality of second bit line gating sub-circuits 32 connected by the plurality of bit lines in different bit line groups can be connected to different second bit line gating control lines PreC. For example, the two second bit line gating sub-circuits 32 connected by the bit lines BL of the bit line group composed of the first bit line BL1 and the second bit line BL2 are connected to the first second bit line gating control line PreC1; the two second bit line gating sub-circuits 32 connected by the bit lines BL of the bit line group composed of the third bit line BL3 and the fourth bit line BL4 are connected to the second second bit line gating control line PreC2; and the two second bit line gating sub-circuits 32 connected by the bit lines BL of the bit line group composed of the fifth bit line BL5 and the sixth bit line BL6 are connected to the third second bit line gating control line PreC3.

[0071] In some embodiments, the first word line gating sub-circuit 21 can include a first transistor T1, the gate electrode of the first transistor T1 is connected to the first word line gating control line HB_MAT_S, the first electrode is connected to the word line driving terminal HB_SWD, and the second electrode is connected to the common word line CWL, wherein the second electrode of the first transistor T1 can be connected to the common word line CWL through a connection to a step electrode node connected to the common word line CWL.

[0072] In some embodiments, the second word line gating sub-circuit 22 can include a second transistor T2, a gate electrode of the second transistor T2 is connected to the second word line gating control line HB_MAT_Sb, a first electrode is connected to the first preset voltage terminal VSS, and a second electrode is connected to the common word line CWL, wherein the second electrode of the second transistor T2 can be connected to the common word line CWL through a connection to a step electrode node connected to the common word line CWL.

[0073] In some embodiments, the first bit line gating sub-circuit 31 can include a third transistor T3, a gate electrode of the third transistor T3 is connected to the first bit line gating control line SL, a first electrode is connected to the common bit line CBL, and a second electrode is connected to the bit line BL.

[0074] In some embodiments, the second bit line gating sub-circuit 32 can include a fourth transistor T4, a gate electrode of the fourth transistor T4 is connected to the second bit line gating control line PreC, a first electrode is connected to the second preset voltage terminal Vpre, and a second electrode is connected to the bit line BL.

[0075] In some embodiments, the first word line gating control line HB_MAT_S connected to the first word line gating sub-circuit 21 connected to the same common word line CWL and the second word line gating control line HB_MAT_Sb connected to the second word line gating sub-circuit 22 connected to the common word line CWL are not simultaneously active level signals; wherein the active level signal is a signal that causes the corresponding gating sub-circuit to turn on, and the inactive level signal is a signal that causes the corresponding gating sub-circuit to turn off. That is, the first word line gating sub-circuit 21 and the second word line gating sub-circuit 22 connected to the same common word line CWL do not turn on at the same time.

[0076] In some embodiments, the two first word line gating control lines HB_MAT_S connected to the two first word line gating sub-circuits 21 connected to the same word line driving terminal HB_SWD are not simultaneously active level signals; that is, the signal of the same word line driving terminal HB_SWD is only loaded onto one common word line CWL of multiple common word lines CWL connected at the same time.

[0077] In some embodiments, when the signal of the first word line gating control line HB_MAT_S connected to one of the plurality of memory cell arrays of the same memory array is a valid level signal, the signal of the first word line gating control line HB_MAT_S connected to the rest of the memory cell arrays of the same memory array is an invalid level signal, and the signal of the first word line gating control line HB_MAT_S connected to the rest of the memory arrays of the same memory array connected to the same word line driving end HB_SWD is an invalid level signal, only one of the plurality of word line driving ends HB_SWD connected to the memory cell arrays of the same layer is loaded with an activation signal (the activation signal is a signal that causes the memory cell to open) at the same time. For example, the signal of the first word line gating control line HB_MAT_S connected to one of the memory cell arrays of the first memory array MATk is a valid level signal, the signal of the second word line gating control line HB_MAT_Sb connected to the memory cell array is an invalid level signal, the signal of the first word line gating control line HB_MAT_S connected to the memory cell arrays of the other layers of the first memory array MATk is an invalid level signal, the signal of the second word line gating control line HB_MAT_Sb connected to the memory cell arrays of the other layers of the first memory array MATk is a valid level signal, the signal of the first word line gating control line HB_MAT_S connected to each of the memory cell arrays of the second memory array MATk+1 is an invalid level signal, and the signal of the second word line gating control line HB_MAT_Sb connected to each of the memory cell arrays of the second memory array MATk+1 is a valid level signal.

[0078] In some embodiments, the signal PreC of the first bit line gating control line SL connected to the first bit line gating sub-circuit 31 and the second bit line gating control line connected to the second bit line gating sub-circuit 32 connected to the same bit line BL is not a valid level signal at the same time. That is, the first bit line gating sub-circuit 31 and the second bit line gating sub-circuit 32 connected to the same bit line BL are not turned on at the same time.

[0079] In some embodiments, when the signal of the first bit line selection control line SL connected by the plurality of first bit line selection sub-circuits 31 of the plurality of bit lines BL of one bit line group of the same storage array is a valid level signal, the signals of the first bit line selection control lines SL connected by the rest bit line groups of the storage array are all invalid level signals. For example, as shown in FIG. 4, when the signal of the first bit line selection control line SL1 connected by the bit line group composed of the common bit lines BL1 and BL2 in the first storage array MATk is a valid level signal, the signals of the second first bit line selection control line SL2, the third first bit line selection control line SL3 and other first bit line selection control lines in the first storage array MATk are all invalid level signals, the signal of the first second bit line selection control line PreC1 is an invalid level signal, and the signals of the second second bit line selection control line PreC2, the third second bit line selection control line PreC3 and other second bit line selection control lines are all valid level signals.

[0080] In some embodiments, the first word line selection sub-circuit 21, the second word line selection sub-circuit 22, the first bit line selection sub-circuit 31 and the second bit line selection sub-circuit 32 can be manufactured by using a non-CMOS process, so that the first word line selection sub-circuit 21, the second word line selection sub-circuit 22, the first bit line selection sub-circuit 31 and the second bit line selection sub-circuit 32 can be located in the same die as the storage array.

[0081] In some embodiments, the word line selection circuit 100 can be arranged between the storage arrays adjacent along the first direction X.

[0082] The embodiments of the present disclosure further provide an electronic device comprising the memory as described in any of the preceding embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, etc. The storage device can include a memory in a computer, etc., which is not limited herein.

[0083] In some embodiments, the electronic device can further include a control circuit configured to access the memory according to any of the access control methods described above. The control circuit can include a word line driver for generating a driving signal to the common word line, and a driver for generating a control signal to the first word line gate control line, the second word line gate control line, the first bit line gate control line, and the second bit line gate control line, etc. The control circuit and a sense amplifier together implement access to the memory. The control circuit and the sense amplifier can be disposed on different dies from the memory, and the die on which the control circuit is disposed and the die on which the memory is disposed can be connected through hybrid bonding pads. As shown in FIG. 5, the control circuit can be disposed on a peripheral circuit die, and the memory can be disposed on a memory die, and the two are connected through hybrid bonding pads 200. The common bit line is connected to the sense amplifier through the hybrid bonding pads 200.

[0084] The embodiments of the present disclosure provide an access control method, which can be applied to the memory described above, and can include:

[0085] In the data access phase, a valid level signal is loaded on the first word line gate control line HB_MAT_S connected to the common word line CWL connected to the target storage unit to be operated, an invalid level signal is loaded on the first word line gate control line HB_MAT_S connected to other storage unit arrays of the storage array in which the storage unit array in which the target storage unit is located, and an invalid level signal is loaded on the first word line gate control line HB_MAT_S connected to all first word line gate sub-circuits 21 connected to other storage arrays connected to the same word line driving end HB_SWD of the storage array in which the target storage unit is located.

[0086] The data access phase is a phase of reading data or writing data to the storage unit.

[0087] The scheme provided by the embodiments of the present disclosure can achieve loading of the signal of the word line driving end to only one storage unit array.

[0088] In some embodiments, the method further comprises loading an invalid level signal on a second word line gating control line HB_MAT_Sb connected to a second word line gating sub-circuit 22 connected to a common word line CWL connected to the target memory cell, loading a valid level signal on the second word line gating control line HB_MAT_Sb connected to other memory cell arrays of a memory array in which the memory cell array in which the target memory cell is located, and loading a valid level signal on the second word line gating control line HB_MAT_Sb connected to all second word line gating sub-circuits 22 connected to the same word line driving end HB_SWD of other memory arrays connected to the memory array in which the target memory cell is located. That is, the common word line connected to the non-target memory cell is connected to the first preset voltage end VSS to avoid floating.

[0089] In some embodiments, the method can further comprise:

[0090] In some embodiments, the method can further comprise:

[0091] In some embodiments, the method can further comprise:

[0090] In some embodiments, the method can further comprise:

[0091] Although the embodiments of the present application are disclosed as above, the content described is only used to facilitate understanding of the present application, and is not intended to limit the present application. Any person skilled in the art of the present application can make any modification and change in the implementation form and details without departing from the spirit and scope of the present application. The patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A memory, comprising: A plurality of memory arrays distributed along a direction parallel to a substrate, a plurality of first word line gating sub-circuits, and a plurality of first word line gating control lines; the memory array comprises a plurality of memory cell arrays stacked along a direction perpendicular to the substrate and a plurality of common word lines, the memory cell array comprises a plurality of memory cells and a plurality of word lines extending along a direction parallel to the substrate, and the common word line is connected to at least one word line; The common word line is connected to one word line driving end through the first word line gating sub-circuit; the same word line driving end is connected to at least two common word lines through different first word line gating sub-circuits, and the common word lines connected to the same word line driving end belong to different memory arrays; the first word line gating sub-circuit is further connected to the first word line gating control line; the first word line gating sub-circuit is configured to electrically connect or disconnect the word line driving end and the common word line under the control of the first word line gating control line; wherein different common word lines of the same memory array are connected to different word line driving ends.

2. The memory of claim 1, wherein, The same word line driving end is connected to two common word lines through different first word line gating sub-circuits, and the two common word lines connected to the same word line driving end belong to adjacent two memory arrays.

3. The memory of claim 2, wherein, The first word line gating sub-circuit connected to the common word line of the same memory cell array is connected to the same first word line gating control line, and the first word line gating sub-circuit connected to the common word line of different memory cell arrays is connected to different first word line gating control lines.

4. The memory of claim 3, wherein, The memory further comprises a plurality of second word line gating sub-circuits and a plurality of second word line gating control lines, the common word line is further connected to the second word line gating sub-circuit, the second word line gating sub-circuit is further connected to a first preset voltage end and a second word line gating control line, and the second word line gating sub-circuit is configured to electrically connect or disconnect the common word line and the first preset voltage end under the control of the second word line gating control line.

5. The memory of claim 4, wherein, The second word line gating sub-circuit connected to the common word line of the same memory cell array is connected to the same second word line gating control line, and the second word line gating sub-circuit connected to the common word line of different memory cell arrays is connected to different second word line gating control lines.

6. The memory of claim 5, wherein The signals of the first word line gating control line connected to the first word line gating sub-circuit connected to the same common word line and the second word line gating control line connected to the second word line gating sub-circuit connected to the common word line are not simultaneously valid level signals; the signals of the two first word line gating control lines connected to the two first word line gating sub-circuits connected to the same word line driving end are not simultaneously valid level signals; When the signal of the first word line gating control line connected to one memory cell array of the plurality of memory cell arrays of the same memory array is a valid level signal, the signals of the first word line gating control lines connected to the remaining memory cell arrays of the memory array are invalid level signals, and the signals of the first word line gating control lines connected to the remaining memory arrays of the memory array connected to the same word line driving end are invalid level signals.

7. The memory of any one of claims 1 to 6, wherein, The memory further comprises a plurality of first bit line gating sub-circuits and a plurality of first bit line gating control lines; The memory array further comprises a plurality of bit lines extending in a direction perpendicular to the substrate, a plurality of common bit lines connecting at least one bit line, and the common bit line and the bit line being connected by the first bit line gating sub-circuit; the first bit line gating sub-circuit is further connected to the first bit line gating control line; the first bit line gating sub-circuit is configured to electrically connect or disconnect the common bit line and the bit line under the control of the first bit line gating control line.

8. The memory of claim 7, wherein, The memory further comprises a plurality of second bit line gating sub-circuits and a plurality of second bit line gating control lines; The bit line is further connected to the second bit line gating sub-circuit, and the second bit line gating sub-circuit is further connected to a second preset voltage terminal and a second bit line gating control line; the second bit line gating sub-circuit is configured to electrically connect or disconnect the bit line and the second preset voltage terminal under the control of the second bit line gating control line.

9. The memory of claim 8, wherein, The memory cell array comprises a plurality of memory cells arranged in a first direction parallel to the substrate and a second direction; the word line extends in the first direction; the word line connects a row of memory cells arranged in the first direction; Each column of bit lines arranged in the second direction corresponds to L common bit lines; in the same column of bit lines, every L continuous bit lines are divided into a bit line group; the bit lines in the same bit line group are connected to different common bit lines corresponding to the column of bit lines; the first bit line gating sub-circuits connected to the bit lines in the same bit line group are connected to the same first bit line gating control line, and the second bit line gating sub-circuits connected to the bit lines in the same bit line group are connected to the same second bit line gating control line.

10. The memory of claim 9, wherein, The signals of the first bit line gating control line connected to the first bit line gating sub-circuit and the second bit line gating control line connected to the second bit line gating sub-circuit connected to the same bit line are not simultaneously valid level signals; When the signal of the first bit line gating control line connected to the first bit line gating sub-circuit connected to the bit lines in the same bit line group of one memory array is a valid level signal, the signals of the first bit line gating control lines connected to the first bit line gating sub-circuits connected to the bit lines in the remaining bit line groups of the memory array are all invalid level signals.

11. An access control method applied to the memory of any one of claims 1 to 10, comprising: In the data access phase, a valid level signal is loaded on the first word line gating control line connected to the common word line connected to the target memory cell to be operated, an invalid level signal is loaded on the first word line gating control line connected to the memory cell array in which the target memory cell is located, and an invalid level signal is loaded on the first word line gating control line connected to all the first word line gating sub-circuits connected to the same word line driving terminal of the memory array in which the target memory cell is located.

12. The access control method of claim 11, wherein, The memory is the memory of claim 5 or 6, and the method further comprises loading an invalid level signal on a second word line gate control line connected to a second word line gate sub-circuit connected to a common word line connected to the target memory cell, loading a valid level signal on a second word line gate control line connected to a memory cell array other than the memory cell array where the target memory cell is located, and loading a valid level signal on a second word line gate control line connected to all second word line gate sub-circuits connected to the same word line driving end as the memory array where the target memory cell is located.

13. The access control method of claim 11, wherein, The memory is the memory of claim 9 or 10, and the method further comprises: loading a valid level signal on a first bit line gate control line connected to a first bit line gate sub-circuit connected to a bit line group to which the bit line connected to the target memory cell belongs; loading an invalid level signal on a second bit line gate control line connected to a second bit line gate sub-circuit connected to the bit line group to which the bit line connected to the target memory cell belongs; and loading an invalid level signal on a first bit line gate control line connected to a first bit line gate sub-circuit connected to a bit line group other than the bit line group where the target memory cell is located; and loading a valid level signal on a second bit line gate control line connected to a second bit line gate sub-circuit connected to the bit line group other than the bit line group where the target memory cell is located.

14. An electronic device comprising the memory of any one of claims 1 to 10.

15. The electronic device of claim 14, wherein, The electronic device further comprises a control circuit configured to access the memory according to the access control method of any one of claims 11 to 13.

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