Computing task management method and computing device

Abstract

The present application discloses a computing task management method and a computing device. The method comprises: executing the following operations for an i-th computing stage among M computing stages of a computing task, wherein the i-th computing stage is any one of the M computing stages. A management component acquires computing feature information of the i-th computing stage on the basis of a computing subtask that needs to be implemented in the i-th computing stage; the management component determines, from among N computing cores on the basis of the computing feature information of the i-th computing stage, a j-th computing core for executing the i-th computing stage, wherein at least two of the M computing stages need to be executed by different computing cores; the management component sends control information and executable code of the computing task to the j-th computing core; and the j-th computing core executes the i-th computing stage on the basis of the control information and the executable code of the computing task. The present application facilitates improvement of memory access performance during operator execution.

Description

Management method of computing task and computing device

[0001] The present application claims priority to the Chinese patent application No. 202411391468.8, filed on September 30, 2024, and entitled "Management method of computing task and computing device", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of computing, and in particular, to a management method of computing task and a computing device. BACKGROUND

[0003] In recent years, operators (ops) play an important role and have great value in the field of computing, and are basic computing units for implementing computing tasks, which have an important influence on computing performance and computing efficiency when executing computing tasks. Excellent operators can improve the computing performance and computing efficiency of computing tasks and reduce the resource consumption of computing tasks, so that more computing tasks can be completed under the same computing resources. Among them, an operator is used to perform computation based on input data with a specific shape and obtain output with a specific shape. An operator is usually composed of multiple computing stages, and each computing stage is used to execute a part of computing sub-tasks in a computing task.

[0004] At present, when developing an operator, in order to effectively utilize the computing power of a computing core, the input data of the operator when executing a computing task is usually divided into multiple parts, and each computing core in multiple computing cores is used to execute the operator based on one part of the multiple parts of input data. For example, for an operator including five computing stages, the input data of the operator when executing a computing task is divided into four equal parts, and each computing core in four computing cores is used to execute the operator based on one part of the four parts of input data, and each computing core needs to execute five computing stages.

[0005] Since the input data usually needs to be read from the global memory (GM) into the on-core cache (such as buffer) of the computing core in the execution process of the operator, and then the computing operation is performed based on the input data in the on-core cache. In this way, the current operator execution mode will result in poor memory access performance in the execution process of the operator. SUMMARY

[0006] The present application provides a management method of computing task and a computing device. The present application helps to improve the memory access performance in the execution process of the operator. The technical solutions provided by the present application are as follows:

[0007] In a first aspect, the present application provides a method for managing a computing task. The method is applied to a computing device. The computing device has a management component and N computing cores. The computing task includes M computing stages. M and N are positive integers. The method includes: for an i-th computing stage in the M computing stages, the i-th computing stage being any one of the M computing stages, the management component acquires computing characteristic information of the i-th computing stage based on a computing subtask to be implemented by the i-th computing stage, the computing characteristic information being used to indicate a characteristic presented by execution of the computing stage; the management component determines a j-th computing core for executing the i-th computing stage among the N computing cores based on the computing characteristic information of the i-th computing stage, where there are at least two computing stages in the M computing stages, the at least two computing stages needing to be executed by different computing cores, and the j-th computing core being one of the N computing cores; the management component sends control information and executable code of the computing task to the j-th computing core, where the control information sent by the management component to the j-th computing core is used to instruct the j-th computing core to execute the i-th computing stage; and the j-th computing core executes the i-th computing stage based on the control information and the executable code of the computing task.

[0008] The present application is equivalent to dividing the execution process of the computing task in the dimension of the computing cores based on the computing subtasks to be executed by each computing stage, and dividing the plurality of computing stages of the computing task to the plurality of computing cores for execution respectively. In this way, it is not necessary to use the same computing core to execute all the computing stages of the computing task, the computation amount executed by a single computing core is reduced, the total amount of data to be read from the global memory during execution of a computing stage by a single computing core is reduced, and the memory access performance during execution of an operator is improved. At the same time, since the present application reduces the total amount of data to be read from the global memory during execution of a computing stage by a single computing core, the occupancy capacity of the on-core cache of a single computing core is reduced, and the reduced capacity can be used to store data that can be reused during computation, thereby improving the reuse rate of the on-core cache. Furthermore, by dividing the plurality of computing stages of the computing task to the plurality of computing cores for execution respectively, the present application reduces the computation amount executed by a single computing core, and helps to reduce the complexity of pipelining the memory access process and the computation process by a single computing core. In addition, by dividing the plurality of computing stages of the computing task to the plurality of computing cores for execution respectively, the present application enables a computing stage executed later to wait for all the computing results of the computing stages executed earlier by other computing cores before executing computation based on the computing results in a specified order, so that the computation of the computing stage executed later is performed in the specified order each time, which helps to ensure consistency of the computing results of multiple computations, improves the reliability of computation, and better supports sequential sensitive computation.

[0009] In a possible implementation, the calculation characteristic information of the first calculation stage indicates one or more of the following: a total amount of data required by the first calculation stage to transmit to the second calculation stage, a total amount of data of data multiplexed by the first calculation stage and the second calculation stage, or a sensitivity of an order of participation of a calculation result of the second calculation stage in calculation of the first calculation stage, the first calculation stage being any one of the M calculation stages, and the second calculation stage being any one of the M calculation stages other than the first calculation stage.

[0010] Correspondingly, any two calculation stages executed by different calculation cores satisfy one or more of the following conditions: a total amount of data transmitted between the any two calculation stages is less than the first amount threshold, a total amount of data multiplexed by the any two calculation stages is less than the second amount threshold, or a sensitivity of an order of participation of a calculation result of one of the any two calculation stages in calculation of the other of the any two calculation stages is greater than the degree threshold.

[0011] When the total amount of data required by the first calculation stage to transmit to the second calculation stage is less than the first amount threshold, if the first calculation stage and the second calculation stage are scheduled to be executed by different calculation cores, a total amount of data required by a calculation core for executing the first calculation stage to provide to a calculation core for executing the second calculation stage is less than the first amount threshold. Since the data transmitted from the calculation core a to the calculation core b needs to be first stored by the calculation core a to the global memory and then read by the calculation core b from the global memory, when the total amount of data required by the calculation core for executing the first calculation stage to provide to the calculation core for executing the second calculation stage is less than the first amount threshold, it is equivalent to reducing the amount of data written to the global memory by the calculation core for executing the first calculation stage, and reducing the amount of data read from the global memory by the calculation core for executing the second calculation stage, and thus the memory access performance in the operator execution process can be reduced.

[0012] When the total amount of data multiplexed by the first calculation stage and the second calculation stage is less than the second amount threshold, if the first calculation stage and the second calculation stage are scheduled to be executed by different calculation cores, a total amount of data multiplexed by the calculation stages executed by the same calculation core will be greater than the second amount threshold. At this time, in the case that the in-core cache of the calculation core has a specified capacity, the greater the amount of data multiplexed by the calculation stages specified by the same calculation core, on the one hand, the multiplexing rate of the in-core cache can be improved, and on the other hand, the writing and reading out of the data used by the calculation stages between the in-core cache and the global memory can be reduced, and thus the memory access performance in the operator execution process can be improved.

[0013] When the first computing stage is sensitive to the order of the second computing stage's computing result participating in the computation to a degree greater than a degree threshold, the first computing stage may be different when it first targets the second computing stage's computing result and when it later targets the second computing stage's computing result, thereby affecting the reliability of the operator. If the first computing stage and the second computing stage are scheduled to be executed by different computing cores, the order in which the first computing stage computes the second computing stage's computing result can be controlled, ensuring that the first computing stage's computing result when it computes the second computing stage's computing result in multiple computing processes is consistent, thereby improving the reliability of the operator.

[0014] In a possible implementation, in response to the computing characteristic information of the first computing stage indicating that the total amount of data that the first computing stage needs to transmit to the second computing stage, the management component obtains the computing characteristic information of the i-th computing stage based on the computing subtask that the i-th computing stage needs to implement, including: based on the computing subtasks that the first computing stage and the second computing stage need to implement, determining the target computing result output by the first computing stage from the data required for executing the second computing stage; and based on the size of the target computing result, obtaining the total amount of data that the first computing stage needs to transmit to the second computing stage.

[0015] In a possible implementation, in response to the computing characteristic information of the first computing stage indicating that the total amount of data that the first computing stage and the second computing stage share, the management component obtains the computing characteristic information of the i-th computing stage based on the computing subtask that the i-th computing stage needs to implement, including: based on the computing subtasks that the first computing stage and the second computing stage execute, determining the target input data that needs to be used in executing the first computing stage and executing the second computing stage, and determining the target computing result output by the first computing stage from the data required for executing the second computing stage; and based on the size of the target input data and the size of the target computing result, determining the total amount of data that the first computing stage and the second computing stage share.

[0016] In a possible implementation, in response to the computing characteristic information of the first computing stage indicating that the first computing stage is sensitive to the order of the second computing stage's computing result participating in the computation, the management component obtains the computing characteristic information of the i-th computing stage based on the computing subtask that the i-th computing stage needs to implement, including: based on the computing subtask that the first computing stage executes, respectively determining the influence degree of the second computing stage's computing result participating in the computation process of the first computing stage in different orders on the computing result of the first computing stage; and based on the influence degree, determining the sensitivity of the first computing stage to the order of the second computing stage's computing result participating in the computation.

[0017] Optionally, the same computing stage can also be executed by multiple computing cores. In a possible implementation, the method further includes: the management component divides the input data of the i-th computing stage into P groups of input data, P being a positive integer smaller than N. Correspondingly, the management component determines the j-th computing core for executing the i-th computing stage from the N computing cores based on the computing characteristic information of the i-th computing stage, including: the management component determines P computing cores for executing the i-th computing stage from the N computing cores based on the computing characteristic information of the i-th computing stage, the P computing cores corresponding to the P groups of input data.

[0018] In a possible implementation, the method further includes: the management component sends, to each of the P computing cores, indication information of the corresponding group of input data. Correspondingly, the j-th computing core executes the i-th computing stage based on the control information and the executable code of the computing task, including: the j-th computing core executes the i-th computing stage based on the control information, the indication information, and the executable code of the computing task.

[0019] In a possible implementation, the j-th computing core executes a computing operation based on multiple computing results obtained by multiple other computing cores. The other computing cores are the ones other than the j-th computing core from the N computing cores. Before the j-th computing core executes the i-th computing stage based on the control information and the executable code of the computing task, the method further includes: the management component sends, to the j-th computing core, configuration information, the configuration information being used to indicate an execution order of the multiple computing results participating in the computation. Correspondingly, the j-th computing core executes the i-th computing stage based on the control information and the executable code of the computing task, including: the j-th computing core executes the i-th computing stage based on the control information, the configuration information, and the executable code of the computing task.

[0020] The execution order indicated by the configuration information is an order determined according to the computing logic of the computing task. By sending the configuration information to the j-th computing core, the j-th computing core can execute the i-th computing stage for the multiple computing results obtained by the multiple other computing cores according to the configured execution order. In this way, the order of the multiple computing results obtained by the multiple other computing cores participating in the i-th computing stage can be controlled to the configured execution order, ensuring that the computing process is executed according to the execution order in multiple executions of the computing task, thereby ensuring the reliability of the computing task.

[0021] In a second aspect, the present application provides a computing device. The computing device has a management component and N computing cores. A computing task includes M computing stages. M and N are both positive integers. The computing device is configured to perform the following operations for an i-th computing stage in the M computing stages. The i-th computing stage is any one of the M computing stages. The management component is configured to obtain computing characteristic information of the i-th computing stage based on a computing subtask to be implemented by the i-th computing stage, the computing characteristic information being used to indicate a characteristic presented by execution of the computing stage; the management component is further configured to determine a j-th computing core for executing the i-th computing stage among the N computing cores based on the computing characteristic information of the i-th computing stage, wherein there are at least two computing stages in the M computing stages, the at least two computing stages need to be executed by different computing cores, and the j-th computing core is one of the N computing cores; the management component is further configured to send control information and executable code of the computing task to the j-th computing core, wherein the control information sent by the management component to the j-th computing core is used to instruct the j-th computing core to execute the i-th computing stage; and the j-th computing core is configured to execute the i-th computing stage based on the control information and the executable code of the computing task.

[0022] In a possible implementation, the computing characteristic information of the first computing stage indicates one or more of the following: a total amount of data that needs to be transmitted by the first computing stage to a second computing stage, a total amount of data that is multiplexed between the first computing stage and the second computing stage, or a sensitivity of an order in which a result of the second computing stage participates in a computation of the first computing stage, the first computing stage being any one of the M computing stages, and the second computing stage being a computing stage other than the first computing stage in the M computing stages.

[0023] In a possible implementation, any two computing stages executed by different computing cores satisfy one or more of the following conditions: a total amount of data transmitted between the any two computing stages is less than a first quantity threshold, a total amount of data multiplexed between the any two computing stages is less than a second quantity threshold, or a sensitivity of an order in which a result of one of the any two computing stages participates in a computation of the other of the any two computing stages is greater than a degree threshold.

[0024] In a possible implementation, in response to the computing characteristic information of the first computing stage indicating that a total amount of data that needs to be transmitted by the first computing stage to a second computing stage, the management component is specifically configured to: determine a target computing result output by the first computing stage from data required for execution of the second computing stage based on computing subtasks to be implemented by the first computing stage and the second computing stage; and obtain the total amount of data that needs to be transmitted by the first computing stage to the second computing stage based on a size of the target computing result.

[0025] In a possible implementation, the computing feature information of the first computing stage indicates that the first computing stage shares data with the second computing stage. The management component is specifically configured to: determine, based on the computing subtasks executed by the first computing stage and the second computing stage, target input data that is required by both the execution of the first computing stage and the execution of the second computing stage, and target computing result that is output by the first computing stage and required by the second computing stage; and determine, based on the size of the target input data and the size of the target computing result, the total amount of data shared by the first computing stage and the second computing stage.

[0026] In a possible implementation, the computing feature information of the first computing stage indicates that the first computing stage is sensitive to the order in which the computing result of the second computing stage participates in the computation. The management component is specifically configured to: determine, based on the computing subtasks executed by the first computing stage, the influence degree of the computing result of the second computing stage on the computing result of the first computing stage when the computing result of the second computing stage participates in the computation of the first computing stage in different orders; and determine, based on the influence degree, the sensitivity of the first computing stage to the order in which the computing result of the second computing stage participates in the computation.

[0027] In a possible implementation, the management component is further configured to divide the input data of the i-th computing stage into P groups of input data, where P is a positive integer smaller than N. The management component is specifically configured to determine, based on the computing feature information of the i-th computing stage, P computing cores from the N computing cores for executing the i-th computing stage, the P computing cores corresponding to the P groups of input data. Correspondingly, the management component is further configured to send, to each of the P computing cores, indication information of the group of input data corresponding to the computing core. Correspondingly, the j-th computing core is specifically configured to execute the i-th computing stage based on the control information, the indication information, and the executable code of the computing task.

[0028] In a possible implementation, in response to the j-th computing core performing a computing operation based on a plurality of computing results obtained by a plurality of other computing cores, the other computing core is one of the N computing cores other than the j-th computing core. The management component is further configured to send, to the j-th computing core, configuration information indicating the order in which the plurality of computing results participate in the computation. Correspondingly, the j-th computing core is specifically configured to execute the i-th computing stage based on the control information, the configuration information, and the executable code of the computing task.

[0029] In a third aspect, the present application provides a computing device, including a memory and a processor, the memory storing program instructions, and the processor executing the program instructions to perform the method in the first aspect of the present application and any possible implementation manner thereof.

[0030] In a fourth aspect, the present application provides a computer readable storage medium, which is a non-volatile computer readable storage medium, and which includes program instructions that, when executed on a computing device, cause the computing device to perform the method provided in the first aspect of the present application and any possible implementation thereof.

[0031] In a fifth aspect, the present application provides a computer program product including instructions which, when executed on a computer, cause the computer to perform the method provided in the first aspect of the present application and any possible implementation thereof. BRIEF DESCRIPTION OF DRAWINGS

[0032] FIG. 1 is a structural schematic diagram of a computing device according to an embodiment of the present application;

[0033] FIG. 2 is a flowchart of a method for managing a computing task according to an embodiment of the present application;

[0034] FIG. 3 is a flowchart of a method for obtaining computing characteristic information of an i-th computing stage according to an embodiment of the present application;

[0035] FIG. 4 is a flowchart of another method for obtaining computing characteristic information of an i-th computing stage according to an embodiment of the present application;

[0036] FIG. 5 is a flowchart of still another method for obtaining computing characteristic information of an i-th computing stage according to an embodiment of the present application;

[0037] FIG. 6 is a flowchart of another method for managing a computing task according to an embodiment of the present application;

[0038] FIG. 7 is a schematic diagram of computing logic of an operator according to an embodiment of the present application;

[0039] FIG. 8 is a schematic diagram of computing logic of a computing stage executed by a computing core according to an embodiment of the present application;

[0040] FIG. 9 is a schematic diagram of computing logic of a computing stage executed by another computing core according to an embodiment of the present application;

[0041] FIG. 10 is a schematic diagram of computing logic of another operator according to an embodiment of the present application;

[0042] FIG. 11 is a schematic diagram of execution of an operator according to an embodiment of the present application;

[0043] FIG. 12 is a schematic diagram of execution of another operator according to an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the purposes, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0045] For the sake of understanding, the technologies and backgrounds involved in the embodiments of the present application will be introduced first.

[0046] In recent years, operators have an important position and value in the field of computing, are the basic computing units for implementing computing tasks, and have an important influence on the computing performance and computing efficiency of executing computing tasks. Excellent operators can improve the computing performance and computing efficiency of computing tasks, reduce the resource consumption of computing tasks, and enable them to complete more computing tasks under the same computing resources. For example, artificial intelligence (AI) is one of the most transformative and influential technologies in today's technology field, and almost penetrates into various fields such as medicine, finance, transportation and manufacturing. Operators have an important position and value in the field of AI. Operators are the basic computing units in deep learning algorithms, and have an important influence on the performance and efficiency of deep learning models for implementing deep learning algorithms. Excellent operators can improve the efficiency and performance of deep learning models, reduce the resource consumption of deep learning models, and enable them to complete more computing tasks under the same computing resources. Among them, operators are used to perform calculations based on input data with a specific form and obtain output with a specific form. An operator is usually composed of multiple computing stages, and each computing stage is used to execute a part of the computing subtasks in the computing task.

[0047] At present, when developing operators, in order to effectively utilize the computing power of computing cores, the input data of the operator when performing the computing task is usually divided into multiple parts, and each computing core in the multiple computing cores is used to perform the operator based on one part of the multiple input data. For example, for an operator including five computing stages, the input data of the operator when performing the computing task is divided into four equal parts, and each computing core in the four computing cores is used to perform the operator based on one part of the four input data, and each computing core needs to perform five computing stages.

[0048] Since the operator execution process usually needs to first read the input data from the global memory into the on-core cache (such as buffer) of the computing core, and then perform the computing operation based on the input data in the on-core cache. The access speed of the global memory is generally slow, and it has several times or even orders of magnitude speed difference with the on-core cache. However, the current operator execution mode needs multiple computing cores to perform the operation of reading the input data from the global memory into the on-core cache of the computing core, resulting in poor memory access performance in the operator execution process.

[0049] In addition, the current operator execution mode also has some disadvantages. Typical ones are: poor memory reuse. For example, if an operator has multiple matrix (cube, C) calculations, for hardware accelerators that separate matrix calculations from vector (vector, V) calculations, or hardware accelerators with small in-core caches, each matrix calculation often needs to use all the in-core caches, causing the left and right matrices used in the next loop to be moved from global memory to in-core cache, and the data in the in-core cache cannot be effectively reused. A hardware accelerator is a computer hardware device designed specifically to perform certain specific tasks. In general, they are designed to support certain specific applications or operating systems and can provide additional computing power when processing tasks associated with them.

[0050] Data dependency complexity is also a typical disadvantage of the current operator execution mode. For example, since memory access and calculation are usually completed by two different hardware units, the calculation core needs to flow the memory access and calculation when executing the operator. When the execution logic of the operator is complex, the calculation time of multiple calculation stages is different, or some calculation stages may need to access global memory space, which usually causes the flow arrangement of the operator to be complex, and the reuse of the in-core cache to be complex.

[0051] The influence of sequence sensitivity on the reliability of the operator is also a typical disadvantage of the current operator execution mode. For example, hardware accelerators often have multiple calculation cores, and the current operator execution mode needs to cut the operator according to the input data to different calculation cores for calculation, and the execution order of each calculation core is uncertain. If the calculation behavior of the operator involves the calculation results of multiple calculation cores, such as accumulating the calculation results of multiple calculation cores, due to the uncertainty of the calculation order of multiple calculation cores, the order of the calculation results of multiple calculation cores participating in the calculation may be different when the operator is executed multiple times, which may cause the calculation result of the operator to be inconsistent, which affects the reliability of the operator. The typical representative of high sequence sensitivity requirement is floating point calculation, so it has strong appeal to the reliability of the operator.

[0052] In view of this, the embodiments of the present application provide a method for managing a computing task and a computing device. The method is applied to the computing device. The computing device has a management component and N computing cores, the computing task includes M computing stages, and M and N are positive integers. The method includes: for the i-th computing stage in the M computing stages, the management component obtains the computing feature information of the i-th computing stage based on the computing sub-tasks to be implemented by the i-th computing stage, the computing feature information is used to indicate the features presented by the execution of the computing stage; the management component determines the j-th computing core for executing the i-th computing stage based on the computing feature information of the i-th computing stage in the N computing cores, wherein there are at least two computing stages in the M computing stages, the at least two computing stages need to be executed by different computing cores, and the j-th computing core is one of the N computing cores; the management component sends control information and executable code of the computing task to the j-th computing core, wherein the control information sent by the management component to the j-th computing core is used to instruct the j-th computing core to execute the i-th computing stage; and the j-th computing core executes the i-th computing stage based on the control information and the executable code of the computing task.

[0053] In this way, the present application is equivalent to dividing the execution process of the computing task in the dimension of the computing core based on the computing sub-tasks to be executed by each computing stage, and dividing the multiple computing stages of the computing task to multiple computing cores for execution respectively. In this way, it is not necessary to use the same computing core to execute all the computing stages of the computing task, which reduces the amount of computation executed by a single computing core, and correspondingly reduces the total amount of data to be read from the global memory during the execution of the computing stage by a single computing core, which helps to improve the memory access performance during the execution of the operator. At the same time, since the present application reduces the total amount of data to be read from the global memory during the execution of the computing stage by a single computing core, the occupation capacity of the on-core cache of the single computing core is reduced, which can be used to store the data that can be reused during the computing process, and the reuse rate of the on-core cache can be improved. Moreover, by dividing the multiple computing stages of the computing task to multiple computing cores for execution respectively, the present application reduces the amount of computation executed by a single computing core, which helps to reduce the complexity of the pipeline arrangement of the memory access process and the computing process by a single computing core. In addition, by dividing the multiple computing stages of the computing task to multiple computing cores for execution respectively, the present application enables the computing core to wait for all the computing results of the computing stages executed in front by other computing cores before executing the computing stages executed in back according to the specified order based on these computing results, so that the computing is performed according to the specified order in the process of executing the computing stages executed in back multiple times, which helps to ensure the consistency of the computing results of multiple times, improve the reliability of the computing, and better support the order-sensitive computing.

[0054] The technical solutions of the present application are described in detail from the aspects of implementation scenarios, method flows, hardware devices, etc. The application scenarios of the embodiments of the present application are described below.

[0055] The implementation scenario involved in the management method of computing tasks provided by the embodiments of the present application includes a computing device. The computing device is configured with the management method of computing tasks provided by the embodiments of the present application. The computing device can be a server or a multi-core hardware accelerator, etc. For example, the computing device is a server used for performing general computing in a data center. FIG. 1 is a structural schematic diagram of a computing device provided by an embodiment of the present application. As shown in FIG. 1, the computing device 10 includes a processor 101, a communication interface 102, an external memory 103, an internal memory (also referred to as a physical memory) 104, a basic input output system 105 (BIOS), and a bus 106. The processor 101 is provided with a cache medium 107. The processor 101, the communication interface 102, the external memory 103, the internal memory 104, the basic input output system 105, and the cache medium 107 are connected to each other through the bus 106.

[0056] The processor 101 can be a special-purpose hardware chip. The special-purpose hardware chip is a hardware module with high performance processing. The special-purpose hardware chip includes a digital signal processor, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The processor 101 can also be a general-purpose processor, for example, a central processing unit (CPU), a microprocessor, a graphics processing unit (GPU), a network processor (NP), or a combination of a CPU and an NP. The CPU is, for example, a single-CPU, or a multi-CPU.

[0057] In a possible implementation, the computing core in the present application can be a processor core of the processor 101. At this time, the processor 101 can be a multi-core processor, i.e., the processor 101 has multiple processor cores. Correspondingly, the management component in the present application can be one of the multiple processor cores, or the management component is a component in the computing device 10 that has a management function. In this way, the essence of the management component in the present application scheduling a computing task to the computing core for execution is that the management component schedules M computing stages of the computing task to the multiple processor cores of the processor 101 for execution.

[0058] In another implementation, an external device is plugged into the computing device 10, and the external device is configured with computing cores having computing capabilities. At this time, the computing core in the present application can be a computing core of the external device. The management component in the present application is a processor core of the processor 101 or a component in the computing device 10 that has a management function. In this case, the processor 101 can be a single-core processor or a multi-core processor. In this way, the essence of the management component in the present application scheduling a computing task to the computing core for execution is that the management component schedules M computing stages of the computing task to the multiple computing cores of the external device for execution. For example, the external device is a hardware accelerator, a system on chip (SoC), or a multi-training card. Among them, the SoC encapsulates multiple chips.

[0059] The communication interface 102 uses a transceiving module such as, but not limited to, a transceiver to implement communication with other devices or communication networks, such as an Ethernet, a radio access network (RAN), a wireless local area network (WLAN), and the like. For example, the communication interface 102 can be any one or any combination of the following devices: a network interface (such as an Ethernet interface), a wireless network card, and the like, which have network access functions.

[0060] The external memory 103 is used to store executable codes or data generated when executing an application program, etc. For example, the external memory 103 is used to store an operating system 108. The executable codes stored in the external memory 103 can be read into the memory and executed by the processor 101 to implement the functions corresponding to the executable codes. Similarly, the data stored in the external memory 103 can be read into the memory and accessed by the processor 101 to perform corresponding processing according to the data. The external memory 103 is, for example, a read-only memory or other type of static storage device that can store static information and instructions, a random access memory or other type of dynamic storage device that can store information and instructions, a electrically erasable programmable read-only memory, a read-only optical disc or other optical disc storage, an optical disc storage (including a compact disc, a laser disc, an optical disc, a digital versatile disc, a Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired executable codes in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. For example, the external memory 103 is used to store an egress port queue, etc. The external memory 103 is, for example, independently present and connected to the processor 101 through the bus 106. Alternatively, the external memory 103 and the processor 101 are integrated together. For example, the external memory 103 can include a volatile memory such as a random-access memory (RAM). The external memory 103 can also include a non-volatile memory such as a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD). Alternatively, the external memory 103 can further include a combination of the above-mentioned types of memories.

[0061] The memory 104 is used to temporarily store data and instructions required by the processor 101 during operation. For example, the memory 104 is used to store an operating system read from the external storage 103 into the memory 104 when the computing device is started, and data generated when an application is executed. Since the memory 104 has a faster read and write speed, the memory 104 is usually used as a data bridge between the external storage 103 and the processor 101. That is, during the operation of the computing device, the data required by the processor 101 can be read from the external storage 103 into the memory 104 in advance, so that the processor 101 reads the required data from the memory 104 to ensure the computing speed of the processor 101. The memory 104 of the present application can be various storage media capable of temporarily storing data required by the processor 101 during operation. The memory 104 is, for example, independently present and connected to the processor 101 through the bus 106. For example, the memory 104 is a dynamic random access memory (DRAM).

[0062] The cache medium 107 has a faster read and write speed than the memory 104, and the cache medium 107 is usually used as a data bridge between the memory 104 and the processor 101. That is, during the operation of the computing device, the data required by the processor 101 can be read from the memory 104 into the cache medium 107 in advance, so that the processor 101 reads the required data from the cache medium 107 to ensure the computing speed of the processor 101. The cache medium of the present application can be various storage media capable of caching data in the memory of the processor. The cache medium 107 and the processor 101 are integrated together. For example, the cache medium is a static random access memory (SRAM) or a magnetic random access memory (MRAM), and the cache medium in the present application can be a storage medium arranged in the processor and arranged outside the processor core. For example, when the SRAM is a three-level cache, the cache medium in the present application is the last level cache (LLC) of the SRAM, that is, the third level cache L3 cache. For another example, the cache medium includes a four-level cache, and when the third level cache and the fourth level cache are arranged outside the processor core, the cache medium in the present application is the third level cache and the fourth level cache.

[0063] The basic input and output system 105 is used to perform self-checking and initialization on various components in the computing device, and serves as a transmission medium between software programs and hardware to transmit information between software programs and hardware.

[0064] The bus 106 is any type of communication bus that interconnects the internal components of the computing device (e.g., the external memory 103, the processor 101, the communication interface 102). For example, the bus 106 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in FIG. 1, but this does not mean that there is only one bus or only one type of bus. In the embodiments of the present application, the above-mentioned components inside the computing device are interconnected by the bus 106. Alternatively, the above-mentioned components inside the computing device 10 can also be communicatively connected to each other by means other than the bus 106. For example, the above-mentioned components inside the computing device 10 are interconnected by internal logic interfaces.

[0065] It should be noted that the above-mentioned multiple components can be respectively arranged on chips independent of each other, or at least partially or entirely arranged on the same chip. Whether to arrange each component independently on different chips or to integrate them on one or more chips often depends on the needs of product design. The embodiments of the present application do not limit the specific implementation form of the above-mentioned components. Moreover, the descriptions of the corresponding processes of the above-mentioned figures each have their own emphasis, and the parts not described in detail in a certain process can be referred to the related description of other processes.

[0066] In the above-mentioned embodiments, the implementation can be entirely or partially realized by software, hardware, firmware, or any combination thereof. When realized by software, the implementation can be realized in the form of a computer program product entirely or partially. The computer program product providing a program development platform includes one or more computer instructions, which, when loaded and executed on a computing device, realize part or all of the functions of the computing task management method provided by the embodiments of the present application.

[0067] Moreover, the computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium stores computer program instructions providing a program development platform.

[0068] In an implementation manner, the computing task management method provided by the embodiments of the present application can be realized by running an executable program on a computing device. Alternatively, the executable program implementing the computing task management method can be presented in the form of an application installation package, and after a server installs the application installation package, the executable program therein can be run to implement the computing task management method provided by the embodiments of the present application.

[0069] As an example, the present application can be applied to the development and optimization of operators in an AI model to optimize the performance of the operators, support deterministic calculation, and save the on-core cache of the computing core. As an example, the present application can be applied to both inference and training products using AI models. Inference products using AI models are, for example, products such as robots, drones, autonomous vehicles, video surveillance, and education platforms. Training products using AI models are, for example, training servers or systems configured with a system-on-chip, multiple training cards, and / or multiple servers. At present, there are often very complex operators in AI models and a large amount of data needs to be processed. Moreover, in AI models, many operators perform floating-point calculations. Therefore, applying the present application to the development and optimization of operators in an AI model is beneficial to better memory reuse, simplifying complex data dependencies, and better supporting order-sensitive calculations in the AI model, thereby improving operator performance and reducing workspace memory overhead.

[0070] It should be understood that the above is an example of the implementation scenario of the management method of the computing task provided by the embodiments of the present application, and does not constitute a limitation on the implementation scenario of the management method of the computing task. Those skilled in the art can know that, as the business needs change, the implementation scenario can be adjusted according to the application needs, and the embodiments of the present application do not make specific limitations. Moreover, when the management method of the computing task provided by the embodiments of the present application is applied to other scenarios, the executable program of the method can also be presented in the form of an application installation package or in other ways, and the embodiments of the present application do not make one-by-one enumeration.

[0071] The implementation process of the management method of the computing task provided by the embodiments of the present application is described below. The computing task includes M computing stages. When executing the management method of the computing task, the computing device needs to execute the following steps 201 to 207 for each of the M computing stages. The implementation process of the management method of the computing task is described below by taking the computing device executing the following steps 201 to 207 for the i-th computing stage as an example. The i-th computing stage is any one of the M computing stages included in the computing task.

[0072] FIG. 2 is a flowchart of a management method of a computing task provided by an embodiment of the present application. As shown in FIG. 2, the management method of the computing task includes the following steps:

[0073] Step 201, the management component obtains the computing feature information of the i-th computing stage based on the computing sub-tasks that need to be implemented in the i-th computing stage. The computing feature information is used to indicate the features presented by the execution of the computing stage.

[0074] After obtaining the computing task, the management component can obtain the multiple computing stages included in the computing task according to the computing logic of the computing task, and obtain the computing subtasks required to be implemented by each computing stage. The computing subtasks required to be implemented by the computing stage are used to indicate one or more of the following: an operation type of a computation required to be performed by the computing stage, input data required for performing the computation, a computation result obtained by the computation, or a saving manner of the computation result. The operation type is used to indicate an algorithm or a computation expression used for performing the computation on the input data. The input data required for the computation is an object to which the computation core performs the computation. Here, the input data can be represented by an identifier of the input data or an acquisition address of the input data. The identifier of the input data is used to uniquely indicate the data. For example, the identifier of the input data is a name of the data. The acquisition address of the input data enables the computation core to read the unique data from the address. The present application does not make a specific limitation on the representation manner of the identifier of the input data and the representation manner of the acquisition address of the input data. The computation result obtained by the computation is an operation result of the computation required to be performed by the computing stage. The saving manner of the computation result includes a saving format of the computation result and / or a storage address of the computation result, etc. The saving format of the computation result is usually determined by the operation of the computation. For example, the saving format of the computation result of a matrix computation is determined by the computation manner of the matrix computation. Alternatively, the computing stage can also specify a specified manner for saving the computation result. For example, it is assumed that the computation result of the matrix computation is a matrix, but the computing stage specifies that the elements in the matrix are sequentially stored in a text format, and thus the saving format of the computation result is the text.

[0075] For example, it is assumed that the computing logic of the operator is represented by the following executable program, and the content after " / / " in each line of the program below is a comment on the current line of the program.

[0076] The management component can obtain two computing stages of the computing task implemented by the operator according to the executable program after obtaining the operator. One of the computing stages is an n loop represented by for(n) {......}, and the other computing stage is an m loop represented by for(m) {......}. The computing subtask required to be implemented by the n loop is A0.gm[m], B0.gm[n], A1.gm[m], B1.gm[n], A2.gm[m], B2.gm[n], A3.gm[m], and B3.gm[n] when n takes different values, and then the matrix calculation and vector calculation processes are correspondingly performed. The operation type of the computing required to be performed by the computing stage includes the matrix calculation and the vector calculation. The matrix calculation and the vector calculation are algorithms used for performing the computing. The input data required for the computing stage to perform the computing includes A0.gm[m], B0.gm[n], A1.gm[m], B1.gm[n], A2.gm[m], B2.gm[n], A3.gm[m], and B3.gm[n] when m takes different values. The input data is represented by the identification of the input data. The computing subtask required to be implemented by the m loop is A0.gm[m], B0.gm[n], A1.gm[m], B1.gm[n], A2.gm[m], B2.gm[n], A3.gm[m], and B3.gm[n] when m takes different values, and then the matrix calculation and vector calculation processes are correspondingly performed. The operation type of the computing required to be performed by the computing stage includes the matrix calculation and the vector calculation. The matrix calculation and the vector calculation are algorithms used for performing the computing. The input data required for the computing stage to perform the computing includes A0.gm[m], B0.gm[n], A1.gm[m], B1.gm[n], A2.gm[m], B2.gm[n], A3.gm[m], and B3.gm[n] when m takes different values. The input data is represented by the identification of the input data.

[0077] After the management component obtains the computing sub-tasks to be executed in the i-th computing stage, the management component can determine the computing characteristic information of the i-th computing stage based on the computing sub-tasks to be executed in the i-th computing stage. The computing characteristic information of the computing stage is used to indicate the characteristics that the computing core can present when executing the computing stage. For example, the computing characteristic information of the first computing stage indicates one or more of the following: the total amount of data that the first computing stage needs to transmit to the second computing stage, the total amount of data that the first computing stage multiplexes with the second computing stage, or the sensitivity of the first computing stage to the order of the second computing stage's computing results participating in the computation. The first computing stage is any one of the M computing stages, and the second computing stage is any one of the M computing stages except the first computing stage. For example, the management component can determine the data that the i-th computing stage needs to obtain and the amount of data, the data source of the data that the i-th computing stage needs to obtain, the amount of data obtained from different data sources, the data that the i-th computing stage needs to output and the amount of data, the order of the input data of the i-th computing stage participating in the computation, and the like according to the computing sub-tasks to be executed in the i-th computing stage. Based on this information, the management component can determine the computing characteristic information of the i-th computing stage. The sensitivity of the first computing stage to the order of the second computing stage's computing results participating in the computation refers to the degree to which the change in the order of the second computing stage's computing results participating in the computation affects the results of the first computing stage.

[0078] The data that the i-th computing stage needs to obtain is the input data required by the computing core to execute the computing operation of the i-th computing stage. The data that the i-th computing stage needs to obtain and the amount of data is the total amount of input data required by the computing core to execute the computing operation of the i-th computing stage. As described above, the computing sub-tasks to be implemented by the computing stage can indicate the input data required for the computation, and thus the data that the i-th computing stage needs to obtain can be obtained according to the indication of the computing sub-tasks. For example, when the input data indicated by the computing sub-tasks is represented by an identifier of the input data or an acquisition address of the input data, the data that the i-th computing stage needs to obtain can be determined according to the identifier or the acquisition address. The size of the data stored in the computing device is usually recorded in the computing device, and thus the total amount of data that the i-th computing stage needs to obtain can be obtained by querying the record of the size of the stored data in the computing device.

[0079] The data source of the data required by the i-th computing stage generally includes data stored in the computing device or the computing result output by other computing stages. After determining the data required by the i-th computing stage, whether the data is the computing result output by other computing stages can be queried according to the identifier of the data. If the data is the computing result output by other computing stages, the data is derived from the computing result of other computing stages. If the data is not the computing result output by other computing stages, the data is derived from the storage medium of the computing device. The data stored in the computing device can be selected as the data stored in the global memory of the computing device. After determining the source of the data, the data amount of the data obtained from different data sources can be obtained according to the size of each data. For example, the data amount of the data obtained from a certain data source can be equal to the sum of the sizes of all data obtained from the data source.

[0080] The data output by the i-th computing stage is the computing result of the computing operation of the i-th computing stage. The data amount of the data required to be output by the i-th computing stage is the data amount of the computing result of the computing operation of the i-th computing stage. The data amount of the computing result of the i-th computing stage can be determined according to the operation type of the computation performed by the i-th computing stage and the total data amount of the input data to which the computing operation is performed. The operation type determines the data amount of the computing result of the computing operation performed on a single input data. For example, because the computing principles of matrix computation and vector computation are different, the data amount of the computing result of the computing operation performed on a single input data when the type of the computing operation is matrix computation is generally different from the data amount of the computing result of the computing operation performed on a single input data when the type of the computing operation is vector computation. After determining the data amount of the computing result of the computing operation performed on a single input data, because the computing core needs to perform the computing operation on each input data when performing the computing operation of the i-th computing stage, the data amount of the data output by the i-th computing stage can be equal to the product of the data amount of the computing result of the computing operation performed on a single input data and the total number of the input data to which the computing operation is performed.

[0081] The order in which the input data of the i-th computing stage participates in the computation refers to the order in which the input data participates in the computation in the computing process of the i-th computing stage. For example, assuming that the computing operation of the computing stage is d1=a×b×c, the order in which the input data a participates in the computation in the computing process is 1, the order in which the input data b participates in the computation in the computing process is 2, and the order in which the input data c participates in the computation in the computing process is 3. For another example, assuming that the computing operation of the computing stage is d2=a×(b×c), the order in which the input data a participates in the computation in the computing process is 3, the order in which the input data b participates in the computation in the computing process is 1, and the order in which the input data c participates in the computation in the computing process is 2.

[0082] When the content indicated by the calculation characteristic information of the calculation stage is different, the implementation manner of determining the calculation characteristic information is different. The following three examples are taken as examples to illustrate the implementation manner of determining the calculation characteristic information.

[0083] In the first implementation manner, in response to the calculation characteristic information of the first calculation stage indicating that the total amount of data required by the first calculation stage to transmit to the second calculation stage. As shown in FIG. 3, the management component obtains the calculation characteristic information of the i-th calculation stage based on the calculation sub-tasks required by the i-th calculation stage to be implemented, including:

[0084] Step 201a1, based on the calculation sub-tasks required by the first calculation stage and the second calculation stage to be implemented, determining the target calculation result output by the first calculation stage in the data required to execute the second calculation stage.

[0085] The data required by the first calculation stage to transmit to the second calculation stage is the calculation result output by the first calculation stage in the input data of the second calculation stage. Therefore, when determining the total amount of data required by the first calculation stage to transmit to the second calculation stage, the management component needs to first determine the target calculation result output by the first calculation stage in the data required to execute the second calculation stage. According to the foregoing description, the management component can determine the data source of the data required by the i-th calculation stage to be obtained according to the calculation sub-tasks required by the i-th calculation stage to be executed, and can determine the target calculation result output by the first calculation stage in the data required to execute the second calculation stage according to the data source. For example, the calculation operation of the second calculation stage is d1=a×b×c, and by querying the input data a, it can be obtained that the input data b and c are all calculation results output by the first calculation stage, and the input data b and c are all from the storage medium of the computing device. Therefore, the target calculation result output by the first calculation stage in the data required to execute the second calculation stage is a.

[0086] Step 201a2, obtaining the total amount of data required by the first calculation stage to transmit to the second calculation stage based on the size of the target calculation result.

[0087] After the management component obtains the target calculation result output by the first calculation stage in the data required to execute the second calculation stage, the total amount of data required by the first calculation stage to transmit to the second calculation stage can be obtained according to the size of the target calculation result. For example, the total amount of data required by the first calculation stage to transmit to the second calculation stage is equal to the sum of the sizes of all target calculation results output by the first calculation stage in the data required to execute the second calculation stage.

[0088] In the second implementation, in response to the calculation characteristic information of the first calculation stage indicating that the total amount of data of the data reused by the first calculation stage and the second calculation stage, the management component obtains the calculation characteristic information of the ith calculation stage based on the calculation subtask to be implemented by the ith calculation stage, including:

[0089] In step 201b1, based on the calculation subtasks performed by the first calculation stage and the second calculation stage, the target input data required by both the execution of the first calculation stage and the execution of the second calculation stage, and the target calculation result output by the first calculation stage and required by the second calculation stage are determined.

[0090] The data reused by the first calculation stage and the second calculation stage includes two parts of data. One part of the data is the input data required by both the first calculation stage and the second calculation stage, which is the target input data required by both the execution of the first calculation stage and the execution of the second calculation stage. The other part of the data is the calculation result output by the first calculation stage and required by the second calculation stage, which is the target calculation result determined by the first calculation stage in the data required by the second calculation stage. According to the foregoing description, the management component can determine the data source of the data required by the ith calculation stage according to the calculation subtask to be performed by the ith calculation stage, and can determine the target data and the target calculation result according to the data source. For example, according to the calculation subtask to be performed by the first calculation stage, the data required by the first calculation stage and the calculation result output by the first calculation stage are obtained. According to the calculation subtask to be performed by the second calculation stage, the data required by the second calculation stage is obtained. Then, the management component determines the target input data required by the first calculation stage in the input data of the second calculation stage, and determines the target calculation result output by the first calculation stage.

[0091] In step 201b2, based on the size of the target input data and the size of the target calculation result, the total amount of data of the data reused by the first calculation stage and the second calculation stage is determined.

[0092] After the management component determines the target input data required by both the execution of the first calculation stage and the execution of the second calculation stage, and the target calculation result output by the first calculation stage and required by the second calculation stage, the total amount of data of the data reused by the first calculation stage and the second calculation stage can be obtained according to the size of the target input data and the size of the target calculation result. For example, the total amount of data of the data reused by the first calculation stage and the second calculation stage is equal to the sum of the size of the target input data and the size of the target calculation result.

[0093] In the third implementation, in response to the computing feature information of the first computing stage indicating that the first computing stage is sensitive to the order in which the computing result of the second computing stage participates in the computation, the management component obtains the computing feature information of the i th computing stage based on the computing sub-tasks that need to be implemented by the i th computing stage, including:

[0094] Step 201c1, based on the computing sub-tasks executed by the first computing stage, respectively determine the influence degree of the computing result of the second computing stage participating in the computation process of the first computing stage in different orders.

[0095] When the management component obtains the sensitivity of the first computing stage to the order in which the computing result of the second computing stage participates in the computation, it can first determine the influence degree of the computing result of the second computing stage participating in the computation process of the first computing stage in different orders, and then obtain the sensitivity of the first computing stage to the order in which the computing result of the second computing stage participates in the computation according to the influence degree. In a possible implementation, the management component can obtain the computing result of the first computing stage when the computing result of the second computing stage participates in the computation process of the first computing stage in different orders, and then obtain the influence degree of the computing result of the second computing stage participating in the computation process of the first computing stage in different orders according to the computing result. In this process, the correct order of the computing result of the second computing stage participating in the computation can be obtained according to the computing sub-tasks executed by the first stage, and the computing result of the second computing stage can be made to participate in the computation in the correct order to obtain the computing result of the first computing stage. Then, adjust the order in which the computing result of the second computing stage participates in the computation, and obtain the computing result of the first computing stage after the adjustment. Then, according to the computing result obtained by participating in the computation in the correct order and the computing result obtained after the adjustment, the influence degree of the computing result of the second computing stage participating in the computation process of the first computing stage in different orders is obtained. In a possible implementation, the influence degree is equal to the ratio of the difference between the computing result obtained after the adjustment and the computing result obtained by participating in the computation in the correct order in the computing result obtained by participating in the computation in the correct order. For example, assuming that the computing operation of the first computing stage is d1=a×b×c, the computing result of the second computing stage is a, the computing result obtained by participating in the computation in the correct order is d10, the computing operation after the adjustment is d1=a×(b×c), and the computing result obtained after the adjustment is d11, then the influence degree is equal to (d11-d10) / d10.

[0096] Step 201c2, based on the influence degree, determine the sensitivity of the first computing stage to the order in which the computing result of the second computing stage participates in the computation.

[0097] The management component obtains the influence degree of the calculation result of the second calculation stage on the calculation result of the first calculation stage when the calculation result of the second calculation stage participates in the calculation process of the first calculation stage in different orders, and then obtains the sensitivity degree of the first calculation stage to the order of the calculation result of the second calculation stage participating in the calculation according to the influence degree. For example, the sensitivity degree of the first calculation stage to the order of the calculation result of the second calculation stage participating in the calculation is equal to the influence degree.

[0098] If the calculation result of the second calculation stage participating in the calculation after the order adjustment is inconsistent with the calculation result before the adjustment, it indicates that the influence degree of the order of the data participating in the calculation on the calculation result of the first calculation stage is greater, and the sensitivity degree of the first calculation stage to the order of the calculation result of the second calculation stage participating in the calculation is greater. If the calculation result of the second calculation stage participating in the calculation after the order adjustment is consistent with the calculation result before the adjustment, it indicates that the influence degree of the order of the data participating in the calculation on the calculation result of the first calculation stage is smaller, and the sensitivity degree of the first calculation stage to the order of the calculation result of the second calculation stage participating in the calculation is smaller, or is not sensitive.

[0099] In step 202, the management component determines the jth calculation core for executing the ith calculation stage based on the calculation characteristic information of the ith calculation stage in the N calculation cores, wherein there are at least two calculation stages in the M calculation stages, the at least two calculation stages need to be executed by different calculation cores, and the jth calculation core is one of the N calculation cores.

[0100] After the management component obtains the computation characteristic information of the i-th computation stage, the management component can determine the j-th computation core for executing the i-th computation stage among the N computation cores based on the computation characteristic information. In a possible implementation, the determination principle is mainly as follows: computation stages with the same or similar characteristics are scheduled to use the same computation core to perform computation, and computation stages with different or greatly different characteristics are scheduled to use different computation cores to perform computation. For example, it is assumed that the computation characteristic information of the first computation stage indicates one or more of the following: the total amount of data that needs to be transmitted from the first computation stage to the second computation stage, the total amount of data that is multiplexed between the first computation stage and the second computation stage, or the sensitivity of the first computation stage to the order in which the computation result of the second computation stage participates in computation. Any two computation stages executed by different computation cores satisfy one or more of the following conditions: the total amount of data transmitted between the two computation stages is less than a first quantity threshold, the total amount of data multiplexed between the two computation stages is less than a second quantity threshold, or the sensitivity of one of the two computation stages to the order in which the computation result of the other of the two computation stages participates in computation is greater than a degree threshold. The values of the first quantity threshold, the second quantity threshold, and the degree threshold can be set according to application requirements, and embodiments of this application do not make specific limitations thereto.

[0101] When the total amount of data that needs to be transmitted from the first computation stage to the second computation stage is less than the first quantity threshold, if the first computation stage and the second computation stage are scheduled to different computation cores for execution, the total amount of data that needs to be provided by the computation core for executing the first computation stage to the computation core for executing the second computation stage is less than the first quantity threshold. Since the data transmitted from the computation core a to the computation core b needs to be first stored in the global memory by the computation core a, and then read from the global memory by the computation core b, when the total amount of data that needs to be provided by the computation core for executing the first computation stage to the computation core for executing the second computation stage is less than the first quantity threshold, it is equivalent to reducing the amount of data written to the global memory by the computation core for executing the first computation stage, and simultaneously reducing the amount of data read from the global memory by the computation core for executing the second computation stage, thereby reducing the memory access performance in the operator execution process.

[0102] When the total amount of data reused by the first and second computing stages is less than the second quantity threshold, if the first and second computing stages are scheduled to be executed by different computing cores, the total amount of data reused by the computing stages executed by the same computing core will be greater than the second quantity threshold. At this time, in the case that the in-core cache of the computing core has a specified capacity, the greater the amount of data reused by the computing stages specified by the same computing core, on the one hand, the reuse rate of the in-core cache can be improved, and on the other hand, the writing and reading out of data used by the computing stages between the in-core cache and the global memory can be reduced, thereby improving the memory access performance in the operator execution process.

[0103] When the sensitivity of the first computing stage to the order of the calculation result of the second computing stage is greater than the degree threshold, the first computing stage may be different when the first computing stage is calculated with respect to the calculation result of the second computing stage first and with respect to the calculation result of the second computing stage later, thereby affecting the reliability of the operator. If the first and second computing stages are scheduled to be executed by different computing cores, the order in which the first computing stage calculates the calculation result of the second computing stage can be controlled, and it is ensured that the calculation result of the first computing stage with respect to the calculation result of the second computing stage is consistent in multiple calculation processes, thereby improving the reliability of the operator.

[0104] Step 203, the management component sends control information and executable code of the computing task to the jth computing core, wherein the control information sent by the management component to the jth computing core is used to instruct the jth computing core to execute the ith computing stage.

[0105] After the management component determines the jth computing core for executing the ith computing stage in the N computing cores, the management component can send control information and executable code of the computing task to the jth computing core to execute the ith computing stage by using the jth computing core. When the computing task includes M computing stages that need to be executed by multiple computing cores, the management component sends executable code of the computing task to the multiple computing cores, that is, the executable code sent by the management component to the multiple computing cores is the same. However, the control information sent by the management component to different computing cores is different, and the control information sent by the management component to any computing core is used to instruct the computing core to execute the computing stage.

[0106] Step 204, the jth computing core executes the ith computing stage based on the control information and the executable code of the computing task.

[0107] After the jth computing core receives the control information and the executable code of the computing task sent by the management component, the jth computing core can determine that the jth computing core needs to execute the ith computing stage based on the control information, and then determine the executable code of the ith computing stage based on the executable code of the computing task, and then execute the ith computing stage by running the executable code of the ith computing stage.

[0108] Optionally, the same computing stage can also be executed by multiple computing cores. In a possible implementation, as shown in FIG. 6, before step 202 is executed, the method for managing a computing task provided in the present application further includes:

[0109] Step 205: The management component divides the input data of the i-th computing stage into P groups of input data, P being a positive integer smaller than N.

[0110] The management component can divide the input data of the i-th computing stage into P groups of input data. For example, the management component divides the input data of the i-th computing stage into multiple equal parts.

[0111] Correspondingly, as shown in FIG. 6, the implementation process of step 202 includes: step 2021, the management component determines, based on the computing characteristic information of the i-th computing stage, P computing cores for executing the i-th computing stage from the N computing cores, the P computing cores corresponding to the P groups of input data.

[0112] The implementation process of this step 2021 can be referred to the relevant description in the previous step 202, but since P computing cores for executing the i-th computing stage need to be determined, when determining that the k-th computing core in the P computing cores needs to use the input data of the computing stage for computation, the k-th group of input data corresponding to the k-th computing core in the P groups of input data is used.

[0113] Correspondingly, as shown in FIG. 6, before the j-th computing core executes step 204, the method for managing a computing task provided in the present application further includes:

[0114] Step 206: The management component sends, to each computing core in the P computing cores, indication information of the group of input data corresponding to the computing core.

[0115] After the management component determines, from the N computing cores, the P computing cores for executing the i-th computing stage, the management component also needs to send, to each computing core in the P computing cores, indication information of the group of input data corresponding to the computing core, so as to indicate to each computing core in the P computing cores the input data needed for executing the i-th computing stage.

[0116] Correspondingly, as shown in FIG. 6, the implementation process of step 204 includes: step 2041, the j-th computing core executes the i-th computing stage based on the control information, the indication information and the executable code of the computing task.

[0117] After the jth computing core receives the control information, the indication information and the executable code of the computing task sent by the management component, the jth computing core can determine that the jth computing core needs to execute the ith computing stage based on the control information, determine the input data that needs to be obtained for executing the ith computing stage based on the indication information, and then determine the executable code of the ith computing stage based on the executable code of the computing task, and then execute the ith computing stage by running the executable code of the ith computing stage. For example, the management component divides the input data of the ith computing stage into P parts, and then uses P computing cores to execute the ith computing stage for the P input data in a one-to-one manner. That is, each computing core in the P computing cores executes the ith computing stage based on one input data.

[0118] In addition, when the jth computing core executes a computing operation based on a plurality of computing results obtained by a plurality of other computing cores executing a computing stage, the other computing core is one of the N computing cores except the jth computing core, and before the jth computing core executes the ith computing stage based on the control information and the executable code of the computing task, the management method of the computing task provided by the present application further comprises: step 207, the management component sends configuration information to the jth computing core, and the configuration information is used to indicate the order of participating in the computation of the plurality of computing results. Correspondingly, the implementation process of step 204 comprises: step 2042, the jth computing core executes the ith computing stage based on the control information, the configuration information and the executable code of the computing task.

[0119] The order indicated by the configuration information is an order determined according to the computing logic of the computing task. By sending the configuration information to the jth computing core through the management component, the jth computing core can execute the ith computing stage for the plurality of computing results obtained by the plurality of other computing cores executing the computing stage according to the configured execution order. In this way, the order of the plurality of computing results obtained by the plurality of other computing cores executing the computing stage participating in the ith computing stage can be controlled to the configured execution order, and the reliability of the computing task is ensured by ensuring that the computing process is executed according to the execution order in multiple executions of the computing task.

[0120] The management method of the computing task provided by the present application is further described below by taking three examples.

[0121] In Example 1, for the executable program in step 201, each loop process of the n loops is a plurality of calculation stages including CCVCCCV. C represents a matrix calculation, and V represents a vector calculation. In the plurality of calculation stages, since the left and right matrices of each matrix calculation are different, after completing each matrix multiplication (MM) calculation, the in-core cache of the calculation core used to perform the calculation process also needs to be used by the next matrix multiplication. For example, after completing mm0, the in-core cache originally used by mm0 also needs to be used by mm1. This will cause the left and right matrices used by the matrix multiplication calculation to be read from the global memory each time the matrix multiplication calculation is performed. However, since the access speed of the global memory is usually slow, a relatively large memory access overhead will be caused.

[0122] Therefore, the management method of the calculation task provided in the present application is used to schedule the calculation stages of the operator, and seven calculation cores are used to perform the operator, and the seven calculation cores perform one calculation stage in the plurality of calculation stages of CCVCCCV. In this way, the executable program in step 201 can be represented by the following executable program, and the annotations of each line of the executable program correspond to the annotations in step 201.

[0123] The reason for this scheduling is that the total amount of data of the data reused between each two stages in the plurality of calculation stages is relatively small, and therefore seven calculation cores are used to perform the seven calculation stages of the operator. In this way, for the matrix calculation in the operator, each matrix calculation can be performed by one calculation core. When each calculation core performs one matrix calculation, the reading process of the left matrix used by the matrix calculation can be lifted to the outer loop, and the memory access overhead of the global memory of the left matrix can be saved by n times, thereby improving the memory access performance. Moreover, since the reading process of the left matrix used by the matrix calculation can be lifted to the outer loop, the left matrix can be reused in the calculation process, and the reuse rate of the in-core cache of the calculation core can be improved.

[0124] In Example 2, it is assumed that the calculation logic of the operator is as shown in FIG. 7. In FIG. 7, read / write gm is a memory access operation between the global memory and the in-core cache. copy is an operation of copying data from the in-core cache. write buffer is an operation of writing data to the in-core cache. V represents a vector calculation. MM represents a matrix calculation. According to FIG. 7, it can be seen that the entire calculation process of the operator has 6-stage data-dependent calculations of VCVVCV.

[0125] If the operator is executed according to the operator execution manner in the related art, the input data of the operator when performing the calculation task is equally divided into N parts, and N calculation cores are used to perform the operator based on the N input data respectively, and the calculation process of each calculation core is completely consistent. For example, for a hardware accelerator with 20 calculation cores, the calculation behavior of each calculation core is the same when processing. For example, for the operator in FIG. 7, each calculation core performs the calculation of 6 stages of VCVVCV. However, this will cause high complexity of the calculation flow arrangement and the allocation of the in-core cache.

[0126] In view of this, since the calculation result of V0.1 needs to be transmitted to MM1 through the global memory, and the total amount of data of the calculation result is less than the first quantity threshold, the present application schedules based on the execution stage of the operator, and uses one calculation core to execute the calculation stages including V0.0, MM0 and V0.1. The calculation logic of the calculation stages executed by the calculation core is shown in FIG. 8. Another calculation core is used to execute the calculation stages including V1.0, MM1 and V1.1. The calculation logic of the calculation stages executed by the calculation core is shown in FIG. 9. Through such scheduling, each calculation core executes only 3 stages of data dependency, that is, the degree of data dependency of the calculation is reduced, and in turn the difficulty of the calculation flow arrangement and the allocation of the in-core cache is reduced.

[0127] Example three, assuming that the calculation logic of the operator is shown in FIG. 10. The operator is composed of four calculation stages of stage0, stage1, stage2 and stage3, and stage3 is a calculation operation of the reduce type. For example, the calculation logic of stage3 is a+x (i.e. a=a+x). And the input data participating in the calculation of stage3 are all floating point data. Since the floating point data is expressed approximately in the computer, it is sensitive to the calculation order. For example, the calculation result of a+b+c may not be equal to the calculation result of a+c+b.

[0128] If the operator is executed according to the operator execution manner in the related art, the input data of the operator when performing the calculation task is divided into four parts, and four calculation cores are used to perform the operator based on the four parts of input data, and the calculation process of each calculation core is completely consistent. For example, the execution of the operator is as shown in FIG. 11, and each calculation core performs the calculation process of stage0-stage1-stage2-stage3. However, in a system with multiple calculation cores, the execution order of multiple calculation cores is usually uncertain, which leads to the fact that the calculation results of the operator executed multiple times may not be consistent. However, in scientific research and engineering practice, the operator is required to produce completely consistent results when the same data and parameters are input each time, so that the calculation process has high reliability. In order to solve the problem of reliability, although the entire calculation process of stage0-stage1-stage2-stage3 can be executed using only a single calculation core. However, this will result in the computing power of the calculation core being only one-nth, which seriously affects the performance of the operator. Or, the calculation results of each calculation core are written to independent spaces, and after all the calculation cores are processed, an accumulation operation is completed by a certain calculation core. However, this scheme will cause the operator workspace to expand sharply, and seriously consume memory resources.

[0129] Therefore, since the input data participating in the calculation of stage3 is all floating-point data, the sensitivity of the order of the calculation results participating in the calculation is relatively high, and the execution stage of the operator is scheduled based on this, and four calculation cores are used to execute the operator. The first to third calculation cores are used to execute the calculation stages including stage0-stage1-stage2, and the fourth calculation core is used to execute the calculation stage including stage3. And the first to third calculation cores perform calculation operations based on one-third of the input data. The execution of the scheduled operator is as shown in FIG. 12.

[0130] Through such scheduling, the calculation operation of stage3 will be completed in one calculation core, and the calculation core can consume the calculation results of the first to third calculation cores in order when executing stage3. In this way, the order of the calculation results of the first to third calculation cores participating in the calculation is fixed, ensuring the determinacy of the calculation, while taking into account the performance and the usage rate of memory resources.

[0131] In summary, the application is equivalent to dividing the execution process of the computing task in the dimension of the computing core based on the computing sub-tasks required to be executed in each computing stage, and dividing the plurality of computing stages of the computing task to the plurality of computing cores for execution respectively. In this way, it is not necessary to use the same computing core to execute all the computing stages of the computing task, the amount of computation executed by a single computing core is reduced, and the total amount of data required to be read from the global memory during the execution of the computing stage by a single computing core is reduced, which helps to improve the memory access performance during the execution of the operator. At the same time, since the application reduces the total amount of data required to be read from the global memory during the execution of the computing stage by a single computing core, the occupancy capacity of the on-core cache of the single computing core is reduced, which can be used to store the data that can be reused during the computing process, and the reuse rate of the on-core cache can be improved. Moreover, by dividing the plurality of computing stages of the computing task to the plurality of computing cores for execution respectively, the amount of computation executed by a single computing core is reduced, which helps to reduce the complexity of the pipelining of the memory access process and the computing process by a single computing core. In addition, by dividing the plurality of computing stages of the computing task to the plurality of computing cores for execution respectively, the computing stage executed later can wait for all the computing results of the computing stage executed earlier by other computing cores, and then execute the computing based on the computing results in the specified order, so that the computing in the computing stage executed later is performed in the specified order each time, which helps to ensure the consistency of the computing results and improve the reliability of the computing, and better support the sequential sensitive computing.

[0132] It should be noted that the order of the steps of the management method of the computing task provided by the embodiments of the application can be adjusted appropriately, and the steps can be increased or decreased as appropriate. Any person skilled in the art can easily think of changes within the scope of the technology disclosed by the application, which should be covered within the protection scope of the application, and therefore will not be described again.

[0133] The above describes the management method of the computing task of the embodiments of the application. Corresponding to the above method, the embodiments of the application also provide a computing device. FIG. 1 is a structural schematic diagram of a computing device provided by an embodiment of the application. Based on the following plurality of components shown in FIG. 1, the computing device shown in FIG. 1 can perform all or part of the operations shown in FIG. 2 or FIG. 6. It should be understood that the computing device can include more additional components than the shown components or omit part of the shown components, and the embodiments of the application do not limit this.

[0134] The computing device has a management component and N computing cores. The computing task includes M computing stages. M and N are both positive integers. The computing device is configured to perform the following operations for the i-th computing stage in the M computing stages. The i-th computing stage is any one of the M computing stages.

[0135] The management component is configured to obtain the computation characteristic information of the i-th computation stage based on a computation subtask to be implemented by the i-th computation stage, and the computation characteristic information is configured to indicate a characteristic presented by the i-th computation stage.

[0136] The management component is further configured to determine the j-th computation core for executing the i-th computation stage from the N computation cores based on the computation characteristic information of the i-th computation stage, wherein there are at least two computation stages in the M computation stages, the at least two computation stages need to be executed by different computation cores, and the j-th computation core is one of the N computation cores.

[0137] The management component is further configured to send control information and executable code of the computation task to the j-th computation core, wherein the control information sent by the management component to the j-th computation core is configured to instruct the j-th computation core to execute the i-th computation stage.

[0138] The j-th computation core is configured to execute the i-th computation stage based on the control information and the executable code of the computation task.

[0139] In a possible implementation, the computation characteristic information of the first computation stage indicates one or more of the following: a total amount of data required by the first computation stage to transmit to a second computation stage, a total amount of data multiplexed between the first computation stage and the second computation stage, or a sensitivity of an order in which a result of the second computation stage participates in computation of the first computation stage, the first computation stage being any one of the M computation stages, and the second computation stage being a computation stage other than the first computation stage in the M computation stages.

[0140] In a possible implementation, any two computation stages executed by different computation cores satisfy one or more of the following conditions: a total amount of data transmitted between the any two computation stages is less than a first quantity threshold, a total amount of data multiplexed between the any two computation stages is less than a second quantity threshold, or a sensitivity of an order in which a result of one of the any two computation stages participates in computation of the other of the any two computation stages is greater than a degree threshold.

[0141] In a possible implementation, in response to the computation characteristic information of the first computation stage indicating that a total amount of data required by the first computation stage to transmit to a second computation stage, the management component is specifically configured to: determine a target computation result output by the first computation stage from data required for executing the second computation stage based on computation subtasks to be implemented by the first computation stage and the second computation stage; and obtain the total amount of data required by the first computation stage to transmit to the second computation stage based on a size of the target computation result.

[0142] In a possible implementation, in response to the computing feature information of the first computing stage indicating that the first computing stage shares data with the second computing stage, the management component is specifically configured to: determine, based on the computing subtask executed by the first computing stage, target input data required by both the execution of the first computing stage and the execution of the second computing stage, and target computing result output by the first computing stage from the data required by the execution of the second computing stage; and determine, based on the size of the target input data and the size of the target computing result, the total amount of data shared by the first computing stage and the second computing stage.

[0143] In a possible implementation, in response to the computing feature information of the first computing stage indicating that the first computing stage is sensitive to the order in which the computing result of the second computing stage participates in the computation, the management component is specifically configured to: determine, based on the computing subtask executed by the first computing stage, the influence degree of the computing result of the second computing stage on the computing result of the first computing stage when the computing result of the second computing stage participates in the computation of the first computing stage in different orders; and determine, based on the influence degree, the sensitivity of the first computing stage to the order in which the computing result of the second computing stage participates in the computation.

[0144] In a possible implementation, the management component is further configured to divide the input data of the i th computing stage into P groups of input data, where P is a positive integer smaller than N. The management component is specifically configured to determine, based on the computing feature information of the i th computing stage, P computing cores from the N computing cores for executing the i th computing stage, where the P computing cores correspond to the P groups of input data. Correspondingly, the management component is further configured to send, to each of the P computing cores, indication information of the group of input data corresponding to the computing core. Correspondingly, the j th computing core is specifically configured to execute the i th computing stage based on the control information, the indication information, and the executable code of the computing task.

[0145] In a possible implementation, in response to the j th computing core performing a computing operation based on a plurality of computing results obtained by a plurality of other computing cores, the other computing core is one of the N computing cores except the j th computing core. The management component is further configured to send, to the j th computing core, configuration information indicating the order in which the plurality of computing results participate in the computation. Correspondingly, the j th computing core is specifically configured to execute the i th computing stage based on the control information, the configuration information, and the executable code of the computing task.

[0146] Embodiments of the present application also provide a computer program product containing instructions. The computer program product can be a software or program product containing instructions, which can run on a computing device or be stored in any available medium. When the computer program product runs on at least one computing device, the at least one computing device is caused to perform the management method of the computing task.

[0147] The embodiments of the present application also provide a computer readable storage medium. The computer readable storage medium can be any available medium or data storage device that can be accessed by a computing device and include one or more available media or data storage devices including a computer readable medium. The available medium can be a magnetic medium, (e.g., a floppy diskette, a hard disk drive, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state hard drive) or the like. The computer readable storage medium includes instructions that instruct the computing device to perform the management method of the computing task, or instruct the computing device to perform the management method of the computing task.

[0148] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by programs instructing relevant hardware to complete, and the programs can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0149] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals involved in the present application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions. For example, the raw data and executable codes involved in the present application are obtained under sufficient authorization.

[0150] In the embodiments of the present application, the terms "first", "second" and "third" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise explicitly limited.

[0151] In the present application, the term "and / or" is only used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are in an "or" relationship.

[0152] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the protection scope of the technical solutions of the embodiments of the present application.

Claims

1. A management method of a computing task, characterized by, The method is applied to a computing device having a management component and N computing cores, the computing task includes M computing stages, M and N are positive integers, the method includes: for the i-th computing stage in the M computing stages, the following operations are performed, the i-th computing stage is any one of the M computing stages; The management component obtains the computing characteristic information of the i-th computing stage based on the computing sub-tasks to be implemented by the i-th computing stage, and the computing characteristic information is used to indicate the characteristics presented by executing the computing stage; The management component determines the j-th computing core for executing the i-th computing stage among the N computing cores based on the computing characteristic information of the i-th computing stage, wherein there are at least two computing stages in the M computing stages that need to be executed by different computing cores, and the j-th computing core is one of the N computing cores; The management component sends control information and executable code of the computing task to the j-th computing core, wherein the control information sent by the management component to the j-th computing core is used to instruct the j-th computing core to execute the i-th computing stage; The j-th computing core executes the i-th computing stage based on the control information and the executable code of the computing task.

2. The method of claim 1, wherein The computing characteristic information of the first computing stage indicates one or more of: a total amount of data required by the first computing stage to transmit to a second computing stage, a total amount of data of data multiplexed by the first computing stage and the second computing stage, or a sensitivity of the first computing stage to an order in which a result of the second computing stage participates in a computation, the first computing stage being any one of the M computing stages, and the second computing stage being a computing stage other than the first computing stage among the M computing stages.

3. The method of claim 2, wherein Any two computing stages executed by different computing cores satisfy one or more of the following conditions: a total amount of data transmitted between the any two computing stages is less than a first quantity threshold, a total amount of data multiplexed between the any two computing stages is less than a second quantity threshold, or a sensitivity of one of the any two computing stages to an order in which a result of the other of the any two computing stages participates in a computation is greater than a degree threshold.

4. The method of claim 2 or 3, wherein, In response to the computing characteristic information of the first computing stage indicating that a total amount of data required by the first computing stage to transmit to a second computing stage, the management component obtains the computing characteristic information of the i-th computing stage based on the computing sub-tasks to be implemented by the i-th computing stage, comprising: Based on the computing sub-tasks to be implemented by the first computing stage and the second computing stage, determining a target computing result output by the first computing stage among data required to execute the second computing stage; based on the size of the target input data and the size of the target calculation result, determine a data total amount of data multiplexed by the first calculation stage and the second calculation stage.

5. The method of any one of claims 2 to 4, wherein, In response to the calculation characteristic information of the first calculation stage indicating that the first calculation stage is sensitive to the order in which the calculation result of the second calculation stage participates in the calculation, the management component, based on the calculation subtask that the ith calculation stage needs to implement, acquires the calculation characteristic information of the ith calculation stage, including: based on the calculation subtask executed by the first calculation stage, respectively determine the influence degree of the calculation result of the second calculation stage participating in the calculation process of the first calculation stage in different orders; based on the influence degree, determine the sensitivity of the first calculation stage to the order in which the calculation result of the second calculation stage participates in the calculation.

6. The method of any one of claims 2 to 5, wherein, The method further comprises: The management component divides the input data of the ith calculation stage into P groups of input data, where P is a positive integer less than N; The management component determines a jth calculation core for executing the ith calculation stage among the N calculation cores based on the calculation characteristic information of the ith calculation stage, including:

7. The method of any one of claims 1 to 6, wherein, The management component determines P calculation cores for executing the ith calculation stage among the N calculation cores based on the calculation characteristic information of the ith calculation stage, where the P calculation cores correspond to the P groups of input data. The method further comprises: The management component sends indication information of the input data corresponding to each of the P calculation cores to each of the P calculation cores; The jth calculation core executes the ith calculation stage based on the control information and the executable code of the calculation task, including:

8. The method of claim 7, wherein, The jth calculation core executes the ith calculation stage based on the control information, the indication information, and the executable code of the calculation task. In response to the jth calculation core performing a calculation operation based on a plurality of calculation results obtained by a plurality of other calculation cores, the other calculation cores being one of the N calculation cores other than the jth calculation core, before the jth calculation core executes the ith calculation stage based on the control information and the executable code of the calculation task, the method further comprises: ​ ​ 9. The method of any one of claims 1 to 8, wherein, ​ The management component sends configuration information to the jth computing core, where the configuration information is used to indicate an order in which the plurality of computing results participate in computation. The jth computing core executes the ith computing stage based on the control information and the executable code of the computing task. The jth computing core executes the ith computing stage based on the control information, the configuration information and the executable code of the computing task.

10. A computing device, comprising: The computing device has a management component and N computing cores, the computing task includes M computing stages, M and N are positive integers, and the computing device is configured to perform the following operations for an ith computing stage in the M computing stages, where the ith computing stage is any one of the M computing stages. The management component is configured to obtain computing feature information of the ith computing stage based on a computing subtask that needs to be implemented by the ith computing stage, where the computing feature information is used to indicate a feature presented by execution of the computing stage. The management component is further configured to determine a jth computing core for executing the ith computing stage from the N computing cores based on the computing feature information of the ith computing stage, where there are at least two computing stages in the M computing stages that need to be executed by different computing cores, and the jth computing core is one of the N computing cores. The management component is further configured to send control information and executable code of the computing task to the jth computing core, where the control information sent by the management component to the jth computing core is used to instruct the jth computing core to execute the ith computing stage. The jth computing core is configured to execute the ith computing stage based on the control information and the executable code of the computing task.

11. The computing device of claim 10, wherein The computing feature information of the first computing stage indicates one or more of: a total amount of data that needs to be transmitted by the first computing stage to a second computing stage, a total amount of data that is multiplexed by the first computing stage and the second computing stage, or a sensitivity of the first computing stage to an order in which a result of the second computing stage participates in computation, where the first computing stage is any one of the M computing stages, and the second computing stage is a computing stage other than the first computing stage in the M computing stages.

12. The computing device of claim 10 or 11, wherein Any two computing stages executed by different computing cores satisfy one or more of the following conditions: a total amount of data transmitted between the any two computing stages is less than a first quantity threshold, a total amount of data multiplexed between the any two computing stages is less than a second quantity threshold, or a sensitivity of one of the any two computing stages to an order in which a result of the other of the any two computing stages participates in computation is greater than a degree threshold.

13. The computing device of claim 11 or 12, wherein, In response to the computing feature information of the first computing stage indicating a total amount of data that needs to be transmitted by the first computing stage to a second computing stage, the management component is specifically configured to: determining, from data required for executing the second computing stage, a target computing result output by the first computing stage based on computing sub-tasks required to be implemented by the first computing stage and the second computing stage; obtaining a total amount of data required to be transmitted by the first computing stage to the second computing stage based on a size of the target computing result.

14. The computing device of any of claims 11 to 13, wherein, In response to the computing feature information of the first computing stage indicating that the first computing stage and the second computing stage share data, the management component is specifically configured to: determining, based on computing sub-tasks executed by the first computing stage and the second computing stage, a target input data required to be used by both the first computing stage and the second computing stage, and a target computing result output by the first computing stage from data required for executing the second computing stage; determining a total amount of data shared by the first computing stage and the second computing stage based on a size of the target input data and a size of the target computing result.

15. The computing device of any of claims 11 to 14, wherein, In response to the computing feature information of the first computing stage indicating a sensitive degree of the first computing stage to an order in which a computing result of the second computing stage participates in a computation, the management component is specifically configured to: determining, based on a computing sub-task executed by the first computing stage, an influence degree of the second computing stage on a computing result of the first computing stage when the computing result of the second computing stage participates in a computation process of the first computing stage in different orders respectively; determining the sensitive degree of the first computing stage to the order in which the computing result of the second computing stage participates in the computation based on the influence degree.

16. The computing device of any one of claims 10 to 15, wherein: the management component is further configured to divide input data of the ith computing stage into P groups of input data, the P being a positive integer smaller than the N; and the management component is specifically configured to determine, based on computing feature information of the ith computing stage, P computing cores from the N computing cores for executing the ith computing stage, the P computing cores corresponding to the P groups of input data.

17. The computing device of claim 16, wherein: the management component is further configured to send, to each of the P computing cores, indication information of a group of input data corresponding to the computing core; and the jth computing core is specifically configured to execute the ith computing stage based on the control information, the indication information, and executable code of the computing task.

18. The computing device of any of claims 10 to 17, wherein, In response to the jth computing core performing a computing operation based on a plurality of computing results obtained by a plurality of other computing cores, the other computing cores being one of the N computing cores other than the jth computing core; the management component is further configured to send, to the jth computing core, configuration information indicating an order in which the plurality of computing results participate in a computation; and the jth computing core is specifically configured to execute the ith computing stage based on the control information, the configuration information, and the executable code of the computing task.

19. A computing device, comprising: A computing device comprising a processor and a plurality of memories having stored therein program instructions, the processor executing the program instructions causing the computing device to perform the method of any of claims 1 to 9.

20. A computer-readable storage medium, characterized in that, Program instructions causing a computing device to perform the method of any of claims 1 to 9 when executed on the computing device.

21. A computer program product comprising instructions, wherein: Program instructions causing a cluster of computing devices to perform the method of any of claims 1 to 9 when executed on the cluster of computing devices.

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