Control system optimization problem compiling method, device and system and computer readable storage medium

Abstract

The invention relates to the technical field of automatic control, in particular to a control system optimization problem compiling method, device and system and a computer readable storage medium, and the method comprises the steps: obtaining a to-be-compiled optimization problem, and recognizing the structure information and feature information of the to-be-compiled optimization problem; obtaining parameter information of the embedded hardware, and matching and optimizing a corresponding numerical solution algorithm in combination with the structure and the feature information to obtain an optimized numerical solution algorithm; converting the optimized algorithm, structure information and parameter information into a first embedded execution code without dynamic memory allocation; performing memory and cache optimization on the memory layout of the first embedded execution code to generate a second embedded execution code; compiling the second embedded execution code into a binary file adaptive to embedded hardware, and deploying the binary file; the environment parameters are obtained and transmitted into embedded hardware, the target control solution is obtained by operating the binary file and solving based on the environment parameters, and the calculation efficiency and hardware compatibility in an embedded scene are improved.

Description

Technical Field

[0001] This application relates to the field of automatic control technology, and in particular to a method, apparatus, system, and computer-readable storage medium for compiling a control system optimization problem. Background Technology

[0002] In the field of embedded control systems, solving control optimization problems is crucial for ensuring real-time control of devices such as automotive ECUs (Electronic Control Units) and drone flight controllers, directly affecting system response accuracy and operational stability.

[0003] Currently, these types of problems are handled by relying on general-purpose optimization solvers, which calculate the system dynamics, objective function, and constraints by calling pre-defined general algorithms. However, the core drawback of this approach is that it cannot resolve the contradiction between real-time performance and resource adaptability: embedded hardware generally has limited memory and CPU computing power, while general-purpose solvers contain a large amount of redundant logic, which not only consumes too much memory resources but also causes the computation time to far exceed the millisecond-level response requirements.

[0004] This contradiction directly leads to lag in the response of key control functions such as MPC (Model Predictive Control) and trajectory planning, which cannot meet the real-time requirements of embedded control systems and restricts the performance of equipment. There is an urgent need for a solution to the control optimization problem that can resolve the contradiction between real-time performance and resource adaptation.

[0005] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] The main purpose of this application is to provide a compilation method, apparatus, system, and computer-readable storage medium for control system optimization problems, aiming to achieve automated compilation and adaptation of control system optimization problems and improve computational efficiency and hardware compatibility in embedded scenarios.

[0007] To achieve the above objectives, this application provides a compilation method for a control system optimization problem, applied to a control system including embedded hardware. The compilation method for the control system optimization problem includes: Obtain the problem to be compiled and optimized, and identify its structural and feature information; Obtain parameter information of embedded hardware, and based on structural information, feature information and parameter information, obtain the corresponding numerical solution algorithm and optimize the numerical solution algorithm to obtain the optimized numerical solution algorithm; The optimized numerical solution algorithm, structural information, and parameter information are transformed into the first embedded execution code without dynamic memory allocation; The memory layout of the first embedded execution code is optimized for memory and cache to obtain the second embedded execution code with optimized memory and cache. The second embedded execution code is compiled into a binary file corresponding to the embedded hardware, and the binary file is deployed to the embedded hardware; The system acquires environmental parameters, passes them to the embedded hardware, and runs the binary file through the embedded hardware to obtain the target control solution of the problem to be compiled and optimized based on the environmental parameters.

[0008] Furthermore, to achieve the above objectives, this application also provides a control system optimization problem compilation apparatus deployed in a control system, the control system further including embedded hardware, and the control system optimization problem compilation apparatus comprising: The data acquisition module is used to acquire the problem to be compiled and optimized, and to identify the structural and feature information of the problem to be compiled and optimized; The algorithm optimization module is used to obtain parameter information of embedded hardware, and based on structural information, feature information and parameter information, obtain the corresponding numerical solution algorithm and optimize the numerical solution algorithm to obtain the optimized numerical solution algorithm. The code conversion module is used to convert the optimized numerical solution algorithm, structural information and parameter information into first embedded executable code without dynamic memory allocation; The code optimization module is used to optimize the memory layout of the first embedded execution code in terms of memory and cache, so as to obtain the second embedded execution code after memory and cache optimization. The code compilation module is used to compile the second embedded execution code into a binary file corresponding to the embedded hardware, and to deploy the binary file to the embedded hardware. The parameter calculation module is used to obtain environmental parameters, pass the environmental parameters to the target embedded hardware, and run the binary file through the target embedded hardware to obtain the target control solution of the problem to be compiled and optimized based on the environmental parameters.

[0009] In addition, to achieve the above objectives, this application also provides a control system, which includes a kiln, a memory, a processor, and a control system optimization problem compiler stored in the memory and executable on the processor. When the control system optimization problem compiler is executed by the processor, it implements the steps of the above-described control system optimization problem compilation method.

[0010] In addition, to achieve the above objectives, this application also provides a computer-readable storage medium storing a compiler for a control system optimization problem, wherein the compiler, when executed by a processor, implements the steps of the above-described compilation method for the control system optimization problem.

[0011] This application provides a method for compiling optimization problems in control systems. The method involves acquiring the optimization problem to be compiled and identifying its structural and feature information to achieve accurate modeling. It then acquires the parameter information of the embedded hardware, and based on the structural, feature, and parameter information, obtains the corresponding numerical solution algorithm and optimizes it to achieve deep adaptation between the algorithm and the embedded hardware. The optimized numerical solution algorithm, structural information, and parameter information are then transformed into first embedded executable code without dynamic memory allocation, avoiding system instability caused by runtime dynamic memory fragmentation. Finally, the method optimizes the memory layout of the first embedded executable code. Memory and cache optimization is performed to obtain a second embedded execution code with optimized memory and cache, further reducing hardware resource consumption. The second embedded execution code is compiled into a binary file corresponding to the embedded hardware, and the binary file is deployed to the embedded hardware to achieve full compatibility of the code with the instruction set and interface protocol of the target embedded hardware. Environmental parameters are obtained and passed to the embedded hardware. By running the binary file on the embedded hardware, the target control solution of the problem to be compiled and optimized can be obtained based on the environmental parameters. This enables real-time response to dynamic changes in the scene and outputs an effective control solution that meets the hardware carrying capacity limit and system safety boundary, thereby improving the computational efficiency and hardware compatibility in embedded scenarios. Attached Figure Description

[0012] Figure 1 This is a flowchart illustrating the first embodiment of the compilation method for the control system optimization problem of this application; Figure 2 This is a flowchart illustrating the second embodiment of the compilation method for the control system optimization problem of this application; Figure 3 This is a flowchart illustrating the third embodiment of the compilation method for the control system optimization problem of this application; Figure 4 This is a schematic diagram of the structure of the compilation device for the control system optimization problem involved in the embodiments of this application; Figure 5 This is a schematic diagram of the control system involved in the embodiments of this application.

[0013] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0014] This application provides a compilation method for a control system optimization problem, referring to... Figure 1 As shown, Figure 1 This is a flowchart illustrating the first embodiment of the compilation method for the control system optimization problem of this application.

[0015] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0016] In the field of embedded control, optimization solutions for scenarios such as MPC control and trajectory planning are crucial for the stable operation of equipment. Currently, these problems mostly rely on general-purpose optimization solvers, which handle related calculations through preset general algorithms. However, embedded hardware has limited memory and computing power, while general-purpose solvers have a lot of redundant logic, which not only consumes too many resources but also makes it difficult to meet the millisecond-level real-time response requirements, resulting in lag in control functions.

[0017] This application provides a method, apparatus, system, and computer-readable storage medium for compiling control system optimization problems, thereby improving computational efficiency and hardware compatibility in embedded scenarios.

[0018] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a device capable of implementing the above functions, like a control system. The following description uses a control system as an example to illustrate this embodiment and the subsequent embodiments.

[0019] This application presents a compilation method for optimizing control system problems, applied to a control system including embedded hardware. The method includes the following implementation steps S10 to S60.

[0020] Step S10: Obtain the problem to be compiled and optimized, and identify the structural and feature information of the problem to be compiled and optimized; As an example, the application scenarios of this application are embedded real-time control optimization scenarios or optimization problem solving scenarios for resource-constrained hardware, covering but not limited to various specific scenarios that require efficient adaptation to hardware resources and the achievement of millisecond-level optimization solutions, such as automotive electronic control, drone flight control, robot motion planning, and precise control of industrial equipment.

[0021] Optionally, this control system is a hardware-software co-operation system for embedded real-time control scenarios. Its core purpose is to automate the compilation and efficient solution of control optimization problems, making it widely adaptable to resource-constrained applications with stringent real-time requirements, such as automotive ECUs, UAV flight control, and robot motion planning. The system uses "end-to-end compilation" as its core logic, forming a complete functional closed loop consisting of a problem input module, a structure analysis module, an algorithm customization module, a code generation module, and an embedded deployment module. Its core workflow is as follows: the problem input module receives system dynamics, objective functions, and constraints input by the user in a high-level description, supporting multiple input methods such as MATLAB API and visual modeling tools, and automatically converts flexible expressions into a standard format through a symbolic resolution mechanism; the structure analysis module automatically identifies the multi-stage sparse structure of the optimization problem, constructs a KKT system sparse matrix, and mines the core features of the problem; the algorithm customization module selects the optimal algorithm (such as Quadratic convex QP) based on the structural features. Programming (quadratic programming) uses methods such as the primitive dual interior-point method and SQP method to tailor general logic for customization; the code generation module generates pure C code without external dependencies and reduces resource consumption through static memory allocation, cache line optimization and other techniques; the embedded deployment module compiles the code into binary files adapted to the target hardware to complete deployment and operation.

[0022] Optionally, this control system also has the following advantages: First, it has strong hardware adaptability, supporting ARM and RISC-V (Reduced Instruction Set...) It offers several advantages over traditional embedded hardware architectures, including Computing-V (a fifth-generation reduced instruction set architecture), hardware-level efficiency improvements through instruction pipeline and cache structure optimization, outstanding real-time performance (solving problems with 1000+ variables in milliseconds, reducing computational complexity from O(n³) to O(n²), high resource efficiency (reducing memory usage by over 50% with no dynamic memory allocation, adapting to resource-constrained embedded environments), good scalability (supporting various optimization problem types such as convex QP and NLP (Nonlinear Programming) with a 100% deployment success rate, meeting real-time control needs in different scenarios), high code maintainability (the generated solver.c / solver.h retains logical comments and modular structure (separation of initialization / iteration / convergence judgment), facilitating secondary integration and reuse), strong verifiability of solution results (PC simulation and embedded execution results are consistent at the bit-level, support CRC check, meeting ASIL-B functional safety audit requirements), and low worst-case execution time (WCET). The worst-case execution time is predictable, and static allocation and fixed iteration counts allow for a strict definition of the upper limit of the solution time, making it suitable for safety-critical systems such as automobiles and flight control systems. Eighth, it has good cross-platform consistency, with pure C implementation and platform macro definition control, supporting multiple architecture hardware such as ARM, RISC-V, DSP (Digital Signal Processor), and GPU, allowing one model to be deployed on multiple platforms.

[0023] Optionally, embedded hardware refers to hardware devices suitable for embedded systems, including but not limited to ARM Cortex series, RISC-V architecture chips, and automotive ECU (Electronic Control Unit); structural information refers to the association pattern between decision variables and constraints in the optimization problem, including but not limited to multi-stage association structures; feature information refers to the core attribute characteristics of the optimization problem, including but not limited to the sparse distribution characteristics of decision variables; multi-stage association structure refers to the recursive and coupled structural pattern of decision variables and constraints in the time or task dimension of the optimization problem; sparse distribution characteristics of decision variables refer to the characteristic that most elements in the decision variables are zero or locally coupled, and non-zero elements are concentrated; symbol resolution and semantic mapping mechanism refers to the processing logic that automatically identifies different forms of expressions and converts them into a unified standard format.

[0024] Optionally, the embedded hardware includes an ARM Cortex series processor, which receives the optimization problem to be compiled from the user via the MATLAB API and visual modeling tools. The input includes system dynamic equations, objective functions, and constraints. Through symbolic resolution and semantic mapping mechanisms, the input expressions of different forms are transformed into a unified standard format. Based on the system dynamic equations, structural information is identified, and variable coupling relationships are detected through symbolic resolution and dependency graph analysis. Combined with the constraints, feature information is identified, the distribution pattern of non-zero elements is statistically analyzed, and a sparse matrix is ​​automatically constructed.

[0025] Optionally, the embedded hardware is an automotive ECU platform device. Users can manually set the problem size parameters, or the system can automatically recommend adjustments based on the hardware computing power. Variable boundaries can be manually entered, or obtained by the system through an industry standard database or device calibration file. The system identifies the generalized multi-stage characteristics of non-temporally ordered multi-subproblems through block sparsity analysis. The sparse matrix construction does not require additional input of sparse information, and the identification results are transmitted through an internal intermediate representation interface.

[0026] Optionally, the structural recognition results (including strip structure features, sparse matrix patterns, variable coupling relationships, and block topology information) are transmitted through the intermediate representation interface (IR) inside the system, encapsulating information such as decision variable index mapping table, KKT matrix non-zero element coordinate table, and block topology, for subsequent steps to access with zero copy, without the need to generate independent intermediate files.

[0027] Optionally, users can manually set problem size parameters (such as the prediction step size N, state dimension n, and input dimension m of MPC (Model Predictive Control)). Alternatively, the system can automatically estimate resource consumption based on the computing power characteristics of the embedded hardware (including CPU frequency, memory capacity, cache level, and real-time scheduling cycle), combined with the problem type and algorithm complexity model, and recommend or adjust the appropriate problem size range to avoid excessive computational latency or insufficient memory due to improper parameter settings.

[0028] Optionally, variable boundaries (such as u_min / u_max, x_min / x_max) can be manually input by the user according to the actual control scenario, or the system can automatically obtain recommended boundary ranges by connecting to industry standard databases, equipment calibration files, or sensor self-test data based on variable physical semantic recognition (such as categories such as torque, current, speed, etc.). The system supports multi-source boundary priority rules, with user input having the highest priority, followed by equipment calibration data, and finally industry standard default values.

[0029] This embodiment adapts to the characteristics of embedded hardware, automates the acquisition of optimization problems and the identification of their structure and features, fully explores the core attributes of the problems, provides precise support for subsequent algorithm customization and code optimization, significantly improves compilation and adaptation efficiency, adapts to embedded resource-constrained scenarios, and ensures the real-time performance and reliability of subsequent solutions.

[0030] Step S20: Obtain the parameter information of the embedded hardware. Based on the structural information, feature information and parameter information, obtain the corresponding numerical solution algorithm and optimize the numerical solution algorithm to obtain the optimized numerical solution algorithm. Optionally, embedded hardware parameter information refers to the core attribute data of embedded hardware, including but not limited to hardware computing power, memory capacity, cache structure, instruction set architecture, etc.; numerical solution algorithm refers to numerical calculation methods used to solve optimization problems, including but not limited to primal dual interior-point methods, sequential quadratic programming (SQP) methods, etc., which approximate the optimal solution through mathematical iteration, matrix operations, etc.; optimized numerical solution algorithm refers to efficient numerical algorithms that are customized and optimized based on problem structure and hardware parameters and adapted to embedded scenarios. After removing redundant logic and adapting to hardware characteristics, they have the characteristics of low resource consumption and high real-time performance.

[0031] Optionally, acquire parameter information of the embedded hardware, including hardware computing power, memory capacity, cache structure, and instruction set architecture; based on the identified multi-stage correlation structure and sparse distribution characteristics of decision variables, select basic numerical solution algorithms that support staged computation (such as the primordial dual interior-point method of convex QP), and extract general computational logic that adapts to hardware computing power and memory capacity; combine cache structure and instruction set architecture to perform collaborative optimization of algorithms and sparse data processing logic units, and cut off general logic that is irrelevant to the current problem (such as multi-problem compatible modules and operation instructions that are not adapted to hardware).

[0032] Optionally, the embedded hardware is a RISC-V architecture chip, and the parameter information also includes parameter acquisition capability; the system automatically analyzes the hardware computing power characteristics, estimates resource consumption by combining the problem type and algorithm complexity model; for nonlinear constraint optimization problems, the SQP method is selected, a dedicated QP solver is called in each iteration, the data access mode is optimized based on the hardware cache structure, incompatible operation instructions are trimmed according to the instruction set architecture, and the iteration strategy is customized to reduce the number of iterations (e.g., 10-15 times).

[0033] Optionally, the algorithm selection is based on the problem structure identification results: for convex quadratic programming problems, the primal dual interior-point method + sparse Cholesky decomposition or LDL is preferred. For band decomposition and nonlinear constrained optimization problems, the SQP method is selected, and a dedicated QP solver is called for each iteration. For block diagonal or weakly coupled multi-subproblem structures, a block-based iterative solver is selected. For high-sparse structures without significant bandwidth regularity, the CSR / CSC (Compressed Sparse Column) sparse compressed storage format is combined with a general sparse linear system solver.

[0034] Optionally, the general logic of the pruning includes algorithm branches that do not match the current problem type (such as pruning SQP framework code for convex QP problems, pruning convex QP solver code for NLP problems), multi-hardware adaptation modules, and multi-problem compatibility processing code. Only the core computational logic required by the current problem and target hardware is retained. After pruning, numerical stability is ensured by a hybrid solution strategy of fixed-point approximation + double-precision critical path, which will not affect the reliability of the algorithm.

[0035] This embodiment achieves customized optimization of the algorithm through deep adaptation of hardware parameters and problem structure. It avoids redundant calculations in general algorithms and improves the utilization of hardware resources, making the algorithm's computational efficiency precisely match the performance of embedded hardware. The computational complexity is reduced from O(n³) to O(n²), laying the foundation for subsequent code generation and millisecond-level solution.

[0036] Step S30: Transform the optimized numerical solution algorithm, structural information, and parameter information into the first embedded execution code without dynamic memory allocation; Optionally, the first embedded execution code refers to the execution code generated based on the optimized numerical solution algorithm, problem structure information, and hardware parameters, without dynamic memory allocation, and adapted to the embedded scenario; without dynamic memory allocation means that all memory space is planned and allocated during the compilation stage, and no additional memory needs to be requested or released during runtime, thus avoiding memory fragmentation; static memory planning means that the allocation size and address of storage resources such as arrays and cache blocks are determined during the compilation stage according to the algorithm requirements and hardware memory capacity, and the storage layout is fixed in advance.

[0037] Optionally, by combining optimized numerical solution algorithms (such as the primal dual interior-point method of convex QP), multi-stage correlation structures, and the memory capacity and instruction set architecture parameters of embedded hardware, static memory planning is carried out to determine the storage resource allocation scheme according to the storage requirements and operation logic of sparse matrices; the algorithm is decomposed into modular code frameworks such as initialization, iterative calculation, and result output, retaining the operation logic that is only adapted to the current problem; combined with the sparse distribution characteristics of decision variables, the code of each module is integrated and instruction compatibility is optimized, and loop unrolling and constant folding techniques are applied to generate the first embedded execution code without dynamic memory allocation and without external dependency libraries.

[0038] Optionally, the embedded hardware is a RISC-V architecture chip. Based on the optimized SQP algorithm, block sparse structure and hardware parameters, static memory is planned using CSR sparse index compression format; incompatible operation instructions are trimmed according to the hardware instruction set architecture, and CPU cache line alignment is performed on the code data layout; the code structure is made clear through modular decomposition, containing only the specific operations required for trajectory planning, and the generated code supports direct deployment, with memory usage meeting the requirements of embedded resource constraints.

[0039] Optionally, static memory planning adopts the CSR sparse index compression format, which specifies the storage layout and fixed size of sparse matrices, intermediate variables, and iterative cache areas. Combined with the sparse distribution characteristics of decision variables (5-10 non-zero elements per row in MPC problems and 8-12 in trajectory planning problems), storage allocation is optimized to further reduce memory usage.

[0040] This embodiment avoids runtime memory allocation overhead and fragmentation through static memory planning, improves adaptability through modular code generation, and optimizes instruction and data layout by combining hardware characteristics. This ensures code portability while reducing memory usage and computational redundancy, providing support for subsequent cache optimization and millisecond-level solving.

[0041] Step S40: Optimize the memory layout of the first embedded execution code to obtain the second embedded execution code after memory and cache optimization; Optionally, memory and cache optimization refers to the optimization of code data layout and access patterns based on the memory capacity, cache structure and access characteristics of embedded hardware, including but not limited to memory layout adjustment, cache line alignment, and data access continuity optimization; the second embedded executable code refers to the embedded executable code that, after memory and cache optimization, is adapted to the hardware storage system and significantly improves data access efficiency and running speed.

[0042] Optionally, first obtain the memory capacity, cache structure, and instruction set architecture parameters of the embedded hardware, analyze the data access frequency and correlation of the first embedded execution code; adjust the memory allocation according to the principle of "centralized storage of high-frequency data and continuous layout of related data", and arrange the core algorithm data in alignment according to the cache line size; apply loop technology to optimize the continuity of data access, reduce runtime cache misses and memory access latency, and integrate the optimization logic to obtain the second embedded execution code.

[0043] Optionally, the embedded hardware is an automotive ECU platform, whose cache supports multi-level storage and NEON (Advanced SIMD for ARM) vectorized instructions. Based on the characteristics of the hardware cache hierarchy, the system stores frequently used sparse matrix indices in high-speed cache and low-frequency data in ordinary memory. Data grouping is optimized according to the instruction set architecture to adapt matrix operations to the hardware's vectorized processing capabilities. Redundant calculations are simplified through constant folding, further improving code execution efficiency. The generated second embedded execution code has no external dependencies and adapts to the hardware's real-time scheduling requirements.

[0044] This embodiment optimizes data layout and access patterns by deeply adapting to the characteristics of embedded hardware storage and instructions, thereby significantly improving cache hit rate and greatly reducing memory access overhead. At the same time, it simplifies redundant calculations, providing key support for subsequent compilation, deployment, and millisecond-level solving, ensuring that the code runs efficiently and stably in resource-constrained environments.

[0045] Step S50: Compile the second embedded execution code into a binary file corresponding to the embedded hardware, and deploy the binary file to the embedded hardware; Optionally, a binary file refers to a file format in which the second embedded executable code, after being compiled and adapted to the embedded hardware instruction set architecture, can run directly on the hardware, including but not limited to static libraries (.a) and dynamic libraries (.so); compilation adaptation parameters refer to compilation configuration information adapted to the embedded hardware, including but not limited to the target compiler type, instruction set optimization options, compilation optimization level, etc.; deployment interface parameters refer to deployment-related configuration information supported by the embedded hardware, including but not limited to interface protocol, storage path, running permissions, etc.

[0046] Optionally, obtain the compilation adaptation parameters (including instruction set architecture and optimization level requirements) and deployment interface parameters of the embedded hardware; select the default cross-compiler for the adapted hardware, arm-linux-gnueabihf-gcc for ARM architecture and riscv64-unknown-elf-gcc for RISC-V architecture; compile the second embedded executable code according to the compilation adaptation parameters, enable the -O3 optimization level and the vector instruction optimization corresponding to the hardware, and generate a binary file in static library format; deploy the binary file to the embedded hardware through the path and protocol specified by the deployment interface parameters, and link it directly into the application.

[0047] Optionally, the embedded hardware is an automotive ECU platform, and the user selects a custom cross-compiler (such as CCS (CodeComposer Studio) compiler); the system adjusts the compilation logic according to the hardware compilation adaptation parameters to adapt to the hardware's cache structure and instruction pipeline characteristics; the second embedded execution code is compiled into a binary file that meets the real-time scheduling requirements of the ECU, and deployment is completed through the deployment interface supported by the hardware; after deployment, the binary file has no external dependencies, can directly respond to hardware running instructions, and supports status indicator feedback in fault conditions.

[0048] Optionally, the compilation tools support multiple platform default toolchains: ARM architecture corresponds to arm-linux-gnueabihf-gcc or aarch64-linux-gnu-gcc, RISC-V architecture corresponds to riscv64-unknown-elf-gcc, automotive ECU platform corresponds to CCS or TASKING compiler, and general x86 platform corresponds to gcc / clang; the compilation output supports static library (.a) or dynamic library (.so) format. Real-time control systems preferentially use static libraries to be directly linked into the application to ensure deterministic operation.

[0049] This embodiment ensures complete compatibility between the binary file and the embedded hardware through compilation configuration adapted to hardware characteristics and flexible deployment methods, achieving a 100% deployment success rate. At the same time, it maximizes the hardware's computing performance, providing a stable and reliable operating foundation for millisecond-level solutions to optimization problems.

[0050] Step S60: Obtain the environment parameters, pass the environment parameters to the embedded hardware, run the binary file through the embedded hardware, and obtain the target control solution of the problem to be compiled and optimized based on the environment parameters; Optionally, the environmental parameters refer to the external scene data required to solve the problem to be compiled and optimized, including but not limited to the current state of the device, the target position, the physical constraint boundary, and the real-time operating conditions; the target control solution refers to the optimal control output that satisfies the optimization objective and constraint conditions obtained by the embedded hardware after running the binary file based on the environmental parameters, including but not limited to the control input and trajectory points.

[0051] Optionally, based on the parameter acquisition capabilities of the embedded hardware and the environmental parameter types of the control system, environmental parameters such as the current state of the device and constraint boundaries are acquired in real time. The environmental parameters are then transmitted to the embedded hardware with deployed binary files. The hardware runs the binary files and calculates the environmental parameters using a customized primal-dual interior-point method, sequentially completing state vector loading, sparse matrix decomposition, iterative solution, and constraint satisfaction verification. The obtained intermediate control solutions are then format-converted and adapted to output the optimal control input. The entire process takes approximately 4.8ms ± 0.3ms and supports optimization problems with approximately 300 variables.

[0052] Optionally, the embedded hardware is a UAV flight control device. Environmental parameters include real-time position, speed, target flight path, and obstacle information. The device continuously acquires environmental parameters through hardware parameter acquisition capabilities and transmits them to the device. It runs a binary file to perform trajectory planning and solve the problem, adopts a preset initial point strategy to improve the convergence speed, and optimizes the number of iterations to 10-15. During the solution process, a lightweight state management module is built-in. If the iteration fails to converge, it outputs the previous feasible solution and a restart suggestion. If the value is abnormal, it returns the default control value. Finally, it outputs the trajectory point target control solution adapted to the flight control system, which takes 9.6ms ± 0.5ms, meeting the real-time trajectory adjustment requirements of the UAV.

[0053] Optionally, the solver has a built-in lightweight state management module with different handling strategies for different fault scenarios: normal convergence returns state flag 0 and the optimal solution; iteration failure returns state flag 1, the previous feasible solution, and a restart suggestion; infeasible constraints return state flag 2 and the boundary point of the feasible region, triggering backoff control; numerical anomalies (such as NaN, inf) return state flag 3 and stop solving, returning the default control value; after enabling debug mode (DEBUG_FLAG=1), fault prompt information can be output through the ECU serial port or log.

[0054] Optionally, the MPC problem can be solved within 5ms and the trajectory planning problem within 10ms. This refers to the complete execution time from inputting the current state / environment parameters to outputting the optimal control quantity, including state vector loading, sparse matrix calculation and decomposition, iterative solution, and result output. The system supports a total decision variable scale of 1000+ (the sum of state variables and control variables). When the sparsity is high (bandwidth <10%), it can maintain a solution time of 10-20ms. When the hardware performance limit is exceeded, a prompt will be displayed suggesting that the step size or variable scale be reduced.

[0055] This embodiment achieves millisecond-level efficient solution of optimization problems by accurately collecting and transmitting environmental parameters and combining them with a hardware-customized solution algorithm. The accuracy and real-time performance of the target control solution are adapted to the needs of embedded scenarios, while having a complete fault tolerance mechanism to ensure the stable operation of the control system under complex working conditions.

[0056] This embodiment achieves accurate modeling of the optimization problem by acquiring the problem to be compiled and optimized, and identifying its structural and feature information. It then acquires the parameter information of the embedded hardware, and based on the structural, feature, and parameter information, obtains the corresponding numerical solution algorithm and optimizes it to obtain an optimized numerical solution algorithm, achieving deep adaptation between the algorithm and the embedded hardware. The optimized numerical solution algorithm, structural information, and parameter information are then transformed into first embedded executable code without dynamic memory allocation, avoiding system instability caused by runtime dynamic memory fragmentation. Finally, memory and cache optimization is performed on the memory layout of the first embedded executable code. The second embedded execution code, optimized for memory and cache, further reduces hardware resource consumption. This second embedded execution code is compiled into a binary file corresponding to the embedded hardware, and then deployed to the embedded hardware, ensuring full compatibility of the code with the target embedded hardware's instruction set and interface protocol. Environmental parameters are acquired and passed to the embedded hardware. By running the binary file on the embedded hardware, the target control solution for the problem to be compiled and optimized can be obtained based on the environmental parameters. This enables real-time response to dynamic changes in the scenario, outputting an effective control solution that meets hardware capacity limits and system safety boundaries, thereby improving computational efficiency and hardware compatibility in embedded scenarios.

[0057] Furthermore, based on the above, a second embodiment of the compilation method for the control system optimization problem in this embodiment is proposed, referring to... Figure 2 As shown, Figure 2 This is a flowchart illustrating the second embodiment of the compilation method for the control system optimization problem of this application. In some feasible embodiments, the structural information is a multi-stage correlation structure, and the feature information is the sparse distribution characteristics of the decision variables. The above step S10 includes the following implementation steps S201-S203.

[0058] Step S201: Receive the optimization problem to be compiled by the user in a preset description, wherein the optimization problem to be compiled includes at least the system dynamic equations and constraints; Step S202: Based on the system dynamics equations, identify the multi-stage associated structure; Step S203: Based on the constraints, identify the sparse distribution characteristics of the decision variables.

[0059] Optionally, the preset description method refers to the high-level input forms supported by the system, including but not limited to MATLAB API (Application Programming Interface), visual modeling tools, text configuration files, Python / C++ SDK (Software Development Kit), etc.; system dynamic equation: a mathematical expression describing the law of change of system state, including but not limited to the form x(k+1)=Ax(k)+Bu(k); constraint conditions refer to the restrictions on variables in the optimization problem, including but not limited to physical boundary constraints, performance constraints, collision avoidance constraints, etc.; multi-stage correlation structure refers to the recursive and coupled structural pattern of decision variables and constraints in the time or task dimension in the optimization problem, including time-series, parallel, hierarchical, etc.; sparse distribution characteristics of decision variables refer to the characteristic that most elements in the decision variables are zero or locally coupled, and non-zero elements are concentrated.

[0060] Optionally, the system receives the optimization problem to be compiled from user input via a preset description method. The input includes at least the system dynamics equations and constraints. Users can input the objective function and constraints in the form of natural expressions. The system automatically converts any equivalent dynamic expression into an internally unified standard description format through symbolic resolution and semantic mapping mechanisms. Based on the system dynamics equations, the system identifies the temporal index or recursive relationship of variables through symbolic resolution and dependency graph analysis techniques, constructs a directed dependency graph of decision variables and constraints, and analyzes topological features to identify multi-stage association structures, including temporal chain coupling or non-temporal block sparse coupling. Based on the constraints, the system uses an automatic differentiation engine to calculate the Jacobian matrix of the constraints, statistically analyzes the distribution pattern of non-zero elements, identifies the sparse distribution characteristics of decision variables, constructs a sparse matrix representation of the KKT (Karush–Kuhn–Tucker) system, and determines sparse mode parameters such as the number of non-zero elements in each row.

[0061] This embodiment adapts to different user habits through diverse input methods, eliminating the need for users to manually standardize expressions. It automates structure and feature recognition, fully exploits the multi-stage and sparse characteristics of optimization problems, and provides accurate basis for subsequent algorithm customization and static code optimization. This significantly reduces modeling complexity and manual intervention costs, and improves the adaptability and efficiency of the compilation process.

[0062] Furthermore, based on the above, a third embodiment of the compilation method for the control system optimization problem in this embodiment is proposed, referring to... Figure 3 As shown, Figure 3This is a flowchart of the third embodiment of the compilation method for the control system optimization problem of this application. In some feasible embodiments, the above step S20 includes the following implementation steps S301-S304.

[0063] Step S301: Obtain parameter information of the embedded hardware, wherein the parameter information includes at least hardware computing power information, memory capacity information, cache structure information and instruction set architecture information; Step S302: Determine the basic numerical solution algorithm that supports staged computation corresponding to the multi-stage association structure, and determine the sparse data processing logic unit corresponding to the basic numerical solution algorithm based on the sparse distribution characteristics of decision variables. Step S303: Determine the general computational logic in the basic numerical solution algorithm that corresponds to the hardware computing power information and memory capacity information, and use the general computational logic as the numerical solution algorithm; Step S304: Based on the cache structure information, multi-stage association structure and instruction set architecture information, perform collaborative optimization on the sparse data processing logic unit and numerical solution algorithm to obtain the optimized numerical solution algorithm.

[0064] Optionally, hardware computing power information refers to the computing performance data of the embedded hardware, including but not limited to CPU clock speed, number of cores, and computing speed; cache structure information refers to the configuration information of the embedded hardware cache, such as cache level, capacity, and cache line size; instruction set architecture information refers to the instruction set standards supported by the embedded hardware, including but not limited to the instruction specifications of architectures such as ARM and RISC-V; basic numerical solution algorithms refer to basic computational methods adapted to multi-stage correlation structures, including but not limited to the primal dual interior-point method and the sequential quadratic programming (SQP) method; sparse data processing logic units refer to computational modules specifically designed to handle the sparse distribution characteristics of decision variables, including but not limited to sparse matrix decomposition and sparse indexing; and collaborative optimization processing refers to the integrated optimization of algorithms and data processing logic based on hardware characteristics and problem structure, including but not limited to parameter configuration, logic pruning, and process adaptation.

[0065] Optionally, obtain parameter information of the embedded hardware, including at least hardware computing power, memory capacity, cache structure, and instruction set architecture information; based on the type of multi-stage correlation structure (temporal or parallel), determine the basic numerical solution algorithm supporting staged computation, matching the primal dual interior-point method for convex quadratic programming problems, and matching the SQP method for nonlinear programming problems; based on the sparse distribution characteristics of decision variables (such as banded structure or block sparse structure), determine the corresponding sparse data processing logic unit, such as sparse Cholesky decomposition or LDL. The (Lower Diagonal Lower Transpose) strip decomposition module extracts general computational logic from the basic algorithm that matches the hardware's computing power and memory capacity as the numerical solution algorithm. Redundant logic such as multi-hardware adaptation and multi-problem compatibility is trimmed. The data access mode is optimized based on cache structure information, the computation process is adjusted in combination with multi-stage association structure, the operation instructions are optimized to adapt to the instruction set architecture, and the sparse data processing logic unit and numerical solution algorithm are collaboratively optimized. The upper limit of the number of iterations is customized to 10-15 times, and parameters such as adaptive step size are configured to obtain the optimized numerical solution algorithm.

[0066] This embodiment achieves precise customization and efficient optimization of the algorithm through deep synergistic adaptation between hardware characteristics and problem structure. It fully leverages the computational advantages brought by sparse structure and maximizes the performance of hardware, significantly reducing computational complexity and redundant overhead. This provides high-performance and highly adaptable algorithmic support for subsequent code generation and embedded real-time solving.

[0067] Furthermore, based on the above, in some feasible embodiments, step S30 above may also include the following implementation steps D401 to D403.

[0068] Step D401: Perform static memory planning on the optimized numerical solution algorithm, multi-stage correlation structure, and memory capacity information to obtain a static memory planning scheme; Step D402: Based on the static memory planning scheme, the optimized numerical solution algorithm, and the multi-stage association structure, the algorithm code is decomposed to obtain a modular algorithm code framework; Step D403: Based on the modular algorithm code framework, the sparse distribution characteristics of decision variables, and the instruction set architecture information, perform code integration and compatibility optimization to obtain the first embedded execution code without dynamic memory allocation.

[0069] Optionally, static memory planning refers to the pre-planning of the allocation size, address, and layout of storage resources such as arrays, cache blocks, and sparse matrices during the compilation phase, based on the optimization algorithm requirements, multi-stage associative structures, and hardware memory capacity, without requiring dynamic allocation at runtime. Modular algorithm code framework refers to the code structure that breaks down the optimized numerical solution algorithm into independent modules such as initialization, iterative calculation, convergence judgment, and result output, with clear interfaces and logical decoupling for each module. Compatibility optimization refers to the optimization operation that adjusts the code instruction format, data alignment, and operation logic for embedded hardware instruction set architecture to ensure that the code runs stably and efficiently on the target hardware.

[0070] Optionally, static memory planning can be carried out by combining optimized numerical solution algorithms (such as the primordial dual interior-point method of convex QP, SQP method), multi-stage association structures (temporally chained coupling or block sparse coupling), and memory capacity information of embedded hardware, using CSR (Compressed Sparse Coding). Row (compressed sparse row storage format) sparse index compression format allocates storage resources, clearly defines the storage layout and fixed size of sparse matrices, intermediate variables, and iterative cache areas, and eliminates runtime dynamic memory allocation; based on the static memory planning scheme, the algorithm is functionally divided into modular code frameworks such as initialization, sparse matrix decomposition, iterative solution, convergence judgment, and result output, with each module independently implementing specific functions and interacting through standardized interfaces; combining the sparse distribution characteristics of decision variables (e.g., 5-10 non-zero elements per row in MPC problems, 8-12 in trajectory planning problems) and hardware instruction set architecture information, the code of each module is integrated, and compilation optimization techniques such as loop unrolling and constant folding are applied to trim redundant logic that is incompatible with multiple problems and not adapted to hardware, and CPU cache line alignment is performed on the data layout to generate the first embedded execution code without dynamic memory allocation. The code only contains the calculations required for the current problem and has no external dependency libraries.

[0071] This embodiment avoids runtime memory fragmentation and allocation overhead through static memory planning, improves code maintainability and reusability through modular decomposition, ensures hardware adaptability through compatibility optimization, and reduces storage usage (memory usage is reduced by more than 50%) by sparse index compression. This lays a solid foundation for subsequent memory and cache optimization and efficient deployment, and ensures real-time solution performance in embedded scenarios.

[0072] Furthermore, based on the content of any of the above embodiments, in some feasible embodiments, the above step S40 includes the following implementation steps E501-E503.

[0073] Step E501: Based on the memory capacity information and the data access characteristics of the first embedded execution code, perform memory layout adjustment processing to obtain the first intermediate code with optimized memory layout; Step E502: Based on the cache structure information and the first intermediate code, perform cache adaptation optimization processing to obtain the second intermediate code adapted to the cache; Step E503: Based on the first intermediate code, the second intermediate code, and the instruction set architecture information, perform optimization logic integration processing to obtain the second embedded execution code.

[0074] Optionally, data access characteristics refer to attributes such as the frequency of data reading and writing, access order, and correlation in the first embedded execution code, including but not limited to high-frequency access data groups and consecutively accessed data blocks; memory layout adjustment processing refers to the process of adjusting the storage location, arrangement order, and grouping method of data in memory according to the hardware memory capacity and data access characteristics to optimize data read and write efficiency; cache adaptation optimization processing refers to the process of optimizing data storage and access patterns based on the hardware cache structure (such as cache level and cache line size) to improve cache hit rate; intermediate code refers to the transitional code generated during the optimization process, which carries the memory and cache optimization logic and provides the foundation for the final generation of the second embedded execution code.

[0075] Optionally, the memory capacity information of the embedded hardware and the data access characteristics of the first embedded execution code are obtained. The memory layout is adjusted according to the principle of "centralized storage of high-frequency data and continuous layout of associated data". High-frequency access data such as sparse matrix indexes and iterative intermediate variables are centrally allocated to contiguous memory areas to reduce memory fragmentation and random access overhead. According to the hardware cache structure information, the first intermediate code is cache-adapted and optimized, and the core algorithm data is aligned according to the cache line size to reduce the probability of cache misses. Combining the instruction set architecture information, the memory layout optimization and cache adaptation optimization logic are integrated. Loop unrolling technology is applied to improve data access continuity and adapt to the characteristics of the hardware instruction pipeline, so that the data access process and the hardware storage system are efficiently matched, generating the second embedded execution code with optimized memory and cache.

[0076] This embodiment optimizes data storage and access patterns by precisely adapting to hardware memory and cache characteristics, significantly reducing memory access latency. At the same time, it adapts to hardware instruction execution characteristics, improving resource utilization efficiency during code execution and providing key support for efficient solution of embedded hardware.

[0077] Furthermore, based on the content of any of the above embodiments, in some feasible embodiments, in the compilation method for the control system optimization problem, step S50 includes the following implementation steps F501 to F502.

[0078] Step F501: Based on the compilation adaptation parameters of the embedded hardware and the second embedded execution code, perform code compilation processing to obtain the binary file after code compilation; Step F502: Deploy the binary file to the embedded hardware according to the binary file and the deployment interface parameters of the embedded hardware.

[0079] Optionally, compilation adaptation parameters refer to compilation configuration information adapted to embedded hardware, including but not limited to target compiler type, instruction set optimization options, compilation optimization level, hardware macro definitions, and SIMD (Single Instruction Multiple Data) instruction enablement configuration; deployment interface parameters refer to deployment-related configuration information supported by embedded hardware, including but not limited to interface protocol, storage path, runtime permissions, linking method, and hardware adaptation macro definitions.

[0080] Optionally, the system obtains the compilation adaptation parameters and deployment interface parameters for the embedded hardware. The compilation adaptation parameters cover the target compiler type, instruction set optimization options, compilation optimization level, and hardware macro definitions. The system provides a configurable cross-compilation process, which by default adapts to compilers for different hardware architectures. For ARM (Advanced RISC Machines) architecture, it corresponds to arm-linux-gnueabihf-gcc or aarch64-linux-gnu-gcc; for RISC-V architecture, it corresponds to riscv64-unknown-elf-gcc; and for automotive ECU platforms, it corresponds to the CCS or TASKING compiler. Users can also declare and replace custom cross-compilers in the generated configuration. The second embedded executable code is compiled according to the compilation adaptation parameters, and the corresponding optimization level and hardware vector instruction optimization are enabled to generate binary files in static library (.a) or dynamic library (.so) format. Real-time control systems preferentially use the form of directly linking static libraries into the application. According to the storage path, linking method, and hardware adaptation requirements specified by the deployment interface parameters, the binary files are deployed to the embedded hardware. The deployment process does not require additional dependent libraries and completes the runtime environment configuration through the hardware-supported interface.

[0081] This embodiment ensures full compatibility between binary files and various embedded hardware through a flexible and configurable compilation and deployment mechanism, greatly improving deployment efficiency and adaptability. The generated files can run stably on the target hardware, providing a reliable operating foundation for the efficient solution of optimization problems.

[0082] Furthermore, based on the content of any of the above embodiments, in some feasible embodiments, the parameter information in the compilation method for the optimization problem of the control system also includes the parameter acquisition capability of the embedded hardware, and step S60 includes the following implementation steps J601 to J603.

[0083] Step J601: Based on the parameter acquisition capability and the environmental parameter type of the control system, obtain the environmental parameters when the binary file is executed; Step J602: Input the target environment parameters into the embedded hardware, run the binary file through the embedded hardware to calculate the control solution of the target environment parameters and verify the constraint satisfaction, and obtain the effective intermediate control solution of the problem to be compiled and optimized. Step J603: Based on the intermediate control solution and the output adaptation parameters of the control system, perform format conversion and adaptation processing on the intermediate control solution to obtain and output the target control solution of the problem to be compiled and optimized.

[0084] Optionally, parameter acquisition capability refers to the performance of embedded hardware in acquiring external data through sensors, interfaces, etc., including but not limited to acquisition frequency, data accuracy, supported parameter types, interface protocol compatibility, etc.; output adaptation parameters refer to the configuration information of the control system interface, including but not limited to data format, transmission protocol, output accuracy requirements, interface timing matching rules, etc.; effective intermediate control solution refers to the preliminary control solution that meets the constraints of the optimization problem (such as physical boundaries and performance limitations) after constraint satisfaction verification, providing a basis for the target control solution.

[0085] Optionally, the embedded hardware's parameter information includes parameter acquisition capabilities. Based on these capabilities and the environmental parameter types of the control system (such as device status, target location, obstacle information, etc.), the corresponding environmental parameters are acquired in real time. These environmental parameters are then transmitted to the embedded hardware with deployed binary files. The hardware runs the binary files and calculates the control solution for the environmental parameters using customized algorithms (such as the primordial dual interior-point method of convex QP or the SQP method for nonlinear constraints). Constraint satisfaction is verified synchronously, and solutions that do not meet physical boundaries and performance requirements are eliminated to obtain valid intermediate control solutions. Combined with the output adaptation parameters of the control system, the intermediate control solutions undergo data format conversion, precision adjustment, and interface timing adaptation processing to generate and output the target control solution. The hardware has a built-in lightweight state management module. If iteration fails to converge or numerical anomalies occur, it outputs corresponding status flags and feasible solutions (e.g., outputting the previous feasible solution and restart suggestion when iteration fails to converge, and returning the default control value when numerical anomalies occur), ensuring the continuity of the solution process.

[0086] Optionally, the system receives an MPC problem description input by the user via the MATLAB API, where the user defines the system dynamics equation as x(k+1)=Ax(k)+Bu(k) and the objective function as ∑(x(k)). Qx(k)+u(k) The constraints, Ru(k), include u_min ≤ u(k) ≤ u_max and x_min ≤ x(k) ≤ x_max. The problem size can be manually set by the user to N=20 steps, state dimension n=4, and input dimension m=2, or it can be automatically recommended and adjusted by the system based on the target hardware computing power. The variable boundaries are manually entered by the user according to the actual control scenario. The system also supports connecting to industry standard databases and equipment calibration files to obtain recommended ranges, and determines the final constraints according to the priority rule of user input > equipment calibration data > industry standard default values.

[0087] Optionally, the multi-stage sparse structure of the MPC problem is analyzed. Symbolic analysis and dependency graph analysis techniques are used to identify the temporal indices and recursive relationships of variables, constructing a directed dependency graph of decision variables and constraints to determine its temporally chain-coupled multi-stage correlation structure. An automatic differential engine is used to calculate the Jacobian matrix of constraints and the Hessian matrix of the Lagrangian function, statistically analyzing the distribution patterns of non-zero elements to automatically construct a sparse matrix representation of the KKT system. The sparse pattern of the decision variables is identified as {u0, u1, ..., u...}. 19 The analysis of the strip structure formed by state coupling determines that there are approximately 5-10 non-zero elements in each row. The structure recognition results are transmitted through the internal intermediate representation interface (IR), which encapsulates information such as the decision variable index mapping table and the matrix non-zero element coordinate table for zero-copy access in subsequent steps.

[0088] Optionally, based on the identified attributes of the convex quadratic programming problem, the primal dual interior-point method + sparse Cholesky decomposition is selected as the basic numerical solution algorithm; a general computational logic adapted to the hardware computing power and memory capacity is extracted, and the data access mode is optimized by combining the hardware cache structure; non-adaptive computational instructions are trimmed according to the instruction set architecture; a correlation simplification strategy is applied, and the solution of the previous time step is used as the initial point to improve the convergence speed; the upper limit of the number of iterations is customized to 10-15 times; the convergence performance is optimized by dynamic barrier adjustment and adaptive step size control of the central path; and a hybrid solution strategy of fixed-point approximation + double-precision critical path is adopted to ensure numerical stability.

[0089] Optionally, a dedicated C code solver.c / solver.h is generated, employing CSR sparse index compression format for static memory planning. This clearly defines the storage layout and fixed size of the sparse matrix, intermediate variables, and iterative cache, eliminating runtime dynamic memory allocation. The algorithm is functionally broken down into modular code frameworks such as initialization, sparse matrix decomposition, iterative solving, convergence judgment, and result output. Each module interacts through a standardized interface. Compilation optimization techniques such as loop unrolling and constant folding are applied, and the data layout is aligned to CPU cache lines. The generated code contains only the computations required for the MPC problem, removing redundant logic such as multi-problem compatibility and multi-hardware adaptation. It has no external dependency libraries, and the source code size is less than 100KB.

[0090] Optionally, a configurable cross-compilation process is adopted, using the arm-linux-gnueabihf-gcc compiler corresponding to the ARM architecture to compile the generated C code into a static library (.a) format binary file adapted for the ARM Cortex-A72 processor. Users can also declare and replace the custom cross-compiler in the generation configuration. The binary file is deployed on the vehicle ECU and directly linked into the application. The current state x(k) and environmental parameters are input in real time. The solver completes the state vector loading, sparse matrix calculation and decomposition, iterative solution and result output according to the complete execution process, with an average time of 4.8ms ± 0.3ms. It supports optimization problems with a scale of about 300 variables. The solver has a built-in lightweight state management module. Normal convergence returns the state flag 0 and the optimal control input u(k). In abnormal scenarios, feasible solutions or default control quantities are fed back according to preset strategies. After the debug mode is enabled, fault prompts can be output through the ECU serial port.

[0091] Optionally, the system receives a trajectory planning problem description input by the user via the MATLAB API. User-defined states include position, velocity, and acceleration; input is control force; constraints cover collision avoidance, energy minimization, and boundary conditions; and the objective function is set to minimize a combined energy consumption and time factor. Users can manually set the problem size parameters, or the system can automatically recommend an appropriate range based on the computing power characteristics of the UAV flight control hardware (CPU frequency, memory capacity, etc.). Variable boundaries can be manually input, and the system can also automatically obtain recommended boundaries based on variable physical semantic recognition (such as velocity and acceleration categories) by connecting to the UAV industry standard database or equipment calibration files. The final constraints are determined according to the priority rule of user input > equipment calibration data > industry standard default values.

[0092] Optionally, the multi-stage structure of the trajectory planning problem is analyzed. Symbolic analysis and dependency graph analysis techniques are used to identify the sparsity of constraints on states and inputs, and a directed graph of the dependency between decision variables and constraints is constructed to determine its parallel multi-stage correlation structure. An automatic differentiation engine is used to calculate the Jacobian matrix of constraints and the Hessian matrix of Lagrange functions, and the distribution pattern of non-zero elements is statistically analyzed to automatically construct a sparse matrix representation of the KKT system, identifying sparse patterns with approximately 8-12 non-zero elements per row. The structure identification results are transmitted through an internal intermediate representation interface (IR), encapsulating information such as the decision variable index mapping table and the matrix non-zero element coordinate table for zero-copy access in subsequent steps, without the need to generate independent intermediate files.

[0093] Optionally, based on the identified nonlinear constraint optimization problem attributes, the SQP method is selected as the basic numerical solution algorithm, and a dedicated QP solver is called in each iteration; general computational logic adapted to the computing power and memory capacity of UAV flight control hardware is extracted, and the data access mode is optimized in combination with the hardware cache structure; non-adaptive computational instructions are trimmed according to the instruction set architecture; an iterative strategy is customized for the trajectory planning problem, the parameterized optimization scheme is optimized to improve the convergence speed, a preset initial point strategy (standard initial position) is adopted to start the solution, the upper limit of the customized number of iterations is 10-15, and the convergence performance is optimized by dynamic barrier adjustment and adaptive step size control of the center path to ensure numerical stability under the embedded platform.

[0094] Optionally, a dedicated C code solver, trajectory_solver.c / trajectory_solver.h, is generated. Static memory planning is performed using the CSR sparse index compression format, clearly defining the storage layout and fixed size of the sparse matrix, intermediate variables, and iterative cache, eliminating runtime dynamic memory allocation. The algorithm is functionally broken down into modular code frameworks such as initialization, sparse matrix decomposition, iterative solving, convergence judgment, and result output. Each module interacts through standardized interfaces. The cache access mode is optimized for UAV flight control hardware, applying compilation optimization techniques such as loop unrolling and constant folding. CPU cache line alignment is performed on the data layout. The generated code contains only the specific operations required for trajectory planning, removing redundant logic for multi-problem compatibility and multi-hardware adaptation. There are no external dependency libraries, and the source code size is less than 100KB.

[0095] Optionally, a configurable cross-compilation process is adopted, using the default compiler adapted to the UAV flight control hardware architecture. Alternatively, users can declare and replace the default compiler in the generated configuration to compile the generated C code into a static library (.a) format binary file. The binary file is then deployed to the unmanned control system (such as an autonomous vehicle or robot), and environmental parameters and target positions are transmitted in real time. The solver completes the state vector loading, sparse matrix calculation and decomposition, iterative solution, and result output according to the complete execution process, with an average execution time of 9.6ms ± 0.5ms, supporting optimization problems with approximately 800 variables. The solver has a built-in lightweight state management module. Upon normal convergence, it returns a state flag of 0 and a trajectory point. In abnormal scenarios, it provides feedback on feasible solutions or default control variables according to preset strategies. After enabling debug mode, fault prompts can be output through the device serial port.

[0096] This embodiment transforms the trajectory planning optimization problem into a dedicated embedded solver through an end-to-end compilation process. The system response time is reduced from 1000ms to the millisecond level, the computational complexity is reduced from O(n³) to O(n²), memory usage is reduced by more than 50%, and the deployment success rate reaches 100%. It meets the real-time and reliability requirements of scenarios such as UAV flight control and robot motion planning. At the same time, it has good cross-platform consistency and verifiable solution results, and supports bit-level comparison of PC simulation and embedded execution results as well as CRC (Cyclic Redundancy Check) verification.

[0097] This embodiment ensures the real-time and accuracy of data acquisition by precisely matching hardware acquisition capabilities with environmental parameter types. Combined with constraint verification and output adaptation, the target control solution not only meets optimization requirements but also adapts to the control system interface. At the same time, it relies on fault tolerance mechanisms to improve operational stability, providing an efficient and reliable execution basis for embedded real-time control.

[0098] In addition, this application also provides a compiler for a control system optimization problem; please refer to [reference needed]. Figure 4 , Figure 4 This is a schematic diagram of the structure of the control system optimization problem compilation device involved in the embodiments of this application. The control system optimization problem compilation device provided in this application is deployed in the control system, which also includes embedded hardware. The control system optimization problem compilation device includes: The data acquisition module H01 is used to acquire the problem to be compiled and optimized, and to identify the structural information and feature information of the problem to be compiled and optimized; The algorithm optimization module H02 is used to obtain the parameter information of the embedded hardware, and based on the structural information, the feature information and the parameter information, obtain the corresponding numerical solution algorithm and optimize the numerical solution algorithm to obtain the optimized numerical solution algorithm. The code conversion module H03 is used to convert the optimized numerical solution algorithm, the structural information and the parameter information into first embedded executable code without dynamic memory allocation; The code optimization module H04 is used to optimize the memory layout of the first embedded execution code to obtain the second embedded execution code after memory and cache optimization. The code compilation module H05 is used to compile the second embedded execution code into a binary file corresponding to the embedded hardware, and deploy the binary file to the embedded hardware; The parameter calculation module H06 is used to acquire environmental parameters, pass the environmental parameters to the target embedded hardware, and run the binary file through the target embedded hardware to obtain the target control solution of the optimization problem to be compiled based on the environmental parameters.

[0099] The control system optimization problem compilation apparatus provided in this application, employing the control system optimization problem compilation method in the above embodiments, can solve the control optimization problem that conflicts between real-time performance and resource adaptation. Compared with the prior art, the beneficial effects of the control system optimization problem compilation system provided in this application are the same as those of the control system optimization problem compilation method provided in the above embodiments, and other technical features of this control system optimization problem compilation system are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0100] In addition, this application also provides a control system. Please refer to... Figure 5 , Figure 5 This is a schematic diagram of the control system involved in the embodiments of this application.

[0101] This application provides a control system, which includes: at least one embedded hardware, a processor, and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the control system optimization problem compilation method in Embodiment 1 above.

[0102] The following is for reference. Figure 5 , Figure 5 This is a schematic diagram of the control system involved in the embodiments of this application, showing a schematic diagram of the control system suitable for implementing the embodiments of this application. Figure 5 The control system shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0103] like Figure 5As shown, the control system may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the control system. The processing device 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following devices can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows the control system to communicate wirelessly or wiredly with other devices to exchange data. Although a control system with various devices is shown in the figure, it should be understood that implementation or possession of all the devices shown is not required. More or fewer devices may be implemented alternatively.

[0104] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0105] The control system provided in this application employs the control system optimization problem compilation method in the above embodiments, which can solve the control optimization problem that conflicts between real-time performance and resource adaptation. Compared with the prior art, the beneficial effects of the control system provided in this application are the same as those of the control system optimization problem compilation method provided in the above embodiments, and other technical features of this control system are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0106] Furthermore, this application provides a computer-readable storage medium. This computer-readable storage medium stores a compiler for the control system optimization problem, which, when executed by a processor, implements the steps of the aforementioned compilation method for the control system optimization problem.

[0107] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0108] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0109] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0110] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A compilation method for a control system optimization problem, characterized in that, Applied to a control system, which includes embedded hardware, the compilation method for optimizing the control system includes: Obtain the problem to be compiled and optimized, and identify the structural and feature information of the problem to be compiled and optimized; Obtain the parameter information of the embedded hardware, and based on the structural information, the feature information and the parameter information, obtain the corresponding numerical solution algorithm and optimize the numerical solution algorithm to obtain the optimized numerical solution algorithm; The optimized numerical solution algorithm, the structural information, and the parameter information are transformed into first embedded execution code without dynamic memory allocation. The memory layout of the first embedded execution code is optimized for memory and cache to obtain the second embedded execution code with optimized memory and cache. The second embedded execution code is compiled into a binary file corresponding to the embedded hardware, and the binary file is deployed to the embedded hardware; The environment parameters are obtained and passed to the embedded hardware. The binary file is then run through the embedded hardware to obtain the target control solution of the problem to be compiled and optimized based on the environment parameters.

2. The compilation method for the control system optimization problem as described in claim 1, characterized in that, The structural information is a multi-stage association structure, and the feature information is the sparse distribution feature of the decision variables. The steps of obtaining the problem to be compiled and optimizing, and identifying the structural information and feature information of the problem to be compiled and optimized, include: The system receives a compilation optimization problem input by a user in a preset description, wherein the compilation optimization problem includes at least system dynamic equations and constraints. Based on the system dynamics equations, the multi-stage correlation structure is identified; Based on the constraints, the sparse distribution characteristics of the decision variables are identified.

3. The compilation method for the control system optimization problem as described in claim 2, characterized in that, The steps of obtaining parameter information of the embedded hardware, obtaining a corresponding numerical solution algorithm based on the structural information, the feature information, and the parameter information, and optimizing the numerical solution algorithm to obtain an optimized numerical solution algorithm include: Obtain parameter information of the embedded hardware, wherein the parameter information includes at least hardware computing power information, memory capacity information, cache structure information and instruction set architecture information; Determine the basic numerical solution algorithm that supports staged computation corresponding to the multi-stage association structure, and determine the sparse data processing logic unit corresponding to the basic numerical solution algorithm based on the sparse distribution characteristics of the decision variables. Determine the general computational logic in the basic numerical solution algorithm that corresponds to the hardware computing power information and the memory capacity information, and use the general computational logic as the numerical solution algorithm; Based on the cache structure information, the multi-stage association structure, and the instruction set architecture information, the sparse data processing logic unit and the numerical solution algorithm are jointly optimized to obtain the optimized numerical solution algorithm.

4. The compilation method for the control system optimization problem as described in claim 3, characterized in that, The step of converting the optimized numerical solution algorithm, the structural information, and the parameter information into first embedded executable code without dynamic memory allocation includes: The optimized numerical solution algorithm, the multi-stage correlation structure, and the memory capacity information are subjected to static memory planning processing to obtain a static memory planning scheme. Based on the static memory planning scheme, the optimized numerical solution algorithm, and the multi-stage association structure, the algorithm code is decomposed to obtain a modular algorithm code framework. Based on the modular algorithm code framework, the sparse distribution characteristics of the decision variables, and the instruction set architecture information, code integration and compatibility optimization are performed to obtain the first embedded execution code without dynamic memory allocation.

5. The compilation method for the control system optimization problem as described in claim 4, characterized in that, The step of optimizing the memory layout of the first embedded execution code to obtain the memory-optimized second embedded execution code includes: Based on the memory capacity information and the data access characteristics of the first embedded execution code, memory layout adjustment processing is performed to obtain the first intermediate code with optimized memory layout; Based on the cache structure information and the first intermediate code, cache adaptation optimization processing is performed to obtain the second intermediate code adapted to the cache. Based on the first intermediate code, the second intermediate code, and the instruction set architecture information, optimization logic integration processing is performed to obtain the second embedded execution code.

6. The compilation method for the control system optimization problem as described in claim 5, characterized in that, The step of compiling the second embedded execution code into a binary file corresponding to the embedded hardware and deploying the binary file to the embedded hardware includes: Based on the compilation adaptation parameters of the embedded hardware and the second embedded execution code, code compilation processing is performed to obtain the compiled binary file; The binary file is deployed to the embedded hardware according to the binary file and the deployment interface parameters of the embedded hardware.

7. The compilation method for the control system optimization problem as described in claim 6, characterized in that, The parameter information also includes the parameter acquisition capability of the embedded hardware. The steps of acquiring environmental parameters, transmitting the environmental parameters to the embedded hardware, and running the binary file through the embedded hardware to obtain the target control solution of the problem to be compiled and optimized based on the environmental parameters include: Based on the parameter acquisition capability and the environmental parameter type of the control system, obtain the environmental parameters when the binary file is executed; The target environment parameters are passed to the embedded hardware, and the binary file is run through the embedded hardware to calculate the control solution of the target environment parameters and verify the constraint satisfaction, so as to obtain the effective intermediate control solution of the optimization problem to be compiled. Based on the intermediate control solution and the output adaptation parameters of the control system, the intermediate control solution is format-converted and adapted to obtain and output the target control solution of the problem to be compiled and optimized.

8. A compiler for a control system optimization problem, characterized in that, The control system optimization problem compilation device is deployed in the control system, which also includes embedded hardware. The control system optimization problem compilation device includes: The data acquisition module is used to acquire the problem to be compiled and optimized, and to identify the structural information and feature information of the problem to be compiled and optimized; The algorithm optimization module is used to obtain the parameter information of the embedded hardware, and based on the structural information, the feature information and the parameter information, obtain the corresponding numerical solution algorithm and optimize the numerical solution algorithm to obtain the optimized numerical solution algorithm. The code conversion module is used to convert the optimized numerical solution algorithm, the structural information and the parameter information into first embedded executable code without dynamic memory allocation; The code optimization module is used to optimize the memory layout of the first embedded execution code to obtain the second embedded execution code after memory and cache optimization. The code compilation module is used to compile the second embedded execution code into a binary file corresponding to the embedded hardware, and to deploy the binary file to the embedded hardware; The parameter calculation module is used to acquire environmental parameters, pass the environmental parameters to the target embedded hardware, and run the binary file through the target embedded hardware to obtain the target control solution of the optimization problem to be compiled based on the environmental parameters.

9. A control system, characterized in that, The control system includes embedded hardware, a processor, a memory, and a control system optimization problem compiler stored in the memory that can be executed by the processor, wherein when the control system optimization problem compiler is executed by the processor, it implements the steps of the control system optimization problem compilation method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a compiler for the control system optimization problem, wherein when the compiler is executed by a processor, it implements the steps of the compilation method for the control system optimization problem as described in any one of claims 1 to 7.

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