Performance optimization method and system for MPI parallel application, medium and program product

Abstract

The invention discloses a performance optimization method and system for MPI parallel application, a medium and a program product. The method comprises the steps that PMU counter data, NUMA memory access data and network state data in an NUMA system are obtained; performing intelligent decision-making to determine performance bottleneck types and optimization actions of the NUMA system, wherein the performance bottleneck types comprise scheduling imbalance, memory competition and communication delay; and executing an optimization action under the determined performance bottleneck type to realize scheduling optimization on the MPI parallel application when the performance bottleneck type is scheduling imbalance, memory optimization on the MPI parallel application when the performance bottleneck type is memory competition, and network optimization on the MPI parallel application when the performance bottleneck type is communication delay. The invention aims to realize the performance breakthrough of MPI parallel application under the NUMA architecture with more than 128 cores through collaborative optimization and dynamic decision of multi-dimensional resources.

Description

Technical Field

[0001] This invention belongs to the field of application optimization technology in the field of computer software technology, specifically involving a performance optimization method, system, medium and program product for MPI parallel applications. Background Technology

[0002] With the popularization of multi-core CPUs and distributed computing, MPI applications in fields such as meteorological simulation and molecular dynamics face the following key challenges: (1) Scheduling imbalance: The traditional Linux scheduler (CFS) does not recognize the communication dependencies between MPI processes and may migrate processes between different NUMA nodes. Process migration destroys data locality, making data already loaded on a certain node need to be accessed across nodes, thus causing a sharp increase in remote memory access latency. (2) Memory contention: Concurrent access to memory by multiple processes leads to increased bandwidth contention. When using the default 4KB small pages, the TLB hit rate decreases and the page table traversal overhead increases. For example, in a scenario with 128 processes in parallel, the TLB miss rate may surge, and the system overhead increases significantly. (3) Network communication latency: MPI communication is usually based on the TCP / IP protocol stack, and the transmission of a large amount of data in kernel mode generates significant overhead. Collective communication operations (such as MPI_Bcast) are easily affected by buffer configuration and protocol efficiency, and communication performance becomes one of the application performance bottlenecks. In large-scale multi-core NUMA architectures, each CPU core can access the local memory of its own node quickly, but accessing remote nodes requires an interconnect bus, significantly increasing latency. Existing technology discloses a multi-task scheduling and management system for NUMA architectures, comprising multiple nodes. One node deploys a service component and a scheduling component, while another deploys an execution component. Users generate task lists based on task requirements. The scheduling component can balance user task priorities, ensure CPUs prioritize access to local node memory, and balance load across nodes, effectively preventing CPUs from accessing memory across nodes. However, the task scheduling management in these existing technologies only focuses on optimizing CPU affinity under NUMA architectures and does not address memory bandwidth isolation or network protocol acceleration. How to achieve better performance optimization for MPI parallel applications remains a critical technical problem that urgently needs to be solved. Summary of the Invention

[0003] The technical problem to be solved by this invention is to provide a performance optimization method, system, medium and program product for MPI parallel applications, which addresses the above-mentioned problems in the prior art. This invention aims to achieve a performance breakthrough for MPI parallel applications under a NUMA architecture with more than 128 cores through multi-dimensional resource collaborative optimization and dynamic decision-making.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A performance optimization method for MPI parallel applications includes the following steps: S101, obtain PMU counter data, NUMA memory access data and network status data in the NUMA system; S102, intelligent decision-making is performed based on PMU counter data, NUMA memory access data and network status data to determine the performance bottleneck type of the NUMA system and its optimization actions. The performance bottleneck type includes scheduling imbalance, memory contention and communication latency. S103, execute optimization actions under the determined performance bottleneck type, so as to optimize the scheduling of MPI parallel application when the performance bottleneck type is scheduling imbalance, optimize the memory of MPI parallel application when the performance bottleneck type is memory contention, and optimize the network of MPI parallel application when the performance bottleneck type is communication latency.

[0005] Optionally, the PMU counter data in step S101 includes L1 cache hit rate, the NUMA memory access data includes cross-NUMA access ratio, and the network status data includes network throughput; step S102, when making intelligent decisions based on PMU counter data, NUMA memory access data, and network status data to determine the performance bottleneck type of the NUMA system and its optimization actions, includes determining the performance bottleneck type of the NUMA system based on L1 cache hit rate, cross-NUMA access ratio, and network throughput using a decision tree: S201, determine whether the L1 cache hit rate is less than the preset threshold. If it is, determine that the performance bottleneck of the NUMA system is memory contention and jump to step S103; otherwise, jump to step S202. S202, determine whether the cross-NUMA access ratio is greater than the preset threshold. If it is, determine that the performance bottleneck of the NUMA system is scheduling imbalance and jump to step S103; otherwise, jump to step S203. S203, determine whether the network throughput is less than the preset threshold. If it is, determine that the performance bottleneck of the NUMA system is communication delay and jump to step S103; otherwise, maintain the current configuration, end and exit.

[0006] Optionally, when making intelligent decisions based on PMU counter data, NUMA memory access data, and network state data to determine the performance bottleneck type of the NUMA system and its optimization actions in step S102, the following steps are taken: using the PMU counter data, NUMA memory access data, and network state data in the NUMA system as the "system state" of the reinforcement learning algorithm model; using the optimization actions under various performance bottleneck types as the "actions" of the reinforcement learning algorithm model; and using the pre-trained reinforcement learning algorithm model to decide on the "action" to be executed based on the current "system state". After step S103, the following steps are taken: obtaining the performance improvement of the MPI parallel application after the NUMA system executes the optimization action as the "reward" of the reinforcement learning algorithm model; and using the obtained "reward" to update the model parameters of the reinforcement learning algorithm model.

[0007] Optionally, when step S102 makes intelligent decisions based on PMU counter data, NUMA memory access data, and network status data to determine the performance bottleneck type of the NUMA system and its optimization actions, the optimization actions when the performance bottleneck type is scheduling imbalance include: adjusting the CPU affinity of the MPI parallel application process, binding the MPI parallel application process to the NUMA node, and starting and stopping hyper-threading; the optimization actions when the performance bottleneck type is memory contention include: adaptively adjusting the memory page size configuration of the memory pages where hot spots occur, and executing the hot memory page local copying mechanism between NUMA nodes to copy the hot memory pages to the memory of the NUMA node where the MPI parallel application process is located; the optimization actions when the performance bottleneck type is communication latency include: accelerating MPI communication through the shared memory protocol SMC under the premise of supporting the shared memory protocol SMC, and binding the network card interrupt to the NUMA node where the MPI parallel application process is located.

[0008] Optionally, the adaptive adjustment of the memory page size configuration for hotspot occurrences includes: using a sliding window to count the access frequency of each memory page or memory segment, determining the size of hotspot pages whose access frequency exceeds a threshold; if the size of a hotspot page whose access frequency exceeds the threshold is the default size, then switching the area containing the hotspot page whose access frequency exceeds the threshold to a preset larger page; if the size of a hotspot page whose access frequency exceeds the threshold is the preset larger page size, then switching the area containing the hotspot page whose access frequency exceeds the threshold to a preset maximum page; if the size of a non-hotspot page whose access frequency does not exceed the threshold is a non-default size, then restoring it to the default size.

[0009] Optionally, accelerating MPI communication via the Shared Memory Protocol (SMC) while supporting SMC includes: S201, the first MPI process A of the MPI parallel application sends a TCP synchronization request message to the second MPI process B. S202, the second MPI process B returns TCP synchronization request and response messages to the first MPI process A; S203, the first MPI process A returns a TCP response message carrying the negotiation options for the Shared Memory Protocol (SMC) to the second MPI process B. Provided that both the first MPI process A and the second MPI process B support the SMC protocol, they continue to create an RDMA connection in user mode. S204, when the first MPI process A sends a message to the second MPI process B, it uses the remote memory direct access write operation with immediate value in the remote memory direct access protocol to merge the data and description information of multiple small messages smaller than the preset threshold and send them together, so that the second MPI process B can directly obtain the data of multiple small messages from memory.

[0010] Optionally, the hot memory page local copying mechanism between NUMA nodes, which copies hot memory pages to the memory of the NUMA node where the MPI parallel application process resides, includes: S301, the first MPI process A of the MPI parallel application accesses the target hot memory page X, obtains the data of the target hot memory page X and stores it in the first NUMA node A where the first MPI process A is located; S302, when the second MPI process B of the MPI parallel application accesses the target hot memory page X across nodes, the data of the target hot memory page X is recorded by the page replicator, and the data of the target hot memory page X is copied to the memory of the second NUMA node B where the second MPI process B is located; S303, when the second MPI process B of the MPI parallel application accesses the target hot memory page X across nodes again, the local copy page is directly hit in the memory of the second NUMA node B to avoid cross-node access.

[0011] The present invention also provides a performance optimization system for MPI parallel applications, including an interconnected microprocessor and a memory, wherein the microprocessor is programmed or configured to execute the performance optimization method for the MPI parallel application.

[0012] The present invention also provides a computer-readable storage medium storing a computer program or instructions that are programmed or configured to execute a performance optimization method for the MPI parallel application via a processor.

[0013] The present invention also provides a computer program product, including a computer program or instructions that are programmed or configured to perform a performance optimization method for the MPI parallel application via a processor.

[0014] Compared with existing technologies, this invention mainly achieves the following beneficial effects: 1. By linking and coordinating the optimization of scheduling, memory, and network resources, this invention avoids the bottlenecks caused by single-dimensional optimization, such as simply optimizing CPU affinity while ignoring memory bandwidth contention. It improves the execution efficiency of MPI applications through cross-level, multi-dimensional intelligent optimization strategies. 2. This invention uses intelligent decision-making based on PMU counter data, NUMA memory access data, and network status data to determine the performance bottleneck type of the NUMA system and its optimization actions. It achieves intelligent decision-making based on real-time collected performance data (such as PMU events, NUMA memory access statistics, network throughput, etc.), enabling dynamic adaptive adjustment of optimization strategies. 3. This invention supports deployment in multiple types of MPI applications and under different hardware architectures, offering good compatibility. 4. This invention can further utilize the results of executing optimization actions under the determined performance bottleneck type to optimize the decision-making of optimization actions, enabling the optimization system to have continuous learning capabilities and iteratively update strategies based on optimization feedback, thus bringing the performance tuning scheme closer to the optimal level. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the basic process of the method in an embodiment of the present invention.

[0016] Figure 2 This is a flowchart illustrating how intelligent decision-making using decision trees determines the performance bottleneck type of a NUMA system in an embodiment of the present invention.

[0017] Figure 3 This is a flowchart illustrating the workflow of the reinforcement learning algorithm model in this embodiment of the invention.

[0018] Figure 4 This is a flowchart illustrating the acceleration of MPI communication via the Shared Memory Protocol (SMC) in an embodiment of the present invention.

[0019] Figure 5 This is a flowchart illustrating the local copying mechanism of hot memory pages in an embodiment of the present invention.

[0020] Figure 6 This is a schematic diagram of the three-layer collaborative optimization architecture in an embodiment of the present invention. Detailed Implementation

[0021] The performance optimization method for MPI parallel applications in this embodiment aims to achieve coordinated optimization across three dimensions: scheduling, memory, and network. To enable those skilled in the art to better understand the technical solution of this invention, the following will provide a more detailed description of the technical solution in conjunction with the accompanying drawings of the embodiments of this invention.

[0022] like Figure 1 As shown, the performance optimization method for MPI parallel applications in this embodiment includes the following steps: S101, obtain PMU counter data, NUMA memory access data and network status data in the NUMA system; S102, intelligent decision-making is performed based on PMU counter data, NUMA memory access data and network status data to determine the performance bottleneck type of the NUMA system and its optimization actions. The performance bottleneck type includes scheduling imbalance, memory contention and communication latency. S103, execute optimization actions under the determined performance bottleneck type, so as to optimize the scheduling of MPI parallel application when the performance bottleneck type is scheduling imbalance, optimize the memory of MPI parallel application when the performance bottleneck type is memory contention, and optimize the network of MPI parallel application when the performance bottleneck type is communication latency.

[0023] In step S101 of this embodiment, when obtaining PMU counter data, NUMA memory access data, and network status data in the NUMA system, the PMU counter data, NUMA memory access data, and network status data can adopt the required indicators as needed. For example, as an optional implementation, the PMU counter data in step S101 of this embodiment includes L1 cache hit rate, the NUMA memory access data includes cross-NUMA access ratio, and the network status data includes network throughput. Specifically, obtaining the PMU counter data, NUMA memory access data, and network status data in step S101 of this embodiment involves subscribing to the required hardware performance events (PMU counter data, NUMA memory access data, and network status data) through the interface of the oeAware-manager framework. The specific implementation code is as follows: Subscribe("pmu", {"L1D_CACHE_MISS", "IPC"}); Subscribe("numa", {"cross_node_access"}); Subscribe("net", {"throughput"}); In this context, Subscribe is the subscription function in the oeAware-manager framework. "pmu", "numa", and "net" refer to PMU counter data, NUMA memory access data, and network status data, respectively. "L1D_CACHE_MISS" is the L1 cache hit rate, "IPC" is the number of instructions per cycle (unused), "cross_node_access" is the cross-NUMA access ratio, and "throughput" is the network throughput. Real-time data is published to a shared queue for use in intelligent decision-making.

[0024] like Figure 2As shown, in step S102 of this embodiment, when making intelligent decisions based on PMU counter data, NUMA memory access data, and network status data to determine the performance bottleneck type and optimization actions of the NUMA system, a decision tree is first used to perform multi-level judgments on the current performance characteristics, and then the corresponding optimization modules are triggered. If the L1 cache hit rate is insufficient, memory optimization is prioritized; if the cross-NUMA access ratio is too high, scheduling optimization is performed; if the network throughput is below the threshold, network optimization is performed. After each optimization module is executed, new performance data is re-collected for use in the next round of decision-making. Specifically, determining the performance bottleneck type of the NUMA system through the decision tree based on the L1 cache hit rate, cross-NUMA access ratio, and network throughput includes: S201, determine whether the L1 cache hit rate is less than a preset threshold (which can be set according to actual needs, for example, 70%). If it is true, determine that the performance bottleneck of the NUMA system is memory contention and jump to step S103; otherwise, jump to step S202. S202, determine whether the cross-NUMA access ratio is greater than a preset threshold (which can be set according to actual needs, for example, 20%). If it is true, determine that the performance bottleneck of the NUMA system is scheduling imbalance and jump to step S103; otherwise, jump to step S203. S203, determine whether the network throughput is less than a preset threshold (the value can be set according to actual needs, such as 50%). If it is true, determine that the performance bottleneck of the NUMA system is communication delay and jump to step S103; otherwise, maintain the current configuration, end and exit.

[0025] In step S102 of this embodiment, a reinforcement learning mechanism is introduced. When making intelligent decisions based on PMU counter data, NUMA memory access data, and network state data to determine the performance bottleneck type of the NUMA system and its optimization actions, step S102 includes using the PMU counter data, NUMA memory access data, and network state data (such as L1 hit rate, cross-node access ratio, communication latency, etc.) in the NUMA system as the "system state" of the reinforcement learning algorithm model, and using the optimization actions under various performance bottleneck types (adjusting affinity, switching between large pages or duplicate pages, enabling SMC, etc.) as the "actions" of the reinforcement learning algorithm model. The pre-trained reinforcement learning algorithm model decides to obtain the "action" that needs to be executed based on the current "system state". After step S103, the method further includes obtaining the performance improvement of the MPI parallel application after the NUMA system executes the optimization action as the "reward" of the reinforcement learning algorithm model, and using the obtained "reward" to update the model parameters of the reinforcement learning algorithm model. Figure 3The "Decision Agent" in this embodiment refers to the intelligent agent of the reinforcement learning algorithm model. It can employ reinforcement learning algorithms such as Q-learning. The "current performance state," composed of PMU counter data, NUMA memory access data, and network state data from the NUMA system, is used as input to the "Decision Agent." Based on the current "system state," the "Decision Agent" decides which "action" needs to be performed. Then, by executing the optimization action under the determined performance bottleneck type, it obtains "performance feedback" as a "reward" for the "Decision Agent." This reward is used to update the model parameters of the reinforcement learning algorithm model. After multiple rounds of optimization iterations, the resource allocation strategy is updated, continuously approaching the optimal configuration. Thus, the intelligent decision in step S102 not only relies on the static decision tree threshold but also utilizes historical optimization feedback to "learn" more effective scheduling and resource allocation strategies. Similar studies have shown that machine learning models such as decision trees and neural networks can predict MPI optimization parameters and significantly improve performance (achieving over 90% speedup). This embodiment extends this approach to online dynamic tuning. Through this reinforcement learning closed loop, the adaptive optimization strategy can continuously evolve based on real-time feedback: initially, initial rules provided by the decision tree can be used; as feedback accumulates, the reinforcement learning agent autonomously discovers better resource allocation schemes, solving complex optimization scenarios that are difficult to cover with static rules. This mechanism enables this embodiment to maintain high optimization efficiency under varying MPI application loads.

[0026] When making intelligent decisions based on PMU counter data, NUMA memory access data and network status data in step S102 to determine the performance bottleneck type of the NUMA system and its optimization actions, (1) when the performance bottleneck type is scheduling imbalance, the optimization actions include: adjusting the CPU affinity of the MPI parallel application process, binding the MPI parallel application process to the NUMA node and starting and stopping hyperthreads; (2) when the performance bottleneck type is memory contention, the optimization actions include: adaptively adjusting the memory page size configuration of the memory pages where hot spots appear, executing the hot memory page local copying mechanism between NUMA nodes to copy the hot memory pages to the memory of the NUMA node where the MPI parallel application process is located; (3) when the performance bottleneck type is communication latency, the optimization actions include: accelerating MPI communication through the shared memory protocol SMC under the premise of supporting the shared memory protocol SMC, and binding the network card interrupt to the NUMA node where the MPI parallel application process is located.

[0027] In optimization actions when the performance bottleneck is scheduling imbalance, the CPU affinity of MPI processes can be dynamically adjusted based on the real-time load of each NUMA node. For example, `sched_setaffinity` can be called to bind processes to the corresponding CPU set. Hyper-threading can be dynamically enabled or disabled as needed to balance the load and reduce cache conflicts. Through process binding and affinity settings, threads are guaranteed to access local memory as much as possible. Furthermore, hyper-threading (SMT) can be enabled or disabled as needed to balance the load and improve cache and memory access locality. Traditional operating system schedulers allow thread migration in NUMA systems to improve load balancing, but this may lead to data and thread separation, thereby reducing performance. This embodiment avoids this problem through dynamic binding.

[0028] In this embodiment, the optimization actions for memory contention as a performance bottleneck specifically include two parts: AdaptiveHugepageManager automatically switches the size of large pages based on recent page access frequency; PageReplicator records the access count of each memory page, and when a page is detected as a hotspot and frequently accessed across nodes, it is copied to the memory of the NUMA node where the accessing process resides. This significantly reduces remote memory access latency and improves bandwidth utilization when sharing data among multiple processes.

[0029] To address the frequent memory accesses in large-scale parallel applications, this embodiment proposes a dynamic big-page switching algorithm to adaptively adjust the memory page size configuration for hotspot memory pages. By utilizing hardware monitoring to statistically analyze page access frequency, the algorithm automatically switches to larger pages when hotspots occur, reducing TLB misses and page table traversal overhead. Simultaneously, memory pages frequently accessed remotely by multiple processes are locally copied to the NUMA node memory of each requesting process, further reducing cross-node access latency and improving memory locality. In this embodiment, the adaptive adjustment of the memory page size configuration for hotspot memory pages includes: using a sliding window to statistically analyze the access frequency of each memory page or memory segment, determining the size of hotspot pages whose access frequency exceeds a threshold; if the size of a hotspot page exceeding the threshold is the default size, then the region containing the hotspot page exceeding the threshold is switched to a preset larger page; if the size of a hotspot page exceeding the threshold is the preset larger page size, then the region containing the hotspot page exceeding the threshold is switched to a preset maximum page; if the size of a non-hotspot page whose access frequency does not exceed the threshold is not the default size, then it is restored to the default size. For example, as an optional implementation, a sliding window is used to count the access frequency of each memory page or segment. Hot pages with access frequencies exceeding a threshold are switched to larger pages (2MB) to reduce TLB misses. When the system has sufficient total memory and 2MB pages are currently in use, a larger 1GB page is then switched to accommodate the large dataset. This dynamic large page switching algorithm adaptively adjusts the memory page size configuration for hot pages, reducing memory page management and TLB overhead. Compared to traditional static configuration, this embodiment can flexibly adjust large page usage at runtime based on actual access patterns, significantly improving memory access efficiency.

[0030] In optimization actions where the performance bottleneck is communication latency, after the process establishes a TCP connection, `enable_smc_acceleration` is called to check if the peer supports Shared Memory Communication (SMC). If it does, the module switches to SMC communication and uses `RDMA_WRITE_WITH_IMMEDIATE` to merge data and control information when sending small messages, achieving zero-copy transmission. Furthermore, the module can bind network card interrupts to the CPU of the NUMA node where the MPI process resides to optimize network I / O locality. To achieve zero-copy acceleration in MPI communication using the Shared Memory Communication (SMC) protocol, this embodiment checks whether the peer supports the SMC protocol during the MPI communication connection establishment phase. If it does, it switches to the SMC / RDMA channel and uses the `RDMA_WRITE_WITH_IMMEDIATE` feature to merge data and control information for transmission, achieving zero-copy data transmission and significantly reducing communication overhead. Figure 4As shown, in this embodiment, accelerating MPI communication through the Shared Memory Protocol (SMC) while supporting SMC includes: S201, the first MPI process A of the MPI parallel application sends a TCP synchronization request message to the second MPI process B. S202, the second MPI process B returns TCP synchronization request and response messages to the first MPI process A; S203, the first MPI process A returns a TCP response message carrying the negotiation options for the Shared Memory Protocol (SMC) to the second MPI process B. Provided that both the first MPI process A and the second MPI process B support the SMC protocol, they continue to create an RDMA connection in user mode. S204, when the first MPI process A sends a message to the second MPI process B, it uses the Remote Memory Direct Access (RDMA_WRITE_WITH_IMMEDIATE) write operation with immediate values ​​in the Remote Memory Direct Access protocol to merge the data and description information of multiple small messages and send them together, so that the second MPI process B can directly obtain the data of multiple small messages from memory. For example... Figure 4 As shown, after a regular TCP three-way handshake, MPI processes carry the SMC negotiation option in the second handshake (ACK) message. If both parties support the SMCv2.1 protocol, an RDMA connection is created in user space (including the establishment of queue pairs (QP) and memory regions (MR)). After establishing the RDMA channel, the system uses the remote memory direct access write operation (RDMA_WRITE_WITH_IMMEDIATE) to merge data and description information for small messages (<1KB), reducing the number of packets and kernel switching. Throughout the process, SMC is compatible with the standard socket interface and can transparently replace TCP, allowing applications to enjoy performance improvements without any modifications. Furthermore, in this embodiment, network card interrupts are bound to the NUMA node where the MPI process's thread resides, localizing network interrupt handling and reducing latency caused by cross-node interrupt transfer, thus improving network I / O affinity and throughput efficiency. Through these measures, this embodiment achieves significant communication performance improvements without modifying the MPI application code.

[0031] In addition to using big-page optimization, this embodiment also introduces a page replication mechanism for cross-node shared data. The system monitors the access frequency of each memory page across different processes. Once it detects that a page is frequently accessed remotely by multiple processes, it can replicate the page to the NUMA node where the requesting process resides. Figure 5As shown, in this embodiment, the hot memory page local copying mechanism between NUMA nodes to copy hot memory pages to the memory of the NUMA node where the MPI parallel application process resides includes: S301, the first MPI process A of the MPI parallel application accesses the target hot memory page X, obtains the data of the target hot memory page X and stores it in the first NUMA node A where the first MPI process A is located; S302, when the second MPI process B of the MPI parallel application accesses the target hot memory page X across nodes, the data of the target hot memory page X is recorded by the page replicator, and the data of the target hot memory page X is copied to the memory of the second NUMA node B where the second MPI process B is located; S303, when the second MPI process B of the MPI parallel application accesses the target hot memory page X across nodes again, it directly hits the locally copied page in the memory of the second NUMA node B to avoid cross-node access. In this way, this embodiment further improves the locality of memory access, keeping a copy of the data shared by multiple processes on each node, fundamentally reducing cross-node access latency.

[0032] Figure 6 This is a schematic diagram of the three-layer collaborative optimization architecture in this embodiment. See also... Figure 6The three-layer collaborative optimization architecture of this embodiment includes: (1) Data acquisition layer: Through the plugin mechanism of the oeAware-manager framework, it subscribes to and collects performance indicators such as PMU counters (e.g., cache hit / miss events), NUMA memory access statistics (e.g., cross-node access ratio) and network throughput in real time. (2) Intelligent decision layer: Based on the intelligent decision engine composed of C4.5 decision tree and reinforcement learning, it analyzes the collected feature vectors and identifies the main performance bottleneck types of MPI applications. The decision layer uses the decision tree for fast classification and judgment, and introduces reinforcement learning components to continuously update the scheduling and resource allocation strategies based on the performance feedback of previous optimizations. (3) Execution optimization layer: It consists of a scheduling optimization module, a memory optimization module and a network optimization module. Each module performs specific optimization actions in conjunction with the bottleneck type output by the decision layer. The optimization actions include: scheduling optimization (dynamically adjusting the CPU affinity between the MPI process and NUMA nodes and starting / stopping SMT threads); memory optimization (adaptively switching the large page size based on page access frequency, while simultaneously copying hot pages locally); and network optimization (negotiating the SMC protocol and using RDMA_WRITE_WITH_IMMEDIATE to accelerate communication, while binding network card interrupts to the corresponding NUMA nodes). The execution layer sends the optimized performance data back to the data acquisition layer through a feedback mechanism, forming a closed-loop iterative optimization. The decision engine of the intelligent decision layer feeds the input feature vectors (including L1 cache hit rate, cross-NUMA access ratio, network throughput, etc.) into the decision tree for bottleneck classification, while the reinforcement learning agent simultaneously learns and optimizes the strategy. The decision tree primarily uses fast threshold judgment (e.g., low L1 hit rate triggers memory optimization, high cross-node access triggers scheduling optimization, and low network utilization triggers network optimization), while reinforcement learning continuously improves the strategy based on historical feedback. Each optimization module executes corresponding actions based on the decision results and feeds the new performance indicators back to the intelligent decision layer, forming an adaptive adjustment closed loop. The deployment steps of the three-layer collaborative optimization architecture in this embodiment include: (1) compiling the plugin: implementing the above core module as an oeAware-manager plugin, such as libmpi_tune.so, and installing it in the system plugin directory; (2) configuring oeAware-manager: editing the oeAware configuration file, loading the libmpi_tune.so plugin, and setting an appropriate running cycle; (3) starting monitoring: running oeawarectl to load and start the plugin, and the system enters the closed-loop adaptive optimization state.

[0033] The performance optimization method for MPI parallel applications in this embodiment significantly improves the performance of MPI applications in a multi-NUMA node environment through cross-layer and multi-modal collaborative optimization means. Experimental results show that after optimization, the running time of typical applications such as OpenFOAM fluid simulation is on average shortened by more than 10% compared with that before optimization; the MPI collective communication latency is significantly reduced; the remote memory access ratio is reduced by dozens of percentage points. At the same time, after introducing the reinforcement learning algorithm model, the performance pattern can be continuously learned in multiple rounds of iteration, and the optimization effect is further improved over time. Compared with traditional single optimization methods, the performance optimization method for MPI parallel applications in this embodiment provides a more comprehensive way to improve performance while ensuring compatibility.

[0034] In summary, the innovation points of the method in this embodiment are mainly reflected in the following structural and functional combinations: First, the "three-layer collaborative optimization architecture" (data collection layer, intelligent decision-making layer, execution optimization layer) proposed in this embodiment is a system structure not available in the prior art. This architecture realizes a real-time closed-loop feedback control mechanism from performance collection, intelligent analysis to resource adjustment, which is different from the traditional one-way monitoring-based tuning framework and can complete the full-link optimization of collection - decision - execution - feedback within 100 ms. Second, a dual-model fusion structure of "decision tree + reinforcement learning" is introduced in the intelligent decision-making layer of this embodiment, realizing the self-learning and adaptive adjustment of performance optimization strategies. This combined structure has the ability of online evolution and can automatically update scheduling and resource strategies according to real-time feedback, breaking through the existing decision-making methods based on static rules or fixed thresholds, which belongs to an innovation at the algorithm layer. Third, a dual-mechanism structure of "adaptive large page switching + local replication of hot pages" is constructed in the memory optimization module. The former dynamically selects 2MB or 1GB large pages based on page access frequency, and the latter actively copies hot pages to the local NUMA node when multi-process remote access is frequent. The two work together to improve the TLB hit rate while reducing cross-node access latency, which is not seen in the existing kernel-level memory management solutions. In addition, the MPI communication acceleration structure based on the SMC protocol proposed in this embodiment is also not available in the prior art. This mechanism automatically negotiates the SMC channel during the TCP connection establishment process, constructs an RDMA data path in the user state and uses RDMA_WRITE_WITH_IMMEDIATE to achieve zero-copy transmission, combined with the NUMA binding of network card interrupts, forming a transparent protocol layer acceleration system that can take effect without modifying MPI applications. Finally, each module in this embodiment realizes cross-dimensional linkage optimization through the publish / subscribe mechanism of oeAware-manager, enabling three types of resources, namely CPU scheduling, memory access, and network communication, to work together under the same optimization logic.

[0035] Furthermore, this embodiment also provides a performance optimization system for MPI parallel applications, including a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to execute the performance optimization method for the MPI parallel application. This embodiment also provides a computer-readable storage medium storing a computer program or instructions programmed or configured to execute the performance optimization method for the MPI parallel application via a processor. This embodiment also provides a computer program product, including a computer program or instructions programmed or configured to execute the performance optimization method for the MPI parallel application via a processor.

[0036] Those skilled in the art will understand that the technical solutions provided by this invention may take the form of a method, system, or computer program product. Therefore, this invention may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this invention may take the form of a computer program product embodied on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, produce an implementation of the flowchart... Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0037] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A performance optimization method for MPI parallel applications, characterized in that, Includes the following steps: S101, obtain PMU counter data, NUMA memory access data and network status data in the NUMA system; S102, intelligent decision-making is performed based on PMU counter data, NUMA memory access data and network status data to determine the performance bottleneck type of the NUMA system and its optimization actions. The performance bottleneck type includes scheduling imbalance, memory contention and communication latency. S103, execute optimization actions under the determined performance bottleneck type, so as to optimize the scheduling of MPI parallel application when the performance bottleneck type is scheduling imbalance, optimize the memory of MPI parallel application when the performance bottleneck type is memory contention, and optimize the network of MPI parallel application when the performance bottleneck type is communication latency.

2. The performance optimization method for MPI parallel applications according to claim 1, characterized in that, The PMU counter data in step S101 includes L1 cache hit rate, the NUMA memory access data includes cross-NUMA access ratio, and the network status data includes network throughput. Step S102, when making intelligent decisions based on the PMU counter data, NUMA memory access data, and network status data to determine the performance bottleneck type of the NUMA system and its optimization actions, includes determining the performance bottleneck type of the NUMA system using a decision tree based on the L1 cache hit rate, cross-NUMA access ratio, and network throughput. S201, determine whether the L1 cache hit rate is less than the preset threshold. If it is, determine that the performance bottleneck of the NUMA system is memory contention, and jump to step S103. Otherwise, proceed to step S202; S202, determine whether the cross-NUMA access ratio is greater than the preset threshold. If it is true, determine that the performance bottleneck of the NUMA system is scheduling imbalance, and jump to step S103. Otherwise, proceed to step S203; S203, determine whether the network throughput is less than the preset threshold. If it is, determine that the performance bottleneck of the NUMA system is communication delay and jump to step S103; otherwise, maintain the current configuration, end and exit.

3. The performance optimization method for MPI parallel applications according to claim 1, characterized in that, Step S102, when making intelligent decisions based on PMU counter data, NUMA memory access data, and network state data to determine the performance bottleneck type of the NUMA system and its optimization actions, includes using the PMU counter data, NUMA memory access data, and network state data in the NUMA system as the "system state" of the reinforcement learning algorithm model, and using the optimization actions under various performance bottleneck types as the "actions" of the reinforcement learning algorithm model. The pre-trained reinforcement learning algorithm model decides to obtain the "action" that needs to be executed based on the current "system state". After step S103, it also includes obtaining the performance improvement degree of the MPI parallel application after the NUMA system executes the optimization action as the "reward" of the reinforcement learning algorithm model, and using the obtained "reward" to update the model parameters of the reinforcement learning algorithm model.

4. The performance optimization method for MPI parallel applications according to claim 1, characterized in that, When step S102 uses PMU counter data, NUMA memory access data, and network status data to make intelligent decisions to determine the performance bottleneck type of the NUMA system and its optimization actions, the optimization actions for performance bottleneck type of scheduling imbalance include: adjusting the CPU affinity of the MPI parallel application process, binding the MPI parallel application process to the NUMA node, and starting and stopping hyper-threading; the optimization actions for performance bottleneck type of memory contention include: adaptively adjusting the memory page size configuration of memory pages where hot spots occur, and executing the hot memory page local copying mechanism between NUMA nodes to copy the hot memory pages to the memory of the NUMA node where the MPI parallel application process is located; the optimization actions for performance bottleneck type of communication latency include: accelerating MPI communication through the shared memory protocol SMC under the premise of supporting the shared memory protocol SMC, and binding the network card interrupt to the NUMA node where the MPI parallel application process is located.

5. The performance optimization method for MPI parallel applications according to claim 4, characterized in that, The adaptive adjustment of memory page size configuration for hotspot occurrences includes: using a sliding window to count the access frequency of each memory page or memory segment, determining the size of hotspot pages whose access frequency exceeds a threshold; if the size of a hotspot page whose access frequency exceeds the threshold is the default size, then switching the area containing the hotspot page whose access frequency exceeds the threshold to a preset larger page; if the size of a hotspot page whose access frequency exceeds the threshold is the preset larger page size, then switching the area containing the hotspot page whose access frequency exceeds the threshold to a preset maximum page; if the size of a non-hotspot page whose access frequency does not exceed the threshold is not the default size, then restoring it to the default size.

6. The performance optimization method for MPI parallel applications according to claim 4, characterized in that, The method of accelerating MPI communication via the Shared Memory Protocol (SMC) while supporting the SMC protocol includes: S201, the first MPI process of the MPI parallel application sends a TCP synchronization request message to the second MPI process; S202, the second MPI process returns TCP synchronization request and response messages to the first MPI process; S203, the first MPI process returns a TCP response message carrying the negotiation options for the Shared Memory Protocol (SMC) to the second MPI process. Provided that both the first and second MPI processes support the SMC protocol, they continue to establish RDM connections in user space. S204, when the first MPI process sends a message to the second MPI process, it uses the remote memory direct access write operation with immediate value in the remote memory direct access protocol to merge the data and description information of multiple small messages smaller than the preset threshold and send them together, so that the second MPI process can directly obtain the data of multiple small messages from memory.

7. The performance optimization method for MPI parallel applications according to claim 4, characterized in that, The hot memory page local copying mechanism between NUMA nodes copies hot memory pages to the memory of the NUMA node where the MPI parallel application process resides, including: S301, the first MPI process of the MPI parallel application accesses the target hot memory page, obtains the data of the target hot memory page, and stores it in the first NUMA node where the first MPI process is located; S302, when the second MPI process of the MPI parallel application accesses the target hot memory page across nodes, the data of the target hot memory page is recorded by the page replicator and copied to the memory of the second NUMA node where the second MPI process is located; S303: When the second MPI process of the MPI parallel application accesses the target hot memory page across nodes again, it directly hits the local copy page in the memory of the second NUMA node to avoid cross-node access.

8. A performance optimization system for MPI parallel applications, comprising interconnected microprocessors and memory, characterized in that, The microprocessor is programmed or configured to execute the performance optimization method for the MPI parallel application according to any one of claims 1 to 7.

9. A computer-readable storage medium storing a computer program or instructions, characterized in that, The computer program or instructions are programmed or configured to execute, via a processor, the performance optimization method for the MPI parallel application described in any one of claims 1 to 7.

10. A computer program product, comprising a computer program or instructions, characterized in that, The computer program or instructions are programmed or configured to execute, via a processor, the performance optimization method for the MPI parallel application described in any one of claims 1 to 7.

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