Deep space exploration low-power-consumption AI navigation algorithm processing system based on storage and calculation integrated architecture

Abstract

The invention discloses a deep space exploration low-power-consumption AI navigation algorithm processing system based on a storage and calculation integrated architecture, the system adopts the storage and calculation integrated architecture based on RRAM cross arrays and calculates an AI navigation algorithm, the system comprises an RRAM storage and calculation core, a dynamic configuration PE array, an anti-radiation controller and an on-chip storage interaction unit, the RRAM storage and calculation core comprises a plurality of independent RRAM cross arrays, in-situ execution of matrix-vector multiplication and vector-matrix multiplication is supported; the dynamic configuration PE array is used for processing nonlinear operation, and dynamic switching of two parallel granularity modes of 16 * 16 and 4 * 4 is supported through a configuration register; the anti-radiation controller is used for repairing radiation induction errors in real time and coordinating task scheduling of the storage and calculation core and the PE array; and the on-chip storage interaction unit adopts an SRAM (Static Random Access Memory) as an intermediate cache and is used for temporarily storing intermediate data. The problem of high power consumption of an AI navigation system for extreme environment detection can be solved.

Description

Technical Field

[0001] This invention belongs to the field of deep space exploration and artificial intelligence hardware co-design technology, and more specifically relates to a low-power AI navigation algorithm processing system for deep space exploration based on an in-memory computing architecture. Background Technology

[0002] Lunar exploration, as a crucial starting point for deep space exploration, not only provides important evidence for humanity's understanding of the evolution of the solar system, but also holds strategic significance in areas such as resource development and interstellar travel. Since the 20th century, dozens of lunar exploration missions have been carried out globally. Among them, mobile exploration platforms for extreme environment exploration (referred to as "lunar rovers") undertake core tasks such as lunar surface sampling, environmental monitoring, and topographic mapping. With the increasing sophistication of exploration targets (such as polar water ice detection and lunar soil structure analysis) and the extension of mission cycles (from several days to several months), higher demands are placed on the autonomous navigation capabilities of lunar rovers—they need to achieve high-precision positioning, path planning, and obstacle avoidance without real-time ground control, while simultaneously meeting stringent power consumption constraints.

[0003] The unique lunar environment presents multiple challenges to navigation system design: First, the Moon lacks a Global Navigation Satellite System (GNSS), rendering traditional satellite-based positioning methods ineffective. Autonomous navigation technologies integrating multiple sensors, such as visual odometry (VO), inertial measurement units (IMU), and lidar (LiDAR), are required. Second, the extreme temperature variations on the lunar surface (-180°C to 120°C), coupled with strong radiation and dust pollution, place extreme demands on the stability and energy efficiency of electronic equipment. Third, the lunar rover carries limited energy (typically solar panels or radioisotope thermoelectric generators), and excessive power consumption will directly shorten mission lifespan or even lead to mission failure. According to data released by NASA regarding the Yutu-2 rover, the navigation system accounts for over 35% of the rover's total power consumption, with storage access and data transport accounting for over 60%, becoming a core bottleneck restricting its endurance.

[0004] In recent years, breakthroughs in artificial intelligence (AI) technology in fields such as computer vision and sensor fusion have provided new solutions for lunar surface navigation. Deep learning-based visual odometry (such as CNN-SLAM) can significantly improve positioning accuracy by extracting lunar terrain features through end-to-end learning; while reinforcement learning-based path planning algorithms can quickly adapt to the complex lunar environment. However, the high computational complexity of AI algorithms creates a sharp contradiction with the limited computing power and energy consumption resources of lunar rovers—the visual feature extraction module, with ResNet-18 as its backbone network, requires more than 1 billion multiply-accumulate operations per frame of image processing, exceeding the capabilities of traditional von Neumann architectures. In the Neumann architecture (computation and storage separation), the energy consumption of "data transfer" is 10 to 100 times that of the computation itself, which poses a huge obstacle to the practical application of AI navigation algorithms on lunar rovers.

[0005] In-Memory Computing (IMC) architecture is a breakthrough for von Neumann architecture. The disruptive technology addressing the von Neumann bottleneck enables "in-situ computation" by embedding computing units into memory arrays (such as cross-arrays based on resistive RAM), significantly reducing energy consumption during data transport. This technology has already demonstrated immense potential in the field of edge AI; for example, IBM's in-memory computing chip achieved over 100 times the energy efficiency of traditional GPUs on the MNIST dataset. Combining in-memory computing architecture with lunar AI navigation algorithms holds promise for solving the high power consumption problem at the hardware level, but two key challenges need to be overcome: first, how to adapt to the heterogeneous computing requirements of multiple tasks (feature extraction, attitude calculation, etc.) in navigation algorithms; and second, how to achieve efficient co-design of algorithms and in-memory computing hardware while ensuring navigation accuracy.

[0006] Therefore, researching the parallel implementation of low-power AI navigation algorithms based on in-memory computing architecture has important theoretical and engineering value for improving the autonomous exploration capabilities of lunar rovers and promoting the development of deep space exploration technology. Summary of the Invention

[0007] This invention aims to solve the high power consumption problem of AI navigation for extreme environment exploration, and provides a low-power AI navigation algorithm processing system for deep space exploration based on an in-memory computing architecture, so as to overcome or at least partially solve the above problems.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: This invention provides a low-power AI navigation algorithm processing system for deep space exploration based on an in-memory computing architecture. The system employs an in-memory computing architecture based on an RRAM cross-array to compute AI navigation algorithms. The system includes: an RRAM in-memory computing core, a dynamically configurable PE array, a radiation-hardened controller, and an on-chip memory interaction unit, wherein: The RRAM computing core is a fusion unit of computation and storage, including multiple independent RRAM cross arrays, supporting in-situ execution of matrix-vector multiplication and vector-matrix multiplication, and can directly carry out intensive operations such as convolutional layers and matrix multiplication; The dynamically configured PE array is used to handle nonlinear operations, and supports dynamic switching between two parallel granularity modes, 16×16 and 4×4, through the configuration register. The radiation-resistant controller integrates an error detection and correction module to perform real-time repair of radiation-induced errors in the RRAM memory core and coordinate the task scheduling between the memory core and the PE array. The on-chip storage interaction unit uses SRAM as an intermediate cache to temporarily store intermediate data such as feature maps and covariance matrices, reducing the frequency of interaction with off-chip storage.

[0009] Furthermore, the system dynamically configures the PE array granularity according to the navigation task type: when processing visual feature extraction tasks, the RRAM computing core activates all RRAM cross arrays, and the PE array is configured in a 16×16 fine-grained mode to accelerate convolution operations through spatial parallelism; when switching to EKF filtering tasks, only 2 RRAM cross arrays are activated, and the PE array is switched to a 4×4 coarse-grained mode to complete matrix operations with the goal of efficient resource utilization.

[0010] Furthermore, the RRAM core storage unit realizes data storage and calculation through the change of resistance state, and uses HfO2-ZrO2 composite oxide as the resistive switching layer of RRAM.

[0011] Furthermore, the memory cell adopts a metal-insulator-metal structure, with the lower electrode made of TiN material and the upper electrode made of Pt material.

[0012] Furthermore, each data bit of the RRAM cross array is stored by multiple physically independent RRAM cells, and the result is output through a majority voter; the majority voter is integrated into the column gating circuit of the cross array, and when a single RRAM cell flips due to radiation, the majority voter masks the erroneous data.

[0013] Furthermore, the PE array adopts a reconfigurable architecture. Each PE unit consists of an arithmetic unit, local registers, and an interconnect network interface. The arithmetic unit supports 8-bit / 16-bit integer and 32-bit / 64-bit floating-point operations, and the operation precision is switched by configuration signals. The local registers are used to temporarily store input data and intermediate results. Adjacent PEs are connected through two bidirectional data channels, supporting data broadcasting and point-to-point transmission.

[0014] Furthermore, the radiation controller has a built-in radiation dose monitoring module. When the cumulative dose exceeds the radiation dose threshold, it automatically triggers a dynamic refresh mechanism: performing row-by-row read-correct-write operations on the RRAM cross array to restore the drifted resistance state to the initial value; at the same time, for calculation errors in matrix operations, a check vector is added after the matrix-vector multiplication operation to verify the result in real time. If the error exceeds the preset value, a local recalculation is initiated.

[0015] Furthermore, when processing visual feature extraction tasks, the system adopts a fixed-weight-data-flow mapping strategy, pre-writing the convolution kernel weights into the row electrodes of the RRAM cross array. The input feature map is divided into 16×16 sub-blocks and then input block by block through the column electrodes. The convolution operation of each sub-block is implemented through matrix-vector multiplication, and the output result is processed by a 16×16PE array to complete ReLU activation and pooling operations.

[0016] Furthermore, when processing EKF filtering tasks, the system employs a matrix block-parallel computation mapping strategy, specifically including: State prediction stage: The rotation matrix and state vector are stored in the first two rows of the RRAM cross array, vector-matrix multiplication is performed, and the result is accumulated by floating point using a 4×4PE array; Measurement update phase: The covariance matrix is ​​divided into 16 sub-blocks in 4×4 sub-blocks, and each sub-block is operated by a coarse-grained PE; the matrix inversion operation is completed through the collaborative computation of the PE array, and the Cholesky decomposition method is used to reduce the computational complexity. Results integration: The calculation results of each PE are aggregated through a shared register, and the state vector and covariance matrix are updated after verification by the radiation protection controller.

[0017] As can be seen from the above technical solution, compared with the prior art, the beneficial effects of the present invention are as follows: 1. Significantly reduce system power consumption: By migrating the core multiply-accumulate operations to the storage unit for in-situ execution through the RRAM in-memory computing architecture, the energy consumption of data transfer is greatly reduced.

[0018] 2. Efficiently adapt to heterogeneous computing requirements: A dynamic "task-hardware" mapping mechanism is proposed. By dynamically switching between 16×16 and 4×4 PE arrays, the fine-grained parallel requirements of feature extraction and the coarse-grained parallel requirements of EKF filtering are matched respectively, thereby improving the utilization rate of PE arrays and effectively avoiding resource waste.

[0019] 3. Ensure high navigation accuracy: While significantly reducing power consumption, it improves positioning accuracy and reduces attitude angle error, meeting the high-precision requirements of deep space exploration.

[0020] 4. Meets the reliability requirements of extreme environments: Through multiple radiation-resistant designs such as HfO2-ZrO2 composite materials, TMR hardening, and dynamic refresh, the error rate is reduced, meeting the long-term stable operation requirements of strong radiation environments such as the lunar surface.

[0021] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings.

[0022] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0025] Figure 1 A schematic diagram illustrating the working principle of the in-memory computing architecture based on RRAM cross-array provided in an embodiment of the present invention; Detailed Implementation To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0026] In the description of this invention, it should be noted that while some processes described in this application specification and drawings include multiple operations appearing in a specific order, it should be clearly understood that these operations may be performed in any order or in parallel. Furthermore, various numbers and other designations are for descriptive purposes only and should not be construed as indicating or implying relative importance. It should be noted that the word "comprising" does not exclude the presence of components or steps not listed in the claims. This invention can be implemented by means of hardware comprising several different components and by means of a suitably programmed computer.

[0027] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0028] In this embodiment of the invention, the technical solution is described in detail in six parts, arranged as follows: Part 1 defines the objective and innovation of the invention. Part 2 analyzes in detail the computational characteristics of the lunar AI navigation algorithm, including the computational load and data flow of the feature extraction module of visual odometry and the filtering module of inertial navigation fusion, providing a basis for subsequent hardware architecture design. Part 3 proposes a memory-computing integrated architecture based on RRAM cross array, introducing the radiation-resistant design of the storage unit, the dynamic configuration mechanism of the PE array, and the mapping method between the algorithm and hardware. Part 4 constructs an experimental verification platform, including the generation of a dataset simulating the lunar environment, an FPGA prototype verification system for the memory-computing integrated chip, and testing methods for power consumption and accuracy. Part 5 presents the experimental results, comparing and analyzing the solution with traditional architectures from three dimensions: power consumption reduction ratio, navigation accuracy, and resource utilization, verifying the effectiveness of the solution. Part 6 summarizes the technical solution and its advantages, pointing out future directions for expansion, such as the implementation of memory-computing integrated computing with multi-sensor fusion and fault-tolerant mechanisms under space radiation.

[0029] 1. Objectives and innovations of this invention: The application of existing in-memory computing technology in the aerospace field is still blank. This invention aims to solve the high power consumption problem of AI navigation systems for extreme environment exploration. It proposes a low-power parallel implementation scheme based on an in-memory computing architecture (a low-power AI navigation algorithm processing system for deep space exploration based on an in-memory computing architecture). The specific objectives include: (1) designing a hardware-algorithm co-architecture that couples storage and computing, and migrating the core multiply-accumulate operation of the AI ​​navigation algorithm to the in-memory computing unit to reduce storage access power consumption by more than 90%; (2) proposing a parallel granularity dynamic adaptation mechanism, and customizing the PE array size according to the computational characteristics of different tasks such as feature extraction and attitude calculation in the navigation algorithm, thereby increasing the hardware resource utilization rate to more than 80%; (3) under the premise of ensuring navigation accuracy (positioning error <0.5m / 100m, attitude angle error <0.3°), reducing the overall system power consumption by more than 60% to meet the needs of long-term autonomous exploration on the lunar surface. This paper proposes a novel "task-hardware" dynamic mapping mechanism, customizing the parallel granularity based on the computational characteristics of each stage of the navigation algorithm: a fine-grained PE array of 16×16 is used in the feature extraction stage (e.g., CNN convolutional layers) to match pixel-level parallel requirements; a coarse-grained PE array of 4×4 is used in the pose calculation stage (e.g., EKF filtering iteration) to adapt to vector-level parallel requirements. The PE array size is dynamically switched via hardware configuration registers, avoiding resource waste caused by a single granularity and improving energy efficiency by over 40%.

[0030] The technical principles and specific implementation methods of the present invention are described in detail below: 2. Computational Characteristics Analysis of Lunar AI Navigation Algorithms: Autonomous navigation systems for extreme environment exploration need to achieve real-time positioning and attitude estimation in the complex lunar environment, which relies on a fusion algorithm of visual odometry (VO) and inertial navigation system (INS). This section analyzes the key modules of the AI ​​navigation algorithm (visual feature extraction and inertial navigation fusion filtering) from three dimensions: computational complexity, data flow, and parallelism characteristics, providing a quantitative basis for the customized design of in-memory computing architecture.

[0031] 2.1 Feature extraction module for visual odometry: Visual odometry estimates the rover's trajectory by matching features from consecutive frames of images and is the core sensing unit for lunar surface navigation. Deep learning-based feature extraction modules (such as the backbone network in CNN-SLAM) are more robust than traditional geometric methods (SIFT, ORB), but their computational characteristics and hardware requirements differ significantly. Taking the ResNet-18 network commonly used in lunar exploration as an example, the computational process of this module can be divided into two stages: feature extraction (convolutional layers, activation layers) and feature matching (attention mechanism, similarity calculation). Its computational characteristics are analyzed below: 2.1.1 Distribution of computational load: The total computational cost of ResNet-18 in processing a single frame of a 512×512 resolution lunar image is approximately 1.2×10¹. 0 This operation comprises 98.3% convolutional layers, making it the most computationally intensive core. Specifically, the computational cost of each convolutional layer can be calculated using the following formula: O_conv=2×K×K×C_in×C_out×H_out×W_out Where K is the kernel size, C_in / C_out is the number of input / output channels, and H_out / W_out is the output feature map size; Taking the first convolutional layer (K=7, C_in=3, C_out=64, H_out=W_out=256) as an example, the computational cost per operation is approximately 2×7×7×3×64×256×256≈4.7×10^64. 8 This operation mainly consists of multiply-accumulate (MAC) operations. The activation layer (such as ReLU) and pooling layer account for less than 2% of the computation, but they require non-linear transformation of the feature value of each pixel, exhibiting fine-grained data dependency characteristics.

[0032] The feature matching stage employs the Transformer attention mechanism, which calculates (Q×K) through self-attention. To achieve cross-frame feature association (×V), a single-frame matching requires approximately 3.2×10⁻⁶ units. 9 The MAC operation involves matrix multiplication (85%) and requires frequent access to the feature map storage (each frame of feature map data is approximately 256×256×64=4MB).

[0033] 2.1.2 Data Flow Characteristics: The data flow of the feature extraction module exhibits a "pyramid-like hierarchical transmission" characteristic: the input image (3×512×512=768KB) is progressively compressed in spatial dimension and expanded in channel dimension through convolutional layers, generating a high-level feature map of 16×16×512 (16×16×512=131072B). The input data of each convolutional layer (the previous layer feature map) needs to be read repeatedly K×K times (convolutional kernel sliding), resulting in a data reuse rate as high as K² times. However, intermediate results need to be temporarily stored in on-chip cache; otherwise, frequent off-chip memory accesses will occur.

[0034] Taking the bottleneck structure of ResNet-18 (1×1 convolution → 3×3 convolution → 1×1 convolution) as an example, the input feature map (256×256×64) of the 1×1 convolution needs to be compressed to 256×256×16 by the 1×1 convolution kernel before being fed into the 3×3 convolution layer for processing. The intermediate data needs to be transferred between the three levels of buffers, and the total amount of data transferred is about 20 times that of the input image (15.36MB), which far exceeds the energy consumption of the computation itself.

[0035] 2.1.3 Parallelism Potential: This module possesses inherent fine-grained parallelism: the computation of each output pixel in the convolutional layer is independent, and parallel acceleration can be achieved through spatial parallelism (pixel-level) and channel parallelism (feature map dimension); the multi-head attention computation in the Transformer attention mechanism can be split and executed in parallel by "head". Theoretically, a 16×16 fine-grained PE array can improve the computational efficiency of convolutional layers by 256 times, but it needs to match the block storage strategy of the feature map—for example, dividing the 256×256 feature map into 16×16 sub-blocks, with each PE responsible for the convolution operation of one sub-block, thereby reducing communication overhead by reducing cross-sub-block data interaction.

[0036] 2.2 Filtering module for inertial navigation fusion: The inertial navigation system (IMU) measures the motion state of the rover in real time through accelerometers and gyroscopes, but the error accumulates over time (typical drift rate of 0.1° / h), requiring fusion correction with a visual odometry system. The extended Kalman filter (EKF) is currently the mainstream fusion algorithm, but its computational characteristics differ significantly from those of the feature extraction module, as detailed below: 2.2.1 Distribution of computational load: The core operations of EKF include state prediction (based on IMU data) and measurement update (fused with VO data), with a single filtering iteration requiring approximately 8.5 × 10⁻⁶ computations. 4 This operation involves matrix operations, accounting for 92% of the total. The state prediction stage requires solving the kinematic equations, involving the multiplication of a 3×3 rotation matrix and a 6-dimensional state vector (1.8×10⁻⁶).4 The measurement update phase requires calculating the Kalman gain, which includes 3×3 matrix inversion (approximately 5×10³ operations) and multiple matrix multiplications (total MAC approximately 6×10³). 4 Second-rate).

[0037] Compared to visual feature extraction, EKF has only 0.7% of the computational cost, but it requires higher computational precision (64-bit floating-point precision must be retained) and has a short iteration interval (usually 50Hz, i.e., 20ms / time), making it sensitive to real-time performance.

[0038] 2.2.2 Data Flow Characteristics: The data flow of EKF exhibits a "closed-loop feedback" characteristic: raw IMU data (accelerometer, angular velocity, 12 bytes / frame) and pose data output by the VO (6DoF, 48 bytes / frame) are used as inputs. These are then processed through state prediction to generate a priori estimates (15-dimensional state vector, 60 bytes), which are then updated and corrected through measurements to become posterior estimates (60 bytes). Simultaneously, the covariance matrix (15×15, 900 bytes) is updated. While the data volume is small (total data volume per iteration <1KB), the high frequency of reading and writing the covariance matrix, coupled with strict data dependencies in matrix operations (e.g., matrix inversion requires prior multiplication results), leads to a low data reuse rate (typically <5%).

[0039] 2.2.3 Parallelism Potential: Coarse-grained parallelism: Matrix multiplication can be performed in parallel by row / column blocks (e.g., 3×3 matrix multiplication can be decomposed into 9 scalar multiplications in parallel), but nonlinear operations such as matrix inversion have recursive dependencies, limiting the degree of parallelism. Experiments show that a 4×4 coarse-grained PE array can meet the parallel requirements of EKF—each PE is responsible for the operation of a sub-matrix block, and intermediate results are exchanged through shared memory, achieving a speedup of 3.2 times compared to a single core, while avoiding the resource waste of fine-grained arrays (PE utilization can be increased to 85%).

[0040] 2.3 Constraints of Algorithm Characteristics on Hardware Design: Based on the above analysis, the heterogeneous nature of lunar AI navigation algorithms imposes clear constraints on in-memory computing architectures: (1) Power consumption constraints: The high data transfer volume (15.36MB / frame) of visual feature extraction requires deep coupling between storage and computing, and needs to support in-situ execution of MAC operations to reduce off-chip access; (2) Parallel granularity constraints: Feature extraction requires a 16×16 fine-grained PE array to match pixel-level parallelism, EKF filtering requires a 4×4 coarse-grained array to adapt to matrix-level parallelism, and the hardware must support dynamic granularity switching. (3) Precision and real-time constraints: The 64-bit floating-point precision of EKF requires the storage unit to support high-precision operations, while the 50Hz filtering frequency requires the overall architecture latency to be <20ms.

[0041] These constraints provide key basis for the customized design of the in-memory computing architecture in Part 3 (such as RRAM cross-array configuration and PE array dynamic mapping mechanism).

[0042] 3. In-memory computing architecture design based on RRAM cross-connect array: To address the heterogeneous computing characteristics and low-power requirements of lunar AI navigation algorithms, this invention proposes a memory-computing integrated architecture based on an RRAM cross-array. This architecture reduces data transfer energy consumption through deep coupling of storage and computation, and supports dynamic switching of parallel granularity to adapt to the differentiated needs of feature extraction and filtering modules. Furthermore, to address the strong radiation environment of the lunar surface, radiation-hardened storage units and an architecture-level fault-tolerance mechanism are designed to ensure stable system operation.

[0043] 3.1 Overall Architecture Design: The core idea of ​​in-memory computing architecture is to break through the limitations of von Neumann architecture. The bottleneck of separating storage and computation in the Neumann architecture is addressed by achieving "in-situ computation" of data through an RRAM crossover array. This architecture adopts a hybrid architecture of "heterogeneous multi-core + in-memory array," mainly composed of four modules: RRAM in-memory core, dynamically configurable PE array, radiation-hardened controller, and on-chip storage interaction unit. The overall architecture working principle is as follows: Figure 1 As shown.

[0044] In this embodiment of the invention, the RRAM in-memory core is a fusion unit of computation and storage, composed of eight independent RRAM cross arrays (each array being 1024×1024 in size). It supports in-situ execution of matrix-vector multiplication (MVM) and vector-matrix multiplication (VMM), and can directly handle intensive operations such as convolutional layers and matrix multiplication. The dynamically configured PE array handles nonlinear operations (such as ReLU activation and matrix inversion), and supports real-time switching between 16×16 and 4×4 parallel granularities through configuration registers. The radiation-hardened controller integrates an error detection and correction (EDAC) module to perform real-time repair of radiation-induced errors in the RRAM units and coordinate task scheduling between the in-memory core and the PE array. The on-chip storage interaction unit uses 32KB of SRAM as an intermediate cache to temporarily store intermediate data such as feature maps and covariance matrices, reducing the frequency of interaction with off-chip storage.

[0045] The architecture's workflow follows a dynamic "task-hardware" mapping principle: when processing visual feature extraction tasks, the RRAM in-memory core activates all eight cross arrays, and the PE array is configured in a 16×16 fine-grained mode to accelerate convolution operations through spatial parallelism; when switching to the EKF filtering task, only two RRAM cross arrays are activated, and the PE array switches to a 4×4 coarse-grained mode to complete matrix operations with the goal of efficient resource utilization. A radiation-resistant controller monitors the operating status of each module throughout the process, correcting detected errors in real time to ensure that computational accuracy is not affected by radiation.

[0046] 3.2 Radiation-resistant design of RRAM memory cells: RRAM memory cells achieve data storage and computation through changes in resistance states. However, their oxide layers are susceptible to resistance state reversals (single-event effects) under bombardment by high-energy particles from the lunar surface, leading to calculation errors. To meet aerospace-grade reliability requirements, this invention incorporates radiation-resistant design at three levels: materials, cell structure, and circuitry. 3.2.1 Material and Unit Structure Optimization: This invention selects HfO2-ZrO2 composite oxide as the resistive switching layer of RRAM. Experiments show that the radiation hardness of this material is more than 3 times higher than that of traditional HfO2, and the resistive state drift rate is less than 5% at a radiation dose of 100 klad(Si). The memory cell adopts a metal-insulator-metal (MIM) structure. TiN material is used for the lower electrode to enhance interface stability, and a Pt layer is used for the upper electrode to suppress oxygen ion diffusion, thereby increasing the single-event upset (SEU) threshold of the cell to 80 MeV. cm² / mg, far exceeding the typical radiation environment on the lunar surface (maximum particle energy approximately 50 MeV). (cm² / mg).

[0047] 3.2.2 Triple Modular Redundancy (TMR) Hardened Circuit: This invention employs a triple modular redundancy (TMR) design at the memory cell array level: each data bit is stored by three physically independent RRAM cells, and the result is output through a majority voter. When a single cell flips due to radiation, the voter can shield erroneous data, ensuring output correctness. Experimental data shows that the TMR design can reduce the system's error rate, meeting the reliability requirements of lunar missions for more than six months. Simultaneously, to avoid area overhead caused by redundancy, the voter is integrated into the column gating circuit of the cross-array, keeping the additional area overhead within 15%.

[0048] 3.2.3 Dynamic refresh and error correction: In this invention, the radiation-resistant controller incorporates a radiation dose monitoring module. When the cumulative dose exceeds 50 krad (Si), a dynamic refresh mechanism is automatically triggered: the RRAM array is read, corrected, and written row by row to restore the drifted resistance state to its initial value. Simultaneously, to address calculation errors in matrix operations, an error correction algorithm based on a check matrix is ​​designed—by appending a check vector after the MVM operation, the result is verified in real time. If the error exceeds a threshold, a local recalculation is initiated. The correction latency is controlled within 100 ns, ensuring no impact on the algorithm's real-time performance.

[0049] 3.3 PE array dynamic configuration mechanism: In this invention, to adapt to the differentiated parallel requirements of the feature extraction and filtering modules, the PE array adopts a reconfigurable architecture, dynamically switching between 16×16 and 4×4 granularities through configuration registers. The core of this mechanism is "hardware resource pooling + task granularity mapping," specifically designed as follows: 3.3.1 Reconfigurable PE unit structure: Each PE unit consists of an arithmetic logic unit (ALU), local registers, and an interconnect network interface. The ALU supports 8-bit / 16-bit integer and 32-bit / 64-bit floating-point operations, and the arithmetic precision can be switched via a configuration signal (8-bit integers for feature extraction and 64-bit floating-point for EKF filtering). The local registers are 256 bytes deep and are used to temporarily store input data and intermediate results, reducing access to the on-chip cache. The interconnect network uses a two-dimensional mesh topology, with adjacent PEs connected by two bidirectional data channels, supporting data broadcasting and point-to-point transmission, with latency less than one clock cycle (10 ns).

[0050] 3.3.2 Parallel Granularity Switching Logic: In the 16×16 fine-grained mode, all 256 PE units are activated, with each PE processing a 16×16 sub-block of the feature map. Sliding window calculations of the convolution kernel are achieved through column-oriented interconnects. Data exchange between PEs is pixel-level, and the interconnect network bandwidth is configured at 128 bits / cycle to ensure parallel transmission of feature map data. In the 4×4 coarse-grained mode, every 16 PEs are merged into a "super PE" through configuration signals, forming a 4×4 coarse-grained array. Data sharing within each super PE is achieved through shared registers, primarily handling matrix block operations (such as 3×3 matrix multiplication in EKF). The interconnect network bandwidth is reduced to 32 bits / cycle to lower static power consumption.

[0051] Granularity switching is achieved through a 2-bit control signal in the configuration register. The switching process takes 3 clock cycles (30ns), which is much shorter than the switching interval of the algorithm tasks (the switching cycle for feature extraction and filtering tasks is about 20ms), thus not introducing significant overhead. Experiments show that the dynamic configuration mechanism can maintain the resource utilization of the PE array at 92% during feature extraction and increase it to 85% during filtering tasks, which is more than 45% higher than the fixed granularity design (average utilization of 58%).

[0052] 3.4 Algorithm-Hardware Mapping Methods: Efficient mapping between algorithms and hardware is key to leveraging the advantages of in-memory computing architecture. Targeted mapping strategies need to be developed based on the computational characteristics and data flow of different modules.

[0053] 3.4.1 Mapping of the visual feature extraction module: The mapping of ResNet-18 convolutional layers adopts a "fixed weights - data flow" strategy: the convolutional kernel weights are pre-written into the row electrodes of the RRAM cross array, and the input feature map is divided into 16×16 sub-blocks and then input block by block through the column electrodes. The convolution operation of each sub-block is implemented through in-situ MVM of the RRAM array, and the output results are processed by a 16×16 PE array to complete ReLU activation and pooling operations. The specific mapping steps are as follows: Weight mapping: Expand the 3×3 convolution kernel into a 9×C_out weight matrix and write it into the row of the RRAM cross array (1024 rows), where C_out is the number of output channels (maximum support 512 channels). Data segmentation: The 256×256 input feature map is divided into 256 sub-blocks of 16×16, and each sub-block is input to the RRAM array through column electrodes; In-situ computation: The RRAM array performs MVM operations on the input sub-blocks and the weight matrix, and outputs the convolution result of the feature sub-blocks (16×16×C_out). Post-processing: The 16×16PE array performs ReLU activation (8-bit integer operation) on the output result, and compresses it to 8×8×C_out through maximum pooling, and writes it to the on-chip SRAM.

[0054] This mapping method can reduce the computational power consumption of convolutional layers by 94.7% (compared to traditional GPUs), mainly due to the reduction in data transport—the transmission distance of feature sub-blocks between the RRAM array and the PE array is less than 1mm, which reduces the power consumption by three orders of magnitude compared to off-chip DDR access.

[0055] 3.4.2 Mapping of the EKF filter module: The EKF filter mapping is based on "matrix block-parallel computation," with a focus on optimizing the efficiency of Kalman gain calculation. State prediction stage: The 3×3 rotation matrix and the 6-dimensional state vector are stored in the first two rows of the RRAM cross array. Vector-matrix multiplication is performed by VMM operation, and the result is accumulated by floating point (64-bit precision) using a 4×4PE array. Measurement update phase: The 15×15 covariance matrix P is divided into 16 sub-blocks of 4×4 size, and each sub-block is processed by a coarse-grained PE. The matrix inversion operation is performed through collaborative computation of the PE array, and the Cholesky decomposition method is used to reduce computational complexity. Results integration: The calculation results of each PE are aggregated through a shared register, and the state vector and covariance matrix are updated after verification by the radiation-resistant controller. The whole process takes 18ms, which meets the real-time requirement of 50Hz.

[0056] This mapping method reduces the single iteration time of EKF from 65ms (traditional CPU implementation) to 18ms through coarse-grained parallelism, while power consumption is reduced by 72.3% due to the low power consumption characteristics of the RRAM array.

[0057] 3.5 Architecture-level power consumption optimization: This invention addresses the energy constraints on the lunar surface by optimizing power consumption from the perspectives of task scheduling and circuit design, specifically including: Dynamic Voltage and Frequency Scaling (DVFS): Automatically adjusts core voltage and clock frequency according to task load—using a high-performance mode of 1.2V / 1GHz for feature extraction and switching to a low-power mode of 0.8V / 200MHz for filtering tasks, which can reduce dynamic power consumption by 35%. Array sleep mechanism: Inactive RRAM cross arrays and PE cells enter sleep state, shutting down the clock and power paths, reducing static power consumption to below 5mW; Data locality optimization: By using a tiered storage strategy for on-chip SRAM (32KB L1 cache + 256KB L2 cache), the data reuse rate is increased to 80%, off-chip memory access is reduced by 90%, and I / O power consumption is further reduced.

[0058] Simulation results show that the average power consumption of this architecture when handling lunar navigation tasks is 1.2W, which is 73.3% lower than the traditional "GPU+DDR" architecture (4.5W), meeting the power consumption constraints of the lunar rover.

[0059] 4. Construction of the experimental verification platform: To verify the effectiveness of the RRAM cross-array-based in-memory computing architecture in lunar AI navigation, this invention constructs a complete experimental verification platform, including the generation of a dataset simulating the lunar environment, an FPGA prototype verification system for the in-memory computing chip, and quantitative testing methods for power consumption and accuracy. This platform allows for the reproduction of lunar navigation scenarios and objective evaluation of the proposed architecture's performance metrics (power consumption reduction rate, navigation accuracy, and resource utilization).

[0060] 4.1 Dataset generation for simulating the lunar environment: The lunar environment has unique characteristics such as low gravity, no atmosphere, strong radiation, and rugged terrain (craters, lunar rocks, lunar dust). Directly using Earth environment datasets would lead to insufficient generalization of the algorithm. Therefore, it is necessary to construct a multimodal dataset that closely resembles the real lunar surface, covering images, inertial measurement data, and ground truth trajectories. The specific generation method is as follows: 4.1.1 Lunar surface terrain modeling and image acquisition: Based on data from NASA's Lunar Reconnaissance Orbiter (LRO) laser altimeter (5m resolution), a 10km×10km digital elevation model (DEM) of the lunar surface was constructed using the 3D modeling tool Blender. This model includes typical terrain features: craters with diameters ranging from 50-200m (maximum slope of 30°), scattered lunar rocks (0.5-3m in height), and plains covered with lunar dust. To simulate variations in lunar illumination (solar altitude angle 10°-60°), the azimuth and intensity parameters of the virtual light source were set, generating RGB images (512×512 resolution, 10fps) under different lighting conditions. The model includes 10,000 frames of training data and 2,000 frames of test data.

[0061] To address the unique optical characteristics of the lunar surface (high albedo and hard shadows caused by the absence of atmospheric scattering), the Cycles physical rendering engine was used to simulate the reflectance spectrum of lunar materials. The spectral reflectance of lunar regolith increases with wavelength in the 400-700nm band (a phenomenon known as "redshift"), while lunar rocks exhibit lower reflectance and a flatter spectral curve. The rendered images were then compared spectrally with lunar surface photographs transmitted back from actual lunar missions to ensure that the error in reflectance characteristics was less than 8%.

[0062] 4.1.2 Inertial Measurement Data and Trajectory Truth Generation: Inertial Measurement Unit (IMU) data was generated based on a dynamic model for extreme environment exploration. The rover's mass was set to 250 kg, wheelbase 1.5 m, maximum travel speed 0.2 m / s, and IMU sampling frequency 100 Hz. The data included acceleration (range ±10 m / s²) and angular velocity (range ±200° / s), and typical errors were injected: zero-bias instability (0.1° / h), random walk (0.01° / h), and Gaussian white noise (acceleration 0.01 m / s², angular velocity 0.01° / s).

[0063] Five typical paths (straight line, turning, climbing, and obstacle avoidance) are planned through the preset trajectory generation module. Each path is 500m long. The true trajectory is generated using the principle of motion capture system. Ten "beacons" are placed in the virtual scene. The real-time pose of the patrol vehicle is calculated by the triangulation method (position error <0.1m, attitude angle error <0.05°) as the benchmark for evaluating the accuracy of the algorithm.

[0064] 4.1.3 Dataset Annotation and Augmentation: Feature annotation was performed on the generated image data, including key navigation feature points such as lunar rock edges and crater outlines (50-100 points per frame) for evaluating the feature matching accuracy of visual odometry. To enhance the robustness of the dataset, data augmentation strategies were introduced: lunar dust occlusion (occlusion rate 0-20%), image noise (Gaussian noise σ=0-5), and motion blur (blur kernel 3×3-7×7) were added to simulate the imaging effect of extreme environment exploration in complex environments. The final dataset has a total size of 150GB and includes image sequences, IMU data, ground truth trajectories, and feature annotation files, in a format compatible with the ROS navigation data package standard.

[0065] 4.2 FPGA Prototype Verification System for In-Memory Computing Chips: Due to the high cost and long cycle of RRAM in-memory computing chip fabrication, this invention uses an FPGA prototype verification system for functional and performance verification. This system can simulate the key characteristics of the in-memory computing core (in-situ computing, dynamic parallel granularity) and supports docking with real sensors.

[0066] 4.2.1 FPGA Hardware Platform: The Xilinx Kintex UltraScale KCU116 development board was selected as the core verification platform. Its main chip, XC7K325T, includes 326K logic units, 20.4Mb of RAM, and 360 DSP slices, meeting the prototype implementation requirements of the in-memory computing architecture. The system configuration is as follows: External storage: 4GB DDR4 SDRAM (analog off-chip storage), 128MB QSPI Flash (storage profile); Sensor interfaces: USB 3.0 (for connecting to simulated lunar surface images), SPI interface (for connecting to an IMU simulator); Debugging interfaces: JTAG (program download), Ethernet (data upload to host computer); Power supply module: Adjustable DC power supply (supports 0.8-1.2V voltage adjustment, simulates DVFS function).

[0067] 4.2.2 FPGA Mapping of the In-Memory Computing Core: Implementing key modules of an in-memory computing architecture on FPGA using the hardware description language (Verilog): RRAM cross array simulation: Eight 1024×1024 virtual cross arrays are constructed using block RAM (BRAM). Each array is simulated in parallel by multiplying and adding operations through DSP slicing. MVM / VMM operations are supported, and the latency is controlled within 20ns (comparable to a real RRAM array). Dynamic PE array: 256 configurable PEs are constructed using logic units, and the 16×16 / 4×4 mode switching is controlled by the status register. The interconnection network is implemented using an on-chip bus with configurable bandwidth (32-128 bits / cycle). Radiation hardening controller: integrates an EDAC module (based on Hamming code) to perform real-time error detection and correction on the data in BRAM, simulating the TMR hardening effect; On-chip storage interaction unit: maps 32KB L1 cache and 256KB L2 cache, adopts LRU (Least Recently Used) replacement strategy, and cache hit rate can be monitored in real time.

[0068] 4.2.3 Hardware and software co-verification environment: Establishing a collaborative verification framework of "FPGA prototype + host computer": The host computer (PC) runs a lunar environment simulator, generates images and IMU data, and sends them to the FPGA via Ethernet; The FPGA executes the in-memory computing architecture navigation algorithm, outputs the positioning and attitude results, and sends them back to the host computer. The host computer uses MATLAB to compare the output of the algorithm with the true value trajectory in real time and calculates the error index (root mean square error RMSE). Develop dedicated debugging tools that can monitor FPGA internal signals (PE array status, RRAM data, power consumption monitoring values) online, and support breakpoint debugging and performance profiling.

[0069] The prototype system can operate stably at a clock frequency of 100MHz, with a functional coverage of over 95%, accurately reproducing the core characteristics of the in-memory computing architecture and providing reliable support for verification before chip tape-out.

[0070] 4.3 Test methods for power consumption and accuracy: To comprehensively evaluate the performance of the proposed architecture, a scientific testing method needs to be established to quantify the power consumption reduction ratio and navigation accuracy, while conducting comparative experiments with traditional architectures.

[0071] 4.3.1 Power Consumption Test Method: Power consumption is measured using a combination of hardware monitoring and software modeling. Dynamic power consumption test: A high-precision current sensor (TIINA226, accuracy ±0.1%) was connected in series at the power input of the FPGA prototype system. Voltage and current data were collected in real time by a host computer to calculate dynamic power consumption. During the test, visual feature extraction (1000 frames of images) and EKF filtering (10000 iterations) were run respectively, and the average power consumption and peak power consumption were recorded. Static power consumption test: Put the system into sleep mode (only keep the necessary circuits powered), measure the standby current, and calculate the static power consumption; In-memory computing core power consumption modeling: Power consumption simulation of the RRAM cross array netlist is performed using Synopsys Prime Power tool. The computational load distribution of the lunar navigation algorithm is input to obtain the theoretical power consumption value, which is then calibrated with the measurement results of the FPGA prototype (error controlled within 10%). Comparative experiment: A traditional architecture platform (NVIDIA Jetson TX2 GPU + DDR4 memory) was built, the same navigation algorithm was run, and the same test method was used to measure power consumption. The power consumption reduction ratio of the proposed architecture was calculated.

[0072] 4.3.2 Navigation accuracy test method: Based on the generated lunar surface dataset, the algorithm performance is evaluated from two dimensions: positioning accuracy and attitude accuracy. Positioning accuracy: The RMSE between the position output by the computer vision odometry and the true trajectory; Attitude accuracy: Calculate the RMSE of attitude angles (roll angle, pitch angle, yaw angle); Robustness test: Different levels of noise (image noise, IMU zero bias) are added to the dataset, and the algorithm accuracy is tested as a function of noise intensity to evaluate the system's anti-interference ability. Comparative experiment: The accuracy of AI algorithms combined with traditional navigation algorithms (such as ORB-SLAM3+INS fusion) on the same dataset is compared to verify the advantages of AI algorithms combined with in-memory computing architecture.

[0073] 4.3.3 Resource utilization rate testing method: The resource utilization of the PE array and RRAM cross-array is statistically analyzed using the internal monitoring module of the FPGA prototype system. PE utilization rate: Records the percentage of active PEs under the 16×16 / 4×4 model; Feature extraction utilization is required to be >90%, and filtering utilization to be >80%. RRAM array utilization: The proportion of cross array rows actually used in the operation to the total number of rows is used to evaluate the effectiveness of weight mapping; Storage bandwidth utilization: This measures the ratio of actual data transfer volume between on-chip cache and external storage to theoretical bandwidth, verifying the effectiveness of data locality optimization.

[0074] The above testing methods can comprehensively quantify the performance indicators of the in-memory computing architecture in lunar navigation scenarios, providing reliable data support for subsequent experimental result analysis.

[0075] 5. Experimental Results and Analysis: This section, based on the experimental verification platform built in Part 4, quantitatively evaluates the performance of the in-memory computing architecture based on RRAM cross-array in lunar AI navigation. Through comparative experiments with a traditional architecture (NVIDIA Jetson TX2 GPU + DDR4 memory), the effectiveness of the proposed solution is verified from three core dimensions: power consumption reduction ratio, navigation accuracy, and resource utilization. The rationality and limitations of the experimental results are also analyzed.

[0076] 5.1 Power Consumption Performance Comparison: Power consumption is a core constraint of extreme environment detection and navigation systems. The experiment compares the FPGA prototype verification system with the traditional architecture platform to evaluate the energy consumption optimization effect of the in-memory computing architecture. The test results are shown in Table 1.

[0077] Table 1. Comparison of power consumption performance of different architectures

[0078] As shown in Table 1, the in-memory computing architecture achieves significant power consumption reduction in all test scenarios: Visual feature extraction stage: Thanks to the in-situ computation characteristics of the RRAM cross array, data transport energy consumption is reduced (from 2.1W to 0.16W), and single-frame image processing power consumption is reduced from 2.8W to 0.32W. This is because the multiplication and addition operations of convolution are completed directly within the storage unit, avoiding the frequent transfer of feature map data between the GPU and DDR4 in the traditional architecture (approximately 15.36MB of data transport per frame).

[0079] EKF filtering stage: The dynamic configuration of the 4×4 coarse-grained PE array improves the resource utilization of matrix operations, reduces redundant power consumption compared to the traditional single-core computing mode of GPUs, and lowers power consumption per iteration. At the same time, the precision requirements of 64-bit floating-point operations are achieved through dedicated circuitry in the PE unit without introducing additional power overhead.

[0080] Overall system power consumption: The average power consumption of the in-memory computing architecture is 1.2W, which is only 26.7% of that of the traditional architecture (4.5W). The significant reduction in static power consumption is due to the array sleep mechanism - the power path of the inactive RRAM cross array and PE cell is turned off, and the leakage current is controlled within 5mA.

[0081] To further verify the accuracy of the power consumption model, the measurement results of the FPGA prototype were compared with the simulation data from Synopsys PrimePower. The error between the two was less than 8%, indicating that the power consumption modeling of the in-memory computing core has high reliability. The effect test of the Dynamic Voltage-Frequency Scaling (DVFS) strategy showed that in 1.2V / 1GHz mode, the feature extraction frame rate reached 10fps; after switching to 0.8V / 200MHz mode, the power consumption of the filtering task decreased, proving that the voltage regulation mechanism can dynamically optimize energy consumption according to the task load.

[0082] 5.2 Navigation accuracy assessment: While ensuring low power consumption, navigation accuracy is the core indicator of system practicality. The experiment was conducted based on a simulated lunar surface dataset to test the accuracy of the visual odometry and EKF fusion algorithm, and compared with the traditional algorithm (ORB-SLAM3+INS). The results are shown in Table 2.

[0083] Table 2 Comparison of Navigation Accuracy (RMSE) of Different Algorithms and Architectures

[0084] Experimental results show that the AI ​​navigation algorithm based on the in-memory computing architecture outperforms traditional solutions: Positioning accuracy: In flat areas (such as Mare Tranquillitatis on the Moon), the visual odometry based on ResNet-18, through deep learning feature extraction, is more robust to changes in lunar illumination, with a positioning RMSE of 0.28m / 100m, an improvement over ORB-SLAM3 (0.32m / 100m); in rugged areas (near craters), the AI ​​algorithm achieves a feature matching accuracy of 91% for lunar rock edges (compared to 83% for traditional algorithms), further improving positioning accuracy.

[0085] Attitude accuracy: The fusion of EKF filtering and visual odometry further reduces attitude angle errors, with roll and pitch RMSE of 0.29° and yaw of 0.38°, all meeting the accuracy requirements for lunar surface navigation (<0.5°). This is thanks to the high-precision support of the in-memory computing architecture for the filtering algorithm—the cumulative error of 64-bit floating-point operations is less than 0.01° / h.

[0086] In robustness testing, after adding 20% ​​lunar dust occlusion and Gaussian noise with σ=5 to the dataset, the positioning accuracy of the in-memory computing architecture decreased by 18% (compared to 35% for the traditional architecture), demonstrating that the AI ​​algorithm combined with in-memory computing hardware has better anti-interference capabilities. Error source analysis shows that the main error originates from the non-ideal nature of the simulation calculation of the RRAM cross array (approximately 0.03m positioning error), which can be further reduced to within 0.01m through calibration algorithms.

[0087] 5.3 Resource Utilization Analysis: Resource utilization directly affects the energy efficiency ratio of the architecture. The experiment used the internal monitoring module of the FPGA prototype to count the utilization rate of the PE array and the RRAM cross array. The results are shown in Table 3.

[0088] Table 3 Resource Utilization of In-Memory Computing Architecture

[0089] PE array utilization: In the 16×16 fine-grained mode, the pixel-level feature extraction and PE utilization reached 92.3%, which is 57.5% higher than that of the traditional GPU stream processor (58.6%). In the 4×4 coarse-grained mode, the matrix block operation increased the PE utilization of EKF filtering to 85.1%, which is more than double that of the CPU core (42.3%), proving that the dynamic granularity switching mechanism effectively avoids resource waste.

[0090] RRAM cross array: The weight mapping strategy achieves a storage density of 89.7% for convolution kernels and matrix data, with no obvious idle rows / columns, verifying the effectiveness of the "fixed weights - data flow" mapping method.

[0091] On-chip cache: The LRU replacement strategy enables the L1 / L2 cache hit rate to reach 78.5%, which is 50.7% higher than the traditional architecture's 52.1%, and reduces off-chip storage access by 90%, further reducing I / O power consumption.

[0092] Resource bottleneck analysis shows that the utilization rate of the RRAM cross array is limited by the matching degree between the convolution kernel size (3×3) and the array size (1024×1024). It can be further improved to over 95% by dynamically adjusting the array blocks. The peak utilization rate of the PE array occurs in the convolutional layer computation stage of feature extraction (98.7%), proving that the fine-grained parallel design is highly compatible with the algorithm characteristics.

[0093] 5.4 Comprehensive Performance Evaluation: Based on the above experimental results, the performance advantages of the in-memory computing architecture in lunar AI navigation can be summarized as follows: Energy efficiency ratio: The positioning accuracy achieved per watt of power consumption (m / W) is used as an indicator. The energy efficiency ratio of the in-memory computing architecture is 0.23m / W, which is 3.3 times that of the traditional architecture (0.07m / W). Real-time performance: Feature extraction frame rate reaches 10fps, EKF filtering frequency is 50Hz, which meets the real-time navigation requirements for extreme environment detection (requirement >5fps). Reliability: In a 100krad(Si) radiation dose test, the system has a fault-free operating time of >1000 hours and its single-event upset resistance meets aerospace-grade requirements.

[0094] A comparison with existing research (as shown in Table 4) shows that this architecture outperforms similar in-memory computing designs in terms of power consumption reduction and accuracy balance, especially in dynamic granularity adaptation and radiation resistance design.

[0095] Table 4 Performance comparison with existing studies

[0096] In summary, the experimental results fully verify the effectiveness of the in-memory computing architecture based on RRAM cross array in lunar AI navigation. Its low power consumption, high precision, and high resource utilization provide key technical support for the long-term autonomous exploration of the lunar rover.

[0097] 6. Summary: This invention addresses the core issue of excessively high storage access power consumption in extreme environment exploration and navigation systems by proposing a storage-computing integrated architecture based on RRAM cross-arrays and implementing a parallel design for low-power AI navigation algorithms. Through innovative storage-computing coupling, the multiply-accumulate operations in the visual odometry and inertial navigation fusion algorithm are performed in-situ within the storage unit. Combined with a parallel granularity adaptation mechanism (a 16×16 fine-grained PE array for feature extraction and a 4×4 coarse-grained PE array for attitude calculation), the energy consumption bottleneck and resource waste associated with traditional architectures are effectively solved. Experimental results show that, under simulated lunar conditions, this scheme reduces storage access power consumption and overall system power consumption while maintaining high navigation accuracy. The resource utilization of both the PE array and the RRAM cross-array is improved, achieving an energy efficiency ratio 3.3 times that of traditional architectures. Furthermore, through triple-modular redundancy reinforcement and a dynamic refresh mechanism, the system can operate stably under a 100 klad(Si) radiation dose, meeting aerospace-grade reliability requirements. Future research could further optimize the nonlinear correction algorithm for real RRAM devices, expand the implementation of in-memory computing through multi-sensor fusion, and conduct long-term reliability testing under extreme temperature environments, providing more comprehensive technical support for long-term autonomous detection in extreme environments. The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses disclosed in the embodiments, since they correspond to the systems disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the system section description.

[0098] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A low-power AI navigation algorithm processing system for deep space exploration based on an in-memory computing architecture, characterized in that, The system adopts an in-memory computing architecture based on RRAM cross-connect arrays to compute AI navigation algorithms. The system includes: an RRAM computing core, a dynamically configurable PE array, a radiation-hardened controller, and an on-chip memory interaction unit. The RRAM computing core is a fusion unit of computing and storage, including multiple independent RRAM cross arrays, supporting in-situ execution of matrix-vector multiplication and vector-matrix multiplication, and carrying intensive operations of convolutional layers and matrix multiplication; The dynamically configured PE array is used to handle nonlinear operations and supports dynamic switching between two parallel granularity modes, 16×16 and 4×4, through configuration registers. The radiation-resistant controller is used to repair radiation-induced errors in the RRAM memory core in real time and coordinate the task scheduling between the memory core and the PE array. The on-chip storage interaction unit uses SRAM as an intermediate cache to temporarily store intermediate data.

2. The system according to claim 1, characterized in that, The system dynamically configures the PE array granularity according to the navigation task type: when processing visual feature extraction tasks, the RRAM computing core starts all RRAM cross arrays, and the PE array is configured in a 16×16 fine-grained mode to accelerate convolution operations through spatial parallelism; when switching to EKF filtering tasks, only 2 RRAM cross arrays are activated, and the PE array is switched to a 4×4 coarse-grained mode to complete matrix operations with the goal of efficient resource utilization.

3. The system according to claim 1, characterized in that, The RRAM core storage unit realizes data storage and calculation through the change of resistance state, and uses HfO2-ZrO2 composite oxide as the resistive switching layer of RRAM.

4. The system according to claim 3, characterized in that, The memory cell adopts a metal-insulator-metal structure, with the lower electrode made of TiN material and the upper electrode made of Pt material.

5. The system according to claim 1, characterized in that, Each data bit of the RRAM cross array is stored by multiple physically independent RRAM cells, and the result is output by a majority voter. The majority voter is integrated into the column gating circuit of the cross array, and the majority voter masks erroneous data when a single RRAM cell flips due to radiation.

6. The system according to claim 1, characterized in that, The PE array adopts a reconfigurable architecture. Each PE unit consists of an arithmetic unit, local registers, and an interconnect network interface. The arithmetic unit supports 8-bit / 16-bit integer and 32-bit / 64-bit floating-point operations, and the operation precision is switched by configuration signals. The local registers are used to temporarily store input data and intermediate results. Adjacent PEs are connected through two bidirectional data channels, supporting data broadcasting and point-to-point transmission.

7. The system according to claim 1, characterized in that, The radiation-resistant controller has a built-in radiation dose monitoring module. When the cumulative dose exceeds the radiation dose threshold, it automatically triggers a dynamic refresh mechanism: it performs row-by-row read-correct-write operations on the RRAM cross array to restore the drifted resistance state to the initial value; at the same time, for calculation errors in matrix operations, it adds a check vector after the matrix-vector multiplication operation to verify the result in real time. If the error exceeds the preset value, it initiates a local recalculation.

8. The system according to claim 2, characterized in that, When processing visual feature extraction tasks, the system adopts a fixed weight-data flow mapping strategy. The convolution kernel weights are pre-written into the row electrodes of the RRAM cross array. The input feature map is divided into 16×16 sub-blocks and then input block by block through the column electrodes. The convolution operation of each sub-block is implemented by matrix-vector multiplication. The output result is processed by a 16×16PE array to complete ReLU activation and pooling operations.

9. The system according to claim 2, characterized in that, When processing EKF filtering tasks, this system employs a matrix block-parallel computation mapping strategy, specifically including: State prediction stage: The rotation matrix and state vector are stored in the first two rows of the RRAM cross array, vector-matrix multiplication is performed, and the result is accumulated by floating point using a 4×4PE array; Measurement update phase: The covariance matrix is ​​divided into 16 sub-blocks in 4×4 sub-blocks, and each sub-block is operated by a coarse-grained PE; the matrix inversion operation is completed through the collaborative computation of the PE array, and the Cholesky decomposition method is used to reduce the computational complexity. Results integration: The calculation results of each PE are aggregated through a shared register, and the state vector and covariance matrix are updated after verification by the radiation protection controller.

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