Chip packaging structure, preparation method therefor, and electronic device

Abstract

The present application relates to the technical field of semiconductors, and provides a chip packaging structure, a preparation method therefor, and an electronic device, which aim to address the issue of improving chip packaging structure quality. The chip packaging structure comprises a first chip and a filling portion, the filling portion being arranged around the first chip, and the first chip comprising a substrate, a circuit layer, a redistribution layer, and a dielectric structure, the circuit layer being arranged on the substrate, the redistribution layer being arranged on a side of the circuit layer away from the substrate, and the dielectric structure being arranged around the circuit layer and at least partially located between the circuit layer and the filling portion. The chip package structure is configured for improving chip package structure quality.

Description

Chip packaging structure, preparation method thereof and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411365581.9, filed on September 27, 2024, and entitled "Chip packaging structure, preparation method thereof and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor technology, and in particular to a chip packaging structure, a preparation method thereof and an electronic device. BACKGROUND

[0003] Chips are essential for existing electronic devices to realize rich applications. With the continuous development of semiconductor technology, the manufacturing process of chips is gradually approaching the physical size limit of transistors. Three-dimensional (3D) packaging technology has become an important technical route to improve the integration and performance of chips. In three-dimensional packaging, the pitch between the pins of the chips for electrical connection can be reduced to less than 10 microns, and the conventional micro bump process cannot meet the demand.

[0004] Hybrid bonding (HB) technology can realize higher density electrical signal connection between adjacent chips by directly bonding small size planar copper pads. Therefore, hybrid bonding has gradually become a key technology for three-dimensional stacked packaging and architecture integration design. In the hybrid bonding process, the segmentation of the chip is particularly important. However, in the prior art, the segmentation of the chip is difficult to meet the requirements, and the cutting process of the chip needs to be further optimized to improve the quality of the chip packaging structure. SUMMARY

[0005] The embodiments of the present application provide a chip packaging structure, a preparation method thereof and an electronic device to solve the problem of how to improve the quality of the chip packaging structure.

[0006] To achieve the above-mentioned purpose, the technical solutions adopted by the embodiments of the present application are as follows:

[0007] In a first aspect, the embodiments of the present application provide a chip packaging structure, which comprises a first chip and a filling part, the filling part is arranged around the first chip, the first chip comprises a substrate, a circuit layer, a redistribution layer and a dielectric structure, the circuit layer is arranged on the substrate; the redistribution layer is arranged on the side of the circuit layer away from the substrate; the dielectric structure is arranged around the circuit layer and at least partially located between the circuit layer and the filling part.

[0008] Thus, in the process of cutting to form the first chip, a groove can be formed in the cutting region of the circuit layer by a suitable cutting process, and then a dielectric material is formed in the groove. Thus, the by-products formed due to the cutting process can be covered by the dielectric material. After the cutting to form the independent first chip, the remaining part of the dielectric material is the dielectric structure, and the dielectric structure is still arranged around the circuit layer by the sidewall of the circuit layer, so that the by-products can be prevented from falling off in the use process. In addition, since the dielectric material is formed in the groove, in the subsequent cutting process, there is no metal in the cutting region of the circuit layer, and only the dielectric material can be cut. Therefore, a suitable cutting process can be selected without being limited by the material to be cut. After the cutting process is selected, the cutting interface of the first chip has high quality, so that no gap is formed between the filling part and the dielectric structure when the filling part surrounding the first chip is formed, and the structure failure of the chip packaging structure after long-term use is avoided.

[0009] In a possible implementation of the first aspect, the dielectric structure is located on a side of the redistribution layer close to the substrate and overlaps the redistribution layer in the thickness direction of the substrate. Thus, a groove can be formed on the cutting region of the circuit layer after the circuit layer is formed, and a dielectric material is formed in the groove. Before the redistribution layer is formed, the surface of the circuit layer can be treated, so as to improve the surface quality of the circuit layer. Therefore, the by-products formed on the surface of the circuit layer for forming the groove can be removed, so that the chip packaging structure is not affected by the process of forming the groove.

[0010] In a possible implementation of the first aspect, the sidewall of the substrate, the sidewall of the dielectric structure and the sidewall of the redistribution layer form at least part of the sidewall of the first chip, and the sidewall of the first chip extends in the thickness direction of the substrate. Since the sidewall extends in the thickness direction of the substrate, that is, the sidewall is perpendicular to the surface of the circuit layer arranged by the first chip, the filling performance of the filling material for forming the filling part can be improved when the filling part is formed, and the gap between the filling part and the sidewall can be avoided.

[0011] In a possible implementation of the first aspect, in the direction of the redistribution layer pointing to the substrate, the surface of the dielectric structure away from the filling part gradually approaches the filling part. Since the opening of the groove formed in the cutting region of the circuit layer is larger than the bottom of the groove, that is, the sidewall of the groove is an inclined surface, and in the direction of the redistribution layer pointing to the substrate, the sidewall gradually moves away from the center of the circuit layer, and the shape of the dielectric structure is determined by the shape of the groove, in the direction of the redistribution layer pointing to the substrate, the surface of the dielectric structure away from the filling part gradually approaches the filling part.

[0012] In a possible implementation of the first aspect, the dielectric structure includes a first film layer structure and a second film layer structure, and the first film layer structure is located between the second film layer structure and the circuit layer. In this way, the first film layer structure and the second film layer structure can have different properties, thereby meeting more process requirements.

[0013] In a possible implementation of the first aspect, an absolute value of a difference between a thermal expansion coefficient of the first film layer structure and a thermal expansion coefficient of the circuit layer is smaller than an absolute value of a difference between a thermal expansion coefficient of the second film layer structure and the thermal expansion coefficient of the circuit layer. In this way, while meeting other process requirements, the thermal expansion coefficient of the first film layer structure is similar to the thermal expansion coefficient of the circuit layer, thereby reducing the influence of temperature on the chip packaging structure.

[0014] In a possible implementation of the first aspect, the first chip further includes a buffer structure, the circuit layer includes a central region in which the electrical element is arranged, and the buffer structure penetrates through the circuit layer and is arranged around the central region. In this way, when a groove is formed on the circuit layer, the buffer structure is arranged between the electrical element in the circuit layer and the groove, thereby avoiding affecting the electrical element in the circuit layer.

[0015] In a possible implementation of the first aspect, the redistribution layer includes a dielectric layer and a conductive structure arranged in the dielectric layer, and the dielectric layer is integrally formed with at least part of the dielectric structure. In this way, the dielectric structure can be formed of the same material as the dielectric layer of the redistribution layer and can be formed by a one-time deposition process, thereby reducing process steps and reducing manufacturing costs.

[0016] In a possible implementation of the first aspect, the chip packaging structure further includes a carrier substrate, and the at least two first chips are arranged on the same surface of the adapter plate, and part of the filling portion is arranged between the adjacent at least two first chips. Since the first chip has a good cutting interface, the first chip also has good bonding performance with the carrier substrate, thereby improving the quality of the chip packaging structure.

[0017] In a possible implementation of the first aspect, the chip packaging structure further includes a support plate, the support plate is arranged on a side of the at least two first chips away from the carrier substrate, the carrier substrate is a second chip, the second chip is provided with a pad on a side away from the first chip, and the first chip is connected to the pad through the conductive structure penetrating at least partially through the second chip. In this way, the first chip can be connected to other circuit structures through the second chip.

[0018] In a possible implementation of the first aspect, the carrier substrate is an adapter plate, the adapter plate is provided with a pad on a side away from the first chip, and the first chip is connected to the pad through the conductive structure penetrating at least partially through the adapter plate. In this way, the first chip can be connected to other circuit structures through the adapter plate.

[0019] In a second aspect, the embodiments of the present application provide a method for manufacturing a chip packaging structure. The method comprises the following steps: providing a substrate, the substrate being provided with an initial circuit layer, the initial circuit layer comprising a cutting path; forming a groove on the cutting path, the initial circuit layer forming a circuit layer; filling a dielectric material in the groove; forming a redistribution layer on the circuit layer; cutting the redistribution layer, the dielectric material and the substrate to form a first chip, the dielectric material forming a dielectric structure, the dielectric structure surrounding the circuit layer and at least partially located between the redistribution layer and the substrate in a thickness direction of the substrate; and forming a filling part, the filling part surrounding the first chip and the dielectric structure being located between the circuit layer and the filling part.

[0020] In a possible implementation manner of the second aspect, the dielectric material is formed by forming a first film layer structure to cover surfaces of the groove, and forming a second film layer structure to fill the groove.

[0021] In a possible implementation manner of the second aspect, the dielectric material is further formed on the initial circuit layer; and the redistribution layer is formed by forming a conductive structure in the dielectric material on the initial circuit layer, wherein the dielectric material on the circuit layer forms a dielectric layer, and the conductive structure is arranged in the dielectric layer.

[0022] In a third aspect, the embodiments of the present application provide an electronic device, which comprises a circuit board and the chip packaging structure of any one of the first aspect or the implementation manners of the first aspect, and the chip packaging structure is arranged on the circuit board.

[0023] The advantages of the second aspect and the third aspect above can refer to the description of the first aspect or the implementation manners of the first aspect, and will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0024] FIG. 1 is a schematic diagram of an electronic device according to an embodiment of the present application;

[0025] FIG. 2 is a schematic diagram of a chip packaging structure according to the related art;

[0026] FIG. 3 is an enlarged view of region P in FIG. 2;

[0027] FIG. 4 is a schematic diagram of a chip packaging structure according to an embodiment of the present application;

[0028] FIG. 5 is a possible enlarged view of region G1 in FIG. 4;

[0029] FIG. 6 is another possible enlarged view of region G1 in FIG. 4;

[0030] FIG. 7 is a schematic diagram of another chip packaging structure according to an embodiment of the present application;

[0031] FIG. 8 is a possible schematic diagram of a cross-sectional structure along line A1-A2 in FIG. 7;

[0032] FIG. 9 is a possible enlarged view along region G2 in FIG. 7;

[0033] FIG. 10 is another possible cross-sectional structural schematic view along line A1-A2 in FIG. 7;

[0034] FIG. 11 is another possible enlarged view along region G2 in FIG. 7;

[0035] FIGS. 12-19 are possible structural schematic views of a chip packaging structure provided by embodiments of the present application;

[0036] FIG. 20 is a flowchart of a method for manufacturing a chip packaging structure provided by embodiments of the present application;

[0037] FIGS. 21-38 are possible structural schematic views of a chip packaging structure in a manufacturing process provided by embodiments of the present application. DETAILED DESCRIPTION

[0038] Unless otherwise defined, technical terms or scientific terms used in the present application shall have their ordinary meanings to those skilled in the art. The terms "first", "second", "third", and the like used in the description and claims of the present application do not necessarily mean any sequential or chronological order, number or importance, but are merely used to distinguish different components. Thus, features defined with "first", "second", "third" can explicitly or implicitly include one or more of the features. In the description of embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0039] The orientation terms "left", "right", "up", and "down" are defined relative to the orientation in which the device in the drawing is placed, and it should be understood that these directional terms are relative concepts, which are used for relative description and clarification, and can change accordingly according to the change in the orientation in which the chip or semiconductor packaging structure is placed.

[0040] Referring to FIG. 1, FIG. 1 is a schematic view of an electronic device 10 provided by embodiments of the present application. The electronic device 10 can be different types of user devices or terminal devices, such as a mobile phone, a pad, a personal digital assistant (PDA), a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a household small appliance (for example, a soybean milk machine, a sweeping robot), a drone, an aerospace device, and a vehicle-mounted device, and a communication device such as a wireless network card or a communication base station. The specific type of the electronic device is not specially limited in the present application.

[0041] The electronic device 10 can include a chip package structure 11 and a circuit board 12, and the chip package structure 11 is disposed on the circuit board 12. Exemplarily, the circuit board 12 is provided with conductive wires, and the chip package structure 11 is electrically connected with the conductive wires.

[0042] Referring to FIG. 2, FIG. 2 is a structural schematic diagram of a chip package structure 100 in the related art. The chip package structure 100 can include a plurality of first chips 110 and a carrier substrate 120. At least two first chips 110 in the plurality of first chips 110 can be disposed on the same surface, for example, in FIG. 2, two first chips 110 are disposed on the same surface of the carrier substrate 120. At least two first chips 110 in the plurality of first chips 110 can also be disposed in a stacked manner.

[0043] The first chip 110 can include a substrate 111 and a circuit layer 112, a redistribution layer 113 and a connection layer 114 disposed in sequence on the substrate 111, and the connection layer 114 can be provided with a pad. Similarly, the carrier substrate 120 can also include a substrate 111 and a circuit layer 112, a redistribution layer 113 and a connection layer 114 disposed in sequence on the substrate 111. The first chip 110 can be connected with the connection layer 114 of the carrier substrate 120 through the connection layer 114 of the first chip 110 (as shown in FIG. 2), at this time, the first chip 110 and the carrier substrate 120 are packaged through a face to face (F2F) architecture. It can be understood that the first chip 110 and the carrier substrate 120 can also be packaged through a face to back (F2B) architecture. The first chip 110 and the carrier substrate 120 can be connected through a bonding process, and the bonding process can be bonded through a hybrid bonding process.

[0044] Exemplarily, at least two first chips 110 in the plurality of first chips 110 can also be disposed in a stacked manner. Similarly, two first chips 110 adjacent in the vertical direction can be packaged through a face to face (F2F) architecture, or can be packaged through a face to back (F2B) architecture. The two first chips 110 adjacent in the vertical direction can also be connected through a bonding process.

[0045] When the first chip 110 is arranged on other surfaces by bonding, the surface of the first chip 110 used for bonding has higher requirements. For example, the flatness of the surface has higher requirements. However, in the related art, in the process of cutting to obtain a plurality of chips, the surface of the chip used for bonding can be contaminated. In addition, in the case that there is metal material in the cutting path of the wafer, the debris generated by the metal material during cutting can also aggravate the contamination. For the cutting of metal, the related art usually adopts the process of laser grooving (LG) and then blade saw cutting. However, after cutting, because the laser generates a large amount of heat, the surface of the groove formed by the laser in the process of forming the groove will form a melt, and the by-product 151 will be generated after the melt cools down. Understandably, the by-product 151 can also be formed on the surface near the groove used for bonding, thereby causing contamination and affecting the quality of bonding.

[0046] Please refer to FIG. 3, which is an enlarged view of the region P in FIG. 2. The first chip 110 can be obtained by laser grooving and then blade saw cutting. However, after cutting by the blade, the by-product 151 generated by laser grooving can still be formed on at least part of the side wall of the first chip 110 formed by the side wall of the circuit layer 112, the side wall of the redistribution layer 113 and the side wall of the connection layer 114. At the same time, the by-product 151 can also be generated on the surface of the connection layer 114 away from the substrate 111. Understandably, the surface of the connection layer 114 is the surface of the first chip 110 used for bonding. Therefore, the by-product 151 formed on the bonding surface can destroy the flatness of the bonding surface, thereby affecting the bonding quality. In addition, because laser grooving is adopted, the size of the bottom of the groove formed by the laser is smaller than the size of the opening of the groove, that is, the side wall of the groove is an inclined surface. After blade saw cutting, part of the inclined surface will be reserved, and when the first chip 110 is packaged, the groove formed by the inclined surface between adjacent first chips 110 on the same bonding surface has a shape of small at the top and large at the bottom. Therefore, when the groove is filled, it is difficult to fill the groove due to the poor flow performance of the filler. That is, there can be a gap between the filler 102 formed by the filler and the inclined surface, which can cause structural failure during the aging process of the subsequent chip packaging structure 100, resulting in good and bad. In addition, there can also be by-products on the inclined surface, which can fall off after long-term use and cause contamination.

[0047] To this end, please refer to FIG. 4 and FIG. 5, FIG. 4 is a structural schematic diagram of a chip packaging structure 100 provided by an embodiment of the present application, and FIG. 5 is a possible enlarged view of region G1 in FIG. 4. For ease of illustration, a coordinate system as shown in FIG. 4 is established, in which a first direction X can be a thickness direction of the chip packaging structure 100, and a second direction Y intersects the first direction X, for example, the second direction Y is perpendicular to the first direction.

[0048] The chip packaging structure 100 can include a first chip 110 and a filling part 102, and the filling part 102 can be disposed around the first chip 110. The first chip 110 can be a logic chip, for example, a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC), an application processor (AP), a microcontroller, etc.; the first chip 110 can also be a memory chip, for example, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, etc.; the first chip 110 can also be a power management chip, a radio frequency (RF) chip, a sensor chip, a microelectro-mechanical-system (MEMS) chip, a signal processing chip, a front-end chip, etc.; the first chip 110 can even be a combination of the foregoing various types of chips. The present application does not limit the type of the first chip 110 in the chip packaging structure 11.

[0049] In some embodiments, the filling part 102 is disposed around the first chip 110. In addition, the filling part 102 can also cover a first surface or a second surface of the first chip 110, wherein the first surface and the second surface are two surfaces of the chip facing away from each other in the first direction X. For example, the first surface is a side surface of the first chip 110 on which the circuit is disposed. The filling part 102 can be formed of a dielectric material, for example, can be formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. or any combination thereof. The filling part 102 can be formed by a suitable process, for example, a coating, lamination, etc. process.

[0050] The first surface or the second surface of the first chip 110 can also not be covered by the filling portion 102, as shown in FIG. 4, and a support plate 103 can be disposed on the first surface or the second surface, and the support plate 103 can be attached to the first chip 110 through the bonding layer 104, for example. The one of the first surface or the second surface of the first chip 110 that is not covered can be connected with the carrier substrate 120. The carrier substrate 120 can be a chip or a board. The first chip 110 can be connected with the carrier substrate 120 by bonding, for example, by hybrid bonding.

[0051] The first chip 110 can include a substrate 111, a circuit layer 112, a redistribution layer 113, and a dielectric structure 119.

[0052] The substrate 111 can be formed of silicon, or can be formed of other group III elements, group IV elements, and / or group V elements. For example, the substrate 111 can be made of a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP), or can be made of an alloy semiconductor such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), or gallium indium phosphide (GaInP).

[0053] The substrate 111 can also be in the form of a semiconductor on insulator, such as silicon on insulator (SOI). The semiconductor on insulator substrate can include a substrate body, an insulator layer formed on the silicon substrate body, and a semiconductor material layer formed on the insulator layer, the insulator layer can be a buried oxide or the like, and the semiconductor material layer can be made of silicon, germanium, or the like.

[0054] It can be understood that the thickness direction of the substrate 111 can be consistent with the thickness direction of the chip package structure 100, so the first direction X can also be the thickness direction of the substrate 111.

[0055] The circuit layer 112 is disposed on the substrate 111. The circuit layer 112 can include electrical elements (not shown in FIG. 4) that can be disposed on one side surface of the substrate. The electrical elements can be active devices (e.g., transistors, diodes), capacitors, resistors, etc. For example, the electrical elements can be transistors including gate structures, source regions, and drain regions, where the source regions and the drain regions can be formed from a portion of the substrate 111. The circuit layer 112 can also include interlayer dielectric layers and metal interconnect layers (both not shown in FIG. 4). The interlayer dielectric layers can surround and can cover the electrical elements, and can include dielectric layers and metal plugs that connect with the electrical elements through the dielectric layers. The metal interconnect layers can interconnect the electrical elements to form an integrated circuit, and can include dielectric layers and interconnect structures that can be formed from metallization patterns in the dielectric layers that can be connected with the electrical elements and / or the metal plugs to form the integrated circuit.

[0056] The redistribution layer 113 is disposed on the side of the circuit layer 112 that is away from the substrate 111. The redistribution layer 113 can also include dielectric layers and conductive structures, and the difference between the conductive structures of the redistribution layer 113 and the conductive structures in the circuit layer 112 (i.e., the conductive structures in the metal interconnect layers) is that the conductive structures of the redistribution layer 113 are for redistributing the electrical connections of the first chip 110, i.e., changing the locations of the electrical contacts of the first chip 110, while the conductive structures in the circuit layer 112 are for connecting the electrical elements to form an integrated circuit.

[0057] The dielectric structure 119 can be disposed around the circuit layer 112, i.e., the dielectric structure 119 can be an annular structure that is disposed around the first direction X. For example, the dielectric structure 119 is disposed around the circuit layer 112 in a plane that is perpendicular to the thickness direction of the substrate 111. It can be appreciated that since the filler 102 is disposed around the first chip 110 and the dielectric structure 119 is a part of the first chip 110, the filler 102 is also disposed around the dielectric structure 119, i.e., the dielectric structure 119 is disposed between the circuit layer 112 and the filler 102.

[0058] Further, in the first direction X, the dielectric structure 119 can be at least partially disposed between the substrate 111 and the redistribution layer 113. For example, the dielectric structure 119 can extend only between the substrate 111 and the redistribution layer 113, in which case the dimension of the dielectric structure 119 along the first direction X can be the same as the dimension of the circuit layer 112. For example, the dielectric structure 119 can be partially embedded in the substrate 111 along the first direction X, as shown in FIG. 5, in which case the dimension of the dielectric structure 119 along the first direction X is greater than the dimension of the circuit layer 112. For example, in the first direction X, the side surface of the dielectric structure 119 that is away from the substrate 111 can coincide with the plane in which the side surface of the redistribution layer 113 that is away from the substrate 111 is located, as shown in FIG. 6.

[0059] Thus, in the process of cutting the first chip 110, a portion of the circuit layer 112 can be removed by a process such as laser to form a recess, and then a dielectric material is formed in the recess to cover the sidewall of the recess. Thus, the byproduct 151 formed by the process such as laser can be covered by the dielectric material. After the cutting is completed, the remaining portion of the dielectric material is the dielectric structure 119, which still covers the sidewall of the recess, so that the byproduct 151 can be prevented from falling off during use. In addition, when the recess is formed by the process such as laser, the metal in the recess can also be removed. In the cutting process after the dielectric material is formed, the metal does not need to be cut again, so that a suitable cutting process can be selected without being affected by the material to be cut. For example, a plasma process can be selected for cutting, so that the interface after cutting also has high quality and does not have an inclined surface, that is, the interface of the dielectric structure 119 cut has high quality. Thus, when the filling portion 102 is formed, no gap is formed between the filling portion 102 and the dielectric structure 119, so that the chip package structure 100 is prevented from failing after long-term use.

[0060] In some embodiments, please continue to refer to FIG. 5, the dielectric structure 119 can be located on the side of the redistribution layer 113 close to the substrate 111 and overlaps the redistribution layer 113 in the first direction X. The surface of the dielectric structure 119 away from the substrate 111 can be in contact with the surface of the redistribution layer 113.

[0061] Thus, after the circuit layer 112 is formed, a recess can be formed on the circuit layer 112, and a dielectric material is formed in the recess. It can be understood that, in order to continue to form the redistribution layer 113 on the circuit layer 112, the surface of the circuit layer 112 can be subjected to a chemical mechanical polish (CMP) process before the redistribution layer 113 is formed, so that the surface of the circuit layer 112 is planarized. Thus, the byproduct 151 formed on the surface of the circuit layer 112 for forming the recess can be removed, so that the first chip 110 is not affected by the byproduct 151 generated when the recess is formed. Therefore, even if the process of forming the recess on the circuit layer 112 generates the byproduct 151, it is acceptable.

[0062] In some embodiments, please continue to refer to FIG. 5, the sidewall of the substrate 111, the sidewall of the dielectric structure 119, and the sidewall of the redistribution layer 113 can form at least part of the sidewall F of the first chip 110, which is in contact with the filling portion 102. Exemplarily, the sidewall F can extend along the first direction X, that is, the sidewall F can be perpendicular to the first surface or the second surface of the substrate 111. Thus, when the filling portion 102 is formed, the filling performance of the filling material for forming the filling portion 102 can be improved, so that a gap is prevented from being formed between the filling portion 102 and the sidewall F.

[0063] Referring to FIGS. 7-9, FIG. 7 is a schematic diagram of another chip packaging structure 100 according to an embodiment of the present application, FIG. 8 is a schematic diagram of a possible cross-sectional structure along the line A1-A2 in FIG. 7, and FIG. 9 is a possible enlarged view of the region G2 in FIG. 7. The first chip 110 can further include a buffer structure 116, which penetrates the circuit layer 112 and is disposed adjacent to the dielectric structure 119.

[0064] Exemplarily, the buffer structure 116 can have the same size as the thickness of the circuit layer 112 in the first direction X, that is, the buffer structure 116 extends from the side surface of the circuit layer 112 close to the substrate 111 to the side surface of the circuit layer 112 away from the substrate 111. Exemplarily, a part of the buffer structure 116 can also be embedded in the substrate 111.

[0065] Exemplarily, as described above, the circuit layer 112 includes electrical elements, which can be disposed in a central region 1121 of the circuit layer 112, and an edge region 1122 of the circuit layer 112 surrounds the central region 1121. At this time, the buffer structure 116 can be disposed to surround the central region 1121, that is, the buffer structure 116 is disposed in the edge region 1122.

[0066] A seal ring can also be disposed between the buffer structure 116 and the electrical elements, that is, the buffer structure 116 can be disposed between the seal ring and the dielectric structure 119. The buffer structure 116 can be made of a metal material, such as copper, tungsten, tin, etc. In this way, when a groove is formed on the circuit layer 112, the buffer structure 116 can be used to avoid the influence of the groove forming process on the electrical elements in the central region 1121. For example, when laser slotting is performed, the buffer structure 116 can increase the proportion of heat generated by the laser to be conducted to the air, thereby slowing down the influence of laser slotting on the electrical elements.

[0067] In some embodiments, referring to FIG. 8, the buffer structure 116 can be ring-shaped. That is, the buffer structure 116 can divide the circuit layer 112 into two parts, one of which is inside the buffer structure 116, and the other of which is outside the buffer structure 116 and surrounds the buffer structure 116.

[0068] In some embodiments, referring to FIG. 10 in combination with FIG. 9, FIG. 10 is another possible cross-sectional structure along the line A1-A2 in FIG. 7. The buffer structure 116 can be a plurality of columnar structures, which are arranged around the central region 1121 and penetrate the circuit layer 112. The cross-sectional shape of the columnar structure in a plane perpendicular to the first direction X can be circular, directional, or other shapes.

[0069] In some embodiments, please continue to refer to FIG. 9, the dielectric structure 119 can include a first film layer structure 1191 and a second film layer structure 1192, the first film layer structure 1191 is located between the second film layer structure 1192 and the circuit layer 112. That is, the second film layer structure 1192 does not directly contact the circuit layer 112. Since the first film layer structure 1191 and the second film layer structure 1192 can have different properties, different parts of the dielectric structure 119 can have different properties.

[0070] For example, the filling quality of the first film layer structure 1191 is better than that of the second film layer structure 1192, but the cost of the first film layer structure 1191 is higher than that of the second film layer structure 1192, by using the second film layer structure 1192 to form part of the dielectric structure 119, the filling quality and the cost can be considered.

[0071] For example, the absolute value of the difference between the thermal expansion coefficient of the first film layer structure 1191 and the thermal expansion coefficient of the circuit layer 112 is less than the absolute value of the difference between the thermal expansion coefficient of the second film layer structure 1192 and the thermal expansion coefficient of the circuit layer 112. That is, the thermal expansion coefficient of the first film layer structure 1191 is closer to the thermal expansion coefficient of the circuit layer 112 than the thermal expansion coefficient of the second film layer structure 1192. Understandably, the thermal expansion coefficient of the first film layer structure 1191 and the thermal expansion coefficient of the second film layer structure 1192 can be greater than or less than the thermal expansion coefficient of the circuit layer 112 at the same time.

[0072] Understandably, the dielectric structure 119 can also include more film layer structures, the closer the film layer structure to the circuit layer 112, the closer its thermal expansion coefficient to the thermal expansion coefficient of the circuit layer 112.

[0073] Please continue to refer to FIG. 9, the redistribution layer 113 can include a dielectric layer 1132 and a conductive structure 1131 arranged in the dielectric layer 1132, and the dielectric structure 119 and the dielectric layer 1132 can use the same material. That is, when the dielectric material is formed in the groove, the dielectric material can also be formed on the circuit layer 112. In this way, the dielectric material on the circuit layer 112 can be used to form the redistribution layer 113, so that the dielectric layer 1132 of the redistribution layer 113 is integrated with the dielectric structure 119, that is, integrally formed.

[0074] For example, when the dielectric structure 119 is formed by a single material, the dielectric structure 119 can be integrally formed with the dielectric layer 1132 of the redistribution layer 113, that is, the dielectric structure 119 and the dielectric layer 1132 of the redistribution layer 113 can use the same material and can be formed by a one-time deposition process.

[0075] Exemplarily, the dielectric structure 119 can include a plurality of film layer structures. Referring to FIG. 11, in this case, the dielectric layer 1132 of the redistribution layer 113 can also include a plurality of film layer structures identical to the dielectric structure 119, i.e., the conductive structure of the redistribution layer 113 can be formed in the plurality of film layer structures. For example, the conductive structure can be formed in the plurality of film layer structures by a one damascene process.

[0076] Although the dielectric structure 119 and the dielectric layer 1132 of the redistribution layer 113 both include a plurality of film layer structures, the corresponding film layer structures of the two are integrally formed, and thus, the dielectric structure 119 and the dielectric layer 1132 of the redistribution layer 113 can also be considered as integrally formed. Understandably, after the first film layer structure 1191 is formed in the recess, the portion of the first film layer structure 1191 covering the circuit layer 112 can be removed, and then the second film layer structure 1192 can be continuously formed. In this way, although the dielectric structure 119 can include the first film layer structure 1191 and the second film layer structure 1192, only the second film layer structure 1192 covers the surface of the circuit layer 112, and thus, the dielectric layer 1132 of the redistribution layer 113 can only include the second film layer structure 1192, i.e., the dielectric layer 1132 is integrally formed with a portion of the dielectric structure 119.

[0077] Referring to FIG. 11 and FIG. 7, the first chip 110 can further include a connection layer 114. The connection layer 114 is disposed on the side of the redistribution layer 113 away from the substrate. The connection layer 114 can be used to connect the conductive structure 1131 of the redistribution layer 113 with other chips, a board or a circuit board. The connection layer 114 can include a connection member and a dielectric layer, and the connection member can be connected with the conductive structure 1131 of the redistribution layer 113 through the dielectric layer. The connection member can include a conductive pillar or a bonding pad, etc. Exemplarily, the connection layer 114 can be connected with other chips, a board or a circuit board by bonding, for example, by hybrid bonding.

[0078] As mentioned above, the chip package structure 100 can further include a carrier substrate 120, and the number of the first chips 110 can be at least two. The at least two first chips 110 can be disposed on the same surface of the carrier substrate 120, i.e., the at least two first chips 110 can be disposed in the same plane. Exemplarily, the first chip 110 can be connected with the carrier substrate 120 by bonding through the connection layer 114. Understandably, at this time, a portion of the filling portion 102 is located between two adjacent first chips 110 of the at least two first chips 110.

[0079] Exemplarily, the carrier substrate 120 can be a second chip, which can also be a chip of various types. For example, the chip can also be a computing unit, a memory chip, a radio frequency chip, etc. It can be understood that, when the carrier substrate 120 is a second chip, the chip package structure 100 can further include a support plate 103, which is arranged on a side of the at least two first chips 110 away from the second chip (carrier substrate 120). The side of the second chip away from the first chips 110 can be provided with a pad 121, and the first chips 110 can be connected with the pad 121.

[0080] The second chip (carrier substrate 120) can also include a substrate 111 and a circuit layer 112 and a redistribution layer 113 arranged in sequence on one side of the substrate 111. The other side of the substrate 111 of the carrier substrate 120 can also be provided with a redistribution layer 113. The electrical connection structure 115 penetrates the substrate 111 to connect the circuit layer 112 or the chip on one side of the substrate 111 with the redistribution layer 113 on the other side of the substrate 111. For example, the first chip 110 is connected with the pad 121 through the electrical connection structure 115 penetrating at least partially the second chip. The pad 121 can be a micro-bump, a solder ball, etc. The electrical connection structure 115 can be arranged in a through silicon via (TSV).

[0081] Please refer to FIG. 12, a plurality of first chips 110 can also be arranged in a stack in the first direction X. The substrate 111 of the first chip 110 can be provided with a through silicon via, and the through silicon via can also be provided with an electrical connection structure 115 for connecting electrical elements or circuits on both sides of the first chip 110. Meanwhile, a plurality of first chips 110 can also be arranged in the same plane.

[0082] Exemplarily, the chip package structure 100 can also include a plurality of second chips (carrier substrates 120). Please refer to FIG. 13 and FIG. 14, two second chips (carrier substrates 120) can be arranged in the same plane, and one first chip 110 is arranged on both second chips, that is, a part of the first chip 110 is arranged on one second chip, and another part of the first chip 110 is arranged on the other second chip. In addition, more first chips 110 can also be arranged on the second chips. The first chip 110 and the second chip can be arranged in a face to face (F2F) architecture, as shown in FIG. 13; or the first chip 110 and the second chip can be arranged in a face to back (F2B) architecture, as shown in FIG. 14.

[0083] In some embodiments, the carrier substrate 120 can also be a bridge, i.e. the carrier substrate 120 can also implement a bridge function. Similarly, at least two first chips 110 can be disposed on one side surface of the bridge. The second chip can be disposed with a pad 121 away from the side of the first chip 110, and the first chip 110 can be connected with the pad 121. For example, the first chip 110 is connected with the pad 121 through an electrical connection structure 115 at least partially penetrating the bridge. The electrical connection structure 115 can be disposed in a through silicon via.

[0084] Referring to FIG. 15, various types of first chips 110 can be disposed on the bridge (carrier substrate 120), such as a core die, an input / output die, etc. It can be understood that a via (VIA) region can also be disposed on the carrier substrate 120, and the circuits on the upper and lower sides of the carrier substrate 120 can be connected through the via region. Referring to FIG. 16, the carrier substrate 120 can also be directly disposed on the circuit board 12, so that the first chips 110 on the carrier substrate 120 can be connected with other circuits on the circuit board 12 through the circuit board 12.

[0085] Referring to FIG. 17, the chip packaging structure 100 can further include a global carrier substrate 150, a 3D package, an input / output unit 170, and a high bandwidth memory (HBM) 180, etc. The 3D package, the input / output unit 170, and the high bandwidth memory 180 can be disposed on the same global carrier substrate 150. The 3D package can include a first chip 110 and a carrier substrate 120, and the first chip 110 is disposed on the carrier substrate 120. Thus, the 3D package is disposed on the global carrier substrate 150 through the carrier substrate 120 of the 3D package.

[0086] Referring to FIG. 18, the difference between FIG. 18 and FIG. 17 is that a bridge chip 130 can also be disposed in the global carrier substrate 150. The bridge chip 130 can implement the connection of integrated circuits or electrical elements disposed on the carrier substrate 150, for example, the bridge chip 130 can implement the connection of the 3D package and the high bandwidth memory, so that the high bandwidth memory and the first chip 110 in the 3D package can communicate.

[0087] Referring to FIG. 19, the chip packaging structure 100 can include a global carrier substrate 150, a heat dissipation structure 140, and a 3D package. The heat dissipation structure 140 can be disposed on the global carrier substrate 150, and the 3D package is disposed between the heat dissipation structure 140 and the global carrier substrate 150. Thus, the heat dissipation structure 140 can dissipate heat for the 3D package.

[0088] It can be understood that other components can also be disposed in the chip packaging structure 100, such as sensors, antennas, capacitors, inductors, etc., which will not be described herein.

[0089] Referring to FIG. 20 and FIG. 7, the application further provides a method for manufacturing the chip packaging structure 100. The method comprises the following steps:

[0090] S100, referring to FIG. 21, a substrate 111 is provided, and the substrate 111 is formed with an initial circuit layer 112a, and the initial circuit layer 112a comprises a cutting path 117.

[0091] The material of the substrate 111 can refer to the material of the substrate 111 of the first chip 110 in the chip packaging structure 100. The substrate 111 is formed with the initial circuit layer 112a by a suitable semiconductor process, and the initial circuit layer 112a comprises a plurality of integrated circuit regions, and at least one integrated circuit is formed in each integrated circuit region.

[0092] A plurality of electrical elements constituting the integrated circuit are arranged in the initial circuit layer 112a, for example, the plurality of electrical elements can comprise transistors, diodes, capacitors, resistors, etc. Among them, the transistor can comprise a gate structure, a source region and a drain region, the source region and the drain region are a channel, and the gate structure is arranged on the channel. The source region and the drain region can be formed in the substrate 111 by a photolithography process, an ion implantation process, etc. The channel can be a semiconductor fin, a semiconductor nanosheet, a semiconductor nanowire, etc. The transistor can be a nanostructure field-effect transistor (Nanostructure-FET), a fin field-effect transistor (FinFET), a planar transistor, etc.

[0093] The initial circuit layer 112a can further comprise an interlayer dielectric layer and a metal interconnection layer. The interlayer dielectric layer surrounds and can cover the plurality of electrical elements. The interlayer dielectric layer can comprise a dielectric layer and a metal plug, and the metal plug penetrates the dielectric layer and is connected with the electrical element. The metal interconnection layer can interconnect the electrical elements to form the integrated circuit. The metal interconnection layer can comprise a dielectric layer and an interconnection structure, and the interconnection structure can be formed by a metallization pattern in the dielectric layer, and the metallization pattern can be directly connected with the plurality of metal plugs and / or the electrical elements, so that the plurality of electrical elements form the integrated circuit.

[0094] The cutting path 117 can be arranged around the integrated circuit region, that is, the cutting path 117 is arranged around the integrated circuit region. Some test keys for testing the function of the integrated circuit can be arranged on the cutting path 117. It can be understood that the test keys can comprise a metal material. Therefore, a suitable cutting process needs to be selected when cutting the cutting path 117. The cutting path 117 can also be arranged only between two adjacent integrated circuit regions. In order to facilitate the description, only the cutting path 117 between two integrated circuit regions is shown in FIG. 21.

[0095] In some embodiments, referring to FIG. 22, a barrier layer 118 can also be formed on the side of the initial circuit layer 112a away from the substrate 111. The barrier layer 118 can be used as an etch stop layer when etching other film layers on the barrier layer 118 in subsequent processes. The barrier layer 118 can be formed by CVD, PVD, or other processes. The material of the barrier layer 118 can be one or more of silicon nitride (SiN), silicon carbon nitride (SiCN), or TEOS-based silicon oxide.

[0096] S200, referring to FIG. 23 and in combination with FIG. 22, a groove 127 is formed on the scribe lane 117, and the initial circuit layer 112a forms the circuit layer 112.

[0097] As mentioned above, there can be metal material in the scribe lane 117, and thus some cutting processes cannot be used. For example, it is difficult to remove metal material by plasma cutting process. The metal material can be cut by laser, and the groove 127 formed on the scribe lane 117 can be formed by laser scribing process. Exemplarily, the groove 127 formed by laser scribing process can penetrate the barrier layer 118 (if any) and the initial circuit layer 112a. A portion of the groove 127 can also be formed in the substrate 111. It can be understood that when the groove 127 is formed, the metal material in the scribe lane 117 can not be completely removed, for example, a portion of the metal material can remain near the sidewall of the groove. Since the scribe lane 117 can be arranged around each integrated circuit region of the initial circuit layer 112a, the groove 127 formed on the scribe lane 117 can also be arranged around each integrated circuit region of the initial circuit layer 112a.

[0098] In addition, when the groove 127 is formed by laser scribing process, due to the characteristics of the process, the opening of the groove 127 can be larger than the size of the bottom of the groove 127, that is, the cross-sectional shape of the groove 127 can be trapezoidal, and the long side of the trapezoid is the opening and the short side is the bottom. Thus, the sidewall of the groove 127 is an inclined slope.

[0099] In some embodiments, referring to FIG. 24 and in combination with FIG. 22, since the laser scribing process generates a large amount of heat, in order to reduce the impact on the electrical elements in the integrated circuit region, a buffer structure 116 can also be formed on the edge of each integrated circuit region by a suitable process before the groove 127 is formed.

[0100] Exemplarily, the buffer recesses can be formed by photolithography and etching processes, then the buffer structure 116 can be formed in the buffer recesses by deposition process, and finally the excess material outside the recesses can be removed. It can be understood that the size of the buffer recesses in the first direction X determines the size of the buffer structure 116 in the first direction X. For example, the buffer recesses can extend through the initial circuit layer 112a and into the substrate 111, and the buffer structure 116 formed thereby also extends through the initial circuit layer 112a and into the substrate 111. The material of the buffer structure 116 is as described above, and these materials can be formed in the buffer recesses by suitable processes.

[0101] Exemplarily, a plurality of buffer holes can also be formed by photolithography and etching processes, the plurality of buffer holes are formed in the edge region of the integrated circuit region and surround the integrated circuits in the integrated circuit region, and the distance between the plurality of buffer holes can be equal, which will not be described herein.

[0102] Therefore, due to the provision of the buffer structure 116, when the scribe line 117 is cut by using the laser scribing process, the buffer structure 116 can increase the proportion of heat generated by the laser to be conducted into the air, thereby reducing the thermal effect on the electrical elements. In the following description, the case without the provision of the buffer structure 116 is exemplified, but the case with the provision of the buffer structure 116 is also applicable.

[0103] S300, filling the medium material 139 in the recess 127.

[0104] Please refer to FIGS. 25-26 in combination with FIG. 23, the medium material 139 can be filled in the recess 127 by suitable processes, and the medium material 139 can be TEOS type silicon oxide, silicon nitride, aluminum oxide, thallium nitride, etc. CVD, PVD, etc. processes can be used according to the type of the medium material 139. After the medium material 139 is formed, the medium material 139 outside the recess 127 can be removed, i.e. the medium material 139 covering the circuit layer 112 is removed, thereby achieving planarization. Suitable processes such as CMP, etching, etc. can be used to remove the excess medium material 139.

[0105] In some embodiments, the medium material 139 formed can also include multiple materials. For example, the medium material 139 can be formed by deposition process as multiple film layers, which fill the recesses 127 one by one. In this case, the film layer closer to the circuit layer 112 can have better filling performance or a thermal expansion coefficient closer to that of the circuit layer 112. For example, referring to FIG. 27 and FIG. 23, a first film layer structure 1191 is formed to cover the surfaces of the recesses 127, i.e., the first film layer structure 1191 does not completely fill the recesses 127; then a second film layer structure 1192 is formed to fill the recesses 127. Thus, the recesses 127 are filled by the first film layer structure 1191 and the second film layer structure 1192. The first film layer structure 1191 has better filling performance or a thermal expansion coefficient closer to that of the circuit layer 112 than the second film layer structure 1192. It can be understood that after the medium material 139 is formed, the first film layer structure 1191 and the second film layer structure 1192 outside the recesses 127 can also be removed.

[0106] Thus, the metal clearance area is formed in the cutting groove, so that the subsequent cutting process is not limited by the process, and a cutting process meeting the process requirements can be selected.

[0107] S400, referring to FIG. 28, a redistribution layer 113 is formed on the circuit layer 112.

[0108] In some embodiments, the redistribution layer 113 formed on the circuit layer 112 can be formed by forming a medium layer on the circuit layer 112, and then forming a metallization pattern in the medium layer by damascene process, i.e., forming a conductive structure. That is, after the medium layer is formed, a patterned recess is formed in the medium layer by photolithography and etching process, and then a conductive material is formed in the patterned recess by deposition process, the conductive material fills the patterned recess, and finally the excess conductive material outside the patterned recess is removed, and the conductive material in the patterned recess is the conductive structure.

[0109] It can be understood that since the medium material 139 formed in step S300 can be formed on the circuit layer 112. Therefore, a thicker medium material 139 can be formed on the circuit layer 112 in step S300, and then a planarization process is performed on the medium material 139 on the circuit layer 112, so that the medium material 139 on the circuit layer 112 can serve as the medium layer for forming the redistribution layer 113 in step S400, i.e., the conductive structure can be formed in the medium material 139 on the circuit layer 112. Thus, the process steps can be reduced and the cost can be reduced. In this case, the medium material 139 is integrated with the medium layer of the redistribution layer 113, i.e., formed integrally. When the medium material 139 formed includes multiple film layers, the multiple film layers can also serve as the medium layer for forming the redistribution layer 113 in this step.

[0110] Please refer to FIG. 29, after the redistribution layer 113 is formed, a connection layer 114 can be further formed on the redistribution layer 113. The connection layer 114 can include connection members and a medium layer, the connection members being connected with the conductive structures 1131 of the redistribution layer 113 through the medium layer. The connection members can include conductive pillars or bonding pads, etc. The connection layer 114 can be formed by using similar processes as the redistribution layer 113, and the present application will not be described in detail.

[0111] S500, please refer to FIGS. 30 and 31, and combine with FIGS. 7 and 29, the redistribution layer 113, the medium material 139 and the substrate 111 are cut to form the first chip 110, the medium material 139 forms the medium structure 119, the medium structure 119 surrounds the circuit layer 112, and in the thickness direction of the substrate 111, the medium structure 119 is at least partially located between the substrate 111 and the redistribution layer 112.

[0112] Since the redistribution layer 113 and the connection layer 114 are not formed with metal material in the part above the cutting groove 117 when the redistribution layer 113 and the connection layer 114 are formed, the cutting groove 117 is a metal clearance. Therefore, the cutting groove 117 can be cut by using a suitable process.

[0113] Exemplarily, a plasma dicing (PD) process or the like can be used for cutting. For example, please refer to FIG. 30, a cutting groove 137 is formed by using a plasma dicing process, the cutting groove 137 can not penetrate the substrate 111, and then the substrate 111 is thinned, so that the part of the substrate 111 which is not penetrated by the cutting groove 137 is completely removed. Therefore, a plurality of first chips 110 are separated and obtained, and each first chip 110 can correspond to an integrated circuit region. The cutting groove 137 formed by using the plasma dicing process to cut the connection layer 114, the redistribution layer 113 and the medium material 139 has good groove wall quality and can be substantially perpendicular to the surface of the substrate 111.

[0114] The part of the medium material 139 which is not removed is retained in the chip structure, and this part is the medium structure 119. Therefore, the medium structure 119 surrounds the circuit layer 112. Since the medium material 139 penetrates the circuit layer 112 and can partially extend into the substrate 111, in the thickness direction of the substrate 111, the medium structure 119 can be at least partially located between the substrate 111 and the redistribution layer 113.

[0115] It can be understood that after the substrate 111 is thinned, a through silicon via can be further formed on the first chip 110. For example, in the case that a plurality of first chips 110 are stacked, forming a through silicon via on the first chip 110 can facilitate the connection of electrical elements or circuits on both sides of the first chip 110.

[0116] S600, forming a filling portion 102, the filling portion 102 surrounds the first chip 110, and the dielectric structure 119 is located between the circuit layer 112 and the filling portion 102.

[0117] Please refer to FIG. 32, before forming the filling portion 102, the first chip 110 obtained by cutting can be attached to the carrier substrate 120. As mentioned above, the carrier substrate 120 can be a chip or a board. In order to improve production efficiency, the carrier substrate 120 can be formed on a wafer at this time, that is, a plurality of carrier substrates can not be separated. Therefore, the first chip 110 can be attached to a plurality of carrier substrates 120 at the same time.

[0118] The carrier substrate 120 can also include a connection layer in which a connection member is arranged. The attachment of the first chip 110 to the carrier substrate 120 can be performed by bonding the connection layer of the first chip 110 to the connection layer of the carrier substrate 120. The bonding can adopt a hybrid bonding process.

[0119] A plurality of first chips 110 can be arranged on one carrier substrate 120, and any two of the plurality of first chips 110 can be the same or different. In addition, a plurality of first chips 110 of the plurality of first chips 110 can be arranged on the same surface of the carrier substrate 120.

[0120] Please refer to FIG. 33, after the attachment is completed, there is a gap between any two of the plurality of first chips 110 arranged on the surface of the carrier substrate 120. At this time, the gap can be filled to form the filling portion 102. In this way, the filling portion 102 can surround the first chip 110, and the dielectric structure 119 is located between the circuit layer 112 and the filling portion 102. The formation of the filling portion 102 can adopt a plastic packaging process. Illustratively, the filling material, that is, the material of the filling portion 102 mentioned above, can be formed in the gap. Then, a planarization process is performed, for example, the filling material on the side surface of the first chip 110 away from the carrier substrate 120 is completely removed; if no other circuit is arranged on the surface of the first chip 110 away from the carrier substrate 120, part of the filling material on the surface of the first chip 110 away from the carrier substrate 120 can be retained, and the part of the filling material can be used to protect the first chip 110.

[0121] In some embodiments, please refer to FIG. 34, after the first chip 110 is attached to the carrier substrate 120, a support plate 103, which can also be a substrate, can be arranged on the side of the first chip 110 away from the carrier substrate 120. The support plate 103 can be arranged on the side surface of the first chip 110 and / or the filling portion 102 away from the support plate 103 by an adhesive.

[0122] It can be understood that the carrier substrate 120 can be arranged on a circuit board, the first chip 110 and the circuit board are arranged on opposite sides of the carrier substrate 120, so a through silicon via can also be arranged on the carrier substrate 120. Exemplarily, before forming the through silicon via, the carrier substrate 120 can be thinned, as shown in FIG. 35. Thus, as shown in FIG. 36, the depth of the through silicon via on the carrier substrate 120 can be reduced, so that the production efficiency can be improved. The first chip 110 and the circuit board can be connected through the through silicon via.

[0123] In addition, a redistribution layer 113 can also be arranged on the side of the carrier substrate 120 away from the first chip 110, as shown in FIG. 37. Then, a pad 121 is formed on the redistribution layer 113, as shown in FIG. 38. Thus, the carrier substrate 120 can be connected with the circuit board conveniently. In the case that the plurality of carrier substrates 120 and the support plate 103 are not divided, the plurality of carrier substrates 120 need to be divided again to separate. At this time, the support plate 103 and the filling part 102 located between adjacent carrier substrates 120 can also be cut, so that a plurality of chip package structures 100 are obtained, as shown in FIG. 7. The carrier substrate 120, the filling part 102 and the support plate 103 can be cut by using a suitable cutting process such as a knife wheel cutting, a plasma cutting, a laser cutting, a stealth cutting and the like.

[0124] The above merely illustrates the specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip package structure, characterized by, The first chip and a filling portion, the filling portion is arranged around the first chip, the first chip comprises: a substrate; a circuit layer arranged on the substrate; a redistribution layer arranged on a side of the circuit layer away from the substrate; a dielectric structure arranged around the circuit layer and at least partially located between the circuit layer and the filling portion.

2. The chip package structure of claim 1, wherein, The dielectric structure is located on a side of the redistribution layer close to the substrate and overlaps with the redistribution layer in the thickness direction of the substrate.

3. The chip package structure of claim 1 or 2, wherein, The sidewall of the substrate, the sidewall of the dielectric structure and the sidewall of the redistribution layer form at least part of the sidewall of the first chip, and the sidewall of the first chip extends in the thickness direction of the substrate.

4. The chip package structure of any one of claims 1 to 3, wherein, In the direction of the redistribution layer pointing to the substrate, the surface of the dielectric structure away from the filling portion gradually approaches the filling portion.

5. The chip package structure of any one of claims 1 to 4, wherein, The dielectric structure comprises a first film layer structure and a second film layer structure, and the first film layer structure is located between the second film layer structure and the circuit layer.

6. The chip package structure of claim 5, wherein, The absolute value of the difference between the thermal expansion coefficient of the first film layer structure and the thermal expansion coefficient of the circuit layer is less than the absolute value of the difference between the thermal expansion coefficient of the second film layer structure and the thermal expansion coefficient of the circuit layer.

7. The chip package structure of any one of claims 1-6, wherein, The redistribution layer comprises a dielectric layer and a conductive structure arranged in the dielectric layer, and the dielectric layer is integrally formed with at least part of the dielectric structure.

8. The chip package structure of any one of claims 1-7, wherein, The first chip further comprises a buffer structure, the circuit layer comprises a central region where electrical elements are arranged, and the buffer structure penetrates through the circuit layer and is arranged around the central region.

9. The chip package structure of any one of claims 1-8, wherein, Further comprising a carrier substrate, the number of the first chip is at least two, and at least two of the first chip are arranged on the same surface of the carrier substrate, and a part of the filling portion is arranged between adjacent at least two of the first chip.

10. The chip package structure of claim 9, wherein, Further comprising a support plate, the support plate is arranged on a side of the at least two first chips away from the carrier substrate; The carrier substrate is a second chip, and a pad is arranged on a side of the second chip away from the first chip; The first chip is connected with the pad through a conductive structure penetrating at least partially through the second chip.

11. The chip package structure of claim 9, wherein: The carrier substrate is a conversion plate, and a pad is arranged on a side of the conversion plate away from the first chip; The first chip is connected with the pad through a conductive structure penetrating at least partially through the conversion plate.

12. A method for fabricating a chip packaging structure, characterized in that, The method comprises: providing a substrate, an initial circuit layer is formed on the substrate, and the initial circuit layer comprises a cutting channel; forming a groove on the cutting channel, and forming a circuit layer from the initial circuit layer; filling a dielectric material in the groove; forming a redistribution layer on the circuit layer; cutting the redistribution layer, the dielectric material and the substrate to form a first chip, the dielectric material forms a dielectric structure, the dielectric structure surrounds the circuit layer, and in the thickness direction of the substrate, the dielectric structure is at least partially located between the substrate and the redistribution layer; forming a filling portion, the filling portion surrounds the first chip, and the dielectric structure is located between the circuit layer and the filling portion.

13. The production method according to claim 12, wherein The filling medium material in the groove comprises: forming a first film layer structure, covering the surface of the groove; forming a second film layer structure, filling the groove.

14. The production method according to claim 12 or 13, characterized by, The medium material is also formed on the circuit layer; the forming redistribution layer comprises: forming a conductive structure in the medium material on the circuit layer, wherein the medium material on the circuit layer forms a dielectric layer, and the conductive structure is arranged in the dielectric layer.

15. An electronic device, comprising: The chip packaging structure comprises a circuit board and a chip packaging structure as claimed in any one of claims 1-11, and the chip packaging structure is arranged on the circuit board.

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