Real-time task processing method and related apparatus

Abstract

A real-time task processing method, applied to a real-time operating system. The real-time task processing method comprises: when an executable file of a real-time task is loaded, loading, onto a first memory area of a memory, code and data in the executable file used for implementing a process having an execution duration requirement, and then on the basis of a mapping relationship between the memory and a cache, caching the code and the data on the first memory area onto a first cache area having a higher reading speed. As the first cache area is only used for caching content on the first memory area, it can be ensured that content cached in the first cache area is used for implementing a process having an execution duration requirement, thereby preventing the first cache area from being preempted by other data content, improving the cache hit rate during execution of a real-time task, and further ensuring that the real-time task can be completed within a specified time period.

Description

A processing method of a real-time task and related apparatus

[0001] The present application claims priority to the Chinese Patent Application No. 202411346967.5, filed on September 25, 2024, and entitled "A processing method of a real-time task and related apparatus", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of computers, and in particular, to a processing method of a real-time task and related apparatus. BACKGROUND

[0003] A real-time operating system (RTOS) is an operating system specially used for running real-time tasks. The real-time operating system can ensure that the real-time tasks are completed within a specific time by managing limited hardware resources. In simple terms, the real-time operating system is an operating system that guarantees to complete a specific function within a certain time limit.

[0004] The real-time tasks running on the real-time operating system usually include hard real-time tasks and soft real-time tasks. The hard real-time tasks require that the tasks must be completed within a specified time, otherwise it may cause serious consequences. The soft real-time tasks require that the tasks can be completed as soon as possible, and do not require that the tasks must be completed within a specified time.

[0005] At present, in the real-time operating system, the hard real-time tasks can usually be completed within the specified time. However, in some extreme cases, there may be a situation that part of the hard real-time tasks cannot be completed within the specified time in the real-time operating system, so that the real-time operating system cannot meet the time requirement of the hard real-time tasks, which is easy to cause serious consequences. SUMMARY

[0006] The present application provides a processing method of a real-time task and related apparatus, which can improve the cache hit rate when executing the real-time task, and further ensure that the real-time task can be completed within a specified time.

[0007] In a first aspect, a processing method of a real-time task is provided, which is applied to a real-time operating system. The processing method of the real-time task specifically includes: in the process of loading an executable file of the real-time task, a device loads first code and first data for implementing a key process in the executable file onto a first memory area of a memory, the key process including a process in the real-time task that needs to meet an execution time requirement. The first code can be binary instructions in the executable file, and the first data can be variables or constants in the executable file.

[0008] Then, based on a mapping relationship between the first memory region and the first cache region on the cache, the execution device copies the first code and the first data from the first memory region to the first cache region. The mapping relationship is used to indicate that the first cache region is only used to cache the content stored in the first memory region, and the reading speed of the cache is higher than that of the memory.

[0009] Secondly, in response to obtaining the instruction of executing the critical process, the execution device obtains the first code and the first data from the first cache region without obtaining the first code and the first data from the memory, and executes the critical process.

[0010] In the present solution, when loading the executable file of the real-time task, the code and the data in the executable file for implementing the process with the execution time requirement are loaded onto the first memory region of the memory, and then the code and the data on the first memory region are cached onto the first cache region with a higher reading speed based on the mapping relationship between the memory and the cache. Since the first cache region is only used to cache the content on the first memory region, it can be ensured that the content cached in the first cache region is all for implementing the process with the execution time requirement, avoiding the first cache region being occupied by other data content, improving the cache hit rate when executing the real-time task, and further ensuring that the real-time task can be completed within the specified time.

[0011] In a possible implementation, the capacity of the first cache region is the same as that of the first memory region. In this way, all the content stored in the first memory region can be cached in the first cache region and will not be replaced out.

[0012] In the present solution, by setting the first cache region and the first memory region with the same capacity, the first cache region can cache all the content in the first memory region at the same time, so that the first code and the first data cached in the first cache region will not be replaced out due to insufficient storage space of the first cache region, thereby ensuring that the first code and the first data can be cached in the first cache region at all times. In this way, the execution device can have a 100% hit rate when reading the first code and the first data in the cache, and further ensure that the reading speed of the code and the data when the execution device executes the critical process is deterministic and highest.

[0013] In a possible implementation, during loading of the real-time operating system, the execution device loads second code and second data for implementing the interrupt processing flow and the task scheduling flow onto the first memory region. And, based on the mapping relationship between the first memory region and the first cache region, the execution device copies the second code and the second data from the first memory region to the first cache region. Next, in response to obtaining the interrupt request, the execution device obtains the second code and the second data from the first cache region, and executes the interrupt processing flow and the task scheduling flow to schedule execution of the critical flow.

[0014] The second code includes code for implementing the interrupt processing flow and code for implementing the task scheduling flow. The second data includes data for implementing the interrupt processing flow and data for implementing the task scheduling flow.

[0015] In this solution, in addition to storing the code and data for implementing the critical flow in the first memory region corresponding to the first cache region, the code and data for implementing the interrupt processing flow and the task scheduling flow in the real-time operating system are also stored in the first memory region corresponding to the first cache region, so that all the code and data related to the critical flow are cached in the first cache region, and the interrupt processing flow and the task scheduling flow that may affect the execution efficiency of the critical flow can also be quickly executed, thereby improving the execution efficiency of the critical flow and ensuring that the critical flow can be completed within a limited time.

[0016] In a possible implementation, when loading the executable file of the real-time task, the execution device loads code and data that are not used for implementing the critical flow in the executable file onto the second memory region of the memory. The first memory region and the second memory region do not have a memory region in common, and the content stored on the second memory region cannot be copied to the first cache region.

[0017] In this solution, by storing the code and data for implementing the critical flow and the code and data that are not used for implementing the critical flow in the executable file of the real-time task in different memory regions of the memory, the code and data for executing different flows can be isolated in the memory, the pollution and interference between the memory regions where the code and data for executing different flows in the same real-time task are located can be avoided, and the high hit rate of the code and data for implementing the critical flow in the cache can be ensured.

[0018] In a possible implementation, in the process of loading the executable file of the non-real-time task, the execution device loads the code and data in the executable file of the non-real-time task onto the second memory region. That is, since all the code and data in the executable file of the non-real-time task do not participate in the critical process, all the code and data in the executable file of the non-real-time task are loaded onto the second memory region, so as to ensure that all the code and data corresponding to the non-real-time task will not be cached into the first cache region.

[0019] In a possible implementation, during the running of the execution device, the execution device copies the content in the second memory region to the second cache region based on the mapping relationship between the second memory region and the second cache region on the cache, where the first cache region and the second cache region do not have a coincident cache region.

[0020] In this solution, on the basis of the first cache region in the cache which is specially used to cache the code and data related to the critical process, the second cache region used to cache the code and data related to other processes is further arranged, so that the efficiency of the CPU in executing other processes can be improved as much as possible by using the higher reading speed of the cache without affecting the execution efficiency of the critical process.

[0021] In a possible implementation, the first code and the first data have target marks in the executable file. When the executable file of the real-time task is loaded, the execution device first determines the first code and the first data with the target marks in the executable file; then, the execution device loads the first code and the first data onto the first memory region.

[0022] In a possible implementation, the executable file indicates the storage addresses of the first code and the first data, and the storage addresses are located on the first memory region. When the executable file of the real-time task is loaded, the execution device loads the first code and the first data onto the storage addresses of the first memory region according to the storage addresses of the first code and the first data indicated in the executable file.

[0023] In a possible implementation, the execution duration of the critical process is less than or equal to a preset duration.

[0024] In a second aspect, a real-time task processing apparatus is provided. The real-time task processing apparatus is applied to a real-time operating system, and includes: a loading module, configured to load, in a process of loading an executable file of a real-time task, first code and first data for implementing a critical process in the executable file onto a first memory region of a memory, the critical process including a process in the real-time task that needs to meet a time requirement for execution; a processing module, configured to copy the first code and the first data from the first memory region to a first cache region on a cache based on a mapping relationship between the first memory region and the first cache region, wherein the mapping relationship is used to indicate that the first cache region is used only for caching content stored in the first memory region, and a reading speed of the cache is higher than a reading speed of the memory; and the processing module is further configured to, in response to obtaining an instruction to execute the critical process, obtain the first code and the first data from the first cache region, and execute the critical process.

[0025] In a possible implementation, the capacity of the first cache region is the same as the capacity of the first memory region.

[0026] In a possible implementation, the loading module is further configured to load, in a process of loading the real-time operating system, second code and second data for implementing an interrupt processing process and a task scheduling process onto the first memory region; the processing module is further configured to copy the second code and the second data from the first memory region to the first cache region based on the mapping relationship; and the processing module is further configured to, in response to obtaining an interrupt request, obtain the second code and the second data from the first cache region, and execute the interrupt processing process and the task scheduling process to schedule execution of the critical process.

[0027] In a possible implementation, the loading module is further configured to load, in a process of loading the real-time operating system, second code and second data for implementing an interrupt processing process and a task scheduling process onto the first memory region; the processing module is further configured to copy the second code and the second data from the first memory region to the first cache region based on the mapping relationship; and the processing module is further configured to, in response to obtaining an interrupt request, obtain the second code and the second data from the first cache region, and execute the interrupt processing process and the task scheduling process to schedule execution of the critical process.

[0028] In a possible implementation, the loading module is further configured to load, in a process of loading an executable file of a non-real-time task, code and data in the executable file of the non-real-time task onto the second memory region.

[0029] In a possible implementation, the processing module is further configured to copy content in the second memory region to a second cache region on the cache based on a mapping relationship between the second memory region and the second cache region, wherein the first cache region and the second cache region do not have a coincident cache region.

[0030] In a possible implementation, the first code and the first data have target marks in the executable file, and the loading module is further configured to: determine the first code and the first data with the target marks in the executable file; and load the first code and the first data onto the first memory region.

[0031] In a possible implementation, the executable file indicates storage addresses of the first code and the first data, and the storage addresses are located on the first memory region; and the loading module is further configured to: load the first code and the first data onto the storage addresses of the first memory region according to the storage addresses indicated in the executable file.

[0032] In a possible implementation, the execution duration of the critical process is less than or equal to the preset duration.

[0033] The third aspect of the present application provides a processing apparatus of a real-time task, which can include a processor, the processor being coupled with a memory, and the memory storing program instructions, which, when executed by the processor, implement the method of the first aspect or any implementation manner of the first aspect. For the processor to execute the steps in each possible implementation manner of the first aspect, specific details can be referred to the first aspect, which will not be repeated here.

[0034] The fourth aspect of the present application provides a computer-readable storage medium, which stores a computer program, and when the computer program is run on a computer, the computer program causes the computer to execute the method of any implementation manner of the first aspect.

[0035] The fifth aspect of the present application provides a circuit system, which includes a processing circuit configured to execute the method of any implementation manner of the first aspect.

[0036] The sixth aspect of the present application provides a computer program product, which, when running on a computer, causes the computer to execute the method of any implementation manner of the first aspect.

[0037] The seventh aspect of the present application provides a chip system, which includes a processor configured to support a server to implement the functions involved in any implementation manner of the first aspect, for example, to process the data and / or information involved in the method. In a possible design, the chip system further includes a memory configured to save necessary program instructions and data of the server. The chip system can be composed of a chip, or can include the chip and other discrete devices.

[0038] The advantages of the second aspect to the seventh aspect can be referred to the introduction of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0039] FIG. 1 is a schematic diagram of a system architecture provided by the present application;

[0040] Fig. 2 is a flow diagram of a real-time task processing method provided by the present application;

[0041] Fig. 3 is a diagram of a mapping relationship between a memory and a cache provided by the present application;

[0042] Fig. 4 is a diagram of another mapping relationship between a memory and a cache provided by the present application;

[0043] Fig. 5 is a diagram of a task processing timing in a hard real-time task scenario provided by the present application;

[0044] Fig. 6 is a diagram of a processing flow of real-time tasks and non-real-time tasks provided by the present application;

[0045] Fig. 7 is a diagram of another processing flow of real-time tasks and non-real-time tasks provided by the present application;

[0046] Fig. 8 is a diagram of a cache supporting a set-associative mode provided by the present application;

[0047] Fig. 9 is a diagram of a structure of a real-time task processing apparatus provided by the present application;

[0048] Fig. 10 is a diagram of a structure of an electronic device provided by the present application;

[0049] Fig. 11 is a diagram of a structure of a computer-readable storage medium provided by the present application. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments of the present application.

[0051] The terms "first", "second", "third", "fourth" and the like (if any) in the specification and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein.

[0052] In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device containing a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0053] (1) Real-time Operating System

[0054] A real-time operating system is an operating system that schedules all available resources to complete real-time tasks and controls all real-time tasks to run in coordination.

[0055] (2) Real-time Task

[0056] In a real-time system, there are usually multiple real-time tasks running. These real-time tasks are usually related to certain external devices and can reflect or control the corresponding external devices, thus having a certain degree of urgency. Generally, real-time tasks can be classified from different perspectives.

[0057] According to whether the task execution presents periodic changes:

[0058] a. Periodic real-time task

[0059] The external device periodically sends an excitation signal to the computer, requiring the computer to execute in a specified cycle to periodically control certain external devices.

[0060] b. Non-periodic real-time task

[0061] The excitation signal sent by the external device has no obvious periodicity, but must be associated with a deadline. The deadline can be divided into two parts: the start deadline (i.e., the task must start execution before a certain time) and the completion deadline (i.e., the task must be completed before a certain time).

[0062] According to the requirements of the task for the deadline, real-time tasks can be divided into hard real-time tasks and soft real-time tasks. Among them, hard real-time tasks require the task to be completed within a specified time, otherwise it may cause serious consequences. Soft real-time tasks require the task to be completed as soon as possible, and do not require the task to be completed within a specified time.

[0063] (3) Interrupt

[0064] An interrupt is when the computer encounters an unexpected situation that requires intervention, the computer can automatically stop the running program and switch to processing a new program, and after processing, it returns to the paused program to continue running.

[0065] In the specific implementation of the interrupt, the hardware device or program in the computer can interrupt the normal execution flow of the Central Processing Unit (CPU) by sending an interrupt request to the CPU, thereby triggering the CPU to execute a specific interrupt service program.

[0066] (4) Cache

[0067] Cache refers to a memory that can exchange data at high speed. Generally, the reading speed of cache is higher than that of memory, so cache exchanges data with CPU before memory. That is, when CPU needs to access data, it first searches for data in cache. If CPU can find data in cache (cache hit), CPU directly reads data from cache without accessing memory; if CPU cannot find data in cache (cache miss), CPU continues to search for and read data in memory.

[0068] At present, in real-time operating systems, hard real-time tasks can generally be completed within the specified time. However, in some extreme cases, part of the hard real-time tasks in the real-time operating system may not be completed within the specified time, so that the real-time operating system cannot meet the time requirements of the hard real-time tasks, which may easily lead to serious consequences.

[0069] The applicant found that the main reason why the hard real-time task cannot be completed within the specified time is that the data access delay caused by cache miss is not controlled when CPU accesses the data required for executing the hard real-time task. In simple terms, when CPU needs to execute a hard real-time task, it first searches for the data required for executing the hard real-time task in cache. If the data required for executing the hard real-time task cannot be found in cache, CPU will continue to search for and read the data required for executing the hard real-time task in memory. In some extreme cases, if cache does not store any data required for executing the hard real-time task (for example, cache is preempted by other data), CPU needs to search for and read all the data required for executing the hard real-time task in memory, resulting in a long data access delay, which in turn leads to the situation that the hard real-time task cannot be completed within the specified time.

[0070] The present application provides a real-time task processing method. When loading the executable file of the real-time task, the code and data for implementing the process with execution time requirement in the executable file are loaded onto the first memory area of memory, and then the code and data on the first memory area are cached onto the first cache area with higher reading speed based on the mapping relationship between memory and cache. Since the first cache area is only used to cache the content on the first memory area, it can ensure that the content cached in the first cache area is used to implement the process with execution time requirement, avoid the first cache area being preempted by other data content, improve the cache hit rate when executing the real-time task, and thus ensure that the real-time task can be completed within the specified time.

[0071] Please refer to Fig. 1, which is a schematic diagram of a system architecture provided by the present application. As shown in Fig. 1, in the system architecture, the execution device 101 may, for example, be a physical host or a physical server or the like. The execution device 101 includes a CPU 1011, a memory 1012 and a cache 1013. The memory 1012 is used to store the code and data of a real-time task running on the execution device 101, and the cache 1013 is used to cache part of the code and data stored in the memory.

[0072] Further, the execution device 101 is in communication connection with a data storage system 102, and is used to obtain the program code stored in the data storage system 102 to implement the processing method of the real-time task provided by the present application. The data storage system 102 may, for example, be implemented by a storage device deployed on the execution device 101, for example, the execution device 101 is a physical server, and the data storage system 102 is a hard disk deployed on the physical server. The data storage system 102 may also be implemented by a storage device independent of the execution device, for example, the execution device 101 is a computing server, and the data storage system 102 is a data server specially storing program code.

[0073] During work, the execution device 101 can obtain the program code and related data required by the processing method of the real-time task from the data storage system 102, and provide an efficient thread calling system service on the execution device 101 based on the processing method of the real-time task provided by the present application.

[0074] The execution device 101 runs a real-time operating system, which is used to control all real-time tasks to run coordinately based on the real-time operating system. Specifically, the execution device 101 running the real-time operating system may, for example, be a device in the fields of aerospace, military, medical, industry, consumer electronics, automotive electronics, energy, high-end manufacturing, Internet of Things, etc., such as a computer, an Internet of Things device or a wireless control device.

[0075] For example, please refer to Fig. 2, which is a flowchart of a processing method of a real-time task provided by the present application. As shown in Fig. 2, the processing method of the real-time task is applied to a real-time operating system, and the processing method of the real-time task includes the following steps 201-203.

[0076] In step 201, during loading of an executable file of a real-time task, the first code and the first data in the executable file for implementing a critical process are loaded onto a first memory area of the memory, and the critical process includes a process with an execution time requirement in the real-time task.

[0077] In the running process of the execution device, in order to be able to execute real-time tasks, the execution device often needs to load the executable file of the real-time task first, that is, load the executable task of the real-time task from the hard disk to the memory. Among them, the execution device can trigger the loading of the executable file of the real-time task at startup; or after startup, after obtaining the corresponding instruction or external input signal, trigger the loading of the executable file of the real-time task, which is not limited in this application.

[0078] When loading the executable file of the real-time task, the execution device loads different codes and data in the executable file into different memory regions in the memory. Specifically, the execution device loads the first code and the first data in the executable file for implementing the critical process into the first memory region of the memory, and loads other codes and other data in the executable file which are not used to implement the critical process into the memory region other than the first memory region of the memory, so that the codes and data for implementing the critical process are isolated from the codes and data which are not used to implement the critical process in the memory. Among them, the first code can be the binary instruction in the executable file, and the first data can be the variable or constant in the executable file. During the running of the first code, the first data can be read or modified. Based on the first code and the first data, a specific process in the real-time task can be implemented.

[0079] Among them, the critical process can include the process in the real-time task that has an execution time requirement. For example, the critical process can include only the process in the current real-time task that has an execution time requirement, or can include the process in the current real-time task and other real-time tasks (i.e. multiple real-time tasks) that has an execution time requirement. That is, the first code and the first data in the executable file can be used to implement the entire critical process, or can be used to implement only part of the processes in the critical process.

[0080] Optionally, the execution time of the critical process needs to be less than or equal to a preset time length, wherein the preset time length is determined or adjusted according to the type of the critical process itself in the actual application scenario, which is not limited here. Therefore, in the case that the first code and the first data in the executable file are used to implement the entire critical process, the above execution time requirement can refer to the execution time being less than or equal to the preset time length. In the case that the first code and the first data in the executable file are used to implement part of the processes in the critical process, the above execution time requirement can refer to the execution time being less than or equal to a specified time length (wherein the specified time length is less than the preset time length); or the execution time of the process implemented by the first code and the first data and the execution time of other processes need to be less than or equal to the preset time length.

[0081] In general, the process implemented based on the first code and the first data needs to be completed within a certain time length so as to meet the time length requirement of the real-time task.

[0082] In step 202, the first code and the first data are copied from the first memory region to the first cache region based on the mapping relationship between the first memory region and the first cache region on the cache, where the mapping relationship is used to indicate that the first cache region is only used to cache the content stored in the first memory region, and the reading speed of the cache is higher than that of the memory.

[0083] Exemplarily, refer to FIG. 3, which is a schematic diagram of the mapping relationship established between the memory and the cache provided in the present application. As shown in FIG. 3, in the present application, the mapping relationship is established between the first memory region on the memory and the first cache region on the cache, which indicates that the first cache region is only used to cache the content stored in the first memory region. That is, the first cache region will not cache the content on the memory other than the first memory region. In this way, based on the mapping relationship between the first memory region and the first cache region, the execution device can copy the first code and the first data from the first memory region to the first cache region so as to improve the reading speed of the CPU for the first code and the first data subsequently.

[0084] It can be understood that in the execution device, the reading speed of the cache is usually much higher than that of the memory, but due to the cost, the capacity of the cache is usually much smaller than that of the memory. Therefore, in the present step, by establishing the mapping relationship between the first memory region and the first cache region, the first cache region can only be used to cache the content in the first memory region, and will not cache other content outside the first memory region. Moreover, the first memory region is used to store the code and data in the executable file for implementing the process with time length requirement, so as to ensure that other code and data in the executable file which are not used to implement the process with time length requirement will not be cached on the first cache region, thereby ensuring that the first code and the first data will not be replaced out of the first cache region due to the preemption of other code or data, effectively ensuring the hit rate of the CPU when searching for the first code and the first data in the cache.

[0085] Optionally, in order to ensure the hit rate of the cache, the capacity of the first cache region is the same as the capacity of the first memory region. Then, in the case that the capacity of the first cache region is the same as the capacity of the first memory region, all the contents stored in the first memory region can be cached in the first cache region and will not be replaced out. That is, since the first cache region can cache all the contents in the first memory region at the same time, the first code and the first data cached in the first cache region will not be replaced out due to insufficient storage space of the first cache region, thereby ensuring that the first code and the first data can be cached in the first cache region at all times, ensuring that the CPU of the execution device can have a 100% hit rate when reading the first code and the first data in the cache, and further ensuring that the speed of reading the code and the data when the CPU executes the critical process is deterministic and highest.

[0086] Of course, in some scenarios (such as the capacity of the first memory region is large), the capacity of the first cache region can also be smaller than the capacity of the first memory region, which is not specifically limited in the present application.

[0087] It can be understood that in an executable file of a real-time task, a large amount of code and data will be included. However, usually only a small part of the code and the data in the executable file is used to implement a process with an execution time requirement, and most of the other code and data is used to implement a process without an execution time requirement. Therefore, in the case that the first memory region stores the first code and the first data used to implement a process with an execution time requirement, since the storage space occupied by the first code and the first data is small, the first memory region itself can also be a memory region with a small capacity, such as the size of the first memory region being 1 megabyte (MB). In this way, in the case that the capacity of the first memory region is small, although the capacity of the cache is small, it can still ensure that the first cache region with the same capacity as the first memory region can be divided in the cache.

[0088] In step 203, in response to obtaining the instruction to execute the critical process, the first code and the first data are obtained from the first cache region, and the critical process is executed.

[0089] After copying the first code and the first data to the first cache region, if the CPU in the execution device obtains an instruction to execute the critical process, the CPU in the execution device can obtain the first code and the first data from the first cache region, without obtaining the first code and the first data from the memory, and execute the critical process based on the first code and the first data. Of course, if the first code and the first data are only used to implement part of the critical process, the CPU in the execution device also needs to obtain other code and data to implement the entire critical process.

[0090] In the real-time operating system, since the key flow related to the real-time task can be periodically triggered to be executed or triggered to be executed by an external signal, in order to ensure that the key flow can be completed within a preset time length after being triggered to be executed, some corresponding software modules are often deployed in the real-time operating system to ensure the execution of the key flow. Specifically, the real-time operating system can be deployed with an interrupt processing module and a task scheduling module, and the execution of the key flow is ensured by executing the interrupt processing flow and the task scheduling flow by the interrupt processing module and the task scheduling module respectively. That is, when the key flow is executed, the execution device often needs to execute the corresponding interrupt processing flow and task scheduling flow. Therefore, in order to improve the execution efficiency of the key flow, the related codes and data of the interrupt processing flow and the task scheduling flow which affect the execution efficiency of the key flow in the real-time operating system can also be loaded onto the first memory area in the present application.

[0091] Exemplarily, in the process of loading the real-time operating system, the execution device loads the second code and the second data for implementing the interrupt processing flow and the task scheduling flow onto the first memory area.

[0092] After loading the second code and the second data onto the first memory area, based on the mapping relationship between the first memory area and the first cache area, the execution device copies the second code and the second data from the first memory area to the first cache area.

[0093] Then, in response to obtaining the interrupt request, the execution device can obtain the second code and the second data from the first cache area, and execute the interrupt processing flow and the task scheduling flow to schedule the execution of the key flow.

[0094] Among them, the second code includes code for implementing the interrupt processing flow and code for implementing the task scheduling flow. The second data includes data for implementing the interrupt processing flow and data for implementing the task scheduling flow. The interrupt processing flow is a flow triggered to be executed when the CPU in the execution device obtains the signal sent by the timer or the external device signal, and is mainly used to make the CPU pause the currently executed flow and switch to execute the key flow. The task scheduling flow is a flow executed by the CPU after executing the interrupt processing flow or after executing part of the flow in the key flow, and is mainly used to schedule the execution of the real-time task to complete the entire key flow. For example, when the key flow includes a flow composed of multiple real-time tasks, the CPU continues to execute the task scheduling flow after executing the interrupt processing flow, thereby scheduling the execution of the first real-time task; after the CPU completes a real-time task in the key flow, the CPU continues to execute the task scheduling flow, thereby scheduling the execution of the next real-time task in the key flow.

[0095] In the present solution, in addition to storing the code and data for implementing the critical process in the first memory region corresponding to the first cache region, the code and data for implementing the interrupt processing process and the task scheduling process in the real-time operating system are also stored in the first memory region corresponding to the first cache region, so that all the code and data related to the critical process are cached in the first cache region, and the interrupt processing process and the task scheduling process that may affect the execution efficiency of the critical process can also be executed quickly, thereby improving the execution efficiency of the critical process and ensuring that the critical process can be completed within a limited time.

[0096] The above introduces the loading of the code and data related to the critical process into the first memory region corresponding to the first cache region, so that the code and data related to the critical process can finally be cached in the first cache region. The following will introduce how the code and data not related to the critical process are loaded.

[0097] For example, in the process of loading the executable file of the real-time task, the execution device loads the code and data in the executable file of the real-time task that are not used for implementing the critical process onto the second memory region of the memory. The first memory region and the second memory region do not have overlapping memory regions, and the content stored on the second memory region cannot be copied to the first cache region. That is, the second memory region is another region of the memory other than the first memory region. Moreover, since the first cache region only corresponds to the first memory region, the content stored on the second memory region will not be copied to the first cache region.

[0098] In this way, by storing the code and data for implementing the critical process and the code and data not used for implementing the critical process in the executable file of the real-time task in different memory regions of the memory, the code and data for executing different processes can be isolated in the memory, avoiding pollution and interference between the memory regions where the code and data for executing different processes in the same real-time task are located, and ensuring a high hit rate of the code and data for implementing the critical process in the cache.

[0099] Optionally, in the process of loading the executable file of the non-real-time task, the execution device loads the code and data in the executable file of the non-real-time task onto the second memory region. That is, since all the code and data in the executable file of the non-real-time task do not participate in the critical process, all the code and data in the executable file of the non-real-time task are loaded onto the second memory region to ensure that all the code and data corresponding to the non-real-time task will not be cached in the first cache region.

[0100] Optionally, in the execution device, a mapping relationship between the second memory region and the second cache region on the cache is established in advance. In this way, during the running of the execution device, based on the mapping relationship between the second memory region and the second cache region, the execution device can copy the content in the second memory region to the second cache region, wherein the first cache region and the second cache region do not have overlapping cache regions. For example, the execution device copies the code and data in the executable file of the real-time task that are not used to implement the critical process from the second memory region to the second cache region; or the execution device copies the code and data in the executable file of the non-real-time task from the second memory region to the second cache region.

[0101] In general, in the case where the mapping relationship between the second memory region and the second cache region is established, the CPU of the execution device can copy the code and / or data in the second memory region to the second cache region according to the demand for reading the code and / or data during the actual running. Moreover, since the capacity of the second cache region is generally less than that of the second memory region, the content cached in the second cache region can be frequently replaced according to the running of the CPU. However, the replacement of the content cached in the second cache region does not affect the content cached in the first cache region, so that the CPU can quickly read the required code and data from the first cache region when executing the critical process, ensuring the execution efficiency of the critical process.

[0102] In this scheme, on the basis of the first cache region for caching the code and data related to the critical process in the cache, the second cache region for caching the code and data related to other processes is further provided, which can improve the efficiency of the CPU when executing other processes as much as possible by using the higher reading speed of the cache without affecting the execution efficiency of the critical process.

[0103] Exemplarily, refer to FIG. 4, which is a schematic diagram of another mapping relationship between a memory and a cache provided by the present application. As shown in FIG. 4, the memory includes a first memory region and a second memory region, and the cache includes a first cache region and a second cache region.

[0104] The first memory region and the first cache region have a mapping relationship, the capacity of the first memory region is the same as that of the first cache region, and the first memory region is used to store the code and data for implementing the critical process, the interrupt processing process and the task scheduling process in the real-time task. Therefore, based on the mapping relationship between the first memory region and the first cache region, the first cache region is also used to cache only the code and data for implementing the critical process, the interrupt processing process and the task scheduling process in the real-time task.

[0105] In addition, the second memory region has a mapping relationship with the second cache region, the capacity of the second memory region is greater than the capacity of the second cache region, and the second memory region is used to store code and data of non-critical processes in real-time tasks and code and data of non-real-time tasks. Therefore, based on the mapping relationship between the second memory region and the second cache region, the second cache region is used to cache code and data of non-critical processes in real-time tasks and code and data of non-real-time tasks.

[0106] In the process of loading the executable file of the real-time task, in order to accurately store the first code and the first data in the executable file in the first memory region, the present application provides a plurality of possible implementation manners.

[0107] In a possible implementation manner, the first code and the first data have target marks in the executable file.

[0108] When loading the executable file of the real-time task, the execution device first determines the first code and the first data with target marks in the executable file; then, the execution device loads the first code and the first data to the first memory region.

[0109] That is to say, the first code and the first data in the executable file are pre-marked with target marks, and the execution device can identify the code and the data with target marks in the executable file when loading the executable file, and then store the first code and the first data with target marks to the first memory region. For the code and the data without target marks in the executable file, the execution device stores these code and data to other memory regions (such as the second memory region described above) in the memory.

[0110] It should be noted that the developer can add target marks to the code and the data for implementing critical processes when writing the source code of the real-time task, so that when the source code of the real-time task is compiled into an executable file, the executable file including the first code and the first data can be obtained, and the first code and the first data have target marks.

[0111] Alternatively, after the developer writes the source code of the real-time task, the source code can be compiled into an executable file, and the executable file is tested to determine the hot code and the hot data during the running of the executable file. Specifically, during the running of the executable file, if some code and some data are run every time the critical process is executed, the code and the data are considered as the hot code and the hot data, and then the target mark can be added to the hot code and the hot data. For example, after the hot code and the hot data in the executable file are determined, the target mark can be added to the hot code and the hot data in the executable file, or the target mark can be added to the original code and the original data corresponding to the hot code and the hot data in the source code of the executable file, and finally the executable file is compiled, and the hot code and the hot data in the executable file have the target mark.

[0112] In another possible implementation, the executable file indicates the storage addresses of the first code and the first data, and the storage addresses of the first code and the first data are located on the first memory region.

[0113] When the executable file of the real-time task is loaded, the execution device loads the first code and the first data to the storage addresses of the first memory region according to the storage addresses of the first code and the first data indicated in the executable file.

[0114] That is, the first memory region can be pre-divided in the memory of the execution device, and the mapping relationship between the first memory region and the first cache region is established. Moreover, the storage addresses of the first code and the first data in the memory are directly indicated in the executable file, and the storage addresses are located in the first memory region. In this way, when the executable file is loaded, the execution device can load the first code and the first data to the specified storage addresses in the first memory region of the memory according to the indication of the executable file.

[0115] Similarly, the developer can also pre-add the target mark to the code and the data implementing the critical process in the source code of the real-time task, and then allocate the storage addresses in the first memory region to the code and the data with the target mark when the source code is compiled, so that the code and the data implementing the critical process can be stored in the first memory region.

[0116] The above introduces a processing method of a real-time task provided in the application. In order to facilitate understanding, the execution process of the processing method of the real-time task will be introduced in detail below in combination with specific examples.

[0117] Please refer to Fig. 5, which is a task processing timing diagram in a hard real-time task scenario provided by the present application. As shown in Fig. 5, in a task execution scenario, real-time task 1, real-time task 2, non-real-time task and background task need to be executed in a cycle. First, at the beginning of a cycle, a high-precision timer triggers, i.e. the timer sends an interrupt request to the CPU to trigger the task processing flow of the current cycle. After the CPU executes the interrupt processing flow, it goes to the task scheduling flow, thereby scheduling to the high-priority real-time task 1. After the CPU executes the real-time task 1, it continues to execute the task scheduling flow, thereby scheduling to the next-priority real-time task 2. After the CPU executes the real-time task 2, it continues to execute the task scheduling flow, thereby scheduling to the lower-priority non-real-time task. After the CPU executes the non-real-time task, it continues to execute the task scheduling flow, thereby scheduling to the lowest-priority background task, and finally waits for the arrival of the next cycle.

[0118] Among them, the flow of executing real-time task 1 and real-time task 2 constitutes a critical flow, and the critical flow must be completed before the next cycle arrives, so the execution delay of the critical flow must be extremely low and determined. And as can be seen from Fig. 5, the execution delay of the critical flow is actually affected by the interrupt processing flow and the task scheduling flow, so the delay of the interrupt processing flow and the task scheduling flow must also be low enough to avoid affecting the normal execution of the critical flow.

[0119] In the present application, software is used to isolate and concentrate the code and data for implementing the critical flow and the code and data not used for implementing the critical flow, and to allocate cache resources for the code and data for implementing the critical flow in the memory for separate mapping.

[0120] Specifically, as real-time tasks, real-time task 1 and real-time task 2 will be isolated from the code and data of non-real-time tasks and background tasks in the memory. And as real-time tasks, the code and data for implementing the critical flow of real-time task 1 and real-time task 2 will also be isolated from the code and data not used for implementing the critical flow in the memory.

[0121] Please refer to Fig. 6, which is a processing flow diagram of real-time tasks and non-real-time tasks provided by the present application. As shown in Fig. 6, in a real-time operating system, there are real-time tasks and non-real-time tasks running, and the critical flow in the real-time task has real-time requirements, while the non-real-time task does not have real-time requirements. In order to improve the execution efficiency of the critical flow in the real-time task, the processing flow of the real-time task and the non-real-time task in the present application includes the following three stages: 1, task scheduling and cache replacement arrangement coordination; 2, independent mapping of memory and cache partition; 3, deterministic cache replacement. The following will introduce the above three stages in detail.

[0122] Stage 1, task scheduling and cache replacement arrangement coordination.

[0123] In stage 1, in order to ensure that the code and data for implementing the interrupt processing flow, the task scheduling flow and the critical flow can be located in the cache area which will not be replaced by other data, the cache replacement arrangement can be coordinated based on the task scheduling situation in the real-time task execution process. That is, the code and data for implementing the interrupt processing flow, the task scheduling flow and the critical flow are arranged in the cache area which will not be replaced by other data, and the code and data for implementing other flows are arranged in the cache area which will cause data replacement.

[0124] Exemplarily, the real-time operating system can be uniformly compiled and linked with the real-time task and the non-real-time task, share the address space, and thus generate an original image which is an executable file including the code and data of the real-time operating system, the real-time task and the non-real-time task. Of course, in some embodiments, the real-time operating system, the real-time task and the non-real-time task can also be independently compiled, which is not specifically limited here.

[0125] In order to determine the code and data for implementing the critical flow in the real-time task, the original image can be tested and run. In the process of testing and running the original image, the hot code and the hot data in the real-time task execution process can be identified by memory access record analysis, memory access mode modeling and prediction and the like. Then, on the basis of the original image, the identified hot code and hot data can be marked, so as to obtain a marked image which is marked with the hot code and the hot data. Of course, after the hot code and the hot data are identified, the code and data corresponding to the identified hot code and hot data in the source code of the original image can also be marked, so as to specify the loading address of the code and data with the mark as the address in the memory real-time area (i.e. the first memory area) when the source code is compiled, so as to obtain the marked image.

[0126] In addition, the interrupt processing flow and the task scheduling flow which can be executed in the real-time operating system belong to the flow with high real-time requirement, and therefore the code and data for implementing the interrupt processing flow and the task scheduling flow in the real-time operating system can also be marked as the hot code and the hot data, so as to enable the code and data for implementing the interrupt processing flow and the task scheduling flow to be loaded into the memory real-time area.

[0127] In this way, after the original image or the source code corresponding to the original image is marked, it can be ensured that the code and data for implementing the critical flow, and the code and data for implementing the interrupt processing flow and the task scheduling flow can be loaded into the memory real-time area when the execution device loads the marked image.

[0128] The memory is divided into a memory real-time area and a memory non-real-time area (i.e., the second memory area described above), and the memory real-time area and the memory non-real-time area are completely separated in the address space for subsequent cache resource mapping. When the mark image is loaded, the codes and data in the real-time operating system that are not used to implement the interrupt processing flow and the task scheduling flow are loaded into the memory non-real-time area, the codes and data in the real-time task that are not used to implement the critical flow are loaded into the memory non-real-time area, and the codes and data of the non-real-time task are also loaded into the memory non-real-time area.

[0129] Exemplarily, refer to FIG. 7, which is a schematic diagram of a processing flow of a real-time task and a non-real-time task provided by the present application. As shown in FIG. 7, the original image can be divided into a code segment and a data segment. The code segment is specifically.text, which is used to place codes. The data segment includes.rodata,.data,.bss and.stack. The.rodata is used to place read-only data, the.data is used to place normal readable and writable data, the.bss is used to place data initialized to 0, and the.stack is used to place the stack space for program execution. For all the code segments and data segments, the codes or data therein can be marked in the manner described above to load the marked codes and data into the memory real-time area. The codes and data that are not marked are loaded into the memory non-real-time area.

[0130] Stage 2, independent mapping of the memory and the cache partition.

[0131] The memory has been separated into the memory real-time area and the memory non-real-time area through the stage 1 processing. Therefore, in this stage, the segment alignment and the page allocation of the memory management unit (MMU) mapping can be performed according to the hardware specifications of the execution device. For example, if the execution device supports 4K page mapping, the memory real-time area is mapped according to 4K pages.

[0132] The cache in the execution device also allocates resources according to the specifications of the cache itself. For example, for a cache supporting 4-way set-associative with a size of 2M, the number of page resources that can be allocated by the cache is: 2M / 4K / 4 = 128. For example, refer to FIG. 8, which is a schematic diagram of a cache supporting a set-associative mode according to the present application. As shown in FIG. 8, in the case where the cache supports a set-associative mode, the area in the cache can be divided into multiple groups (such as group 1 and group 2), and different groups include different cache areas. For a given address in the memory (such as address 0-11 in FIG. 8), each address corresponds to a fixed group in the cache, i.e., the data under the given address is only cached in the cache area in the corresponding group. For example, the data under address 1, 3, 5, 7, 9 and 11 is only cached in the cache area in the corresponding group 1; the data under address 0, 2, 4, 6, 8 and 10 is only cached in the cache area in the corresponding group 2.

[0133] Specifically, the cache can be divided into a cache real-time area and a cache non-real-time area. The cache real-time area establishes a mapping relationship with the memory real-time area, and the cache non-real-time area establishes a mapping relationship with the memory non-real-time area. In this way, only the code and data in the memory real-time area are cached in the cache real-time area, and the code and data in the memory non-real-time area are not cached in the cache real-time area, thereby ensuring that the code and data in the memory real-time area are cached in the cache real-time area, and the code and data in the memory non-real-time area do not enter the cache real-time area.

[0134] Stage 3, deterministic cache replacement.

[0135] After the above two stages are executed, the execution device can perform deterministic cache replacement when executing the program. Specifically, the code and data stored in the memory real-time area are strictly determined according to the real-time requirement, and only the code and data stored in the memory real-time area can be cached in the cache real-time area, so as to ensure that the hit rate of the cache real-time area is 100% when the execution device executes the critical process. That is, the code and data required by the execution device to execute the critical process can be found in the cache real-time area, thereby ensuring that the time delay of code execution and data access is within a determined range, completely eliminating the uncontrollable factors of time delay caused by cache miss, and achieving the goal that real-time tasks in a real-time operating system with hard real-time requirements must meet the deadline requirement.

[0136] In addition, since the code and data in the memory non-real-time area never enter the cache real-time area, on the cache, cache replacement only occurs in the cache non-real-time area, i.e., the cache non-real-time area replaces the code or data according to the real-time access of the execution device.

[0137] The method provided by the application is described in detail above. Next, a device for executing the method is described.

[0138] Referring to FIG. 9, FIG. 9 is a structural schematic diagram of a real-time task processing apparatus provided by the application. As shown in FIG. 9, the real-time task processing apparatus is applied to a real-time operating system, and the real-time task processing apparatus comprises: a loading module 901 configured to load first code and first data for implementing a critical process in an executable file of a real-time task to a first memory area of a memory in a process of loading the executable file of the real-time task, the critical process comprising a process in the real-time task that needs to meet a time requirement for execution; a processing module 902 configured to copy the first code and the first data from the first memory area to a first cache area on a cache based on a mapping relationship between the first memory area and the first cache area, wherein the mapping relationship is used to indicate that the first cache area is used only for caching content stored in the first memory area, and a reading speed of the cache is higher than a reading speed of the memory; and the processing module 902 is further configured to, in response to obtaining an instruction to execute the critical process, obtain the first code and the first data from the first cache area and execute the critical process.

[0139] In a possible implementation, the capacity of the first cache area is the same as the capacity of the first memory area.

[0140] In a possible implementation, the loading module 901 is further configured to load second code and second data for implementing an interrupt processing process and a task scheduling process to the first memory area in a process of loading the real-time operating system; the processing module 902 is further configured to copy the second code and the second data from the first memory area to the first cache area based on the mapping relationship; and the processing module 902 is further configured to, in response to obtaining an interrupt request, obtain the second code and the second data from the first cache area and execute the interrupt processing process and the task scheduling process to schedule execution of the critical process.

[0141] In a possible implementation, the loading module 901 is further configured to load code and data in the executable file that are not used to implement the critical process to a second memory area of the memory, the first memory area and the second memory area do not have a memory area in common, and content stored in the second memory area cannot be copied to the first cache area.

[0142] In a possible implementation, the loading module 901 is further configured to load code and data in an executable file of a non-real-time task to the second memory area in a process of loading the executable file of the non-real-time task.

[0143] In a possible implementation, the processing module 902 is further configured to copy content in the second memory region to a second cache region on the cache based on a mapping relationship between the second memory region and the second cache region, where the first cache region and the second cache region do not have a cache region in common.

[0144] In a possible implementation, the first code and the first data have target marks in the executable file, and the loading module 901 is further configured to: determine the first code and the first data with the target marks in the executable file; and load the first code and the first data to the first memory region.

[0145] In a possible implementation, the executable file indicates storage addresses of the first code and the first data, and the storage addresses are located on the first memory region; and the loading module 901 is further configured to: load the first code and the first data to the storage addresses of the first memory region according to the storage addresses indicated in the executable file.

[0146] In a possible implementation, the execution duration of the critical process is less than or equal to a preset duration.

[0147] Referring to FIG. 10, FIG. 10 is a structural schematic diagram of an electronic device provided in the present application. As shown in FIG. 10, the electronic device 1000 can specifically be a server, which is not limited herein. Specifically, the electronic device 1000 includes a receiver 1001, a transmitter 1002, a processor 1003 and a memory 1004 (wherein the number of processors 1003 in the electronic device 1000 can be one or more, and one processor is taken as an example in FIG. 10), wherein the processor 1003 can include an application processor 10031 and a communication processor 10032. In some embodiments of the present application, the receiver 1001, the transmitter 1002, the processor 1003 and the memory 1004 can be connected through a bus or other means.

[0148] The memory 1004 can include a read-only memory and a random access memory, and provide instructions and data for the processor 1003. A part of the memory 1004 can also include a non-volatile random access memory (NVRAM). The memory 1004 stores processor and operation instructions, executable modules or data structures, or subsets thereof, or expanded sets thereof, wherein the operation instructions can include various operation instructions for implementing various operations.

[0149] The processor 1003 controls the operation of the electronic device. In particular applications, various components of the electronic device are coupled by a bus system, which can include a data bus, a power bus, a control bus, and a state signal bus, etc. However, for the sake of clarity, the various buses are indicated as a bus system in the figure.

[0150] The method disclosed in the embodiments of the present application can be applied to or implemented by the processor 1003. The processor 1003 can be an integrated circuit chip having a signal processing capability. In the implementation process, the steps of the above method can be completed by hardware integrated logic circuits in the processor 1003 or by instructions in the form of software. The processor 1003 described above can be a general processor, a digital signal processor (DSP), a microprocessor or a microcontroller, and can further include an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0151] The processor 1003 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium in the art. The storage medium is located in the memory 1004, and the processor 1003 reads the information in the memory 1004 and combines the hardware to complete the steps of the above method.

[0152] The receiver 1001 can be used to receive input digital or character information, and generate signal input related to the relevant settings and function control of the electronic device. The transmitter 1002 can be used to output digital or character information through the first interface; the transmitter 1002 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group; the transmitter 1002 can also include a display device such as a display screen.

[0153] The electronic device provided in the embodiments of the present application can be a chip, which includes a processing unit, for example, a processor, and a communication unit, for example, an input / output interface, a pin, a circuit, or the like. The processing unit can execute computer execution instructions stored in a storage unit, so as to enable the chip in the device to execute the method described in the above embodiments. Optionally, the storage unit is a storage unit in the chip, such as a register, a cache, or the like. The storage unit can also be a storage unit outside the chip in the wireless access device, such as a read-only memory (ROM) or other types of static storage device that can store static information and instructions, a random access memory (RAM), or the like.

[0154] Referring to FIG. 11, FIG. 11 is a structural schematic diagram of a computer readable storage medium provided in the present application. The present application further provides a computer readable storage medium. In some embodiments, the method disclosed in FIG. 2 can be implemented as computer program instructions encoded in a computer readable storage medium in a machine readable format or encoded in other non-transitory media or articles.

[0155] FIG. 11 schematically shows a conceptual partial view of an example computer readable storage medium arranged in accordance with at least some embodiments presented herein, the example computer readable storage medium including a computer program for executing a computer process on a computing device.

[0156] In one embodiment, the computer readable storage medium 1100 is provided using a signal bearing medium 1101. The signal bearing medium 1101 can include one or more program instructions 1102, which when executed by one or more processors can provide the functionality or some portion of the functionality described above with respect to FIG. 2.

[0157] In some examples, the signal bearing medium 1101 can embody a computer readable medium 1103, such as, but not limited to, a hard disk drive, a compact disk (CD), a digital video disk (DVD), a digital tape, memory, ROM, or RAM, among others.

[0158] In some embodiments, the signal carrying medium 1101 may comprise a computer-recordable medium 1104, such as, but not limited to, a memory, a read / write (R / W) CD, a R / W DVD, etc. In some embodiments, the signal carrying medium 1101 may comprise a communication medium 1105, such as, but not limited to, digital and / or analog communication media (e.g., fiber optic cables, waveguides, wired communication links, wireless communication links, etc.). Therefore, for example, the signal carrying medium 1101 may be transmitted by a wireless form of communication medium 1105 (e.g., a wireless communication medium conforming to the IEEE 802.X standard or other transmission protocols).

[0159] One or more program instructions 1102 may be, for example, computer-executable instructions or logical implementation instructions. In some examples, the computing device may be configured to provide various operations, functions, or actions in response to one or more program instructions 1102 conveyed to the computing device via a computer-readable medium 1103, a computer-recordable medium 1104, and / or a communication medium 1105.

[0160] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the accompanying drawings of the device embodiments provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0161] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods of the various embodiments of this application.

[0162] In the above-described embodiments, all or some of the embodiments can be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, the embodiments can be implemented in the form of a computer program product.

[0163] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from one website, computer, training device or data center to another website, computer, training device or data center through wired (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can store or be integrated into a training device, data center, etc. data storage device including one or more available media sets. The available media can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)), etc.

Claims

1. A processing method of a real-time task, characterized by, The method is applied to a real-time operating system, and the method comprises: In a process of loading an executable file of a real-time task, first code and first data for implementing a critical process in the executable file are loaded onto a first memory region of a memory, the critical process comprising a process in the real-time task that needs to meet a time requirement for execution; Based on a mapping relationship between the first memory region and a first cache region on a cache, the first code and the first data are copied from the first memory region to the first cache region, wherein the mapping relationship is used to indicate that the first cache region is only used to cache content stored in the first memory region, and a reading speed of the cache is higher than a reading speed of the memory; In response to obtaining an instruction to execute the critical process, the first code and the first data are obtained from the first cache region, and the critical process is executed.

2. The method of claim 1, wherein, A capacity of the first cache region is the same as a capacity of the first memory region.

3. The method according to claim 1 or 2, characterized in that, The method further comprises: In a process of loading the real-time operating system, second code and second data for implementing an interrupt processing process and a task scheduling process are loaded onto the first memory region; Based on the mapping relationship, the second code and the second data are copied from the first memory region to the first cache region; In response to obtaining an interrupt request, the second code and the second data are obtained from the first cache region, and the interrupt processing process and the task scheduling process are executed to schedule execution of the critical process.

4. The method according to any one of claims 1 to 3, characterized in that, The method further comprises: Code and data in the executable file that are not used to implement the critical process are loaded onto a second memory region of the memory, the first memory region and the second memory region do not have a memory region in common, and content stored on the second memory region cannot be copied to the first cache region.

5. The method of claim 4, wherein, The method further comprises: In a process of loading an executable file of a non-real-time task, code and data in the executable file of the non-real-time task are loaded onto the second memory region.

6. The method according to claim 4 or 5, characterized in that, The method further comprises: Based on a mapping relationship between the second memory region and a second cache region on the cache, content in the second memory region is copied onto the second cache region, wherein the first cache region and the second cache region do not have a cache region in common.

7. The method according to any one of claims 1 to 6, characterized in that, The first code and the first data have target marks in the executable file, and the loading of the first code and the first data for implementing the critical process in the executable file onto the first memory region of the memory comprises: The first code and the first data with the target marks are determined in the executable file; The first code and the first data are loaded onto the first memory region.

8. The method according to any one of claims 1 to 6, characterized in that, The executable file indicates storage addresses of the first code and the first data, and the storage addresses are located on the first memory region; The loading of the first code and the first data for implementing the critical process in the executable file onto the first memory region of the memory comprises: loading the first code and the first data into the storage address of the first memory region according to the storage address indicated in the executable file.

9. The method according to any one of claims 1 to 8, characterized in that, An execution time of the critical process is less than or equal to a preset time length.

10. A processing device of a real-time task, characterized by, The device is applied to a real-time operating system, and the device comprises: a loading module, configured to load first code and first data for implementing a critical process in an executable file of a real-time task into a first memory region of a memory during loading of the executable file, the critical process comprising a process in the real-time task that needs to meet an execution time requirement; a processing module, configured to copy the first code and the first data from the first memory region to a first cache region on a cache based on a mapping relationship between the first memory region and the first cache region, wherein the mapping relationship is used to indicate that the first cache region is used only for caching content stored in the first memory region, and a reading speed of the cache is higher than a reading speed of the memory; the processing module is further configured to, in response to obtaining an instruction to execute the critical process, obtain the first code and the first data from the first cache region and execute the critical process.

11. The apparatus of claim 10, wherein, The capacity of the first cache region is the same as the capacity of the first memory region.

12. The device of claim 10 or 11, wherein the loading module is further configured to load second code and second data for implementing an interrupt processing process and a task scheduling process into the first memory region during loading of the real-time operating system; the processing module is further configured to copy the second code and the second data from the first memory region to the first cache region based on the mapping relationship; the processing module is further configured to, in response to obtaining an interrupt request, obtain the second code and the second data from the first cache region and execute the interrupt processing process and the task scheduling process to schedule execution of the critical process.

13. The apparatus of any of claims 10-12, wherein, the loading module is further configured to: load code and data in the executable file that are not used to implement the critical process into a second memory region of the memory, the first memory region and the second memory region do not have overlapping memory regions, and content stored in the second memory region cannot be copied to the first cache region.

14. The apparatus of claim 13, wherein, the loading module is further configured to: during loading of an executable file of a non-real-time task, load code and data in the executable file of the non-real-time task into the second memory region.

15. The apparatus of claim 13 or 14, wherein, the processing module is further configured to: copy content in the second memory region to a second cache region on the cache based on a mapping relationship between the second memory region and the second cache region, wherein the first cache region and the second cache region do not have overlapping cache regions.

16. The apparatus of any one of claims 10-15, wherein, The first code and the first data have target marks in the executable file, and the loading module is further configured to: determine the first code and the first data with the target marks in the executable file; loading the first code and the first data onto the first memory region.

17. The apparatus of any one of claims 10-15, wherein, the executable file indicates a storage address of the first code and the first data, and the storage address is located on the first memory region; the loading module is further configured to: loading the first code and the first data onto the storage address of the first memory region according to the storage address indicated in the executable file.

18. The apparatus of any of claims 10-17, wherein, The execution duration of the critical process needs to be less than or equal to a preset duration.

19. A processing device of a real-time task, characterized by, The apparatus includes a memory and a processor; the memory stores code, and the processor is configured to execute the code; when the code is executed, the apparatus executes the method according to any one of claims 1 to 9.

20. A computer storage medium, comprising, The computer storage medium stores instructions; when the instructions are executed by a computer, the computer implements the method according to any one of claims 1 to 9.

21. A computer program product, characterised in that, The computer program product stores instructions; when the instructions are executed by a computer, the computer implements the method according to any one of claims 1 to 9.

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