Data processing method and related device

Abstract

The present application provides a data processing method and a related device, used for improving the utilization rates of AI processors and improving the data processing efficiency. The method comprises: a first processor splits first data into N pieces of first sub-data, wherein the N pieces of first sub-data are not completely the same, and N is an integer greater than or equal to 2; the first processor acquires N threads, wherein the N threads are in one-to-one correspondence with the N pieces of first sub-data, and each thread among the N threads is used for executing a data processing task of the corresponding first sub-data; the N threads separately call a second processor to process the corresponding first sub-data, to obtain N pieces of second sub-data.

Description

Data processing method and related device

[0001] The present application claims priority from the Chinese patent application No. 202411377436.2 filed on September 29, 2024, and entitled "Data processing method and related device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of artificial intelligence, and in particular to a data processing method and related device. BACKGROUND

[0003] In recent years, edge devices increasingly use neural networks for image processing. These devices rely on built-in specialized artificial intelligence (AI) chips to achieve efficient image classification, facial recognition, and augmented reality (AR) functions. These AI chips are specifically designed to accelerate the computation of deep learning models, enabling edge devices to handle complex image tasks locally, such as real-time scene recognition and object detection.

[0004] When using edge AI chips to perform image neural network inference tasks, due to the constraints of computing power, edge AI chips cannot complete the inference of networks with excessive parameters in a short time. Therefore, an effective method is to split the image into several sub-images, then process the smaller sub-images through the AI chip, and finally fuse and splice the processed sub-images into a result image. Taking sub-images as network input can significantly reduce the network parameter quantity, making it possible to perform inference on the edge.

[0005] In the current technical solution, the entire process is divided into three sub-tasks: splitting sub-images from the original image; processing sub-images using AI chips; and fusing and splicing the processed sub-images into a result image. Each task is executed by a multi-task processing device using one thread. However, the AI chip still waits for the multi-task processing device to complete some operations between processing two sub-images, resulting in low utilization of the AI chip and low overall data processing efficiency. SUMMARY

[0006] The present application provides a data processing method and related device to solve the problem of low utilization of AI processors and low data processing efficiency.

[0007] The first aspect provides a data processing method. The method is applied to a first processor, and the method comprises the following steps: splitting first data into N first sub-data, the N first sub-data being not completely same, N being an integer greater than or equal to 2; obtaining N threads, the N threads corresponding to the N first sub-data in one-to-one manner, each thread in the N threads being used for executing a data processing task of the corresponding first sub-data; and calling, by the N threads, a second processor to process the corresponding first sub-data respectively, so as to obtain N second sub-data. By processing the N first sub-data through the N threads, each thread processes one first sub-data, so that multiple first sub-data can be processed in parallel. The data processing tasks of the corresponding first sub-data are independently executed between the threads, without the need for communication between the threads, so that the data processing delay can be reduced. Moreover, the second processor is called by the N threads to process the corresponding first sub-data respectively, so that the time for the second processor to wait for processing the first sub-data can be reduced, and the utilization rate of the second processor can be improved.

[0008] In a possible implementation, the number of the second processors is 1, and the calling, by the N threads, of the second processor to process the corresponding first sub-data respectively comprises: calling, by the N threads, the second processor to process the corresponding first sub-data through a first mutex. By using the first mutex, it can be ensured that only one thread calls the second processor to process the corresponding first sub-data at the same time, and the time interval for calling the second processor by different threads can be shortened, the idle time of the second processor can be reduced, the utilization rate of the second processor can be improved, and thus the overall efficiency of data processing can be improved.

[0009] In a possible implementation, the number of the second processors is M, M being an integer greater than or equal to 1, and the calling, by the N threads, of the second processor to process the corresponding first sub-data respectively comprises: calling, by the N threads, an idle second processor in the M second processors to process the corresponding first sub-data through a target queue, the target queue being used for storing the first sub-data to be processed by the second processor, or the target queue being used for storing an index corresponding to the first sub-data to be processed by the second processor. By using the target queue, the calling sequence of the N threads for calling the second processor can be controlled, so that the N threads can call the second processor in order, the time interval for calling the second processor by different threads can be shortened, the idle time of the second processor can be reduced, the utilization rate of the second processor can be improved, and thus the overall efficiency of data processing can be improved.

[0010] In a possible implementation, the target queue is a first-in-first-out queue or a last-in-first-out queue.

[0011] In a possible implementation, the method further includes: the N threads write the corresponding second sub-data into a target storage area, the target storage area being used to store second data, the second data being the processed first data. The N threads implement splicing of the second data by writing the corresponding second sub-data into the target storage area, so that the N threads can independently perform data splicing, and the overall data processing efficiency can be improved.

[0012] In a possible implementation, the first sub-data includes overlapping data, the overlapping data being data that coincides in at least two first sub-data, the second sub-data includes to-be-fused data, the to-be-fused data being data processed by the second processor from the overlapping data, the target storage area includes N sub-storage areas, the N sub-storage areas corresponding to the N second sub-data in a one-to-one manner, each sub-storage area includes a first area, the first area being a storage area shared by at least two sub-storage areas; and the N threads writing the corresponding second sub-data into the target storage area includes: a first thread reading third data from the first area in a corresponding sub-storage area, the first thread being any one of the N threads; and the first thread writing fourth data into the first area in the corresponding sub-storage area, the fourth data covering the third data, the fourth data being obtained according to the third data and to-be-fused data in the second sub-data corresponding to the first thread. Thus, for the to-be-fused data corresponding to the overlapping data, the thread can also independently perform fusion without waiting for all to-be-fused data corresponding to the same overlapping data to be obtained before performing fusion processing, so that the data splicing efficiency can be improved, and the overall data processing efficiency can be improved.

[0013] In a possible implementation, each sub-storage area includes a second area, the second area being an area of the sub-storage area other than the first area, and the method further includes: the first thread writing data other than the to-be-fused data in the corresponding second sub-data into the second area. For the data other than the to-be-fused data in the second sub-data, the thread can directly write the data into the second area without waiting for all first sub-data to be processed before writing, so that the data splicing efficiency can be improved, and the overall data processing efficiency can be improved.

[0014] In a possible implementation, the first data is data obtained by sampling a continuous signal. For example, the first data can be image data, audio data, or point cloud data, and the like. The image data can be two-dimensional image data or three-dimensional image data.

[0015] The second aspect provides a data processing apparatus. The apparatus is applied to a first processor, and the apparatus comprises: a processing module configured to split first data into N first sub-data, the N first sub-data being not completely identical, N being an integer greater than or equal to 2; the processing module is configured to obtain N threads, the N threads corresponding to the N first sub-data in one-to-one manner, each thread in the N threads being configured to execute a data processing task of the corresponding first sub-data; and the processing module is configured to invoke a second processor to process the corresponding first sub-data by using the N threads, so as to obtain N second sub-data.

[0016] In a possible implementation, the processing module is configured to invoke the second processor to process the corresponding first sub-data by using the N threads based on a first mutex.

[0017] In a possible implementation, the number of the second processors is M, M being an integer greater than or equal to 1; and the processing module is configured to invoke an idle second processor in the M second processors to process the corresponding first sub-data by using the N threads based on a target queue, the target queue being configured to store the first sub-data to be processed by the second processor, or the target queue being configured to store an index corresponding to the first sub-data to be processed by the second processor.

[0018] In a possible implementation, the target queue is a first-in first-out queue or a last-in first-out queue.

[0019] In a possible implementation, the processing module is configured to write the corresponding second sub-data into a target storage area by using the N threads, the target storage area being configured to store second data, the second data being the processed first data.

[0020] In a possible implementation, the first sub-data comprises overlapping data, the overlapping data being data that is coincident in at least two first sub-data, the second sub-data comprises to-be-fused data, the to-be-fused data being data processed by the second processor on the overlapping data, the target storage area comprises N sub-storage areas, the N sub-storage areas corresponding to the N second sub-data in one-to-one manner, each sub-storage area comprises a first area, the first area being a storage area shared by at least two sub-storage areas; the processing module is configured to read third data from the first area in the corresponding sub-storage area by using a first thread, the first thread being any one of the N threads; and the processing module is configured to write fourth data into the first area in the corresponding sub-storage area by using the first thread, the fourth data covering the third data, the fourth data being obtained according to the third data and the to-be-fused data in the second sub-data corresponding to the first thread.

[0021] In a possible implementation, each sub-storage area includes a second area, the second area being an area other than the first area in the sub-storage area, and the apparatus further includes a processing module configured to write, by the first thread, data other than the to-be-fused data in the corresponding second sub-data to the second area.

[0022] In a possible implementation, the first data is data obtained by sampling a continuous signal. For example, the first data can be image data, audio data, or point cloud data, etc. The image data can be two-dimensional image data or three-dimensional image data.

[0023] In a third aspect, a communication apparatus is provided, which includes a processor and an interface circuit. The interface circuit is configured to receive a signal from another communication apparatus outside the communication apparatus and transmit the signal to the processor or send a signal from the processor to another communication apparatus outside the communication apparatus. The processor is configured to implement the method in any of the preceding first aspect to the second aspect and any possible implementation of any of the aspects by means of logic circuit or executing code instruction.

[0024] In a fourth aspect, a communication apparatus is provided, which includes a processor and an interface circuit. The interface circuit is configured to receive a signal from another communication apparatus outside the communication apparatus and transmit the signal to the processor or send a signal from the processor to another communication apparatus outside the communication apparatus. The processor is configured to implement the function modules of the method in the preceding first aspect and any possible implementation of the first aspect by means of logic circuit or executing code instruction.

[0025] In a fifth aspect, a computer readable storage medium is provided, which stores a computer program or instruction. When the computer program or instruction is executed by a processor, the method in the preceding first aspect and any possible implementation of the first aspect is implemented.

[0026] In a sixth aspect, a computer program product storing an instruction is provided. When the instruction is run by a processor, the method in the preceding first aspect and any possible implementation of the first aspect is implemented.

[0027] In a seventh aspect, a chip system is provided, which includes a processor and can further include a memory. The chip system is configured to implement the method in the preceding first aspect and any possible implementation of the first aspect. The chip system can be composed of a chip or can include a chip and other discrete devices. BRIEF DESCRIPTION OF DRAWINGS

[0028] FIG. 1 is a schematic diagram of a method for performing a data processing task;

[0029] FIG. 2a is an architecture diagram of an application scenario provided by an embodiment of the present application;

[0030] FIG. 2b is another application scenario architecture provided by an embodiment of the present application;

[0031] FIG. 3 is a flow diagram of a data processing method provided by an embodiment of the present application;

[0032] FIG. 4a is a diagram of segmentation of first data provided by an embodiment of the present application;

[0033] FIG. 4b is another diagram of segmentation of first data provided by an embodiment of the present application;

[0034] FIG. 5 is a diagram of structure of a target storage area provided by an embodiment of the present application;

[0035] FIG. 6 is a diagram of structure of a data processing apparatus provided by an embodiment of the present application;

[0036] FIG. 7 is a diagram of structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0037] The present application provides a processing method and related devices to improve the utilization rate of a matrix computing unit in a smart chip, improve the throughput of the smart chip, and thus improve the inference or training efficiency of a neural network model.

[0038] The embodiments of the present application are described below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Those skilled in the art can know that, as technology develops and new scenarios appear, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0039] The terms “first”, “second”, and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. “Multiple” means greater than or equal to 2.

[0040] The term “exemplary” herein means “serving as an example, embodiment, or illustration”. Any embodiment described herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0041] Under the background of big data-big computing, artificial intelligence technologies represented by machine learning have rapidly developed, becoming the core foundation of key technologies such as computer vision, intelligent speech, natural language processing, biometric identification, and recommendation systems, and are widely applied in the fields of transportation, education, finance, medical treatment, smart cities, and gradually becoming one of the main forces to promote the information revolution and social development. The rapid development of artificial intelligence benefits from two important factors, namely, the innovation of algorithm models and the continuous improvement of the computing power of smart chips.

[0042] Current artificial intelligence (AI) applications based on deep neural networks mainly fall into two stages: training and inference. Specifically, training is to train an initial neural network model into a target neural network model (AI model) through a large amount of training processing, so that the AI model can be applied to actual scenarios; and inference is the process of applying the trained AI model to actual scenarios.

[0043] The training and inference of the AI model involve a large amount of matrix multiplication and vector calculation, and the AI model has a large number of parameters, which puts higher requirements on the computing power of the processor for inference and training. In the post-Moore era, although the chip transistor density continues to increase, the power density and performance density have been difficult to further improve, meaning that the computing power cannot be improved through process improvement. Therefore, an important branch of chip development is domain specific architecture (DSA), also known as smart chip, AI chip or AI processor. This type of chip has strong speciality, simple design, customized operation unit according to the specific characteristics of the application, simplified control logic, and designed storage structure and data path suitable for the characteristics of the field, which has obtained high performance and energy efficiency ratio, and has been widely used in high-performance computing, artificial intelligence, cryptography and other fields. AI chips designed specifically for artificial intelligence scenarios belong to a kind of DSA, which are used to accelerate the training and inference of AI models. AI chips can also be referred to as smart chips, AI chips or AI processors, etc. AI chips include graphics processing units (GPUs), tensor processing units (TPUs) and neural processing units (NPUs), etc.

[0044] With the development of artificial intelligence and deep learning, more and more enterprises deploy AI chips on electronic devices and use AI technology, i.e., to achieve specific functions through AI models, such as fingerprint unlocking, image recognition, voice recognition, data enhancement or optimization, etc. Data enhancement or optimization, for example, enhancement or optimization of image data, such as image noise reduction processing, super-resolution reconstruction, image deblurring, contrast enhancement or saturation enhancement, etc. Data enhancement or optimization also includes, for example, enhancement or optimization of audio data, such as voice noise reduction, echo suppression, howling detection and suppression, or voiceprint recognition, etc.

[0045] End-side devices (such as smart phones, tablets, computers, smart wearable devices, smart cameras, or car machines, etc.) increasingly use neural networks for image, audio, and other data processing. These devices rely on built-in AI processors to achieve efficient image classification, facial recognition, and augmented reality (AR) functions. The power consumption, heat dissipation, and volume of end-side devices constrain the computing power of AI processors built into end-side devices, and end-side AI processors cannot complete the inference or training of a network with too much parameter quantity in a short time.

[0046] Therefore, before using an AI processor to process data, an end-side device will split the data to be processed into several sub-data, and then process the sub-data with smaller data quantity through the AI processor, and finally fuse and splice the processed sub-data into result data. In order to ensure that the splicing place of the fused result data is smoother, when splitting data, there will be some data overlap between adjacent sub-data, and the overlapping data needs to be weighted and fused when fusing, so as to ensure the continuity of the splicing place.

[0047] As shown in FIG. 1, the current end-side device divides the data processing task into three sub-tasks, and allocates a thread for each sub-task to process data. The three sub-tasks include: sub-task 1 of obtaining sub-data from original data, sub-task 2 of calling an AI processor to process sub-image, and sub-task 3 of fusing and splicing the processed sub-data into result data. The three threads executing the above three sub-tasks are pipeline threads, that is, each thread is responsible for one of the three sub-tasks, and the processing result is passed to the thread responsible for the next sub-task. For example, the three threads include thread 1, thread 2, and thread 3, thread 1 is used to execute sub-task 1, thread 2 is used to execute sub-task 2, and thread 3 is used to execute sub-task 3. Thread 1 obtains sub-data and synchronizes the sub-data to thread 2. Thread 2 calls an AI processor to process sub-data, and after obtaining the sub-data processed by the AI processor, synchronizes the processed sub-data to thread 3. Thread 3 fuses the processed sub-data into result data after obtaining the processed sub-data. Since there is overlapping data between adjacent sub-data, thread 3 needs to fuse the processed overlapping data when splicing the processed sub-data. Thread 1 continues to obtain the next sub-data after obtaining a sub-data and synchronizing it to thread 2. Thread 2 continues to call the AI processor to process the next sub-data after calling the AI processor to process a sub-data and synchronizing the processed sub-data to thread 3.

[0048] There is too much communication overhead between pipeline threads. Each thread needs to communicate with other threads to wait for data and process the data, which affects the overall data processing efficiency. Moreover, the AI processor is idle during the process of thread 2 waiting to obtain the data to be processed and synchronizing the processed data to other threads, resulting in underutilization of the AI processor and reducing the data processing efficiency. The fusion of the processed sub-data is calculated serially in thread 3, and in a high-load scenario, the time consumption of this step will significantly increase, becoming a performance bottleneck of the entire image processing. The long processing time of thread 3 will cause thread 2 to wait, and also cause the AI processor to be idle, reducing the overall data processing efficiency.

[0049] To solve the above technical problems, the present application provides the following embodiments.

[0050] FIG. 2a is an application scenario architecture diagram provided by an embodiment of the present application. As shown in FIG. 2a, the application scenario architecture diagram includes a hardware device. The hardware device can be a system on chip (SoC), or a smart phone, a tablet, a computer, a smart wearable device, a smart camera, or a car machine, or a server, etc. The hardware device includes a first processor and a second processor. The first processor is a multi-task processor, that is, the first processor can process multiple tasks in parallel. The first processor can be a CPU. The second processor is a single-task processor, that is, the second processor can only execute one task at a time, and for multiple tasks, it needs to be processed serially. The second processor can be an AI processor. The first processor can call the second processor for data processing to improve data processing efficiency.

[0051] In this embodiment, the first processor is configured to split the first data to be processed into N first sub-data. Moreover, the first processor is configured to obtain N threads. The N threads can be created by the first processor, or the N threads can be obtained from a thread pool by the first processor. The N threads correspond to the N first sub-data one by one, that is, one thread in the N threads processes one first sub-data in the N first sub-data, and different threads process different first sub-data. The N threads are parallel threads, and each thread independently executes a data processing task of the corresponding first sub-data. The data processing task executed by each thread can include obtaining the corresponding first sub-data, calling the second processor to process the corresponding first sub-data, and splicing the second sub-data obtained by the second processor processing the first sub-data.

[0052] In a possible implementation, the first processor can also be configured to schedule the threads. Since the second processor is a single-task processor and the N threads are parallel threads, multiple threads in the N threads can simultaneously call the second processor, or other threads request to call the second processor when the second processor is still processing the first sub-data corresponding to one thread, resulting in a conflict. Therefore, the first processor can schedule the threads so that the N threads call the second processor in an orderly manner. It should be noted that since the N threads are independent and parallel threads, the N threads can simultaneously request to call the second processor, or request to call the second processor at different times, which is not limited in the present application.

[0053] In this embodiment, the first processor can schedule the threads by using the first mutex or the target queue, so as to improve the utilization of the second processor.

[0054] The first mutex is used to ensure that the second processor can be called by only one thread at the same time to process the first sub-data. Specifically, when a thread (hereinafter referred to as a first thread) obtains the first mutex, the first thread can call the second processor to process the first sub-data corresponding to the first thread, and other threads are blocked when requesting to obtain the first mutex, so as to be unable to call the second processor. The other threads need to wait until the first thread processes the second sub-data obtained by processing the first sub-data by calling the second processor, and then unlocks the first mutex, and then request to obtain the first mutex. When the second thread obtains the first mutex, the second thread can call the second processor to process the first sub-data corresponding to the second thread.

[0055] The target queue is used to control the sequence of N threads calling the second processor. That is, N threads can be queued through the target queue, so that N threads call the second processor to process the corresponding first sub-data in order. The target queue can indicate the first sub-data to be processed or the index corresponding to the first sub-data to be processed, that is, the target queue can indicate the first sub-data to be processed. Alternatively, the target queue can indicate the thread waiting to schedule the second processor. When the second processor finishes processing the first sub-data corresponding to a thread (the second processor becomes idle), the first processor can determine the next first sub-data to be processed by the second processor according to the target queue. In a possible implementation, after obtaining the corresponding first sub-data, N threads add the corresponding first sub-data to the target queue respectively. The first sub-data in the target queue is the first sub-data to be processed. After the second processor finishes processing a first sub-data (for example, referred to as first sub-data 1), the first processor removes a first sub-data (for example, referred to as first sub-data 2) from the target queue to the second processor for processing, that is, the first processor outputs a first sub-data 2 from the target queue to the second processor, and deletes the first sub-data 2 in the target queue. In another possible implementation, after obtaining the corresponding first sub-data, N threads add the corresponding index to the target queue respectively, and the index can be the storage address of the first sub-data or the identifier of the thread. When the index is the storage address of the first sub-data, the index in the target queue is the storage address of the first sub-data to be processed. After the second processor finishes processing a first sub-data (for example, referred to as first sub-data 1), the first processor obtains the storage address of another first sub-data (for example, referred to as first sub-data 2) from the target queue, obtains the first sub-data 2 from the storage address corresponding to the first sub-data 2, inputs the first sub-data 2 to the second processor, and the first processor deletes the storage address of the first sub-data 2 in the target queue. When the index is the identifier of the thread, the identifier in the target queue is the identifier of the thread waiting to call the second processor to process the corresponding first sub-data. After the second processor finishes processing the first sub-data (for example, referred to as first sub-data 1) corresponding to a thread (for example, referred to as thread 1), the first processor obtains the identifier of another thread (for example, referred to as thread 2) from the target queue, and wakes up the thread 2, and the first processor deletes the identifier of the thread 2 in the target queue. After the thread 2 is woken up, the thread 2 inputs the corresponding first sub-data to the second processor.

[0056] The target queue can be a first-in first-out queue, i.e., a thread of the second processor invoked by a first request calls the second processor to process the corresponding first sub-data first, and a thread of the second processor invoked by a second request calls the second processor to process the corresponding first sub-data later. Alternatively, the target queue can also be a first-in last-out queue, i.e., a thread of the second processor invoked by a first request calls the second processor to process the corresponding first sub-data first, and a thread of the second processor invoked by a second request calls the second processor to process the corresponding first sub-data later. Of course, the target queue can also be other types of queues, i.e., the order of the threads of the second processor to be scheduled in the threads of the second processor waiting to be scheduled indicated by the target queue can be determined by other scheduling manners. For example, there are corresponding priorities for N threads, and the thread with the highest priority can be given priority to call the second processor to process the corresponding first sub-data in the threads of the second processor waiting to be scheduled indicated by the target queue. Specifically, if there is an idle second processor, the first sub-data corresponding to the thread with the highest priority can be given priority to be input into the idle second processor for processing in the first sub-data to be processed indicated by the target queue. Alternatively, the order of the threads of the second processor to be scheduled in the threads of the second processor waiting to be scheduled indicated by the target queue can also be determined by random scheduling, which is not limited here.

[0057] The second processor is configured to process the first sub-data to obtain corresponding second sub-data. The number of the second processors can be one or more. Assuming that the number of the second processors is M, M is an integer greater than or equal to 1. When the number of the second processors is one, i.e., M = 1, the first processor can schedule a thread requesting to call the second processor through a first mutex or a target queue. When the number of the second processors is more than one, i.e., M is greater than 1, the first processor can schedule a thread requesting to call the second processor through a target queue. When M is greater than 1, the M second processors can process the first sub-data at the same time, and one first sub-data is processed by one second processor of the M second processors. When there are k (k is an integer greater than or equal to 1) idle second processors in the M second processors, k first sub-data to be processed are determined according to the target queue and input into the k idle second processors. The k first sub-data to be processed correspond to the k idle second processors one by one, i.e., one idle second processor processes one first sub-data of the k first sub-data to be processed, and different second processors process different first sub-data. K is an integer greater than or equal to 1. Specifically, when the target queue is the first sub-data to be processed, the first processor obtains k first sub-data from the target queue and inputs the k first sub-data into the k idle second processors. When the target queue is a storage address of the first sub-data to be processed, the first processor obtains k storage addresses from the target queue and obtains corresponding k first sub-data according to the k storage addresses, and inputs the k first sub-data into the k idle second processors. When the target queue is an identifier of a thread, the first processor obtains k identifiers from the target queue and wakes up k threads corresponding to the k identifiers, and the k threads input corresponding first sub-data into the k idle second processors. It should be noted that if the number of the first sub-data to be processed / the storage address of the first sub-data to be processed / the identifier of the thread in the target queue is less than k (for example, t), t first sub-data to be processed are obtained according to the target queue and input into t second processors of the k idle second processors.

[0058] Since the N first sub-data are obtained by splitting the first data, after the thread obtains the second sub-data corresponding to the first sub-data processed by the second processor, the thread further needs to perform a splicing process on the second sub-data, and splices the N second sub-data to obtain the second data, which is the data obtained by processing the first data by the second processor. When there is overlapping data between adjacent first sub-data, the adjacent second sub-data (adjacent first sub-data corresponding second sub-data are also adjacent) include the to-be-fused data corresponding to the overlapping data, which is obtained by processing the overlapping data by the second processor. The to-be-fused data in the adjacent second sub-data can be fused according to a weight. For example, the first sub-data 3 and the first sub-data 4 are adjacent, and the first sub-data 3 and the first sub-data 4 include the same overlapping data, that is, the first sub-data 3 and the first sub-data 4 include the same data. The first sub-data 3 is processed by the second processor to obtain the second sub-data 3, and the first sub-data 4 is processed by the second processor to obtain the second sub-data 4. The second sub-data 3 includes the to-be-fused data 3 corresponding to the overlapping data, and the second sub-data 4 includes the to-be-fused data 4 corresponding to the overlapping data. The to-be-fused data 3 and the to-be-fused data 4 can be different, and need to be fused by weighting, so as to ensure that the second data is more smooth and natural.

[0059] In the architecture shown in FIG. 2a, the thread is scheduled by the first processor. In another possible implementation, as shown in FIG. 2b, the hardware device can further include a scheduler, and the thread is scheduled by the scheduler. That is, in the architecture shown in FIG. 2b, the first processor is configured to split the first data to be processed into N first sub-data, and obtain N threads to process the N first sub-data. The scheduler is configured to schedule the N threads to sequentially call the second processor. The second processor is configured to process the first sub-data to obtain second sub-data. The method for scheduling the thread by the scheduler can be the method for scheduling the thread by the first processor in FIG. 2a, which will not be described herein again.

[0060] As shown in FIG. 3, FIG. 3 is a flowchart of a data processing method provided by an embodiment of the present application. The embodiment is based on the architecture shown in FIG. 2a or FIG. 2b, and the execution subject of the embodiment is the first processor in FIG. 2a or FIG. 2b. The embodiment includes the following steps:

[0061] S301: Split the first data into N first sub-data, and the N first sub-data are not completely the same.

[0062] For the first data with a size exceeding the single processing capability of the second processor, the first data can be split to obtain N first sub-data, so that the second processor can process the N first sub-data respectively, thereby completing the processing of the first data. Wherein, N is an integer greater than or equal to 2.

[0063] In this embodiment, the first data can be one-dimensional data, two-dimensional data, three-dimensional data or higher-dimensional data, which is not limited here. The one-dimensional data can be audio data, for example. The two-dimensional data can be two-dimensional image data. The three-dimensional data can be three-dimensional image data or point cloud data, such as nuclear magnetic resonance data or depth image data.

[0064] Optionally, after the N first sub-data are processed into N second sub-data, the N second sub-data also need to be spliced into second data. In order to make the splicing position of the second sub-data in the second data more smooth and natural, there can be a part of data overlap (coincidence) between adjacent first sub-data when the first data is split. The data in the first sub-data that coincides with at least one other first sub-data is the overlapping data. Of course, each first sub-data also includes non-overlapping data other than the overlapping data. Hereinafter, the area where the overlapping data is located is referred to as the overlapping area.

[0065] The first processor can split the first data according to the overlap parameter. In one possible implementation, the overlap parameter can include the size of the first data, the size of the first sub-data and the size of the overlapping area. In another possible implementation, the overlap parameter can include the size of the first data, the number N of the first sub-data and the size of the overlapping area. According to the overlap parameter, the position (or coordinates) of each first sub-data in the first data can be determined to split the first data. Each thread can obtain the corresponding first sub-data from the first data according to the position of the corresponding first sub-data. According to the overlap parameter, the position of each overlapping data in the first data can also be determined, which can be used for data fusion during subsequent data splicing. According to the overlap parameter, the position of the non-overlapping data in each first sub-data can also be determined.

[0066] If the first data is one-dimensional data, the first sub-data obtained by splitting is also one-dimensional data. The size of the first data can be 1*w, the size of the first sub-data can be 1*r (unit: bit / byte), and the size of the overlapping region can be an overlapping length s (unit: bit / byte), s is less than r / 2, and s and r are positive integers. Exemplarily, as shown in FIG. 4a, the first sub-data 1 is adjacent to the first sub-data 2, the first sub-data 2 is adjacent to the first sub-data 1 and the first sub-data 3, assuming that the head position of the first sub-data 1 is 0 and the tail position is r, the position of the first sub-data 1 is represented as (0, r), the position of the first sub-data 2 is (r-s, 2r-s), and the position of the first sub-data 3 is (2r-2s, 3r-2s). The position of the overlapping data of the first sub-data 1 and the first sub-data 2 is (r-s, r), and the size is s. The position of the overlapping data of the first sub-data 2 and the first sub-data 3 is (2r-2s, 2r-s), and the size is s. The position of the non-overlapping data of the first sub-data 1 is (0, r-s), and the position of the non-overlapping data of the first sub-data 2 is (r, 2r-2s). It can be understood that the number of first sub-data in FIG. 4a is only illustrative and should not be construed as a limitation of the present application.

[0067] If the first data is two-dimensional data, the size of the first data can be represented as e*f, and the size of the first sub-data can be represented as p*q, p is the length of the first data in the first dimension, and q is the length of the first data in the second dimension. The first sub-data obtained by splitting the first data can be two-dimensional data, and the size of the overlapping region can include an overlapping length x (unit: bit / byte / pixel) in the first dimension and an overlapping length y (unit: bit / byte / pixel) in the second dimension. Wherein, x and y can be the same or different, which is not limited here. x is less than or equal to p / 2, and y is less than q / 2. Alternatively, x is less than p / 2, and y is less than or equal to q / 2. Wherein, x, y, p and q are positive integers, p is greater than or equal to 2, and q is greater than or equal to 2.

[0068] If x is equal to p, each first sub-data includes at most two adjacent first sub-data, and each overlapping data is the data of the overlap of the two adjacent first sub-data, and the size of the overlapping data is x*y. If y is equal to q, each first sub-data includes at most two adjacent first sub-data, and each overlapping data is the data of the overlap of the two adjacent first sub-data, and the size of the overlapping data is x*y.

[0069] If x is less than p and y is less than q, each first sub-data can include, in addition to the first sub-data adjacent to it by edge, the first sub-data adjacent to it by diagonal. For example, as shown in FIG. 4b, the first sub-data adjacent to the first sub-data 1 include the first sub-data 2, the first sub-data 4 and the first sub-data 5, the first sub-data 1 is adjacent to the first sub-data 2 by edge, the first sub-data 1 is adjacent to the first sub-data 4 by edge, and the first sub-data 1 is adjacent to the first sub-data 5 by diagonal.

[0070] Therefore, the overlapping data in each first sub-data can include two types, one type is the overlapping data between two first sub-data adjacent to each other by edge (hereinafter referred to as edge overlapping data), and the other type is the overlapping data between four first sub-data adjacent to each other by diagonal (hereinafter referred to as diagonal overlapping data). The edge overlapping data further includes the overlapping data between the first sub-data and different other first sub-data. According to the overlapping parameter, the position of each first sub-data in the first data can be determined, so that the N threads can obtain the corresponding first sub-data according to the position. According to the overlapping parameter, the position of each overlapping data in the first data can also be determined, so that subsequent data fusion can be performed according to the position. As shown in FIG. 4b, the first sub-data 1 includes overlapping data 1, overlapping data 2 and overlapping data 3, the overlapping data 1 and the overlapping data 3 are edge overlapping data, and the overlapping data 2 is diagonal overlapping data. The overlapping data 1 is the data overlapping between the first sub-data 1 and the first sub-data 2, the overlapping data 2 is the data overlapping between the first sub-data 1, the first sub-data 2, the first sub-data 4 and the first sub-data 5, and the overlapping data 3 is the data overlapping between the first sub-data 1 and the first sub-data 4. The positions of the four vertices of the first sub-data 1 are (0, 0), (p, 0), (0, q) and (p, q) respectively, the positions of the four vertices of the overlapping data 1 are (p-x, 0), (p, 0), (p-x, q-y) and (p-x, q) respectively, the positions of the four vertices of the overlapping data 2 are (p-x, q-y), (p, q-y), (p-x, q) and (p, q) respectively, and the positions of the four vertices of the overlapping data 3 are (0, q-y), (p-x, q-y), (0, q) and (p-x, q) respectively. It can be understood that FIG. 4b is only an example, and the number of first sub-data in practice can be more or less, which is not limited herein.

[0071] It should be noted that the sizes of the N first sub-data can be the same, i.e., the first data can be evenly divided into N first sub-data; the sizes of the N first sub-data can also not be completely the same, i.e., the first data cannot be evenly divided into N first sub-data, and the size of the first sub-data located in the edge region of the first data can be smaller than the size of the other first sub-data. For example, taking the first data as one-dimensional data, when w = N*r-(N-1)*s, the first data can be evenly divided into N first sub-data, and the sizes of the N first sub-data are the same; when w < N*r-(N-1)*s, there is at least one first sub-data whose size is smaller than 1*r, and the sizes of the N first sub-data are not completely the same. Taking the first data as two-dimensional data, assuming that the number of first sub-data in the first dimension of the first data is i, the number of first sub-data in the second dimension is j, and N = i*j, when e = i*p-(i-1)*x and f = i*q-(i-1)*y, the first data can be evenly divided into N first sub-data; when e < i*p-(i-1)*x and / or f < i*q-(i-1)*y, the first data cannot be evenly divided into N first sub-data, and there is at least one first sub-data whose size is smaller than p*q, and the sizes of the N first sub-data are not completely the same.

[0072] Optionally, when the first data is divided, the size of the first sub-data can be adjusted to make the sizes of the N first sub-data more close or consistent, on the premise that the length of the first sub-data in the same dimension is greater than the dimension of the overlap region.

[0073] Of course, when the first data is split, the overlap region can also not be divided, i.e., there is no overlap region between each first sub-data and the adjacent first sub-data, and the overlap data is not included in the first sub-data, which is not limited here.

[0074] The division of one-dimensional data and two-dimensional data is described above. For three-dimensional data or higher-dimensional data, the split can be performed in at least two dimensions. For example, three-dimensional data can be split in two dimensions or in three dimensions. The split of three-dimensional and higher-dimensional data has the same principle as the split of one-dimensional data and two-dimensional data, which will not be repeated here.

[0075] S302: Obtain N threads, the N threads correspond to the N first sub-data one by one, and each thread in the N threads is used to execute a data processing task of the corresponding first sub-data.

[0076] In this embodiment, the first processor obtains N threads, the N threads correspond to the N first sub-data one by one, and each thread in the N threads is used to execute a data processing task of the corresponding first sub-data. Different threads execute different data processing tasks of different first sub-data. The N threads are parallel threads, and the N threads are independent of each other and do not need to be synchronized. The N threads can be created by the first processor, or the N threads can be obtained from a thread pool by the first processor.

[0077] The data processing task corresponding to each thread includes, for example, obtaining the corresponding first sub-data, calling the second processor to process the corresponding first sub-data, and splicing the second sub-data obtained by processing the first sub-data by the second processor. Alternatively, the thread can also preprocess the corresponding first sub-data before calling the second processor to process the first sub-data, and then call the second processor to further process the preprocessed first sub-data. The preprocessing includes, for example, format conversion, normalization, offset, and the like, so that the preprocessed first sub-data is more suitable for the architecture of the second processor.

[0078] S303: The N threads respectively call the second processor to process the corresponding first sub-data to obtain N second sub-data.

[0079] The thread can call the second processor to process the first sub-data after obtaining the corresponding first sub-data, or after preprocessing the first sub-data.

[0080] When the number of second processors is less than the number N of threads, the second processor is equivalent to a shared resource, and multiple threads may conflict when calling the second processor. In order to reduce the resource consumption caused by the N threads competing for the second processor, the first mutex or the target queue can be used to schedule the threads, so that the N threads can respectively call the second processor to process the corresponding first sub-data. Since the N threads are parallel threads, when the second processor processes the first sub-data corresponding to a thread, at least one thread is waiting to call the second processor, so as to reduce the time for the second processor to wait for processing the first sub-data, thereby improving the utilization rate of the second processor and improving the overall processing efficiency of the data.

[0081] The scheduling of threads by the first mutex or the target queue can refer to the corresponding content of FIG. 2a, and therefore will not be described here.

[0082] Since the N first sub-data are obtained by splitting the first data, the N second sub-data obtained by the second processor processing the N first sub-data need to be spliced into the second data, which is the complete result data. In this embodiment, the N threads can independently and in parallel perform data splicing. Specifically, after a thread obtains the corresponding second sub-data, the thread writes the corresponding second sub-data into a sub-storage area corresponding to the thread in a target storage area. The second sub-data corresponding to the thread is the data obtained by the second processor processing the first sub-data corresponding to the thread. The target storage area is used to store the second data, and the target storage area can be divided into N sub-storage areas, which correspond to the N threads one by one, and different threads correspond to different sub-storage areas. The sub-storage area corresponding to a thread is used to store the second sub-data corresponding to the thread. Therefore, each thread writes the corresponding second sub-data into the corresponding sub-storage area after obtaining the corresponding second sub-data, and the splicing of the second data is completed.

[0083] Optionally, if there is overlapping data between adjacent first sub-data, the data corresponding to the overlapping data in the second sub-data needs to be fused when splicing the second data. In this embodiment, the first data and the second data have the same size, and each first sub-data and the corresponding second sub-data also have the same size. Moreover, the position of each second sub-data in the second data is the same as the position of the corresponding first sub-data in the first data. The position of the overlapping data in the first sub-data is also the same as the position of the to-be-fused data in the corresponding second sub-data. The to-be-fused data in the second sub-data is obtained by the second processor processing the overlapping data in the corresponding first sub-data.

[0084] The sub-storage area includes a first area and a second area. The position of the first area can be determined according to the position of the overlapping data in the first data, and the position of the second area can be determined according to the position of the non-overlapping data in the first data. Since the first data and the second data have the same size, and the position of the overlapping data in the first sub-data is the same as the position of the to-be-fused data in the corresponding second sub-data, the position of the first area is the position of the overlapping data in the first data, and the first area corresponds to the overlapping area in the first sub-data. The position of the second area is the position of the non-overlapping data in the first data. The first area is a storage area shared by at least two sub-storage areas, and is used to store the to-be-fused data after weighting processing. The second area is used to store the data corresponding to the non-overlapping data in the second sub-data.

[0085] After obtaining the corresponding second sub-data, the thread directly writes the data corresponding to the non-overlapping data in the second sub-data, i.e., the data in the second sub-data other than the to-be-fused data, into the second region in the corresponding sub-storage area. For the to-be-fused data in the second sub-data, the thread needs to perform weighted fusion processing and then write the data into the first region in the corresponding sub-storage area. All to-be-fused data corresponding to the same overlapping data needs to be fused. In this embodiment, in order to improve the overall data processing efficiency and reduce the waiting time during data fusion, the threads are independent and parallel, and the threads independently fuse the to-be-fused data when splicing the second sub-data. Specifically, the first thread reads third data from the first region in the corresponding sub-storage area. The first thread is any one of the N threads. The first thread writes fourth data into the first region in the corresponding sub-storage area, and the fourth data covers the third data. The fourth data is obtained according to the second data and the to-be-fused data in the second sub-data corresponding to the first thread. For example, the first thread obtains a corresponding weight, adds the data obtained by processing the to-be-fused data using the weight to the third data, and obtains the fourth data. If no other thread in the N threads writes data into the first region before the first thread writes the fourth data into the first region, the read third data is empty or all zeros, and the first thread processes the to-be-fused data in the corresponding second sub-data according to the weight to obtain the fourth data. When the second thread needs to write data into the first region, the fourth data is read from the first region, the fifth data is obtained according to the to-be-fused data in the second sub-data corresponding to the second thread and the fourth data, and then the fifth data is written into the first region, and the fifth data covers the fourth data. Until all to-be-fused data corresponding to the first region are fused by weighted calculation, the data stored in the first region is the fused data. Thus, different threads can independently perform data fusion without waiting for the AI processor to process all the first sub-data before fusion, which can improve the overall data processing efficiency.

[0086] The to-be-fused data corresponding to the edge overlapping data and the to-be-fused data corresponding to the diagonal overlapping data can be fused by different methods. The to-be-fused data corresponding to the edge overlapping data is two, and the weight of one to-be-fused data is w1, and the weight of the other to-be-fused data is w2 = 1-w1. In a possible implementation, fixed weights can be preconfigured, for example, w1 and w2 are both 0.5. In another possible implementation, for the to-be-fused data corresponding to the edge overlapping data, the weights can be determined by a linear interpolation method. The to-be-fused data corresponding to the diagonal overlapping data is four, and the corresponding weights are also four. For the to-be-fused data corresponding to the diagonal overlapping data, the weights can be determined by a bilinear interpolation method. When the first data is two-dimensional image data, the second data is also two-dimensional image data, the first data and the second data are pixel values, and when the to-be-fused data is fused, the pixel values of each pixel can be calculated by weighting. The thread can determine the weight of the pixel according to the coordinates of the pixel in the to-be-fused data. The closer the pixel is to the adjacent second sub-data, the smaller the weight is.

[0087] Exemplarily, taking FIG. 5 as an example, FIG. 5 is a target storage area corresponding to FIG. 4b, and the target storage area shown in FIG. 5 is used to store second data corresponding to the first data shown in FIG. 4b. It is assumed that sub-storage area 1 in FIG. 5 corresponds to thread 1, and thread 1 is used to execute a data processing task corresponding to first sub-data 1 in FIG. 4b. After thread 1 obtains second sub-data 1 corresponding to first sub-data 1, thread 1 writes second sub-data 1 into sub-storage area 1. Sub-storage area 1 includes first area 1 and second area 1, and second area 1 is used to store data corresponding to non-overlapping data in second sub-data 1. It is assumed that sub-storage area 2 in FIG. 5 corresponds to thread 2, and thread 2 is used to execute a data processing task corresponding to first sub-data 2 in FIG. 4b. After thread 2 obtains second sub-data 2 corresponding to first sub-data 2, thread 2 writes second sub-data 2 into sub-storage area 2. Sub-storage area 2 includes first area 2 and second area 2, and second area 2 is used to store data corresponding to non-overlapping data in second sub-data 2. It is assumed that sub-storage area 4 in FIG. 5 corresponds to thread 4, and thread 4 is used to execute a data processing task corresponding to first sub-data 4 in FIG. 4b. After thread 4 obtains second sub-data 4 corresponding to first sub-data 4, thread 4 writes second sub-data 4 into sub-storage area 4. Sub-storage area 4 includes first area 4 and second area 4, and second area 4 is used to store data corresponding to non-overlapping data in second sub-data 4. It is assumed that sub-storage area 5 in FIG. 5 corresponds to thread 5, and thread 5 is used to execute a data processing task corresponding to first sub-data 5 in FIG. 4b. After thread 5 obtains second sub-data 5 corresponding to first sub-data 5, thread 5 writes second sub-data 5 into sub-storage area 5. Sub-storage area 5 includes first area 5 and second area 5, and second area 5 is used to store data corresponding to non-overlapping data in second sub-data 5. First area 1 includes first area 1A, first area 1B, and first area 1C. First area 1A is used to store data fused from to-be-fused data corresponding to overlapping data 1, first area 1B is used to store data fused from to-be-fused data corresponding to overlapping data 2, and first area 1C is used to store data fused from to-be-fused data corresponding to overlapping data 3. Assuming that the order in which the second processor processes the first sub-data is first sub-data 1, first sub-data 2, first sub-data 4, and first sub-data 5, the order in which the second sub-data is obtained is thread 1, thread 2, thread 4, and thread 5, respectively.

[0088] Taking the fusion of the to-be-fused data corresponding to the overlapping data 1 of thread 1 and thread 2 and the to-be-fused data corresponding to the overlapping data 2 of thread 1, thread 2, thread 4 and thread 5 as an example. After obtaining the second sub-data 1, the thread 1 directly writes the data corresponding to the non-overlapping data in the second sub-data 1 into the second area 1. Moreover, the thread 1 adds the data obtained by performing the weighting processing on the to-be-fused data corresponding to the overlapping data 1 in the second sub-data 1 to the data read from the first area 1A, obtains the fusion data 1, and writes the fusion data 1 into the first area 1A. The thread 1 adds the data obtained by performing the weighting processing on the to-be-fused data corresponding to the overlapping data 2 in the second sub-data 1 to the data read from the first area 1B, obtains the fusion data 2, and writes the fusion data 2 into the first area 1B. The thread 2 adds the data obtained by performing the weighting processing on the to-be-fused data corresponding to the overlapping data 1 in the second sub-data 2 to the fusion data 1 read from the first area 1A, obtains the fusion data 3, and writes the fusion data 3 into the first area 1A. The fusion data 3 is the result data obtained by fusing all the to-be-fused data corresponding to the overlapping data 1. The thread 2 adds the data obtained by performing the weighting processing on the to-be-fused data corresponding to the overlapping data 2 in the second sub-data 2 to the fusion data 2 read from the first area 1B, obtains the fusion data 4, and writes the fusion data 4 into the first area 1B, which covers the fusion data 2 in the first area 1B. The thread 4 adds the data obtained by performing the weighting processing on the to-be-fused data corresponding to the overlapping data 2 in the second sub-data 4 to the fusion data 4 read from the first area 1B, obtains the fusion data 5, and writes the fusion data 5 into the first area 1B, which covers the fusion data 4 in the first area 1B. The thread 5 adds the data obtained by performing the weighting processing on the to-be-fused data corresponding to the overlapping data 2 in the second sub-data 5 to the fusion data 5 read from the first area 1B, obtains the fusion data 6, and writes the fusion data 6 into the first area 1B, which covers the fusion data 5 in the first area 1B. The fusion data 6 is the result data obtained by fusing all the to-be-fused data corresponding to the overlapping data 2.

[0089] Optionally, for the first area, at least two threads write data into the first area, in order to avoid read-write conflict, the second mutex can be used to protect the first area, so that only one thread reads and writes the first area at the same time, and the accuracy of the result data after fusion is ensured.

[0090] In this embodiment, the N threads process the N first sub-data, and each thread processes one first sub-data, so that the plurality of first sub-data can be processed in parallel. The data processing tasks of the corresponding first sub-data are independently executed between threads, without the need for communication between threads, so that the data processing delay can be reduced. Moreover, the N threads respectively call the second processor to process the corresponding first sub-data, so that the time for the second processor to wait for processing the first sub-data can be reduced, and the utilization rate of the second processor can be improved. Furthermore, if there is overlapping data between adjacent first sub-data, the threads independently perform fusion of the to-be-fused data corresponding to the overlapping data in subsequent splicing of the second data, without the need to wait for all the first sub-data to be processed before performing fusion, so that the data fusion efficiency can be improved, thereby improving the overall data processing efficiency.

[0091] The same as the above idea, as shown in FIG. 6, which is a structural schematic diagram of a data processing apparatus provided by the present application. The data processing apparatus 600 is applied to a first processor. The data processing apparatus 600 can be a software module or a hardware module, for example, the first processor or the hardware device described above. The data processing apparatus 600 comprises a processing module 601. The processing module 601 is configured to split the first data into N first sub-data, the N first sub-data are not completely identical, and N is an integer greater than or equal to 2. The processing module 601 is configured to obtain N threads, the N threads correspond to the N first sub-data one by one, and each thread in the N threads is configured to execute a data processing task of the corresponding first sub-data. The processing module 601 is configured to call a second processor to process the corresponding first sub-data by the N threads respectively, to obtain N second sub-data.

[0092] In a possible implementation, the processing module 601 is configured to call the second processor to process the corresponding first sub-data by the N threads based on a first mutex.

[0093] In a possible implementation, the number of second processors is M, and M is an integer greater than or equal to 1. The processing module 601 is configured to call an idle second processor in the M second processors to process the corresponding first sub-data by the N threads based on a target queue. The target queue is configured to store the first sub-data to be processed by the second processor, or the target queue is configured to store an index corresponding to the first sub-data to be processed by the second processor.

[0094] In a possible implementation, the target queue is a first-in first-out queue or a last-in first-out queue.

[0095] In a possible implementation, the processing module 601 is configured to write the corresponding second sub-data into a target storage area by the N threads. The target storage area is configured to store second data, and the second data is the processed first data.

[0096] In a possible implementation, the first sub-data includes overlapping data, the overlapping data being data that coincides in at least two first sub-data, the second sub-data includes to-be-fused data, the to-be-fused data being data processed by the second processor on the overlapping data, the target storage area includes N sub-storage areas, the N sub-storage areas correspond to the N second sub-data in a one-to-one manner, and each sub-storage area includes a first area, the first area being a storage area shared by at least two sub-storage areas; the processing module 601 is configured to read, by a first thread, third data from the first area in the corresponding sub-storage area, the first thread being any one of N threads; and the processing module 601 is configured to write, by the first thread, fourth data in the first area in the corresponding sub-storage area, the fourth data covering the third data, the fourth data being obtained according to the third data and to-be-fused data in the second sub-data corresponding to the first thread.

[0097] In a possible implementation, each sub-storage area includes a second area, the second area being an area in the sub-storage area other than the first area, and the apparatus further includes a processing module 601 configured to write, by the first thread, data other than the to-be-fused data in the corresponding second sub-data into the second area.

[0098] In a possible implementation, the first data is image data or audio data.

[0099] As shown in FIG. 7, FIG. 7 is a structural schematic diagram of an electronic device provided in an embodiment of the present application. In this embodiment, the electronic device 700 can be a target network device in the network device in FIG. 1, for example, an edge switch or a convergence switch. Alternatively, the electronic device 700 can be a server, a server cluster, a computer, a tablet computer, a car machine, a smart phone, an analyzer, a cloud device, a smart wearable device, a SoC, etc.

[0100] The electronic device 700 includes a bus 701, a processor 702, a communication interface 703, and a memory 704. The processor 702, the memory 704, and the communication interface 703 communicate with each other through the bus 701.

[0101] The bus 701 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in FIG. 7, but it does not mean that there is only one bus or only one type of bus.

[0102] The processor 702 can be any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor, a microcontroller, a digital signal processor (DSP), or the like.

[0103] The memory 704 can include volatile memory, such as random access memory (RAM), and non-volatile memory, such as read-only memory (ROM), a floppy disk drive, a hard disk drive, or a solid state drive.

[0104] The memory 704 can be configured to store software code related to the routing processing method, and the processor 702 can execute the steps of the routing processing method or schedule other units to implement corresponding functions.

[0105] It should be understood that the electronic device 700 can be a centralized or distributed device, and the processor 702 in the electronic device 700 can be a hardware circuit (such as an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a general processor, a digital signal processor (DSP), a microprocessor, or a microcontroller, etc.), or a combination of these hardware circuits. For example, the processor can be a hardware system with an execution instruction function, such as a CPU, a DSP, etc., or a hardware system without an execution instruction function, such as an ASIC, an FPGA, etc., or a combination of the hardware system without an execution instruction function and the hardware system with an execution instruction function.

[0106] The present application also provides a computer readable storage medium having a computer program stored thereon, which, when executed by a computer, implements the routing processing method flow of the above method embodiment.

[0107] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiment, and will not be repeated here.

[0108] The application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a computer to implement the routing processing method flow of the method embodiment.

[0109] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiment, and will not be repeated here.

[0110] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the described device embodiments are merely schematic, and the division of units is merely a logical function division, and there can be another division manner in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical or other forms.

[0111] The units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, that is, can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0112] In addition, each functional unit in the various embodiments of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0113] The integrated unit, if in the form of a software function unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on such an understanding, all or part of the technical solutions of the present application can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

Claims

1. A data processing method, characterized by, The method is applied to a first processor, and the method comprises: splitting first data into N first sub-data, the N first sub-data being not completely identical, N being an integer greater than or equal to 2; obtaining N threads, the N threads corresponding to the N first sub-data one by one, each of the N threads being used to execute a data processing task of the corresponding first sub-data; the N threads respectively calling a second processor to process the corresponding first sub-data to obtain N second sub-data.

2. The method of claim 1, wherein, The number of the second processors is 1, and the N threads respectively calling a second processor to process the corresponding first sub-data comprises: the N threads calling the second processor to process the corresponding first sub-data through a first mutex.

3. The method of claim 1, wherein, The number of the second processors is M, M being an integer greater than or equal to 1, and the N threads respectively calling a second processor to process the corresponding first sub-data comprises: the N threads calling an idle second processor of the M second processors to process the corresponding first sub-data through a target queue, the target queue being used to store first sub-data to be processed by the second processor or an index corresponding to the first sub-data to be processed by the second processor.

4. The method according to any one of claims 1 to 3, characterized in that, The method further comprises: the N threads writing the corresponding second sub-data into a target storage area, the target storage area being used to store second data, the second data being the first data after processing.

5. The method of claim 4, wherein, The first sub-data comprises overlapping data, the overlapping data being data coinciding in at least two first sub-data, the second sub-data comprising to-be-fused data, the to-be-fused data being obtained by processing the overlapping data by the second processor, and the target storage area comprising N sub-storage areas, the N sub-storage areas corresponding to the N second sub-data one by one, each of the sub-storage areas comprising a first area, the first area being a storage area common to at least two sub-storage areas. The N threads writing the corresponding second sub-data into a target storage area comprises: a first thread reading third data from the first area in the corresponding sub-storage area, the first thread being any one of the N threads; the first thread writing fourth data into the first area in the corresponding sub-storage area, the fourth data covering the third data, the fourth data being obtained according to the third data and to-be-fused data in the second sub-data corresponding to the first thread.

6. The method of claim 5, wherein, Each of the sub-storage areas comprises a second area, the second area being an area other than the first area in the sub-storage area, and the method further comprises: the first thread writing data other than the to-be-fused data in the corresponding second sub-data into the second area.

7. A data processing apparatus, characterized by, The device is applied to a first processor, and the device comprises: a processing module, configured to split first data into N first sub-data, the N first sub-data being not completely identical, N being an integer greater than or equal to 2; The processing module is configured to obtain N threads, the N threads correspond to the N first sub-data one by one, and each of the N threads is configured to execute a data processing task of the corresponding first sub-data. The processing module is configured to call the second processor to process the corresponding first sub-data by the N threads respectively, to obtain N second sub-data.

8. The apparatus of claim 7, wherein The processing module is configured to call the second processor to process the corresponding first sub-data based on a first mutex by the N threads.

9. The apparatus of claim 7, wherein, The number of the second processors is M, and M is an integer greater than or equal to 1. The processing module is configured to call an idle second processor of the M second processors to process the corresponding first sub-data based on a target queue by the N threads, and the target queue is configured to store the first sub-data to be processed by the second processor or an index corresponding to the first sub-data to be processed by the second processor.

10. The apparatus of any one of claims 7 to 9, wherein The processing module is configured to write the corresponding second sub-data into a target storage area by the N threads, and the target storage area is configured to store second data, which is the processed first data.

11. The apparatus of claim 10, wherein, The first sub-data includes overlapping data, the overlapping data is data that coincides in at least two first sub-data, the second sub-data includes to-be-fused data, the to-be-fused data is obtained by processing the overlapping data by the second processor, and the target storage area includes N sub-storage areas, the N sub-storage areas correspond to the N second sub-data one by one, and each of the sub-storage areas includes a first area, which is a storage area shared by at least two sub-storage areas. The processing module is configured to read third data from the first area in the corresponding sub-storage area by a first thread, and the first thread is any one of the N threads. The processing module is configured to write fourth data into the first area in the corresponding sub-storage area by the first thread, and the fourth data covers the third data, and the fourth data is obtained according to the third data and to-be-fused data in the second sub-data corresponding to the first thread.

12. The apparatus of claim 11, wherein, Each of the sub-storage areas includes a second area, which is an area other than the first area in the sub-storage area, and the apparatus further includes: The processing module is configured to write data other than the to-be-fused data in the corresponding second sub-data into the second area by the first thread.

13. A data processing apparatus, characterized by: The apparatus includes a processor and a memory, The processor is configured to execute a computer program or instructions stored in the memory, and when the processor executes the computer program or instructions, the method in any one of claims 1 to 6 is executed.

14. A chip, characterized by A processor coupled to a memory for executing computer programs or instructions stored in the memory, the processor when executing the computer programs or instructions, performs the method of any one of claims 1 to 6.

15. A computer-readable storage medium, characterized in that, A computer readable medium storing instructions which, when executed on a computer, cause the computer to perform the method of any one of claims 1 to 6.

16. A computer program product, characterised in that, A computer readable medium storing computer readable instructions which, when read and executed by a communications device, cause the communications device to perform the method of any one of claims 1 to 6.

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