Semiconductor structure and manufacturing method therefor

Abstract

Provided in the present disclosure are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate; a first insulating dielectric layer provided on the substrate; a front layer structure provided in the first insulating dielectric layer; a second insulating dielectric layer provided on the first insulating dielectric layer; a third insulating dielectric layer provided on the second insulating dielectric layer; a current layer structure provided in the third insulating dielectric layer and comprising a plurality of first conductive wires arranged at intervals; a first interconnection structure passing through the second insulating dielectric layer to connect some of the first conductive wires and the front layer structure; and a second interconnection structure passing through the first insulating dielectric layer and the second insulating dielectric layer to connect some of the first conductive wires, the first interconnection structure and the second interconnection structure being isolated from each other.

Description

Semiconductor structure and manufacturing method thereof

[0001] Cross-reference to Related Applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202411359347.5, filed on September 26, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0004] Memory is a memory component used to store programs and various data information. The random access memory (RAM) used by a general computer system can be divided into dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory is a commonly used semiconductor memory device in computers, which is composed of many repeated memory units.

[0005] It is necessary to improve the reliability of the semiconductor structure. SUMMARY

[0006] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which can at least improve the reliability of the semiconductor structure.

[0007] According to some embodiments of the present disclosure, in one aspect, a semiconductor structure is provided, comprising: a substrate, the substrate being provided with a first insulating medium layer; a front layer structure, the front layer structure being arranged in the first insulating medium layer; a second insulating medium layer, the second insulating medium layer being arranged on the first insulating medium layer; a third insulating medium layer, the third insulating medium layer being arranged on the second insulating medium layer; a when layer structure, the when layer structure being arranged in the third insulating medium layer and comprising a plurality of first conductive lines arranged at intervals from each other; a first interconnection structure, the first interconnection structure connecting part of the first conductive lines and the front layer structure through the second insulating medium layer; and a second interconnection structure, the second interconnection structure connecting part of the first conductive lines through the first insulating medium layer and the second insulating medium layer, the first interconnection structure and the second interconnection structure being isolated from each other.

[0008] In some embodiments, the second interconnection structure also penetrates the substrate.

[0009] In some embodiments, the first conductive line covers a top surface of the second insulating medium layer, and the first interconnect structure further connects with the front layer structure through the first insulating medium layer.

[0010] In some embodiments, the first interconnect structure and the second interconnect structure further connect with the respective first conductive line through a portion of the third insulating medium layer.

[0011] In some embodiments, the front layer structure includes a transistor, and the transistor is connected with the first interconnect structure.

[0012] In some embodiments, the front layer structure further includes a second conductive line disposed in the first insulating medium layer above the transistor, and the first interconnect structure includes a first interconnect portion connecting the first conductive line and the second conductive line and a second interconnect portion connecting the second conductive line and the transistor, the first interconnect portion connects with the second conductive line through the second insulating medium layer, and the second interconnect portion connects with the transistor through the first insulating medium layer.

[0013] In some embodiments, the semiconductor structure further includes a third interconnect structure, the second conductive line includes a portion connected with the first interconnect structure and a portion connected with the third interconnect structure, and the second conductive line connected with the third interconnect structure is connected to the first conductive line connected with the second interconnect structure through the third interconnect structure.

[0014] In some embodiments, the second interconnect structure includes an insulating liner layer and a conductive interconnect layer, the insulating liner layer is between the first insulating medium layer and the conductive interconnect layer, and the conductive interconnect layer is in direct contact with the second insulating medium layer.

[0015] In some embodiments, the first interconnect structure and the second interconnect structure include different metals.

[0016] In some embodiments, a ratio of a thickness of the second interconnect structure in the second insulating medium layer and a thickness of the second interconnect structure in the third insulating medium layer is 2:1 to 5:1.

[0017] In some embodiments, the first insulating medium layer and the second insulating medium layer include different insulating materials.

[0018] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate being provided with a first insulating medium layer; forming a front layer structure, the front layer structure being arranged in the first insulating medium layer; forming a second insulating medium layer, the second insulating medium layer being arranged on the first insulating medium layer; forming a third insulating medium layer, the third insulating medium layer being arranged on the second insulating medium layer; forming a when layer structure, the when layer structure being arranged in the third insulating medium layer, the when layer structure comprising a plurality of first conductive lines arranged at intervals from each other; forming a first interconnection structure, the first interconnection structure penetrating through the second insulating medium layer to connect part of the first conductive lines and the front layer structure; and forming a second interconnection structure, the second interconnection structure penetrating through the first insulating medium layer and the second insulating medium layer to connect part of the first conductive lines, the first insulating medium layer and the second insulating medium layer being isolated from each other.

[0019] In some embodiments, the method for forming the first interconnection structure comprises: after forming the second insulating medium layer and before forming the third insulating medium layer, etching at least the second insulating medium layer to form a first via abutting the front layer structure; and filling the first via to form the first interconnection structure.

[0020] In some embodiments, the method for forming the when layer structure comprises: after forming the third insulating medium layer, patterning the third insulating medium layer to form the plurality of first conductive lines in the third insulating medium layer, wherein part of the first conductive lines are connected with the first interconnection structure.

[0021] In some embodiments, the method for forming the second interconnection structure comprises: after forming the third insulating medium layer and the when layer structure, etching the substrate and the first insulating medium layer from the substrate towards the first insulating medium layer to form an initial via, the initial via exposing a surface of the second insulating medium layer; forming an insulating liner layer, the insulating liner layer covering a sidewall of the initial via; etching at least the second insulating medium layer until a surface of part of the first conductive lines towards the substrate is exposed to form a second via exposing part of the first conductive lines; and filling the second via to form a conductive interconnection layer, the conductive interconnection layer and the insulating liner layer forming the second interconnection structure.

[0022] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages: by arranging the second insulating medium layer, the first insulating medium layer in the front layer structure and the substrate can be prevented from being contaminated by the second interconnection structure; in addition, the stress between the first interconnection structure and the second interconnection structure can be relieved by the first insulating medium layer and the second insulating medium layer, and the reliability of the semiconductor structure can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0023] One or more embodiments are illustrated by way of example in the drawings and specification hereof, which are not intended to limit the embodiments to the specific embodiments shown, unless otherwise specifically indicated. In the drawings, like reference numerals refer to like elements, and in which:

[0024] FIGS. 1-4 are structural schematic diagrams of a semiconductor structure according to embodiments of the present disclosure;

[0025] FIG. 5 is a flowchart of a method for manufacturing a semiconductor structure according to embodiments of the present disclosure;

[0026] FIGS. 6-18 are structural schematic diagrams of respective steps of a method for manufacturing a semiconductor structure according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0027] As known from the background, the reliability of semiconductor structures needs to be improved.

[0028] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present disclosure, many technical details are presented in order to make the readers better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and based on various changes and modifications of the following embodiments.

[0029] Referring to FIGS. 1 and 2, FIG. 1 is a structural schematic diagram of a semiconductor structure according to an embodiment of the present disclosure, and FIG. 2 is a structural schematic diagram of a semiconductor structure according to another embodiment of the present disclosure.

[0030] In some embodiments, the semiconductor structure includes a substrate 100, and a first insulating medium layer 101 is disposed on the substrate 100.

[0031] The semiconductor structure further includes a front layer structure 102 disposed in the first insulating medium layer 101.

[0032] The semiconductor structure further includes a second insulating medium layer 103 disposed on the first insulating medium layer 101.

[0033] The semiconductor structure further includes a third insulating medium layer 124 disposed on the second insulating medium layer 103.

[0034] The semiconductor structure further comprises: the layer structure 104, when the layer structure 104 comprises a plurality of first conductive lines arranged at intervals, for example, the first conductive line 121 and the first conductive line 122 arranged at intervals through the third insulating medium layer 124.

[0035] The semiconductor structure further comprises: the first interconnection structure 105 connected with the first conductive line 122 and the front layer structure 102 through the second insulating medium layer 103.

[0036] The semiconductor structure further comprises: the second interconnection structure 106 connected with the first conductive line 121 through the first insulating medium layer 101 and the second insulating medium layer 103, and the first interconnection structure 105 and the second interconnection structure 106 are isolated from each other.

[0037] The semiconductor structure provided by the embodiments of the present disclosure comprises the first interconnection structure connecting the front layer structure and the layer structure and the second interconnection structure leading out the layer structure, and the insulating layer combination composed of the second insulating medium layer and the first insulating medium layer is arranged to prevent the existence of an undesired conductive path between the interconnection structures and between the interconnection structure and the front layer structure, thereby affecting the performance and reliability of the device.

[0038] In some embodiments, the material of the substrate 100 can comprise a semiconductor material, for example, but not limited to, silicon. In some embodiments, the material of the substrate 100 can comprise silicon, germanium, or germanium-silicon, etc.; in some embodiments, the material of the substrate 100 can further comprise silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide, etc.; in some embodiments, the material of the substrate 100 can further comprise gallium arsenide phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide, etc. In some embodiments, the substrate 100 can also be a silicon-on-insulator structure.

[0039] In addition, the substrate 100 can be doped according to design requirements (for example, a P-type substrate or an N-type substrate). In some embodiments, the substrate 100 can be doped with P-type doping ions (for example, boron ions, aluminum ions) or N-type doping ions (for example, phosphorus ions, arsenic ions).

[0040] In some embodiments, the first insulating medium layer 101 can be a single-layer structure formed by an insulating material, or a multi-layer structure formed by multiple depositions of an insulating material, for example, a composite film layer composed of multiple layers of silicon dioxide, or a multi-layer structure formed by composite deposition of different insulating materials, for example, a composite film layer composed of at least two of the insulating medium materials such as silicon dioxide, silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon nitride.

[0041] In some embodiments, the front layer structure 102 can be a transistor or other semiconductor device. Embodiments of the present disclosure take the transistor as an example for the front layer structure 102, but this does not constitute a limitation on the type of the front layer structure 102. When the front layer structure 102 is a transistor, a simple schematic diagram of the front layer structure 102 is shown in FIG. 1, which includes a gate oxide layer 111 located on a substrate 100, a gate 112 disposed on the gate oxide layer 111, and an isolation medium layer 113 covering the outside of the gate oxide layer 111 and the gate 112. The gate 112 can be a single-layer structure or a multi-layer structure, and the isolation medium layer 113 can be a single-layer structure or a multi-layer structure. The isolation medium layer 113 and the first insulating medium layer can include the same insulating material or different insulating materials.

[0042] In some embodiments, the second insulating medium layer 103 and the first insulating medium layer 101 include different insulating materials. In some embodiments, when the first insulating medium layer 101 is a multi-layer structure, the material of the portion of the first insulating medium layer 101 adjacent to the second insulating medium 103 is different from the material of the second insulating medium layer 103. For example, the first insulating medium layer 101 includes silicon dioxide, and the second insulating medium layer 103 includes silicon nitride.

[0043] In some embodiments, the third insulating medium layer 124 includes a material different from the second insulating medium layer 103. For example, the third insulating medium layer 124 is silicon dioxide, and the second insulating medium layer 103 is silicon nitride.

[0044] In some embodiments, when the layer structure 104 is a metal wire, such as a copper wire or a tungsten wire, etc. A barrier layer for preventing the diffusion of the metal wire is further disposed between the layer structure 104 and the third insulating medium layer 124, such as tantalum (Ta), tantalum nitride (TaN), cobalt (Co), etc.

[0045] It should be noted that the front layer structure and the layer structure in the embodiments of the present disclosure do not constitute a limitation on the structure itself. In some embodiments, they are used to indicate the positional relationship or the order of formation of the two structures. For example, for the layer structure, the front layer structure means that it is formed before the layer structure, or in terms of positional relationship, it is closer to the substrate.

[0046] In some embodiments, the first interconnection structure 105 and the second interconnection structure 106 include different metal materials. For example, the first interconnection structure includes an interconnection structure composed of metal tungsten or its alloy, and the second interconnection structure 106 includes an interconnection structure composed of metal copper or its alloy.

[0047] In some embodiments, the first interconnection structure 105 and the second interconnection structure 106 are isolated from each other by the first insulating medium layer 101 and the second insulating medium layer 103, and the stress between the first interconnection structure 105 and the second interconnection structure 106 is alleviated by the first insulating medium layer 101 and the second insulating medium layer 103, so as to improve the reliability of the semiconductor structure.

[0048] In some embodiments, the second interconnection structure 106 can be a TSV (Through Silicon Via), that is, the second interconnection structure 106 is in contact with the first conductive line 121 through the substrate 100. By arranging the second interconnection structure 106 to be in contact with the first conductive line 121 through the substrate 100, it is convenient to provide a signal to the second interconnection structure 106 from the other end of the substrate 100 away from the front layer structure 102, so as to facilitate the transmission of the signal to the first conductive line 121, or to facilitate the signal in the first conductive line 121 to be exported.

[0049] With reference back to FIG. 1, in some embodiments, the first conductive line 121 and the first conductive line 122 are covered on the top surface of the second insulating medium layer 103, and the first interconnection structure 105 is further connected with the front layer structure 102 through the first insulating medium layer 101.

[0050] With reference back to FIG. 2, in other embodiments, the first interconnection structure 105 and the second interconnection structure 106 are further connected with the first conductive line 121 and the first conductive line 122 respectively through the third insulating medium layer 124.

[0051] In some embodiments, as shown in FIG. 1, the first interconnection structure 105 is connected with the gate 112 of the front layer structure 102, so as to realize the connection between the first conductive line 122 and the front layer structure 102.

[0052] In some embodiments, as shown in FIG. 2, the front layer structure 102 further includes a connection end 114, such as a source and a drain, arranged in the substrate 100, and the first interconnection structure 105 is connected with the connection end 114, so as to realize the connection between the first conductive line 122 and the front layer structure 102.

[0053] In some embodiments, as shown in FIG. 1 and FIG. 2, the front layer structure 102 includes a plurality of, and the second interconnection structure 106 can be arranged in the first insulating medium layer 101 between two adjacent front layer structures 102.

[0054] Referring to FIG. 3, FIG. 3 is a structural diagram of a semiconductor structure according to an embodiment of the present disclosure. In some embodiments, the front layer structure further comprises a second conductive line 108 and a second conductive line 109 above the transistor 102, the second conductive line 108 and the second conductive line 109 are located in the first insulating medium layer 101 and are isolated from each other. The first interconnection structure 105 comprises a first interconnection part 1051 connecting the first conductive line 122 and the second conductive line 108, and a second interconnection part 1052 connecting the second conductive line 108 and the transistor 102, the first interconnection part 1051 is connected with the second conductive line 108 through the second insulating medium layer 103, and the second interconnection part 1052 is connected with the transistor 102 through the first insulating medium layer 101.

[0055] In some embodiments, the first interconnection part 1051 is further connected with the first conductive line 122 through the partial third insulating medium layer 124.

[0056] In some embodiments, the first interconnection part 1051 and the second interconnection part 1052 can comprise different metals, for example, the first interconnection part 1051 comprises copper or its alloy, and the second interconnection part 1052 comprises tungsten or its alloy.

[0057] In some embodiments, the first interconnection part 1051 can be an integral structure with the first conductive line 122, so as to reduce the contact resistance between the first interconnection part 1051 and the first conductive line 122, and improve the reliability of the connection between the first interconnection part 1051 and the first conductive line 122.

[0058] In some embodiments, the second interconnection part 1052 can be an integral structure with the second conductive line 108, so as to reduce the contact resistance between the second interconnection part 1052 and the second conductive line 108, and improve the reliability of the connection between the second interconnection part 1052 and the second conductive line 108.

[0059] In some embodiments, referring to FIG. 3, the semiconductor structure further comprises a third interconnection structure 110 connected with another second conductive line 109, and the third interconnection structure 110 is connected with the first conductive line 121, so as to realize the connection between the second conductive line 109 and the second interconnection structure 106.

[0060] In the embodiments of the present disclosure, by adding the second conductive line in the front layer structure, the layout of the semiconductor structure can be further compacted, the transmission channels between the conductive lines of each layer can be increased, and the signal transmission density can be improved.

[0061] In some embodiments, the third interconnection structure 110 has the same material as the first interconnection portion 1051, for example, both include copper or its alloy, or the third interconnection structure 110 and the first interconnection portion 1051 can include different materials, for example, the first interconnection portion 1051 includes copper or its alloy, and the third interconnection structure 110 includes tungsten or its alloy.

[0062] With continued reference to FIGS. 1-4, in some embodiments, the second interconnection structure 106 includes an insulating liner layer 1061 and a conductive interconnection layer 1062, the insulating liner layer 1061 is disposed between the first insulating medium layer 101 and the conductive interconnection layer 1062, and the insulating liner layer 1061 can isolate the conductive interconnection layer 1062 from the substrate 100, so as to avoid contamination of the first insulating medium layer 101 by the conductive interconnection layer 1062, and avoid contamination of the substrate 100 by the conductive interconnection layer 1062.

[0063] In some embodiments, the conductive interconnection layer 1062 is directly in contact with the second insulating medium layer 103.

[0064] In some embodiments, the insulating liner layer 1061 is also disposed between the substrate 100 and the conductive interconnection layer 1062, and the conductive interconnection layer 1062 also passes through part of the third insulating medium layer 124 to contact and connect with the first conductive line 121, and the conductive interconnection layer 1062 is directly in contact with the third insulating medium layer 124.

[0065] With continued reference to FIG. 4, FIG. 4 is a structural schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. In some embodiments, the ratio of the thickness D1 of the first interconnection structure 105 in the second insulating medium layer 103 to the thickness D2 of the first interconnection structure 105 in the third insulating medium layer 124 is 2:1-5:1. It can be understood that when the current layer structure includes the second conductive line 108 and the second conductive line 109, the second insulating medium layer 103 is disposed on each second conductive line, and thus the thickness of the second interconnection structure 106 formed is also greater, and thus isolation between the second interconnection structure 106 and the previous layer structure becomes particularly important. By setting the thickness of the second interconnection structure 106 in the second insulating medium layer 103 to be greater than the thickness of the second interconnection structure 106 in the third insulating medium layer 124, isolation between the second interconnection structure 106 and the previous layer structure is enhanced, but the greater the thickness of the second insulating medium layer 103, the more difficult it is to form the second interconnection structure 106 ultimately connected with the first conductive line 121, and thus by setting the ratio of the thickness of the second interconnection structure 106 in the second insulating medium layer 103 to the thickness of the second interconnection structure 106 in the third insulating medium layer 124 to be 2:1-5:1, the protection capability of the second insulating medium layer 103 can be obtained while the process difficulty of forming the second interconnection structure 106 is reduced.

[0066] The semiconductor structure manufacturing method provided by the embodiments of the present disclosure can be used to form the semiconductor structure as shown in FIGS. 1-4. The semiconductor structure manufacturing method provided by the embodiments of the present disclosure will be described below in combination with the accompanying drawings. It should be noted that the same or similar parts of the foregoing embodiments can refer to the corresponding description of the foregoing embodiments, which will not be described here.

[0067] Referring to FIGS. 5-18, FIG. 5 is a flowchart of a semiconductor structure manufacturing method provided by the embodiments of the present disclosure, and FIGS. 6-18 are schematic structural diagrams corresponding to each step of the semiconductor structure manufacturing method provided by the embodiments of the present disclosure.

[0068] Referring to FIG. 5, in some embodiments, the semiconductor structure manufacturing method includes: providing a substrate, the substrate being provided with a first insulating medium layer.

[0069] The semiconductor structure manufacturing method further includes: forming a front layer structure, the front layer structure being disposed in the first insulating medium layer.

[0070] The semiconductor structure manufacturing method further includes: forming a second insulating medium layer, the second insulating medium layer being disposed on the first insulating medium layer.

[0071] The semiconductor structure manufacturing method further includes: forming a third insulating medium layer, the third insulating medium layer being disposed on the second insulating medium layer.

[0072] The semiconductor structure manufacturing method further includes: forming a when layer structure, the when layer structure including a plurality of first conductive lines arranged at intervals from each other, each first conductive line being disposed in the third insulating medium layer.

[0073] The semiconductor structure manufacturing method further includes: forming a first interconnection structure, the first interconnection structure penetrating through the second insulating medium layer to connect part of the first conductive lines and the front layer structure.

[0074] The semiconductor structure manufacturing method further includes: forming a second interconnection structure, the second interconnection structure penetrating through the first insulating medium layer and the second insulating medium layer to connect the first conductive layer, the first interconnection structure and the second interconnection structure being isolated from each other.

[0075] The semiconductor structure manufacturing method provided by the embodiments of the present disclosure will be described below in combination with the accompanying drawings.

[0076] Referring to FIG. 6, a substrate 100 is provided, the substrate 100 being provided with a front layer structure 102. The front layer structure 102 can be a transistor, which includes a gate oxide layer 111 disposed on the substrate 100 and a gate electrode 112 disposed on the gate oxide layer 111. After the gate oxide layer 111 and the gate electrode 112 are formed, an isolation layer 113 is formed to isolate the gate oxide layer 111 and the gate electrode 112, the isolation layer 113 covering the side walls of the gate electrode 112 and the gate oxide layer 111.

[0077] After the formation of the front layer structure 102, a first insulating medium layer 101 is formed to cover the front layer structure 102. The process of forming the first insulating medium layer 101 can employ physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), epitaxy, and other thin film deposition processes. The first insulating medium layer 101 can be a single layer of thin film or a multi-layer thin film structure.

[0078] After the formation of the first insulating medium layer 101, a second insulating medium layer 103 is deposited on the first insulating medium layer 101. The process of forming the second insulating medium layer 103 can employ physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), epitaxy, and other thin film deposition processes.

[0079] After the formation of the second insulating medium layer 103, the first insulating medium layer 101 and the second insulating medium layer 103 are patterned to form a first interconnection structure 105 through the second insulating medium layer 103 and the first insulating medium layer 101. The patterning of the first insulating medium layer 101 and the second insulating medium layer 103 is performed using a photolithography process combined with an etching process. The process of etching the first insulating medium layer 101 and the second insulating medium layer 103 can be dry etching or wet etching.

[0080] After the formation of the first interconnection structure 105, a third insulating medium layer 124 is formed to cover the top of the first interconnection structure 105 and cover the second insulating medium layer 103. The process of forming the third insulating medium layer 124 can employ physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), epitaxy, and other thin film deposition processes.

[0081] Continuing to refer to FIG. 7, in some embodiments, after the formation of the third insulating medium layer 124, the third insulating medium layer 124 is patterned to form a first patterned region 144 and a second patterned region 154 in the third insulating medium layer 124.

[0082] Continuing to refer to FIG. 8, after the formation of the first patterned region 144 and the second patterned region 154, a first conductive line 121 and a first conductive line 122 are formed in the first patterned region 144 and the second patterned region 154, respectively, to complete the preparation of the layer structure 104.

[0083] The process of forming the first conductive line 121 and the first conductive line 122 can employ deposition or electroplating, etc. After the thin film formation process of deposition or electroplating is completed, a surface planarization process is performed, and finally the first conductive line is formed in the third insulating medium layer 124.

[0084] In some embodiments, the first interconnect structure 105 and the underlayer structure 104 can be formed in the same process step, as shown in FIG. 9. After the second insulating dielectric layer 103 is formed, a third insulating dielectric layer 124 is deposited on the second insulating dielectric layer 103. The process of forming the second insulating dielectric layer 103 and the third insulating dielectric layer 124 can be the same as described above and will not be repeated here.

[0085] Referring back to FIG. 10, after the third insulating dielectric layer 124 is formed, the third insulating dielectric layer 124, the second insulating dielectric layer 103 and the first insulating dielectric layer 101 are patterned to form a first patterned region 144' and a second patterned region 154'. In some embodiments, the first patterned region 144' and the second patterned region 154' can be formed in two steps, i.e., the first patterned region 144' or the second patterned region 154' is formed first, and then the second patterned region 154' or the first patterned region 144' is formed. That is, the first patterned region 144' is formed only in the third insulating dielectric layer 124, while the second patterned region 154' is formed in the third insulating dielectric layer 124, the second insulating dielectric layer 103 and the first insulating dielectric layer 101. The process of forming the second patterned region 154' can be a double damascene process.

[0086] Referring back to FIG. 11, after the first patterned region 144' and the second patterned region 154' are formed, a conductive material is deposited in the patterned regions to form a first conductive line 121 and the first interconnect structure 105 and the first conductive line 122 connected to the first interconnect structure 105. At this point, the first interconnect structure 105 and the first conductive line 122 comprise the same conductive material.

[0087] Referring back to FIG. 12, after the third insulating dielectric layer 124 and the underlayer structure 104 are formed, the substrate 100 and the first insulating dielectric layer 101 are etched from the substrate 100 towards the first insulating dielectric layer 101 to form an initial via 118, which exposes a surface of the second insulating dielectric layer 103 towards the first insulating dielectric layer 101.

[0088] Referring back to FIG. 13, after the initial via 118 is formed, a thin film deposition process is used to form an initial insulating liner layer 1061' on the surfaces of the substrate 100 and the first insulating dielectric layer 101, the second insulating dielectric layer 103 exposed by the initial via 118. The material of the initial insulating liner layer 1061' can be silicon dioxide.

[0089] Continuing to refer to FIG. 14, after forming the initial insulating liner layer 1061', the initial insulating liner layer 1061' on the surface of the second insulating medium layer 103 and on the side of the substrate 100 away from the first insulating medium layer 101 is etched away, leaving the initial insulating liner layer 1061' on the surface of the substrate 100 and the first insulating medium layer 101, forming the insulating liner layer 1061 covering the sidewall of the initial via 118.

[0090] Continuing to refer to FIG. 14, after forming the insulating liner layer 1061, the second insulating medium layer 103 is further etched to expose the surface of the first conductive line 121 in the third insulating medium layer 124 facing the second insulating medium layer 103, forming the second via 119 through the substrate 100, the first insulating medium layer 101 and the second insulating medium layer 103.

[0091] After forming the second via 119, a conductive interconnection layer 1062 is formed in the second via 119 using a thin film forming process such as deposition or electroplating, forming a second interconnection structure 106 connected to the first conductive line 121, and finally forming a semiconductor structure as shown in FIGS. 1-2.

[0092] In the above embodiment, by using the second insulating medium layer 103 as the etching stop layer for etching the first insulating medium layer 101, i.e., by selecting materials for the first insulating medium layer 101 and the second insulating medium layer 103 with a high etching selectivity, the first conductive line is prevented from being etched during the etching of the first insulating medium layer 101, and the metal ions in the first conductive line are prevented from diffusing into the first insulating medium layer 101 or even the substrate 100, thus preventing the first insulating medium layer 101 and the substrate 100 from being contaminated by metal ions. When the first conductive line is made of copper, the risk of such copper ion contamination is particularly important to control.

[0093] When the second insulating medium layer 103 is etched to form the second via 119 exposing the first conductive line, the surface of the first conductive line can also be slightly damaged by the etching process, and metal ions can be brought out. Since the insulating liner layer 1061 has already been formed on the exposed sidewall of the first insulating medium layer 101 and the substrate 100 at this time, the metal ions brought out will not diffuse into the first insulating medium layer 101 and the substrate 100, thus avoiding the risk of metal ion contamination.

[0094] In some embodiments, the front layer structure includes, in addition to the transistor 102, a plurality of second conductive lines 108 and second conductive lines 109 isolated from each other, as shown in FIG. 15. Each second conductive line is formed in the first insulating medium layer 101, and the second conductive line 108 is connected to the transistor 102 through a second interconnection portion 1052.

[0095] With continued reference to FIG. 16, after forming the second conductive lines, a second insulating dielectric layer 103 covering the second conductive lines and a third insulating dielectric layer 124 are formed on the first insulating dielectric layer 101, and then a third interconnect structure 110 interconnecting the second conductive lines and a first interconnect portion 1051 interconnecting the second conductive lines on the second interconnect portion 1052 are formed in the second insulating dielectric layer 103 and the third insulating dielectric layer 124. The first interconnect portion 1051 and the second interconnect portion 1052 form a first interconnect structure 105. When the layer structure 104 is also formed in the third insulating dielectric layer 124, the first conductive lines 121 in the layer structure 104 are connected with the third interconnect structure 110, and the first conductive lines 122 in the layer structure 104 are connected with the first interconnect portion 1051.

[0096] In some embodiments, the layer structure 104 and the third interconnect structure 110 and the first interconnect portion 1051 can be formed separately, i.e., the second insulating dielectric layer 103 is deposited first, the first interconnect portion 1051 and the third interconnect structure 110 are formed in the second insulating dielectric layer 103, and then the third insulating dielectric layer 124 is deposited, and the layer structure 104 is formed in the third insulating dielectric layer 124.

[0097] In some embodiments, the layer structure 104 and the third interconnect structure 110 and the first interconnect portion 1051 can be formed simultaneously, i.e., the second insulating dielectric layer 103 and the third insulating dielectric layer 124 are deposited first, and the first interconnect portion 1051, the third interconnect structure 110 and the first conductive lines respectively connected with the first interconnect portion 1051 and the third interconnect structure 110 are formed in the second insulating dielectric layer 103 and the third insulating dielectric layer 124 simultaneously.

[0098] In some embodiments, the third interconnect structure 110 and the first interconnect portion 1051 also interconnect the first conductive lines through part of the third insulating dielectric layer 124, and the first conductive lines and the third interconnect structure 110 and the first interconnect portion 1051 are formed by the same process as described above, which will not be repeated here.

[0099] With continued reference to FIG. 17, after forming the structure shown in FIG. 16, the substrate 100 and the first insulating dielectric layer 101 are etched from the substrate 100 towards the first insulating dielectric layer 101, forming an initial via 218 exposing a surface of the second insulating dielectric layer 103 towards the first insulating dielectric layer 101.

[0100] Continuing to refer to FIG. 18, after the initial via 218 is formed, an insulating liner layer 1061 is formed on the exposed surface of the substrate 100 and the surface of the first insulating dielectric layer 101, and the second insulating dielectric layer 103 is further etched to form a second via 219. The second via 219 exposes the surface of the first conductive line 121.

[0101] When the second insulating dielectric layer 103 is etched to form the second via 219, the surface of the first conductive line 121 can be slightly damaged due to the etching process, and metal ions can be brought out. Since the insulating liner layer 1061 has been formed on the exposed sidewall of the first insulating dielectric layer 101 and the substrate 100 at this time, the metal ions brought out will not diffuse into the first insulating dielectric layer 101 and the substrate 100, thereby avoiding the risk of metal ion contamination.

[0102] After the second via 219 is formed, a conductive interconnection structure 1062 is formed in the second via 219 by using a thin film formation process such as deposition or electroplating, thereby forming a second interconnection structure 106 connected to the first conductive line 121, and finally forming a semiconductor structure as shown in FIGS. 3-4.

[0103] In the embodiments of the present disclosure, by forming the second insulating dielectric layer 103 before forming the second interconnection structure 106, the second interconnection structure 106 can be prevented from contaminating the third insulating dielectric layer 124 in the overlying structure 104. In addition, by forming the first interconnection structure 105 in the second insulating dielectric layer 103, the first interconnection structure 105 and the second interconnection structure 106 are separated by the first insulating dielectric layer 101 and the second insulating dielectric layer 103, thereby relieving the stress between the first interconnection structure 105 and the second interconnection structure 106 through the first insulating dielectric layer 101 and the second insulating dielectric layer 103, and improving the reliability of the semiconductor structure.

[0104] In some embodiments, the material of the second insulating dielectric layer 103 can be different from the material of the first insulating dielectric layer 101, thereby facilitating the etching stop layer for etching the first insulating dielectric layer 101 in the process of forming the second interconnection structure 106, and avoiding the contamination of the second interconnection structure 106 to the third insulating dielectric layer 124 in the overlying structure 104.

[0105] It can be understood that in the process of forming the second interconnection structure 106, a heat treatment process is usually present, and in the heat treatment process, the second interconnection structure 106 will expand in volume, thus stress will be generated around the second interconnection structure 106, and the stress is most concentrated at the end of the second interconnection structure 106. By arranging the second insulating medium layer 103, the stress generated in the process of forming the second interconnection structure 106 can be relieved.

[0106] Since the heat treatment process is present in the process of forming the second interconnection structure 106, the second interconnection structure will expand in volume, and usually no other conductive structure is arranged around the second interconnection structure 106. By arranging the second insulating medium layer 103, the stress generated around the second interconnection structure 106 can be relieved, thus the spacing between the second interconnection structure 106 and the first interconnection structure 105 can be reduced, and the integration of the semiconductor structure can be improved.

[0107] It can be understood by those skilled in the art that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the embodiments of the present disclosure, and therefore the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, comprising: a substrate, a first insulating medium layer disposed on the substrate; a front layer structure disposed in the first insulating medium layer; a second insulating medium layer disposed on the first insulating medium layer; a third insulating medium layer disposed on the second insulating medium layer; a layer structure disposed in the third insulating medium layer, comprising a plurality of first conductive lines arranged at intervals from each other; a first interconnection structure connecting part of the first conductive lines and the front layer structure through the second insulating medium layer; a second interconnection structure connecting part of the first conductive lines, the first interconnection structure and the second interconnection structure through the first insulating medium layer and the second insulating medium layer, and isolated from each other.

2. The semiconductor structure of claim 1, wherein, The second interconnection structure further penetrates the substrate.

3. The semiconductor structure of claim 1, wherein, The first conductive lines cover a top surface of the second insulating medium layer, and the first interconnection structure further connects the front layer structure through the first insulating medium layer.

4. The semiconductor structure of claim 1, wherein, The first interconnection structure and the second interconnection structure further connect each of the first conductive lines through part of the third insulating medium layer, respectively.

5. The semiconductor structure of claim 1, wherein, The front layer structure comprises a transistor connected to the first interconnection structure.

6. The semiconductor structure of claim 5, wherein, The front layer structure further comprises a plurality of second conductive lines, each of which is disposed in the first insulating medium layer above the transistor, the first interconnection structure comprises a first interconnection part connecting part of the first conductive lines and part of the second conductive lines, and a second interconnection part connecting part of the second conductive lines and the transistor, the first interconnection part connects the second conductive lines through the second insulating medium layer, and the second interconnection part connects the transistor through the first insulating medium layer.

7. The semiconductor structure of claim 6, wherein, The semiconductor structure further comprises a third interconnection structure, part of the second conductive lines are connected to the first interconnection structure, and part of the second conductive lines are connected to the third interconnection structure, the second conductive lines connected to the third interconnection structure are connected to the first conductive lines connected to the second interconnection structure through the third interconnection structure.

8. The semiconductor structure of claim 1, wherein, The second interconnection structure comprises an insulating liner layer and a conductive interconnection layer, the insulating liner layer is between the first insulating medium layer and the conductive interconnection layer, and the conductive interconnection layer is in direct contact with the second insulating medium layer.

9. The semiconductor structure of claim 1, wherein, The first interconnection structure and the second interconnection structure comprise different metals.

10. The semiconductor structure of claim 4, wherein, The ratio of the thickness of the second interconnection structure in the second insulating medium layer to the thickness of the second interconnection structure in the third insulating medium layer is 2:1-5:

1.

11. The semiconductor structure of claim 1, wherein, The first insulating medium layer and the second insulating medium layer comprise different insulating materials. 12.A method for manufacturing a semiconductor structure, comprising: providing a substrate, a first insulating medium layer disposed on the substrate; forming a front layer structure disposed in the first insulating medium layer; forming a second insulating medium layer disposed on the first insulating medium layer; forming a third insulating medium layer disposed on the second insulating medium layer; forming a when layer structure disposed in the third insulating medium layer, the when layer structure comprising a plurality of first conductive lines arranged at intervals from each other; forming a first interconnection structure penetrating through the second insulating medium layer to connect part of the first conductive lines and the front layer structure; forming a second interconnection structure penetrating through the first insulating medium layer and the second insulating medium layer to connect part of the first conductive lines, the first interconnection structure and the second interconnection structure being isolated from each other.

13. The method of fabricating a semiconductor structure of claim 12, wherein, The method for forming the first interconnection structure comprises: after forming the second insulating medium layer and before forming the third insulating medium layer, etching at least the second insulating medium layer to form a first via abutting the front layer structure; filling the first via to form the first interconnection structure.

14. The method of fabricating a semiconductor structure of claim 13, wherein, The method for forming the when layer structure comprises: after forming the third insulating medium layer, patterning the third insulating medium layer to form a plurality of the first conductive lines in the third insulating medium layer, wherein part of the first conductive lines are connected with the first interconnection structure.

15. The method of fabricating a semiconductor structure of claim 12, wherein, The method for forming the second interconnection structure comprises: after forming the third insulating medium layer and the when layer structure, etching the substrate and the first insulating medium layer from the substrate towards the first insulating medium layer to form an initial via, the initial via exposing a surface of the second insulating medium layer; forming an insulating liner layer covering a sidewall of the initial via; etching at least the second insulating medium layer until a surface of part of the first conductive lines towards the substrate is exposed to form a second via exposing part of the first conductive lines; filling the second via to form a conductive interconnection layer, the conductive interconnection layer and the insulating liner layer forming the second interconnection structure.

Images