Method for generating parity check matrix, and communication apparatus

Abstract

A method for generating a parity check matrix, and a communication apparatus. The method comprises: acquiring a base matrix, the base matrix comprising a first matrix, the first matrix being a matrix consisting of the first column to the tenth column and the first row to the fourth row of the base matrix, elements comprised in the first column of the base matrix being all non-zero elements, and the first column being a punctured column; and, on the basis of the base matrix, obtaining a parity check matrix of a non-binary low-density parity check (LDPC) code, the parity check matrix being used for LDPC coding or LDPC decoding. The elements comprised in the first column of the base matrix are all non-zero elements, and the first column is a punctured column, such that the code rate of the LDPC code corresponding to the base matrix provided in the method can reach 2 / 3. Compared with the prior art, the method improves the code rate of non-binary LDPC codes, thereby improving coding and decoding performance of non-binary LDPC codes.

Description

Method for generating a parity check matrix and communication device

[0001] The present application claims priority to the Chinese patent application No. 202411354848.4, filed on September 26, 2024, and entitled "Method for generating a parity check matrix and communication device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of coding, and more particularly, to a method for generating a parity check matrix and a communication device. BACKGROUND

[0003] In the field of channel coding, low-density parity check (LDPC) code is one of the most mature and widely used channel coding schemes. Currently, researchers apply multi-element LDPC code in satellite communication and other fields, and how to improve the code rate of multi-element LDPC code suitable for wireless communication has become a research hotspot in the field. SUMMARY

[0004] Embodiments of the present application provide a method for generating a parity check matrix and a communication device to improve the code rate of multi-element LDPC code and enhance the coding and decoding performance of multi-element LDPC code.

[0005] In a first aspect, a method for generating a parity check matrix is provided. The communication device can be a communication device such as a network device or a terminal device, a component configured in the communication device such as a circuit or a chip (such as a modem chip, also known as a baseband chip, or a system on chip (SoC) chip or a system in package (SIP) chip containing a modem core, etc.) inside the communication device, a logic module or software capable of implementing part or all of the functions of the communication device, etc. The present application does not limit this.

[0006] The method comprises: acquiring a base matrix, wherein the base matrix comprises a first matrix, the first matrix is a matrix formed by the 1st column to the 10th column and the 1st row to the 4th row of the base matrix, the first matrix comprises a second matrix, the second matrix is a matrix formed by the 7th column to the 10th column and the 1st row to the 4th row in the first matrix, the column weight of the first column in the second matrix is 3, the column weight of the other columns in the second matrix except the first column is 2, all the elements included in the first column of the base matrix are non-zero elements, and the first column is a puncturing column; and obtaining a check matrix of a multi-element low-density parity-check (LDPC) code according to the base matrix, wherein the check matrix is used for LDPC encoding or LDPC decoding.

[0007] Further, the method can further comprise:

[0008] LDPC encoding or LDPC decoding is performed by using the check matrix.

[0009] It should be understood that the method for generating the check matrix provided in the present application can be applied in the process of encoding at the encoding side and / or the process of decoding at the decoding side.

[0010] It should be further understood that the values of the elements included in the base matrix can be 0 or 1, or the values of the non-zero elements in the base matrix can be different from each other, and the specific values of the non-zero elements can be from a value set corresponding to a multi-element Galois field.

[0011] It should be further understood that the first column in the base matrix is a puncturing column, that is, the first column in the base matrix needs to be punctured after encoding.

[0012] According to the method provided in the present application, the communication device can acquire the check matrix of the multi-element LDPC code according to the base matrix, and perform LDPC encoding or LDPC decoding. Since the size of the first matrix in the base matrix is 4 rows and 10 columns, and all the elements included in the first column in the base matrix are non-zero elements, and the first column is a puncturing column, the code rate of the LDPC code corresponding to the base matrix provided in the present application can reach (10-4) / (10-1)=2 / 3, which improves the code rate of the multi-element LDPC code compared with the prior art, and further improves the encoding and decoding performance of the multi-element LDPC code. In addition, the improvement of the code rate of the multi-element LDPC code can make the multi-element LDPC code more suitable for changing wireless channel environments.

[0013] In some possible implementation manners, the first sequence is {1, 0, 1, 0, 1, 0, 1, 1, 0, 0}, the second sequence is {1, 1, 0, 1, 0, 1, 0, 1, 1, 0}, the third sequence is {1, 0, 0, 1, 1, 0, 1, 0, 1, 1}, and the fourth sequence is {1, 1, 1, 0, 1, 1, 1, 0, 0, 1}.

[0014] It should be understood that the positions of 1 in the first sequence correspond to the positions of non-zero elements in the first row of the first matrix. The positions of 1 in the second sequence correspond to the positions of non-zero elements in the second row of the first matrix. The positions of 1 in the third sequence correspond to the positions of non-zero elements in the third row of the first matrix. The positions of 1 in the fourth sequence correspond to the positions of non-zero elements in the fourth row of the first matrix. The above sequences are merely to reflect the positions of non-zero elements in each of the first to fourth rows of the first matrix.

[0015] It should also be understood that, assuming that the elements in the base matrix take values of 0 and 1, the first matrix can be represented as:

[0016] In some possible implementation manners, the code rate R of the multi-element LDPC code satisfies:

[0017] wherein m = 6, 7, …, 26, 27.

[0018] It should be understood that the highest code rate R of the multi-element LDPC code can reach 2 / 3.

[0019] In some possible implementation manners, the code rate R of the multi-element LDPC code is 0.67.

[0020] In some possible implementation manners, the base matrix includes 25 rows and 31 columns, and the average column weight of the first matrix is 2.4.

[0021] The above is a limitation on the size of the base matrix and the average column weight of the first matrix.

[0022] In some possible implementation modes of the first aspect, the values of the non-zero elements in the i-th row of the base matrix are determined according to elements in a first set, the first set being a set included in an optimal element group of a Galois field GF(q), and the row weight of the i-th row being equal to the number of elements included in the first set, where q is a power of 2, and q is an integer greater than 2.

[0023] It should be understood that the value of q in the Galois field GF(q) can be predefined or preconfigured by a protocol / system, or the value of q can be indicated by indication information.

[0024] Based on the above technical solution, the values of the non-zero elements in each row of the base matrix can be equal to the number of elements included in a selected set from the set of optimal element groups of GF(q) and equal to the row weight of the row (for example, the first set), and the specific values of the non-zero elements in the row are determined based on the elements in the first set. For example, the values of the non-zero elements included in the i-th row of the base matrix can be one-to-one corresponding to the values of the elements in the first set, or the values of the non-zero elements included in the i-th row of the base matrix are obtained by mathematical operation on the values of the elements in the first set.

[0025] In some possible implementation modes of the first aspect, the values of the elements in the base matrix are 0 or 1, and the check matrix of the multi-element LDPC code is obtained according to the base matrix, including: selecting a second set corresponding to the i-th row from the sets included in the optimal element group of the Galois field GF(q) according to the row weight of the i-th row of the base matrix, the row weight of the i-th row being equal to the number of elements included in the second set, q being a power of 2, and q being an integer greater than 2; replacing the non-zero elements in the i-th row of the base matrix with elements related to the elements in the second set to obtain the i-th row of a third matrix; and obtaining the check matrix of the multi-element LDPC code according to the third matrix.

[0026] Based on the above technical solution, the values of the elements in the base matrix are 0 or 1, that is, the base matrix can be regarded as a base matrix of a binary field. When the check matrix of the multi-element LDPC code is obtained according to the base matrix, a third matrix is obtained based on the base matrix, and the check matrix of the multi-element LDPC code is obtained according to the third matrix. The non-zero elements in the i-th row of the third matrix are one-to-one corresponding to the elements 1 in the i-th row of the base matrix, and the specific values of the non-zero elements in the i-th row of the third matrix can be determined based on the row weight of the i-th row, the number of elements included in a selected set from the set of optimal element groups of GF(q) and equal to the row weight of the i-th row (for example, the second set), and the specific values of the non-zero elements in the i-th row of the third matrix are determined based on the elements in the second set.

[0027] In some possible implementation modes, the value of the non-zero element in the jth row of the base matrix is determined according to an element in a third set, the third set being a set corresponding to the row index according to a value mapping relationship of elements in a Galois field GF(q), and the row weight of the jth row is equal to the number of elements included in the third set, where q is a power of 2, and q is an integer greater than 2.

[0028] It should be understood that the value mapping relationship of the elements in the multiple GF(q) can be in the form of a chart, or text, or other forms. The mapping relationship can be predefined or preconfigured by the system / protocol.

[0029] Based on the above technical solution, the value of the non-zero element in each row of the base matrix can be determined from the set (for example, the third set) corresponding to the row index in the value mapping relationship of the elements in GF(q), and the specific value of the non-zero element in the row corresponding to the row index of the row is determined based on the elements in the third set. For example, the row index of the ith row in the base matrix is i, the set (for example, the third set) corresponding to the row index i is selected from the value mapping relationship of the elements in GF(q) according to the row index i, and the values of the non-zero elements included in the third set can be one-to-one corresponding to the values of the non-zero elements in the row i.

[0030] In some possible implementation modes, the value of the element in the base matrix is 0 or 1, and the check matrix of the multiple LDPC code is obtained according to the base matrix, including: selecting a fourth set corresponding to the row index of the jth row in the base matrix from a value mapping relationship of elements in a Galois field GF(q) according to the row index, the row weight of the jth row being equal to the number of elements included in the fourth set, q being a power of 2, and q being an integer greater than 2; replacing the non-zero elements in the jth row in the base matrix with the elements in the fourth set to obtain the jth row of a fourth matrix; and obtaining the check matrix of the multiple LDPC code according to the fourth matrix.

[0031] Based on the above technical solution, the value of the element in the base matrix is 0 or 1, that is, the base matrix can be regarded as a base matrix of a binary field. When the check matrix of the multiple LDPC code is obtained according to the base matrix, the fourth matrix needs to be obtained based on the base matrix, and the check matrix of the multiple LDPC code is obtained according to the fourth matrix. The non-zero element in the ith row of the fourth matrix is one-to-one corresponding to the element 1 in the ith row of the base matrix, and the specific value of the non-zero element in the ith row of the fourth matrix can be determined from the set (for example, the third set) corresponding to the row index i in the value mapping relationship of the elements in GF(q).

[0032] In some possible implementation modes, the method further includes:

[0033] receiving first indication information, the first indication information indicating a value of q corresponding to the multivariate Galois field GF(q).

[0034] It should be understood that the first indication information can be carried in wireless resource control signaling.

[0035] In combination with the first aspect, in some possible implementation manners, in a case where code rates of the multivariate LDPC codes are different, offset values corresponding to at least one nonzero element in the base matrix corresponding to the multivariate LDPC codes are different; and / or, in a case where extension factors of the multivariate LDPC codes are different, offset values corresponding to at least one nonzero element in the base matrix corresponding to the multivariate LDPC codes are different.

[0036] Based on the above technical solution, in the present application, the code rates and / or the extension factors of the multivariate LDPC codes are different, and offset values corresponding to at least one nonzero element in the base matrix are different. Compared with the existing solution in which the same offset value is used for the nonzero elements in the base matrix, the method can design the check matrix in the coding process of the LDPC code in a targeted manner, thereby obtaining higher coding and decoding performance of the LDPC code.

[0037] The second aspect provides a communication apparatus, which is configured to execute the method provided in any one of the above aspects or implementation manners. Specifically, the apparatus can include units and / or modules for executing the method provided in any one of the above aspects or implementation manners, such as a processing unit and / or a transceiving unit.

[0038] In an implementation manner, the apparatus is a sending-end device or a receiving-end device. When the apparatus is the sending-end device or the receiving-end device, the transceiving unit can be a transceiver, or an input / output interface, or a communication interface, or an interface unit; and the processing unit can be at least one processor. Optionally, the transceiver is a transceiving circuit. Optionally, the input / output interface is an input / output circuit.

[0039] In another implementation manner, the apparatus is a chip, a chip system or a circuit used in a sending-end device or a receiving-end device. When the apparatus is the chip, the chip system or the circuit used in the sending-end device or the receiving-end device, the transceiving unit can be an input / output interface, an interface circuit, an output circuit, an input circuit, a pin or a related circuit, etc. on the chip, the chip system or the circuit; and the processing unit can be at least one processor, a processing circuit or a logic circuit, etc.

[0040] The third aspect provides a communication apparatus, which includes at least one processor coupled with a memory, the memory being configured to store a program, and the processor being configured to run the computer program or instructions stored in the memory to execute the method provided in any one of the above aspects or implementation manners.

[0041] In an implementation form, the apparatus is a transmitting device or a receiving device.

[0042] In another implementation form, the apparatus is a chip, a chip system or a circuit for use in a transmitting device or a receiving device.

[0043] In a fourth aspect, a communication apparatus is provided, which comprises at least one processor and a communication interface, the at least one processor being configured to acquire a computer program or instructions stored in a memory via the communication interface, so as to execute the method provided in any one of the aspects or implementation forms thereof. The communication interface can be implemented by hardware or software.

[0044] In an implementation form, the apparatus further comprises the memory.

[0045] In a fifth aspect, a processor is provided, which is configured to execute the method provided in the aspects.

[0046] For the transmitting and acquiring / receiving operations involved in the processor, if no special description is made, or if it is not contrary to the actual role or inherent logic in the related description, it can be understood as the processor output and receive, input, etc. operations, and also can be understood as the transmitting and receiving operations performed by the radio frequency circuit and the antenna, which are not limited in the present application.

[0047] In a sixth aspect, a computer readable storage medium is provided, which stores a computer program or instructions, when the computer program or instructions are run on a computer, the computer is caused to execute the method provided in any one of the aspects or implementation forms thereof.

[0048] In a seventh aspect, a computer program product containing instructions is provided, when the computer program product is run on a computer, the computer is caused to execute the method provided in any one of the aspects or implementation forms thereof.

[0049] In an eighth aspect, a chip or chip system is provided, which comprises a processor, the processor is caused to execute the method provided in any one of the aspects or implementation forms thereof by running a computer program or instructions stored in a memory.

[0050] Optionally, the chip or chip system further comprises a communication interface, the processor can run the computer program or instructions in the memory via the communication interface. The communication interface can be implemented by hardware or software.

[0051] Optionally, as an implementation form, the chip further comprises a memory, the memory is configured to store the computer program or instructions.

[0052] When the method provided in the present application is executed by a chip, the present application does not limit the number of chips for implementing the method of the present application, for example, the method can be executed by one chip, or two or more chips. When the number of chips for implementing the method of the present application is two or more, the chip manufacturers are not limited, and can be the same manufacturer or different manufacturers.

[0053] In a ninth aspect, a communication system is provided, which includes at least one of the transmitter device or the receiver device described above.

[0054] In a tenth aspect, a computer program is provided, which, when running on a computer, causes the method provided in any one of the aspects or the implementation manners thereof to be executed. BRIEF DESCRIPTION OF DRAWINGS

[0055] FIG. 1 is a schematic diagram of a network architecture that can be applicable to the embodiments of the present application.

[0056] FIG. 2 is a schematic diagram of a communication scenario applicable to the embodiments of the present application.

[0057] FIG. 3 is a schematic diagram of a signal processing procedure of a physical layer applicable to the embodiments of the present application.

[0058] FIG. 4 is a schematic block diagram of an apparatus for implementing physical layer processing.

[0059] FIG. 5 is a schematic diagram of a check matrix H of an LDPC provided in the embodiments of the present application.

[0060] FIG. 6 is a Tanner graph of the check matrix H of the LDPC provided in the embodiments of the present application.

[0061] FIG. 7 is a schematic diagram of a structure of a check matrix provided in the embodiments of the present application.

[0062] FIG. 8 is a schematic diagram of two different dimensions of a Raptor-like structure provided in the embodiments of the present application.

[0063] FIG. 9 is a schematic diagram of a relationship between a base graph (BG) selection and a transport block size (TBS) and a rate provided in the embodiments of the present application.

[0064] FIG. 10 is a schematic flowchart of a method for generating a check matrix provided in the present application.

[0065] FIG. 11 is a schematic diagram of a base matrix provided in the embodiments of the present application.

[0066] FIG. 12 is a schematic diagram of a simulation comparison provided in the embodiments of the present application.

[0067] FIG. 13 is a schematic block diagram of a communication apparatus according to an embodiment of the present application.

[0068] FIG. 14 is another schematic block diagram of a communication apparatus according to an embodiment of the present application. DETAILED DESCRIPTION

[0069] In order to understand the embodiments of the present application, the following points are explained before the embodiments of the present application are introduced.

[0070] “For indicating” or “indicating” can include for directly indicating and for indirectly indicating, or in other words, “for indicating” or “indicating” can explicitly and / or implicitly indicate.

[0071] The first, second, etc. various numerical numbers are only for distinguishing, and do not limit the scope of the embodiments of the present application, for example, to distinguish different messages, different information, etc.

[0072] “Predefined” can be realized by pre-storing corresponding codes, tables or other ways that can be used to indicate related information in the device, and the specific implementation manner of the present application is not limited.

[0073] The “protocol” involved can refer to a standard protocol in the communication field, for example, can include a long term evolution (LTE) protocol, a new radio (NR) protocol and related protocols applied in future communication systems, and the present application does not limit this.

[0074] “Example”, “for example”, “exemplarily”, “as (another) example” and the like are used to mean as an example, illustration or description. Any embodiment or design scheme described as “example” in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes.

[0075] The terms “include”, “contain”, “have” and their variants mean “include but not limited to”, unless otherwise specifically emphasized.

[0076] "at least one" means one or more, "multiple" means two or more. "And / or" describes the association relationship of associated objects, which means that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple.

[0077] "when", "if", "in the case of" and "if" all mean that the network element will make corresponding processing under certain objective conditions, not limited to time, and also does not require the network element to have a judgment action when implemented. In addition, in this application, the description of the above-mentioned "when", "if", "in the case of" and "if" conditions can be understood as necessary conditions, and whether the condition is a sufficient condition or a sufficient and necessary condition is not limited. For example, "in the case of A, perform B" can be understood as "in the case of at least A, perform B".

[0078] In addition, the network architecture and business scenarios described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0079] The communication system to which the embodiments of the present application can be applied will be described below.

[0080] Embodiments of the present application can be applied to various communication systems, including but not limited to a 5th generation (5G) system or NR system, an LTE system, a long term evolution-advanced (LTE-A) system, an LTE frequency division duplex (FDD) system, an LTE time division duplex (TDD) system, and the like. It can also be applied to future communication systems. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), an internet of things (IoT) communication system, a narrow band-internet of things (NB-IoT) system, or other communication systems. In addition, it can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and 3rd generation partnership project (3GPP) related communication systems, without limitation.

[0081] A device in a communication system can send a signal to another device or receive a signal from another device. The signal can include information, signaling, or data, etc. The device can also be replaced by an entity, a network entity, a communication device, a communication module, a node, a communication node, etc. The device is taken as an example for description in the present application. For example, the communication system can include at least one terminal device and at least one network device. The network device can send a downlink signal to the terminal device, and / or the terminal device can send an uplink signal to the network device. It can be understood that the terminal device in the present application can be replaced by a first communication apparatus, and the network device can be replaced by a second communication apparatus, both of which perform the corresponding communication method in the present application.

[0082] The radio access network (RAN) device in the present application is a device with wireless transceiving function. The radio access network device can provide wireless communication function service and can access terminal devices to a wireless network. The radio access network can also be referred to as an access network device or a network device. The network device in the embodiments of the present application can refer to a radio access network (RAN) node (or device) applied to a cellular network (or mobile network) to access terminal devices to a wireless network, and can also be a zigbee base station, a bluetooth master (BT master), a bluetooth low energy (BLE) master, a long range radio (Lora) base station, and a wireless fidelity (Wi-Fi) access point.

[0083] The network device can be a base station. The base station can broadly cover various names in the following or be replaced with the following names, such as: Node B (Node B), evolved Node B (eNB), next generation Node B (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), primary station, secondary station, multi-mode wireless (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. The base station can be a macro base station, a micro base station, a relay node, a donor node, or the like, or a combination thereof. The base station can also refer to a communication module, modem, or chip for setting in the aforementioned device or apparatus. The base station can also be a mobile switching center and a device assuming a base station function in D2D, V2X, M2M communication, a device assuming a base station function in a future communication system, etc. The base station can support networks of the same or different access technologies. Alternatively, the RAN node can also be a server, a wearable device, a vehicle or a vehicle-mounted device, etc. For example, the access network device in vehicle to everything (V2X) technology can be a road side unit (RSU). Embodiments of the present application do not limit the specific technology and specific device form adopted by the network device. In some deployments, the network device mentioned in the embodiments of the present application can be a device including a CU, or a DU, or a device including a CU and a DU, or a control plane CU node (central unit-control plane (CU-CP)) and a user plane CU node (central unit-user plane (CU-UP)) and a DU node. For example, the network device can include gNB-CU-CP, gNB-CU-UP and gNB-DU.

[0084] In some deployments, wireless access is facilitated by a plurality of RAN nodes in cooperation to serve a terminal, different RAN nodes respectively implementing part of the functionalities of a base station. For example, a RAN node can be a CU, a DU, a CU-CP, a CU-UP, or a RU, etc. A CU and a DU can be separately arranged, or can also be included in the same network element, for example, in a BBU. A RU can be included in a radio frequency device or a radio frequency unit, for example, in a RRU, an AAU, or a RRH.

[0085] A RAN node can support one or more types of fronthaul interfaces, different fronthaul interfaces respectively corresponding to DUs and RUs having different functions. If the fronthaul interface between a DU and a RU is a common public radio interface (CPRI), the DU is configured to implement one or more of the baseband functions, and the RU is configured to implement one or more of the radio frequency functions. If the fronthaul interface between the DU and the RU is another interface, compared with the CPRI, part of the baseband functions of the downlink and / or the uplink, such as, for a downlink, one or more of precoding, digital beamforming (BF), or inverse fast Fourier transform (IFFT) / adding a cyclic prefix (CP), are implemented in the RU from the DU, and for an uplink, one or more of digital beamforming (BF), or fast Fourier transform (FFT) / removing the CP are implemented in the RU from the DU. In a possible implementation, the interface can be an enhanced common public radio interface (eCPRI). Under the eCPRI architecture, the splitting manner between the DU and the RU is different, corresponding to different categories (Cat) of eCPRI, such as eCPRI Cat A, B, C, D, E, F.

[0086] Taking eCPRI Cat A as an example, for downlink transmission, the DU is configured to implement layer mapping and one or more functions (i.e., one or more of encoding, rate matching, scrambling, modulation, and layer mapping) before layer mapping, and other functions (e.g., one or more of resource element (RE) mapping, digital BF, or IFFT / add CP) after layer mapping are implemented in the RU. For uplink transmission, the DU is configured to implement demapping and one or more functions (i.e., one or more of decoding, de-rate matching, de-scrambling, demodulation, inverse discrete Fourier transform (IDFT), channel equalization, and de-RE mapping) before demapping, and other functions (e.g., one or more of digital BF or FFT / CP removal) after demapping are implemented in the RU. It can be understood that the function descriptions of the DU and the RU corresponding to various types of eCPRI can refer to the eCPRI protocol, which will not be described here.

[0087] In a possible design, the processing unit in the BBU for implementing baseband functions is referred to as a base band high (BBH) unit, and the processing unit in the RRU / AAU / RRH for implementing baseband functions is referred to as a base band low (BBL) unit.

[0088] In different systems, the CU (or CU-CP and CU-UP), DU, or RU can also have different names, but those skilled in the art can understand their meanings. For example, in an open radio access network (open-RAN, O-RAN, or ORAN) system, the CU can also be referred to as an O-CU (open CU), the DU can also be referred to as an O-DU, the CU-CP can also be referred to as an O-CU-CP, the CU-UP can also be referred to as an O-CU-UP, and the RU can also be referred to as an O-RU. Any of the CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module. The network device in this application can be a virtualized device, for example, implemented by general hardware and instantiated virtualization functions, or special hardware and instantiated virtualization functions. The general hardware can be a server, for example, a cloud server.

[0089] In the embodiments of the present application, the apparatus for implementing the function of the network device can be the network device, or can be an apparatus capable of supporting the network device to implement the function, such as a chip system, a hardware circuit, a software module, or a hardware circuit plus a software module. The apparatus can be installed in the network device or used in matching with the network device. In the embodiments of the present application, only the apparatus for implementing the function of the network device is taken as an example for description, and the scheme of the embodiments of the present application is not limited in this way.

[0090] The terminal device in the present application can also be referred to as a user equipment (UE), an access terminal, a user unit, a user station, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent or a user apparatus.

[0091] The terminal device can be a device providing voice / data, for example, a handheld device with wireless connection function, a vehicle-mounted device, etc. At present, some examples of terminals are: mobile phone, tablet computer, notebook computer, palm computer, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, wireless terminal in self driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, cellular phone, cordless phone, session initiation protocol (SIP) phone, wireless local loop (WLL) station, personal digital assistant (PDA), handheld device with wireless communication function, computing device or other processing device connected to a wireless modem, wearable device, terminal device in a 5G network, or terminal device in a future evolved public land mobile network (PLMN), etc., device in a zigbee network, device in a Lora network, Bluetooth slave (BT slave), Bluetooth low energy (BLE) slave, Wi-Fi station (STA), etc. The present embodiment is not limited thereto.

[0092] The terminal device can also be a terminal device in an IoT system, also known as an IoT node. IoT is an important part of future information technology development, and its main technical feature is to connect objects through communication technology and network, so as to realize the intelligent network of man-machine interconnection and object-object interconnection. Connection can be through broadband technology or narrowband technology. IoT technology can achieve mass connection, deep coverage and terminal power saving through, for example, narrowband (NB) technology. IoT technology includes reflection communication technology, spread spectrum technology, ultra wide band (UWB), etc., which will not be described here.

[0093] In addition, the terminal device can further include a smart printer, a train detector, a gas station sensor, and the like, and the main functions include collecting data (part of the terminal device), receiving control information and downlink data of a network device, and transmitting electromagnetic waves to transmit uplink data to the network device.

[0094] By way of example and not limitation, in the embodiments of the present application, the terminal device can also be a wearable device. The wearable device can also be referred to as a wearable smart device, which is a general term for devices that are designed and developed by applying wearable technology to daily wear, such as glasses, gloves, watches, clothing, and shoes. The wearable device is a portable device that is directly worn on the body or integrated into the clothes or accessories of the user. The wearable device is not only a hardware device, but also a powerful function achieved through software support and data interaction and cloud interaction. The general wearable smart device includes a full function, a large size, and can realize complete or partial functions without relying on a smart phone, such as a smart watch or smart glasses, and focuses on a certain application function and needs to cooperate with other devices such as a smart phone, such as various smart bracelets and smart jewelry for monitoring vital signs.

[0095] In the embodiments of the present application, the device for implementing the function of the terminal device can be a terminal device, or a device capable of supporting the terminal device to implement the function, such as a chip system, which can be installed in the terminal device or used in matching with the terminal device. In the embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices. In the embodiments of the present application, only the device for implementing the function of the terminal device is taken as an example for description, and the scheme of the embodiments of the present application is not limited.

[0096] The terminal device in the present application can be a hardware device, a software function running on a special hardware, or a software function running on a general hardware, and can also be a virtualized device, such as a general hardware and an instantiated virtualization function, or a special hardware and an instantiated virtualization function. The general hardware can be a server, such as a cloud server.

[0097] The network device and / or the terminal device can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; can also be deployed on the water surface; and can also be deployed on an airplane, a balloon, and a satellite in the air. The present application does not limit the scenario where the network device and the terminal device are located.

[0098] Exemplarily, FIG. 1 shows a schematic diagram of a network architecture to which the embodiments of the present application can be applied.

[0099] FIG. 1 is a schematic diagram of an architecture of a communication system 10 to which embodiments of the present application are applied. FIG. 1 shows a schematic diagram of a possible, non-limiting architecture of the system. As shown in FIG. 1, the communication system 10 includes a radio access network (RAN) 100 and a core network 200. Optionally, the communication system 10 further includes an Internet 300. The RAN 100 can include at least one RAN node (e.g., 110a and 110b in FIG. 1) and at least one terminal device (e.g., 120a-120j in FIG. 1). The terminal devices can be connected to the RAN devices by wireless means. The terminal devices and the terminal devices, and the RAN devices and the RAN devices, can be connected to each other by wired or wireless means. The RAN nodes 110 are connected to the core network 200 by wireless or wired means. The core network devices in the core network 200 and the RAN nodes 110 in the RAN 100 can be different physical devices respectively, or can be the same physical device integrated with the logical functions of the core network and the logical functions of the RAN.

[0100] FIG. 1 is only a schematic diagram. Other network devices can be included in the communication system 10, such as wireless relay devices and wireless backhaul devices, which are not shown in FIG. 1.

[0101] The RAN 100 can be a 3rd generation partnership project (3GPP)-related cellular system, such as a 4G, 5G mobile communication system, or a future-oriented evolved system. The RAN 100 can also be an ORAN, a cloud radio access network (CRAN), or a zigbee network system, or a wireless fidelity (Wi-Fi) system. The RAN 100 can also be a communication system in which two or more of the above systems are fused.

[0102] The RAN nodes can be base stations deployed in the air, such as the satellite base station 110a, or base stations deployed indoors, such as the micro base station or indoor station 110b. It should be understood that the present application does not limit the specific technology and specific device form of the wireless access network device. For ease of description, a base station is described below as an example of a wireless access network device.

[0103] The terminal devices can be terminal devices deployed in the air, such as the helicopter or unmanned aerial vehicle 120i in FIG. 1, or terminal devices deployed on the ground, such as the mobile phone 120a, 120e, 120f, and 120j, the vehicle 120b, the computer 120g, the printer 120h, the gas station 120c, and the smart home device 120d in FIG. 1.

[0104] Optionally, the terminal device can also be configured to function as a RAN node. For example, a UE can be configured to function as a scheduling entity, which provides sidelink signals between terminal devices in vehicle-to-everything (V2X), device-to-device (D2D), or peer to peer, etc.

[0105] The RAN nodes and the terminal devices can be fixed in place or mobile. The RAN nodes and the terminal devices can be deployed on land, including indoors or outdoors, in hand or in vehicles; can be deployed on water; can also be deployed in the air, on airplanes, balloons and artificial satellites. Embodiments of the present application do not limit the application scenarios of the RAN nodes and the terminal devices.

[0106] The roles of the RAN nodes and the terminal devices can be relative, for example, the helicopter or the drone 120i in FIG. 1 can be configured as a RAN node, and for those terminal devices 120j that access to the RAN 100 through 120i, the terminal device 120i is a RAN node; but for the RAN node 110a, 120i is a terminal device, that is, 110a and 120i communicate through a wireless air interface protocol. Of course, 110a and 120i can also communicate through an interface protocol between RAN nodes, at this time, relative to 110a, 120i is also a RAN node. Therefore, the RAN nodes and the terminal devices can be collectively referred to as communication devices, and 110a, 110b and 120a-120j in FIG. 1 can be referred to as communication apparatuses with their respective functions, such as a communication device with a RAN node function or a communication device with a terminal function.

[0107] In embodiments of the present application, the functions of the RAN node can also be performed by a module (such as a chip) in the RAN node, or by a control subsystem containing RAN node functions. The control subsystem containing RAN node functions herein can be a control center in the application scenarios of the above terminal devices such as smart grid, industrial control, intelligent transportation, smart city, etc. The functions of the terminal device can also be performed by a module (such as a chip) in the terminal device, or by a device containing terminal device functions. The present application does not limit this.

[0108] FIG. 2 is a schematic diagram of several different communication scenarios applicable to the communication method provided by the embodiments of the present application. For example, point-to-point transmission between a RAN node and a terminal or between terminals (e.g., (a) in FIG. 2 is point-to-point transmission between a RAN node and a terminal), multi-hop transmission of a RAN node and a terminal (e.g., (b) in FIG. 2, (c) in FIG. 2), dual connectivity (DC) or multi-connectivity of multiple RAN nodes and a terminal (e.g., (d) in FIG. 2), and the like. It should be noted that the above specific communication application scenarios are only examples and do not limit the application. In particular, from the perspective of services, the embodiments of the present application are applicable to many service scenarios, such as data encoding scenarios in extended reality (XR) services, uplink large capacity scenarios, and the like. In addition, FIG. 2 does not limit the network architecture applicable to the present application, and the present application does not limit uplink, downlink, access link, backhaul link, sidelink (SL), and the like.

[0109] FIG. 3 is a schematic diagram of a signal processing process of a physical layer applicable to the embodiments of the present application. The signal processing of the physical layer can be divided into downlink processing and uplink processing.

[0110] The downlink processing is a process of transmitting information data from a higher layer after physical layer processing. Exemplarily, the downlink processing includes: performing channel coding (which can be referred to as coding for short), modulation, layer mapping, precoding, framing, IFFT, and intermediate radio frequency (IRF) processing on information data of layer 2 (L2) to generate an air interface signal to be transmitted.

[0111] More specifically, the transmitting end of the information data can split the information data from layer 2 into multiple transport blocks (TBs) according to the TB size (TBS) supported by the system, and add a cyclic redundancy check (CRC) code to each TB. If the size of the TB after adding the CRC code exceeds the maximum code block length, the TB can be segmented to obtain multiple code blocks (CBs). Each CB after segmentation can further add a CRC code to obtain a to-be-encoded input corresponding to each CB. The to-be-encoded input is a sequence of bits to be encoded, which can specifically include information bits and check bits (i.e., CRC codes) in the CB corresponding thereto. The transmitting end can perform channel coding, such as LDCP coding, on the to-be-encoded input to obtain a corresponding coded code block. Rate matching is performed on the coded code block, and the coded code block after rate matching is concatenated to form a codeword (CW). The transmitting end can scramble the codeword to generate scrambled bits. The scrambled bits are modulated to obtain modulation symbols. After resource element (RE) mapping of the modulation symbols, the modulation symbols are mapped to multiple REs, and thus values carried on each RE can be obtained. Based on the values carried on the REs, the transmitting end can generate a baseband signal. The baseband signal can be processed by IFR and the like, and then transmitted by an antenna.

[0112] The uplink processing is a process of performing physical layer processing on a signal received through an air interface. For example, the uplink processing includes: performing IFR processing on the received signal to obtain a baseband signal, and then performing FFT, de-framing, demodulation, decoding to complete physical layer signal processing, and delivering the obtained information data to layer 2.

[0113] More specifically, the receiving end of the signal performs IFR processing on the signal received from the antenna to obtain a baseband signal. Thereafter, the physical layer of the receiving end can sequentially perform RE demapping, demodulation, descrambling, rate de-matching, channel decoding and the like on the signal, so as to obtain a bit sequence before encoding, which can specifically include information bits and check bits.

[0114] Optionally, the receiving end can perform channel equalization after completing RE demapping and before demodulation. The channel equalization is based on a channel obtained through channel estimation, and removes the influence of the channel by using an equalization algorithm, so as to ensure correct demodulation of the signal.

[0115] Optionally, the transmitter can perform layer mapping and precoding before RE mapping after modulation. For example, the transmitter can map the modulation symbols to multiple layers, and perform precoding on the modulation symbols after layer mapping to obtain precoded signals. The precoded signals are mapped to multiple REs after RE mapping. Correspondingly, the receiver can perform channel equalization before demapping after performing demapping, and then perform demodulation; or the receiver can perform demapping after performing channel equalization, and then perform demodulation; or the receiver can perform demapping after performing frame demapping, and then perform channel equalization.

[0116] Since the specific implementation of each step in FIG. 3 can be implemented by existing technology, reference can be made to the relevant chapters in the 3rd generation partnership project (3GPP) technical specification (TS) 38.211, which is not described in detail here.

[0117] The apparatus for implementing the physical layer processing described above can be a communication device such as a network device or a terminal, or a mobile communication chip, which is not limited in the present application. Based on different functions, the apparatus can be divided into multiple units (or modules). For example, FIG. 4 is a schematic block diagram of an apparatus for implementing physical layer processing. FIG. 4(a) and (b) respectively show apparatuses 400A and 400B. The apparatus 400A can be used to implement uplink processing, and the apparatus 400B can be used to implement downlink processing.

[0118] As shown in FIG. 4(a) and (b), the apparatuses 400A and 400B respectively include a computing unit, a control unit and a storage unit. The computing unit can be responsible for processing the logical operation of the apparatus, which can specifically include the logical operation of encoding and / or decoding. The storage unit can be responsible for storing data in the computing process, and can also be used to store information related to coding and decoding, such as base graphs. The control unit can be responsible for scheduling and controlling the computing unit and storage resources.

[0119] For example, as shown in FIG. 4(a), the computing unit of the apparatus 400A can be used to perform TB CRC calculation, BG selection, code block segmentation, CB CRC calculation, LDPC encoding and code block concatenation, etc. The BG selection can be a selection from the BG stored in the storage unit.

[0120] For example, as shown in FIG. 4(b), the computing unit of the apparatus 400B can be used to perform de-rate matching, HARQ combining, LDPC decoding, CB CRC checking, TB CRC checking, etc.

[0121] In another possible implementation, the module for implementing LDPC encoding in the apparatus 400A is an encoder. In another possible implementation, the encoder can implement not only the LDPC encoding, but also the pre-processing and / or post-processing of the LDPC encoding. The pre-processing of the LDPC encoding includes one or more of the following, for example: TB CRC calculation, BG selection, code block segmentation, or CB CRC calculation. The post-processing of the LDPC encoding includes code block concatenation, for example. For example, the apparatus 400A is an encoder. Of course, the encoder can implement other functions in addition to the LDPC encoding and the pre-processing and post-processing thereof listed above, which are not limited in the present application.

[0122] In another possible implementation, the module for implementing LDPC decoding in the apparatus 400B is a decoder. In another possible implementation, the decoder can implement not only the LDPC decoding, but also the pre-processing and / or post-processing of the LDPC decoding. The pre-processing of the LDPC decoding includes one or more of the following, for example: de-rate matching or HARQ combining. The post-processing of the LDPC decoding includes one or more of the following, for example: CB CRC or TB CRC. For example, the apparatus 400B is a decoder. Of course, the decoder can implement other functions in addition to the LDPC decoding and the pre-processing and post-processing thereof listed above, which are not limited in the present application.

[0123] In order to facilitate the understanding of the embodiments of the present application, several concepts or terms related to the embodiments of the present application are briefly described. The concepts or terms described below are described based on the concepts or terms defined in the protocol, but it does not mean that the embodiments of the present application can only be applied to the existing system. The concepts or terms related to the embodiments of the present application can be applied to future systems. And the specific names of the concepts or terms (such as concepts or terms related to functional description) can be adjusted as the future system develops.

[0124] 1. LDPC code

[0125] The LDPC code is a kind of linear block code, and its check matrix is a kind of sparse matrix. The number of zero elements in the check matrix of the LDPC is much larger than the number of non-zero elements, or in other words, the row weight and column weight of the check matrix are very small numbers compared with the code length of the LDPC.

[0126] For an information bit sequence with a length of K and an LDPC code with a code length of N, the LDPC code can be uniquely determined by its check matrix. The dimension of the check matrix H is (N-K) * N, and the corresponding code word c can be defined by the check matrix H as follows: c = {c | Hc T = 0, c ∈ {0, 1} N}

[0127] In the check matrix H, each row corresponds to a check equation of the LDPC code, each check equation corresponds to a check node (CN), and the N-K check equations correspond to the N-K check nodes of the LDPC code; each column corresponds to a code element (or code bit) of the LDPC code, each code bit corresponds to a variable node, and the N code elements correspond to the N variable nodes of the LDPC code. A non-zero element h i,j represents the connection between the ith check node and the jth variable node. The number of non-zero elements in each row of the check matrix is the degree of the check node, and the number of non-zero elements in each column is the degree of the variable node. If the degrees of all check nodes are equal and the degrees of all variable nodes are equal, the LDPC code corresponding to the matrix is a regular code, otherwise it is an irregular code. A check matrix H of a regular LDPC code with a code length of 10 and a code rate of 1 / 2 is shown in FIG. 5, where v0, v1, …, v9 represent variable nodes, and c0, c1, …, c4 represent check nodes.

[0128] FIG. 5 is a schematic diagram of a check matrix H of an LDPC code. In FIG. 5, there are 10 variable nodes and 5 check nodes. If a code bit is included in the corresponding check equation, a line is used to connect the variable node and the check node involved, and a Tanner graph is obtained.

[0129] An LDPC code can be represented by a graph model, and common graph models include a Tanner graph, a factor graph, and a tree graph. The Tanner graph is more concise and intuitive. In 1981, Tanner represented the code word of an LDPC code in the form of a graph, which is now called a Tanner graph. The Tanner graph and the check matrix correspond to each other. The Tanner graph is composed of two types of vertices. One type of vertex represents a code bit and is called a variable node. The other type of vertex is a check node and represents a check constraint relationship. Each check node represents a check constraint relationship, which will be described below in conjunction with FIG. 6. In FIG. 6, the degree of a node can be defined as the number of edges connected thereto, which corresponds to the definition of the degree in the matrix description.

[0130] FIG. 6 is a Tanner graph of a check matrix H of an LDPC code.

[0131] As shown in FIG. 6, the Tanner graph represents the check matrix of the LDPC. For example, for a check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes, namely n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the check matrix H, and the m check nodes correspond to the m rows of the check matrix H. A cycle in the Tanner graph is formed by a group of vertices connected together, and the cycle starts and ends at the same vertex in the group, and passes through each node only once. The length of the cycle is defined as the number of edges it contains, and the girth of the graph can also be referred to as the size of the graph, which is defined as the minimum cycle length in the graph. As shown in FIG. 3, the girth is 4, as indicated by the black edges. The variable nodes in the Tanner graph correspond to each column of the check matrix H, i.e., each code bit of the LDPC. The check nodes in the Tanner graph correspond to each row of the check matrix H, i.e., each check bit of the LDPC. The connection between the two types of nodes corresponds to the values of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, it means that the value of the element (i, j) in the H matrix is 1, and if there is no connection, the corresponding element is 0. The connection between the variable nodes and the check nodes can also be referred to as an edge. The connection between the check nodes and the variable nodes can also be described as: the check nodes and the variable nodes have a connection or an edge. The edge relationship between the check nodes and the variable nodes can include the existence of an edge or the non-existence of an edge.

[0132] As described above, the LDPC is a linear block code, which divides the information sequence to be encoded into groups of q bits, and then performs linear operation on the q information bits by the encoder to obtain m check bits, and then combines the q information bits and the m check bits to obtain a code word of length n=q+m. The mapping relationship from the q-bit information bits to the n-bit code word is usually represented by a corresponding check matrix H. According to the check matrix H, the code word sequence can be generated accordingly to complete the encoding process. After the code word sequence is transmitted through the channel, the receiving end device decodes the received signal accordingly to determine the original information bits.

[0133] 2. Column weight and row weight

[0134] For a column of the matrix, the column weight can refer to the number of non-zero elements contained in the column. The column weight can also be referred to as column degree or column degree.

[0135] For a row of the matrix, the row weight can refer to the number of non-zero elements contained in the row. The row weight can also be referred to as row degree or row degree.

[0136] For example, as shown in FIG. 5, the column weight of the first column of the check matrix H is 2, and the row weight of the first row is 4.

[0137] 3. QC-LDPC code

[0138] A quasi-cyclic low density parity check (QC-LDPC) code is a kind of structured LDPC code. Due to the unique structure of its check matrix, the encoding can be implemented by using a simple feedback shift register, which reduces the encoding complexity of the LDPC code. In the case of a long code length, the check matrix H of the LDPC code will be very large, so H is usually expressed in a block form: the complete check matrix H is generated by a plurality of Z c ×Z c sub-matrices. Specifically, the complete check matrix H can be represented by a base matrix H b , each element in H b corresponds to a Z c ×Z c sub-matrix, and each sub-matrix can be represented by the number of cyclic shifts, so that the required storage space of the complete check matrix H is greatly reduced. The elements in the base matrix H b can also be referred to as quasi-cyclic (QC) blocks.

[0139] Based on the base matrix H b and the lifting size Z c , the base matrix H b can be expanded into a complete check matrix for encoding or decoding. Z c may also be referred to as an expansion factor, a lifting factor, an expansion value, an expansion coefficient, or a lifting size, etc.

[0140] Specifically, for a QC-LDPC code of (N, K), the number of check bits is M = N - K, and the check matrix H can be represented as:

[0141] wherein M = m b ×Z, N = n b ×Z, and P i,j represents a cyclic shift matrix of Z × Z dimension or a zero matrix of Z × Z dimension, and the cyclic shift matrix can be simplified by its corresponding cyclic shift coefficient V i,j . For example, the cyclic shift matrix is defined as a cyclic right shift matrix of a unit matrix, and each element "1" in the unit matrix can be cyclically shifted to the right based on the cyclic shift coefficient V i,j . Wherein, when V i,j = -1, P i,j is a zero matrix of Z × Z; when V i,j = 0, P i,jis the identity matrix of Z x Z, i.e., for each element "1" in the identity matrix, the cyclic right shift of 0 bits (or in other words, no shift) is obtained; V i,j ∈ [-1, Z max -1], P i,j is the matrix obtained by cyclic right shifting each element "1" in the identity matrix of Z x Z by V i,j bits, Z max is the maximum value of Z, Z≤Z max .

[0142] The process of converting an element Pij in the parity check matrix H into a cyclic shift matrix or an all-zero matrix can be represented by a conversion function g(V i,j , Z) as follows:

[0143] where % denotes the modulo operation; the value of V i,j may be predefined, for example, by a protocol, such as defined in Table 5.3.2-2 and Table 5.3.2-3 in the 3rd generation partnership project (3GPP) technical specification (TS) 38.212.

[0144] Taking Z = 4 and Z max = 8 as an example, the correspondence between the elements P i,j in the parity check matrix and the cyclic shift matrix or the all-zero matrix is as follows:

[0145] The element "-1" corresponds to the matrix , i.e., the all-zero matrix; the elements "0" to "7" correspond to the cyclic shift matrix, where the elements "0" and "4" correspond to the matrix , the elements "1" and "5" correspond to the matrix , the elements "2" and "6" correspond to the matrix , and the elements "3" and "7" correspond to the matrix

[0146] 4、Base graph (BG) and base matrix

[0147] In some implementations, the base graph can also be simply represented as a table indicating the row and column positions of the non-zero elements. In other implementations, the base graph can be identified by a base matrix.

[0148] The base graph can be represented as a base matrix with dimensions m b x n b . The base matrix can be used to construct the parity check matrix of a QC-LDPC code. The dimensions of the base matrix are m b x nb The dimension of the corresponding check matrix is (m b ×Z)×(n b ×Z). It can be seen that each element in the base matrix can be replaced by a matrix with a dimension of Z×Z to become a sub-matrix with a dimension of Z×Z in the check matrix.

[0149] It should be noted that the matrix with a dimension of Z×Z and the sub-matrix with a dimension of Z×Z are relative to different objects. For an independent element in the base matrix, it can be replaced by a matrix with a dimension of Z×Z, and the matrix with a dimension of Z×Z is only a part of the check matrix, so it is called a sub-matrix of the check matrix.

[0150] The base matrix can include zero elements and non-zero elements. The zero element in the base matrix can be replaced by a zero matrix with a dimension of Z×Z; the non-zero element in the base matrix can be replaced by a circulant check matrix P i,j , i and j represent the row and column positions of the non-zero element in the base matrix, P i,j Specifically, the circulant shift matrix replaced can be determined according to the conversion function g(V i,j , Z) above, which will not be repeated here.

[0151] In the base matrix, the zero element can be represented by 0, the non-zero element can be represented by 1, and the number of bits of the circulant shift can be determined according to the conversion function g(V i,j , Z) above; or, the zero element can be represented by -1, the non-zero element can be represented by 0, and the number of bits of the circulant shift can be determined according to the conversion function g(V i,j , Z) above; or, the zero element can be represented by -1, the non-zero element can be represented by a value greater than or equal to 0, and the number of bits of the circulant shift can be indicated by the value of the non-zero element. The present application does not limit this.

[0152] Currently, two base graphs, BG 1 and BG 2, are defined in the protocol of NR. The base matrix defined by BG 1 has a dimension of 46×68, the core matrix has a dimension of 4×26, and is mainly used in scenarios with high throughput requirements, high code rates, and long code lengths; the base matrix defined by BG 2 has a dimension of 42×52, the core matrix has a dimension of 4×14, and is mainly applied to scenarios with low throughput requirements, low code rates, and short code lengths.

[0153] FIG. 7 is a structural schematic diagram of a check matrix provided by an embodiment of the present application. The structure of the check matrix shown in FIG. 7 is a relatively common Raptor-like structure in the current 5G. As shown in FIG. 7, the check matrix of the Raptor-like LDPC structure includes the following five parts:

[0154] Part A: Information bits of the core array;

[0155] Part B: The parity bit portion of the core array, which has a double diagonal structure;

[0156] Part C: All-zero matrix;

[0157] Part D: The information bit portion of the extended array;

[0158] Part E: The parity bit portion of the extended matrix, which has a single diagonal structure.

[0159] It should be understood that the descriptions of the core matrix, all-zero matrix, and extended matrix mentioned above are all relative to their respective parts. In the parity check matrix, the core matrix can be called the core submatrix, the all-zero matrix can be called the all-zero submatrix (or simply, the all-zero submatrix), and the extended matrix can be called the extended submatrix.

[0160] The verification matrix includes the core matrix H core and extended array H ext Among them, the core array H core Including parts A and B in Figure 7 (shown by thick black lines), it is a high-bitrate parity-check matrix, which can be represented as [AB]. Its dimension is M. core ×N core M core ≤M, N core ≤N, and also satisfies: N core =M core +K. Based on the core array H core Scalable generation of extended matrix H ext This corresponds to parts D and E in Figure 7. Extended array H ext Each additional row adds one column to the parity check matrix H. It should be understood that the names of the various parts above are for ease of distinction only and should not constitute any limitation on this application. For example, part A can also be called the high-bitrate information column region, part B can also be called the high-bitrate core parity check region, and parts D and E can also be called incremental redundancy regions.

[0161] It should be noted that since the parity-check matrix can be generated based on the basis matrix, and each element in the basis matrix can be transformed into a Z×Z matrix, the dimension M of the core matrix is... core ×N core It can also correspond to a basis matrix with dimension (M) core / Z)×(N coreSince the C part in the check matrix is a full zero sub-matrix and the E part is a single diagonal sub-matrix, both of which have relatively regular structures, the A part, the B part and the D part can be mainly described when the check matrix or the base matrix is described. In the following, the C part and the E part will not be described in detail for the convenience of illustration and understanding, but those skilled in the art can understand that the other parts can be obtained according to the foregoing structure after the core matrix and the extension matrix are determined, and then the complete check matrix is obtained.

[0162] It should be further noted that in some other implementations, the core matrix can also include rows and / or columns in addition to the A part and the B part. For example, the number of rows of the core matrix is the number of rows of the matrix [A B] + 1, and the number of columns of the core matrix is the number of columns of the matrix [A B] + 1. The core matrix is defined exemplarily for the convenience of understanding the embodiments of the present application, and should not constitute any limitation on the present application. The present application does not limit the dimension of the core matrix. In the following, the core matrix is still understood as [A B] unless otherwise specified.

[0163] Exemplarily, FIG. 8 is a Raptor-like structure of two different dimensions provided by the embodiments of the present application. The 5G protocol defines two different BGs: BG 1 and BG 2, which are shown in (a) and (b) of FIG. 8, respectively. In the structure shown in (a) of FIG. 8, the size of BG 1 is 46x68, the size of the core matrix H core is 4x26, and it is mainly applied to a scenario with high throughput requirement, high code rate and long code length; in the structure shown in (b) of FIG. 8, the size of BG 2 is 42x52, the size of the core matrix H core is 4x14, and it is mainly applied to a scenario with low throughput requirement, low code rate and short code length.

[0164] In actual application, which BG is used to generate the check matrix and then used for LDPC encoding and decoding can be determined according to the transport block size (TBS) and the code rate (R). FIG. 9 shows an example of the relationship between BG selection and TBS and code rate. As shown in the figure, if A≤292; or A≤3824 and R≤0.67; or R≤0.25, BG 2 is selected; otherwise, BG 1 is selected. Wherein, the message block length A is the TBS excluding the CRC, R is the code rate indicated by the MCS index, which can be understood as the code rate that is expected to be achieved, and can be referred to as the target code rate, rather than the actual code rate.

[0165] Multi-element LDPC code (or referred to as non-binary LDPC code) is an extension of LDPC code, which is characterized in that the elements in the check matrix are no longer limited to the binary field GF(2), but are extended to the multi-element field GF(q), where q is a power of 2, that is, q=2^p, p is a positive integer. Assuming that LDPC codes are constructed in binary field GF(2) and multi-element field GF(q) respectively, the check matrices corresponding to the constructed LDPC codes can be represented as H2 and Hq respectively. Where H2 is composed of elements 0 and 1, and Hq is composed of elements 0, 1, 2,..., q-1. Each element in Hq is a combination of p elements in H2. Assuming that a value a in q=2p in the multi-element field GF(q) is associated with a 1*p binary vector, then by substituting this vector into Hq, the binary representation of Hq can be obtained. The main feature of multi-element LDPC code is that the elements in the check matrix are no longer limited to the binary field GF(2), but are extended to the multi-element field GF(q). This extension brings higher transmission efficiency and stronger error correction capability, and is particularly suitable for complex channel environments that require efficient transmission and multi-element modulation.

[0166] Multi-element LDPC codes have wide application prospects in wireless communication, optical fiber communication, satellite communication, data storage and other fields due to their excellent performance. In particular, in complex channel environments that require efficient transmission and multi-element modulation, multi-element LDPC codes can play a greater role. In addition, with the continuous development of communication technology, the research on multi-element LDPC codes is also deepening, and it is expected to be applied and popularized in more fields in the future.

[0167] In the existing multi-element LDPC code matrix scheme, the check matrix is independently optimized, and is not related to the binary matrix of the NR encoding and decoding standard. The base graph size of the core matrix of the multi-element LDPC code is a full 1 matrix of 2 rows and 4 columns, and it can be seen that the highest code rate supported by the LDPC code is only 0.5. If it is necessary to increase the code rate, it needs to be realized through puncturing, and increasing the code rate through puncturing may cause some loss in the performance of LDPC encoding and decoding.

[0168] In view of the problems existing in the prior art, the present application provides a check matrix generation method, which can optimize the encoding and decoding performance of multi-element LDPC codes by designing the positions of non-zero elements in the base matrix.

[0169] FIG. 10 is a schematic flowchart of a method for generating a check matrix according to an embodiment of the present application. The method shown in FIG. 10 can be performed by a communication device, which can be a communication apparatus such as a network device or a terminal device, a component configured in a communication apparatus such as a circuit or a chip (e.g., a modem chip, also known as a baseband chip, or a SoC chip or a SIP chip containing a modem core, etc.) inside the communication apparatus, a logic module or software capable of implementing part or all of the functions of the communication device, etc., without limitation.

[0170] It should be understood that the check matrix generated based on the method can be used for LDPC encoding or LDPC decoding. Therefore, the method shown in FIG. 10 can be applied to the encoding end, for example, can be performed by the apparatus 400A shown in FIG. 4; or can be applied to the decoding end, for example, can be performed by the apparatus 400B shown in FIG. 4.

[0171] The method 1000 for generating a check matrix shown in FIG. 10 can include steps 1010 to 1020. Each step in the method 1000 shown in FIG. 10 is described in detail below.

[0172] 1001, obtaining a base matrix.

[0173] It should be understood that the base matrix includes a first matrix, which is a matrix composed of the 1st to 4th rows and the 1st to 10th columns of the base matrix, i.e., the first matrix is a 4x10 matrix, and the first matrix is located in the upper left corner of the base matrix. The first matrix includes a second matrix, which is a 4x4 matrix with a column weight of 3 in the first column, and the column weight of the other columns in the second matrix is 2, and the second matrix is located in the 1st to 4th rows and the 7th to 10th columns of the first matrix, i.e., the second matrix is located on the right side of the first matrix.

[0174] In the base matrix, the elements included in the first column all take non-zero values, and the first column is a puncturing column.

[0175] Optionally, the average column weight of the first matrix is 2.4. Optionally, the average column weight is calculated based on the threshold value of the multivariate PRXIT commonly used in the design of the encoding matrix. For example, the number of non-zero elements included in each column of the first matrix is 2.4 on average.

[0176] It should be understood that the non-zero elements in the base matrix in the embodiments of the present application can be represented by 1, or can be represented by a value in a value set corresponding to other multivariate domains. Assuming that the value set of non-zero elements corresponding to the 8-ary field GF(8) is {1, 2, 3, 4, 5, 6, 7}, the specific values of the non-zero elements in the base matrix are from the set {1, 2, 3, 4, 5, 6, 7}.

[0177] In a possible implementation, the first row in the first matrix corresponds to a first sequence, which is a sequence obtained by replacing non-zero elements in the first row with 1, and the first sequence is {1, 0, 1, 0, 1, 0, 1, 1, 0, 0}; the second row in the first matrix corresponds to a second sequence, which is a sequence obtained by replacing non-zero elements in the second row with 1, and the second sequence is {1, 1, 0, 1, 0, 1, 0, 1, 1, 0}; the third row in the first matrix corresponds to a third sequence, which is a sequence obtained by replacing non-zero elements in the third row with 1, and the third sequence is {1, 0, 0, 1, 1, 0, 1, 0, 1, 1}; and the fourth row in the first matrix corresponds to a fourth sequence, which is a sequence obtained by replacing non-zero elements in the fourth row with 1, and the fourth sequence is {1, 0, 0, 1, 1, 0, 1, 0, 1, 1}.

[0178] It is assumed that non-zero elements in the base matrix are 1, and the first matrix in the base matrix can be represented as:

[0179] It is further assumed that values of non-zero elements in the base matrix are from a value set corresponding to a finite field. For example, the value set corresponding to GF(8) is {1, 2, 3, 4, 5, 6, 7}, and the first matrix in the base matrix can be represented as:

[0180] It should be understood that the above is merely an example of the first matrix, and the specific representation of the first matrix is not limited.

[0181] In another possible implementation, the size of the base matrix can be a 25-row and 31-column matrix. As shown in FIG. 11, FIG. 11 shows a matrix obtained by replacing all non-zero elements in the base matrix with 1. The base matrix includes 25 rows and 31 columns. Among them, the first column in the base matrix includes non-zero elements.

[0182] Optionally, the code rate R corresponding to the multi-element LDPC code determined based on the base matrix can satisfy: wherein m = 6, 7, …, 26, 27. It can be seen that when m = 6, the code rate R corresponding to the multi-element LDPC code can reach 2 / 3 (about 0.67).

[0183] It should be understood that the first column in the base matrix is a puncturing column, and accordingly, the code word corresponding to the first column in the base matrix needs to be punctured after the multi-element LDPC code is encoded. It can be seen that the base matrix designed by the method of the present application can enable the highest code rate of the multi-element LDPC code to be

[0184] 1002, obtaining a check matrix of a multi-element LDPC code according to a base matrix.

[0185] In a possible implementation, the value of the non-zero element in the i-th row of the base matrix obtained in step 1001 is determined based on elements in a first set, the first set being a set in an optimal tuple of GF(q), and the row weight of the i-th row being equal to the number of elements included in the first set. Wherein, the q is a power of 2, and the q is an integer greater than 2.

[0186] Wherein, the specific value of q in GF(q) can be predefined by a protocol, or preconfigured by a system, or indicated by indication information, which is not limited in the present application. Assuming that the specific value of q is indicated by indication information, the indication information can carry semi-static indication to the communication device in RRC signaling.

[0187] The optimal tuple of the multi-element domain will be briefly introduced below.

[0188] Wherein, the value of the multi-element domain can be represented in the form of a binary submatrix, and the optimal tuple is obtained for each row of the multi-element matrix including the combination of non-zero elements. The tuple can be replaced by a binary submatrix to obtain a matrix, which can be used as a binary linear block code. Wherein, the tuple with the largest minimum distance and the smallest number of minimum weight code words is selected as the optimal tuple. For details of the optimal tuple, please refer to the existing scheme, which will not be described here.

[0189] Taking GF(8) as an example, assuming that the primitive polynomial of GF(8) can be represented as: p(x) = x 3 + x + 1, and its binary submatrix can be represented as:

[0190] Wherein, the 7 values of the non-zero elements corresponding to GF(8) correspond to different powers of the above matrix A: {A k : k = 1, …, 7}.

[0191] Assuming that the optimal tuple set corresponding to GF(8) is shown in Table 1:

[0192] Table 1: Optimal tuple of GF(8)

[0193] It should be understood that the values in the above table 1 are in the form of powers of primitive elements, and if the values in the above table 1 are filled in the positions of the non-zero elements in the base matrix, the 1 operation needs to be performed on each value in the set, that is, the value of the 0th power of the primitive element is filled in the position corresponding to the non-zero element in the matrix. For example, taking the first row in the first matrix in the above base matrix as an example, assuming that the row weight of the first row in the first matrix is 5, a first set corresponding to a tuple size of 5 is selected from the above table 1 based on the row weight 5, the number of elements included in the first set corresponding to the tuple size of 5 is 5, and the tuple value {0, 1, 2, 4, 5} corresponding to the tuple size of 5 represents the power value of the primitive element. Then, by performing mathematical operations (such as adding 1) on each value in the tuple value {0, 1, 2, 4, 5}, the value of the non-zero element in the first row can be obtained. Wherein the first row can be represented as {1, 0, 2, 0, 6, 0, 3, 5, 0, 0} or {3, 0, 5, 0, 1, 0, 2, 6, 0, 0}, and the order of the values of the non-zero elements in the first row and the tuple value in the optimal tuple can be arbitrary, which is not limited in the present application.

[0194] It should also be understood that the values of the non-zero elements corresponding to the other rows in the base matrix are similar to the values of the non-zero elements in the first row in the above first matrix, and will not be described one by one.

[0195] It is also assumed that the optimal tuple set corresponding to the GF(8) is shown in table 2:

[0196] Table 2: Optimal tuple of GF(8)

[0197] It should be understood that the values in the above table 2 are tuple values of the 0th power of the primitive element, and the values in the table 2 can be directly filled in the positions of the non-zero elements in the base matrix. For example, taking the third row in the first matrix in the above base matrix as an example, assuming that the row weight of the third row in the first matrix is 6, a first set corresponding to a tuple size of 6 is selected from the above table 2 based on the row weight 6, the number of elements included in the first set corresponding to the tuple size of 6 is 6, and the tuple value {1, 2, 3, 4, 5, 6} corresponding to the tuple size of 6 is the tuple value of the 0th power of the primitive element. Then, by directly filling the values in the tuple value {1, 2, 3, 4, 5, 6} into the values of the non-zero elements in the third row. Wherein the third row can be represented as {1, 0, 0, 2, 3, 0, 4, 0, 5, 6} or {2, 0, 0, 3, 1, 0, 4, 0, 6, 5}, and the order of the values of the non-zero elements in the third row and the tuple value in the optimal tuple can be arbitrary, which is not limited in the present application.

[0198] It should also be understood that the values of the non-zero elements corresponding to other rows in the base matrix are similar to the values of the non-zero elements in the third row of the first matrix, and the present application will not be repeated.

[0199] It should also be understood that the above-mentioned replacement of the values of the non-zero elements in the corresponding row based on the values of the tuples in the optimal tuple set can be applied to the check matrix of the entire multi-dimensional LDCP code, or can only be applied to the first matrix in the base matrix.

[0200] Similar to the above-mentioned GF(8), the optimal tuple set corresponding to GF(4) can be represented as Table 3 and Table 4 as follows:

[0201] Table 3

[0202] It should be understood that the values in the above-mentioned Table 3 are the power form of the primitive elements corresponding to GF(4). Similar to the above-mentioned Table 1, when the values in this Table 3 are filled into the positions of the non-zero elements in the base matrix, each value in the set needs to be subjected to a +1 operation, that is, the value of the 0th power of the primitive element is filled into the position of the non-zero element in the matrix. Based on the row weight of each row in the base matrix, the tuple size equal to the row weight is selected from Table 3, the elements in the set corresponding to the tuple size equal to the row weight are subjected to mathematical operations (such as +1 for each value), and filled into the positions of the non-zero elements in the row corresponding to the row weight. The order of the elements included in the optimal tuple set is not limited to the order of the positions of the non-zero elements in the row.

[0203] Table 4

[0204] It should be understood that the values in the above-mentioned Table 4 are the tuple values of the 0th power of the primitive elements corresponding to GF(4). Similar to the above-mentioned Table 2, the values in this Table 4 can be directly filled into the positions of the non-zero elements in the base matrix. Based on the row weight of each row in the base matrix, the tuple size equal to the row weight is selected from Table 4, the elements in the set corresponding to the tuple size equal to the row weight are directly filled into the positions of the non-zero elements in the row corresponding to the row weight. The order of the elements included in the optimal tuple set is not limited to the order of the positions of the non-zero elements in the row.

[0205] It should also be understood that the above-mentioned replacement of the values of the non-zero elements in the corresponding row based on the values of the tuples in the optimal tuple set can be applied to the check matrix of the entire multi-dimensional LDCP code, or can only be applied to the first matrix in the base matrix.

[0206] In another possible implementation manner, in a case where the value of the non-zero element of the ith row in the base matrix obtained in step 1001 is 1, that is, the value of the element in the base matrix is 0 or 1. The communication device obtains the check matrix of the multi-element LDPC code according to the base matrix, comprising: the communication device obtains the check matrix of the multi-element LDPC code according to the third matrix, which is determined according to the base matrix. For example, the determination process of the third matrix can include the following steps 1 and step 2:

[0207] Step 1: according to the row weight of the ith row in the base matrix, a second set corresponding to the ith row is selected from the set including the optimal element group of GF(q), and the row weight of the ith row is equal to the number of elements included in the second set.

[0208] Suppose q = 8, the row weight of the ith row in the base matrix is 5, and the communication device selects a second set corresponding to the row weight 5 from the set including the optimal element group of GF(8) according to the row weight 5 of the ith row. The number of elements included in the second set is 5. In combination with the example of the optimal element group corresponding to GF(8) introduced in step 1001 above, the row with a row weight of 5 in the base matrix can be the first row, which can be represented as {1, 0, 1, 0, 1, 0, 1, 1, 0, 0}. According to the optimal element group of GF(8), the element value corresponding to the element group size 5 can be selected from Table 1 above, that is, the second set can be represented as {0, 1, 2, 4, 5}. According to the optimal element group of GF(8), the element value corresponding to the element group size 5 can be selected from Table 2 above, that is, the second set can be represented as {1, 2, 3, 5, 6}.

[0209] It should be understood that the ith row in the base matrix can be any row in the base matrix.

[0210] Step 2: replace the non-zero elements of the ith row in the base matrix with elements related to the elements in the second set to obtain the ith row of the third matrix.

[0211] As an example, with the example of the optimal element group corresponding to GF(8), the row with a row weight of 5 in the base matrix can be the first row, which can be represented as {1, 0, 1, 0, 1, 0, 1, 1, 0, 0}. According to the optimal element group of GF(8), the element value corresponding to the element group size 5 can be selected from Table 1 above, that is, the second set can be represented as {0, 1, 2, 4, 5}. The communication device adds 1 to each element in the second set respectively, replaces the 1 on the non-zero element in the first row, and obtains the first row of the third matrix. The first row of the third matrix can be represented as {1, 0, 2, 0, 3, 0, 5, 6, 0, 0} or {3, 0, 5, 0, 1, 0, 2, 6, 0, 0}, etc. The values of the elements in the second set correspond one by one to the values of the non-zero elements in the first row, and the corresponding order is not limited.

[0212] As another example, taking the example of the optimal tuple corresponding to GF(8), the row with row weight 5 in the base matrix can be the first row, which can be represented as {1, 0, 1, 0, 1, 0, 1, 1, 0, 0}, and the values of the tuple with a tuple size of 5 are selected from the above Table 1 according to the optimal tuple of GF(8), that is, the second set can be represented as {1, 2, 3, 5, 6}. The communication apparatus can directly replace each element in the second set with 1 on the non-zero element in the first row to obtain the first row of the third matrix, and the first row of the third matrix can be represented as {1, 0, 2, 0, 3, 0, 5, 6, 0, 0} or {3, 0, 5, 0, 1, 0, 2, 6, 0, 0}, and so on. The values of each element in the second set correspond one-to-one to the values of the non-zero elements in the first row, and the corresponding order is not limited.

[0213] Taking the first matrix in the base matrix as an example, the values of the elements included in the first matrix are 0 or 1, and the first matrix can be represented as:

[0214] Suppose q = 8, then according to the optimal tuple of GF(8), the new matrix corresponding to the first matrix can be represented as:

[0215] Similarly, the non-zero elements included in each row of the base matrix are replaced with elements related to the elements in the second set corresponding to the row to obtain a third matrix. That is, the positions of the non-zero elements in the third matrix are the same as the positions of the non-zero elements in the base matrix. The communication apparatus obtains the check matrix of the multi-element LDPC code according to the third matrix, and specifically, the communication apparatus can determine the check matrix of the multi-element LDPC code according to the extension factor and the offset value corresponding to each element.

[0216] In another possible implementation manner, the values of the non-zero elements of the jth row in the base matrix obtained in step 1001 are determined according to elements in a third set, the third set is a set corresponding to the row index according to the element value mapping relationship of the multi-element Galois field GF(q), and the row weight of the jth row is equal to the number of elements included in the third set, where q is a power of 2, and q is an integer greater than 2.

[0217] It should be understood that the element value mapping relationship of GF(q) can be predefined by a protocol or preconfigured by a system, which is not limited by the present application. In the following, taking GF(8) as an example, the element value mapping relationship table of GF(8) is exemplarily given in combination with Table 5:

[0218] Table 5

[0219] It should be understood that the element values of the optimal set of multi-element domains corresponding to different row indexes are shown in Table 5. Each element included in the set of multi-element values corresponds to the position of a non-zero element in the row corresponding to the row index.

[0220] It should be understood that the mapping relationship table shown in Table 5 can also be represented in other forms, such as text or a relationship diagram, and the like.

[0221] For example, the base matrix includes 25 rows and 31 columns, and the set of multi-element values corresponding to each of the 25 row indexes is shown in Table 5. The number of elements included in the set of multi-element values corresponding to each row index is equal to the row weight of the row corresponding to the row index. For example, the row weight of the first row of the base matrix (i.e., the first row of the first matrix) is 5, and the set of multi-element values corresponding to the row index 1 is {2, 1, 6, 4, 7}. The communication device directly fills the values in {2, 1, 6, 4, 7} into the values of the non-zero elements in the first row of the base matrix according to Table 5. The values of the non-zero elements in the first row and the order of the element values in the set of multi-element values can be arbitrary, and the present application does not limit the same.

[0222] In yet another possible implementation, the values of the non-zero elements in the jth row of the base matrix obtained in step 1001 are all 1, i.e., the values of the elements in the base matrix are 0 or 1. The communication device obtains the check matrix of the multi-element LDPC code according to the base matrix, including: the communication device obtains the check matrix of the multi-element LDPC code according to a fourth matrix, which is determined according to the base matrix.

[0223] For example, the determination process of the fourth matrix can include the following steps 3 and 4:

[0224] Step 3: According to the row index of the jth row in the base matrix, select a fourth set corresponding to the row index from the element value mapping relationship of GF(q), and the row weight of the jth row is equal to the number of elements included in the fourth set.

[0225] Assuming that q=8 and j=1, the row index of the first row in the base matrix is 1, and the communication apparatus selects the fourth set corresponding to the row index 1 from the element value mapping relationship of GF(8) according to the row index 1 of the first row, and the fourth set is {2, 1, 6, 4, 7}. In this case, based on the row weight of the first row of the base matrix corresponding to GF(8) described above, the number of elements included in the fourth set corresponding to the row index 1 is equal to 5. In combination with the example of the base matrix corresponding to GF(8) described in step 1001 above, the first row can be represented as {2, 0, 1, 0, 6, 0, 4, 7, 0, 0}, or {6, 0, 7, 0, 2, 0, 4, 1, 0, 0}, and the like. The present application does not limit the order of the values of the non-zero elements included in the ith row and the values of the elements in the fourth set.

[0226] It should be understood that the jth row in the base matrix can be any row in the base matrix, and the values of the non-zero elements included in the other rows in the base matrix are similar to those of the first row described above.

[0227] Step 4: Replace the non-zero elements in the jth row in the base matrix with the elements in the fourth set to obtain the jth row in the fourth matrix.

[0228] As an example, in combination with the element value mapping relationship table (Table 5) of GF(8) described above, the communication apparatus selects the fourth set corresponding to the row index of the jth row from Table 5 above according to the row index of the jth row in the base matrix and Table 5, and replaces the non-zero elements in the jth row in the base matrix with the elements included in the fourth set to obtain the jth row in the fourth matrix. In this case, each element included in the fourth set corresponds to a non-zero element in the jth row in a one-to-one manner, and the order of correspondence is not limited.

[0229] Taking the first matrix in the base matrix as an example, the element values included in the first matrix are 0 or 1, and the first matrix can be represented as:

[0230] Assuming that q=8, the new matrix corresponding to the first matrix can be represented as:

[0231] Similarly, replace the non-zero elements included in each row in the base matrix with the elements related to the elements in the fourth set corresponding to the row to obtain the fourth matrix. That is, the positions of the non-zero elements in the fourth matrix are the same as those of the non-zero elements in the base matrix. The communication apparatus obtains the check matrix of the multi-element LDPC code according to the fourth matrix. Specifically, the communication apparatus can determine the check matrix of the multi-element LDPC code according to the extension factor and the offset value corresponding to each element.

[0232] It should be understood that the communication device determines the check matrix of the multi-element LDPC code according to the fourth matrix, the expansion factor and the offset value, and the detailed description of the check matrix is similar to the existing scheme, which will not be described in detail here.

[0233] In the present application, in the case of different code rates of the multi-element LDPC code, the offset values corresponding to at least one non-zero element of the base matrix corresponding to the multi-element LDPC code are different; and / or in the case of different expansion factors of the multi-element LDPC code, the offset values of at least one non-zero element in the base matrix corresponding to the multi-element LDPC code are different.

[0234] In the following, taking the expansion factor Z=23 as an example, the value of the offset value corresponding to at least one non-zero element in the base matrix in the case of different code rates is exemplarily given.

[0235] Example 1: Assuming that the code rate of the multi-element LDPC code is 0.67, taking the first matrix in the base matrix as an example, the offset values corresponding to each element in the first matrix are shown in Table 6, wherein "-1" represents no value, i.e. the position corresponding to the element "-1" is a zero matrix.

[0236] Table 6

[0237] Example 2: Assuming that the code rate of the multi-element LDPC code is 0.5, taking the matrix composed of the first row to the seventh row and the first column to the thirteenth column in the base matrix as an example, the offset values corresponding to each element in the matrix are shown in Table 7, and the empty position in the matrix represents no value:

[0238] Table 7

[0239] Example 3: Assuming that the code rate of the multi-element LDPC code is 0.4, taking the matrix composed of the first row to the tenth row and the first column to the sixteenth column in the base matrix as an example, the offset values corresponding to each element in the matrix are shown in Table 8, and the empty position in the matrix represents no value:

[0240] Table 8

[0241] Example 4: Assuming that the code rate of the multi-element LDPC code is 0.33, taking the matrix composed of the first row to the thirteenth row and the first column to the nineteenth column in the base matrix as an example, the offset values corresponding to each element in the matrix are shown in Table 9, and the empty position in the matrix represents no value:

[0242] Table 9

[0243] Example Five: Assuming that the code rate of the multi-element LDPC code is 0.25, taking a matrix formed by the 1st to 19th rows and the 1st to 25th columns in the base matrix as an example, the offset values corresponding to the elements in the matrix are shown in Table 10, and the empty positions in the matrix represent no values:

[0244] Table 10

[0245] Example Six: Assuming that the code rate of the multi-element LDPC code is 0.2, taking a matrix formed by the 1st to 25th rows and the 1st to 31st columns in the base matrix as an example, the offset values corresponding to the elements in the matrix are shown in Table 11, and the empty positions in the matrix represent no values:

[0246] Table 11

[0247] Optionally, the method further includes step 1003: performing LDPC encoding or LDPC decoding based on the check matrix.

[0248] As described above, the check matrix can be used for LDPC encoding or LDPC decoding. If the communication device needs to send data, LDPC encoding can be performed based on the check matrix; if the communication device receives data, LDPC decoding can be performed based on the check matrix. The following will briefly describe the process with examples of LDPC encoding and LDPC decoding, respectively.

[0249] LDPC encoding:

[0250] If the communication device needs to send data, the data can be encoded and then sent. Exemplarily, the communication device can pre-process the data obtained from a higher layer to obtain information bits to be encoded, and perform LDPC encoding on the information bits to be encoded based on the check matrix.

[0251] As described above, the check matrix H satisfies:

[0252] wherein c represents information bits to be encoded, including K information bits, for example, denoted as c0, …, c K－1 ; w represents (N+D-K) check bits, for example, denoted as: c K , …, c N+D－K－1 .

[0253] The process of performing LDPC encoding based on the check matrix H is as follows: taking K information bits c0, …, c K－1 as input, since the check matrix H is known, (N+D-K) check bits c K , …, c N+D－K－1The output, i.e., (N+D) encoded bits: c0, …, c K－1 , c K , …, c N+D－K－1 .

[0254] The obtained encoded bits can be modulated, layer mapped, precoded, framed, IFFTed, IRFed, and the like, and then transmitted.

[0255] More detailed descriptions of the steps before and after encoding can be found in the foregoing descriptions in connection with FIG. 3, and will not be repeated here.

[0256] LDPC Decoding:

[0257] If the communication device receives data, the data can be decoded and sent to a higher layer. For example, the communication device can pre-process the signal received from the air interface, such as IRF, FFT, de-framing, de-layer mapping, channel equalization, demodulation, and the like, to obtain encoded bits to be decoded, and perform LDPC decoding on the encoded bits to be decoded based on the check matrix.

[0258] For example, the communication device can use the sum-product algorithm (SPA) and its simplified Min-Sum algorithm for decoding. For convenience of distinction and description, the log-likelihood ratio (LLR) of the (N+D) encoded bits obtained by demodulating the signal received by the communication device is denoted as: q0, …, q N+D-1 , which are also the initial values of the posterior information of each variable node. The SPA algorithm uses the connection relationship between the variable nodes and the check nodes of the check matrix H to iteratively update the posterior information q0, …, q N+D-1 , and finally determines the decision result of each variable node (i.e., the received encoded bits) according to the posterior information More detailed descriptions of the steps before and after decoding can be found in the foregoing descriptions in connection with FIG. 3, and will not be repeated here.

[0259] For convenience of understanding, the process of data transmission is described here by taking the data interaction between the communication device and another communication device as an example. For convenience of distinction and description, the communication device is denoted as communication device #1, and the other communication device with which it communicates is denoted as communication device #2.

[0260] The communication device #1 can preprocess the information data obtained from the higher layer to obtain a bit sequence to be encoded, perform LDPC encoding on the bit sequence to be encoded based on the check matrix, and transmit the obtained encoded bits after modulation, layer mapping, precoding, framing, IFFT, IRF, etc. The communication device #2 can perform IRF, FFT, framing, layer demapping, channel equalization, demodulation, etc. on the received signal to obtain the encoded bits to be decoded, and then transmit the encoded bits to be decoded to the higher layer after LDPC decoding. The check matrix used for LDPC encoding and the check matrix used for LDPC decoding can both be the check matrix obtained based on the above method, i.e., the check matrix obtained based on the first base matrix.

[0261] It can be understood that the communication device #1 and the communication device #2 in the above can be reversed, i.e., the communication device #2 transmits data and performs LDPC encoding, and the communication device #1 receives data and performs LDPC decoding. For the sake of brevity, no longer detailed.

[0262] It should be understood that the generation method of the check matrix shown in FIG. 10 increases the code rate range of the multivariate LDPC code obtained by the base matrix, and the code rate supported by the multivariate LDPC code can reach 0.67, which improves the encoding and decoding performance of the multivariate LDPC code.

[0263] In addition, the method provided in the present application designs the acquisition of the multivariate domain value corresponding to the non-zero elements in the base matrix. One is to select a tuple size equal to the row weight from the optimal tuple of GF(q) corresponding to each row of the base matrix, and select a numerical value corresponding to the position of the non-zero element in the row from the set corresponding to the tuple size. The other is to select a multivariate value set corresponding to the row index from the tuple value mapping relationship of GF(q) corresponding to each row of the base matrix, and select a numerical value corresponding to the position of the non-zero element in the row from the multivariate value set.

[0264] Based on the method provided in the present application, assuming that the information bit length K = 400 and the code rate R = 0.4, FIG. 12 shows a simulation comparison diagram. According to the simulation comparison diagram in FIG. 12, in the case of low signal-to-noise ratio, the method provided in the present application (the normalized new base graph in FIG. 12) is flat with the existing scheme #1 (the medium code rate new base graph in FIG. 12), and in the case of high signal-to-noise ratio, the method provided in the present application is obviously superior to the existing scheme. Among them, the existing scheme #1 can only adapt to each code rate interval of the medium code rate, while the base matrix provided in the present application can be compatible with each code rate below 0.67. Compared with the existing scheme #1, when the frame error rate is 10 -6When the frame error rate is 10 -6 When the frame error rate is 10

[0265] When the frame error rate is 10 -4 When the frame error rate is 10 -7 When the frame error rate is 10

[0266] Table 12

[0267] The above describes the method embodiments provided by the present application in detail in combination with FIG. 7 to FIG. 12. The device embodiments of the present application will be described in combination with FIG. 13 to FIG. 14.

[0268] It can be understood that, to implement the functions in the above embodiments, the devices in FIG. 13 to FIG. 14 include the hardware structure and / or software module for performing the respective functions. Those skilled in the art should easily realize that, in combination with the units and method steps of the examples described in the embodiments disclosed in the present application, the present application can be realized in the form of hardware or a combination of hardware and computer software.

[0269] As an example, FIG. 13 and FIG. 14 are schematic block diagrams of possible devices provided by the embodiments of the present application. These devices can be used to implement the functions of the communication device in the above method embodiments, and thus can also achieve the beneficial effects possessed by the above method embodiments.

[0270] FIG. 13 is a schematic block diagram of a communication device provided by the embodiments of the present application. The device 1300 shown in FIG. 13 can include a processing module 1310 and a communication module 1320.

[0271] In a possible design, the device 1300 can be used to implement the communication method implemented by the communication device in the embodiment shown in FIG. 10. For example, the processing module 1310 is configured to implement the obtaining and compiling code and other processing-related steps performed by the communication device in steps 1001 to 1003 in the method 1000, and the communication module 1320 can be used to implement the sending and / or receiving steps performed by the communication device in the method 1000.

[0272] For example, the processing module 1310 can be configured to: obtain a base matrix; obtain a parity check matrix of a multivariate LDPC code based on the base matrix; and perform LDPC encoding or LDPC decoding based on the parity check matrix.

[0273] The detailed description of the processing module 1310 and the communication module 1320 can be directly obtained by referring to the related description in the method embodiment shown in FIG. 10, and will not be repeated here.

[0274] It should be noted that the communication module can also be referred to as a transceiver module, a transceiver unit, a transceiver, a transceiver, or a transceiver device. The processing module can also be referred to as a processor, a processing board, a processing unit, or a processing device. Alternatively, the communication module is used to perform the sending operation and the receiving operation of the first communication device or the second communication device in the above method, and the device in the communication module for realizing the receiving function can be regarded as a receiving module, and the device in the communication module for realizing the sending function can be regarded as a sending module, that is, the communication module can include a receiving module and a sending module.

[0275] It should also be noted that in a possible design, the foregoing processing module and / or communication module can be implemented by a virtual module, for example, the processing module can be implemented by a software function unit or a virtual device, and the communication module can be implemented by a software function or a virtual device. In another possible design, the processing module or the communication module can also be implemented by an entity device, for example, if the device is implemented by a chip / chip circuit, the communication module can be an input / output circuit and / or a communication interface, and performs an input operation (corresponding to the foregoing receiving operation) and an output operation (corresponding to the foregoing sending operation); the processing module can be an integrated processor or a microprocessor or an integrated circuit.

[0276] The division of the modules in the embodiments of the present application is illustrative, and is only a logical function division. In actual implementation, another division manner can be used. In addition, each function module in each example in the embodiments of the present application can be integrated in one processor, or can be a separate physical existence, or two or more modules can be integrated in one module. The integrated module can be implemented in the form of hardware or in the form of a software function module.

[0277] FIG. 14 is a structural schematic diagram of a communication device provided by another embodiment of the present application. As shown in FIG. 14, the device 1400 includes processing circuitry 1410 and communication circuitry 1420. The processing circuitry 1410 and the communication circuitry 1420 are coupled to each other.

[0278] It can be understood that the processing circuitry 1410 can be one or more processors, or can be all or part of the processing function circuit in the one or more processors.

[0279] It can be understood that the communication circuitry 1420 can be a transceiver or an input / output interface.

[0280] Optionally, the apparatus 1400 further includes a memory 1430 for storing instructions executed by the processing circuit 1410 or storing input data required by the processing circuit 1410 to execute the instructions or storing data generated by the processing circuit 1410 after executing the instructions.

[0281] It can be understood that the memory 1430 can be located outside the processing circuit 1410, or located inside the processing circuit 1410.

[0282] As an example, the processing circuit 1410 is configured to implement the functions of the processing module 1310 described above, and the communication circuit 1420 is configured to implement the functions of the communication module 1320 described above.

[0283] As an example, the apparatus 1400 can be a communication device, or a chip applied to a communication device.

[0284] When the apparatus 1400 is a communication device, the communication circuit can be a transceiver; when the apparatus 1400 is a chip, the communication circuit can be an input / output circuit, a bus, a pin or other types of communication interfaces, wherein the input circuit in the input / output circuit can be used for receiving, and the output interface can be used for transmitting.

[0285] In some embodiments of the present application, a computer program product is also provided, which, when running on a processor, can implement the method of obtaining the check matrix implemented by the communication device in the method embodiments described above.

[0286] In some embodiments of the present application, a computer readable storage medium is also provided, which includes computer instructions, and the computer instructions, when running on a processor, can implement the method of obtaining the check matrix implemented by the communication device in the method embodiments described above.

[0287] In some embodiments of the present application, a communication system is also provided, which includes the communication device described above, and the communication device can be used to implement the method of obtaining the check matrix implemented by the communication device in the method embodiments described above.

[0288] It can be understood that the processor in the embodiments of the present application can be the following devices or all or part of the circuits for processing functions in the following devices: a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSPs), field programmable gate arrays (FPGAs) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor, or any conventional processor.

[0289] The term "unit", "module" and the like used in the specification can be used to represent a computer-related entity, hardware, firmware, a combination of hardware and software, software, or software in execution.

[0290] Those skilled in the art can realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0291] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0292] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0293] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0294] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0295] In the above embodiments, the functions of the various functional units can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, the software can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, the whole or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be magnetic media (such as floppy disk, hard disk, magnetic tape), optical media (such as digital video disc (DVD)), or semiconductor media (such as solid state disk (SSD)) and the like.

[0296] The functions, if implemented in the form of software functional units and sold or used as independent products, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part of the prior art or the part of the technical solutions of the present application can be embodied in the form of software product, which is stored in a storage medium and includes a plurality of instructions for making a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in the embodiments of the present application. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and various media that can store program codes.

[0297] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of generating a check matrix, characterized by, The method comprises: obtaining a base matrix, the base matrix comprising a first matrix, the first matrix being a matrix composed of the 1st to 10th columns and the 1st to 4th rows of the base matrix, the first matrix comprising a second matrix, the second matrix being a matrix composed of the 7th to 10th columns and the 1st to 4th rows in the first matrix, the column weight of the first column in the second matrix being 3, the column weight of the other columns in the second matrix except the first column being 2, the elements in the first column of the base matrix all being non-zero elements, and the first column being a punctured column; obtaining a check matrix of a multi-element low-density parity-check (LDPC) code according to the base matrix, the check matrix being used for LDPC encoding or LDPC decoding.

2. The method of claim 1, wherein: the first row of the first matrix corresponds to a first sequence, the first sequence being {1, 0, 1, 0, 1, 0, 1, 1, 0, 0}, and the first sequence being a sequence corresponding to the non-zero elements in the first row being replaced by 1; the second row of the first matrix corresponds to a second sequence, the second sequence being {1, 1, 0, 1, 0, 1, 0, 1, 1, 0}, and the second sequence being a sequence corresponding to the non-zero elements in the second row being replaced by 1; the third row of the first matrix corresponds to a third sequence, the third sequence being {1, 0, 0, 1, 1, 0, 1, 0, 1, 1}, and the third sequence being a sequence corresponding to the non-zero elements in the third row being replaced by 1; the fourth row of the first matrix corresponds to a fourth sequence, the fourth sequence being {1, 1, 1, 0, 1, 1, 1, 0, 0, 1}, and the fourth sequence being a sequence corresponding to the non-zero elements in the fourth row being replaced by 1.

3. The method according to claim 1 or 2, characterized in that, The code rate R of the multi-dimensional LDPC code satisfies: wherein m = 6, 7, …, 26, 27.

4. The method according to any one of claims 1 to 3, characterized in that, The code rate R of the multi-element LDPC code is 0.

67.

5. The method according to any one of claims 1 to 4, characterized in that, The base matrix comprises 25 rows and 31 columns, and the average column weight of the first matrix is 2.

4.

6. The method of any one of claims 1 to 5, wherein: the values of the non-zero elements in the i-th row of the base matrix are determined according to elements in a first set, the first set being a set included in an optimal element group of a multi-element Galois field GF(q), and the row weight of the i-th row being equal to the number of elements included in the first set, wherein q is a power of 2, and q is an integer greater than 2.

7. The method according to any one of claims 1 to 5, characterized in that, the values of the elements in the base matrix are 0 or 1, obtaining a check matrix of the multi-element LDPC code according to the base matrix, comprising: selecting a second set corresponding to the i-th row from a set included in an optimal element group of a multi-element Galois field GF(q) according to the row weight of the i-th row, the row weight of the i-th row being equal to the number of elements included in the second set, q being a power of 2, and q being an integer greater than 2; replacing the non-zero elements in the i-th row of the base matrix with elements related to the elements in the second set to obtain the i-th row of a third matrix; and obtaining a check matrix of the multi-element LDPC code according to the third matrix.

8. The method of any one of claims 1 to 5, wherein: A value of a non-zero element in a jth row of the base matrix is determined according to an element in a third set, the third set is selected from a set corresponding to a row index according to a mapping relationship of values of elements in a Galois field GF(q), and a row weight of the jth row is equal to a number of elements included in the third set, where q is a power of 2, and q is an integer greater than 2.

9. The method according to any one of claims 1 to 5, characterized in that, A value of an element in the base matrix is 0 or 1, According to the base matrix, a check matrix of the multi-element LDPC code is obtained, including: According to a row index of a jth row in the base matrix, a fourth set corresponding to the row index is selected from a mapping relationship of values of elements in a Galois field GF(q), a row weight of the jth row is equal to a number of elements included in the fourth set, q is a power of 2, and q is an integer greater than 2; Non-zero elements in the jth row in the base matrix are replaced by elements in the fourth set to obtain a jth row of a fourth matrix; According to the fourth matrix, a check matrix of the multi-element LDPC code is obtained.

10. The method of claim 6 or 7, wherein, The method further includes: Receiving first indication information, the first indication information indicating a value of q corresponding to the Galois field GF(q).

11. The method of any one of claims 1 to 10, wherein, In a case where code rates of the multi-element LDPC codes are different, offset values corresponding to at least one non-zero element in the base matrix corresponding to the multi-element LDPC codes are different; and / or In a case where extension factors of the multi-element LDPC codes are different, offset values corresponding to at least one non-zero element in the base matrix corresponding to the multi-element LDPC codes are different.

12. A communications device, characterized by The apparatus includes functional modules for implementing the method of any one of claims 1 to 11.

13. A communications device, characterized by The apparatus includes: One or more processors and a communication circuit, the communication circuit being used for at least one of input or output of signals by the communication device; and the one or more processors being used to implement the method of any one of claims 1 to 11.

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