Memory management method and apparatus, computer device, and storage medium
By generating a state information matrix and an index table array, the problem of low efficiency in memory management is solved, enabling fast memory allocation and reclamation, reducing memory fragmentation, and improving system performance and maintainability.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-09-19
- Publication Date
- 2026-04-02
AI Technical Summary
Existing memory management methods are inefficient in memory allocation and deallocation, have high time overhead, and are limited to memory merging operations where the address of the first memory block is a multiple of 2.
By generating a state information matrix and an index table array, including an inline index table array and a cross-row index table array, unused memory blocks of appropriate size can be quickly located, reducing memory fragmentation and improving memory utilization and system performance.
It achieves fast memory allocation and reclamation, reduces memory fragmentation, improves system response speed and overall performance, and enhances the logical clarity and maintainability of memory management.
Smart Images
Figure CN2025122458_02042026_PF_FP_ABST
Abstract
Description
Memory management method and device, computer device and storage medium
[0001] Cross-reference to Related Applications
[0002] The present application claims priority to the Chinese patent application No. 202411335451.0, filed on September 24, 2024, and entitled "Memory management method and device, computer device and storage medium", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD
[0003] The present application relates to the technical field of memory management, in particular to a memory management method and device, a computer device and a storage medium. BACKGROUND
[0004] The types of computer services are increasing day by day, and the required memory size for running various services is also different. With the increase of the number of memory application and release operations, the memory area is continuously fragmented, resulting in a situation that there is a lot of idle memory but cannot allocate a continuous memory.
[0005] At present, the memory management is usually performed by using a memory buddy algorithm to avoid the above memory fragmentation as much as possible. The algorithm divides all free memory blocks into multiple block linked lists, each linked list contains a continuous memory block of a specific size, thereby achieving fine management of the memory. Specifically, when applying for memory, the memory buddy algorithm allocates the free page in the memory block linked list with the same size as the application size and deletes it from the linked list. If there is no memory block of the same size, the next level is checked, and the remaining part that is not allocated is added to the next level free linked list. Memory release is the reverse process of application.
[0006] However, the above memory management method has a large time overhead in the process of memory application and release, and the iteration splitting / merging operation and traversal of the linked list will affect the efficiency and performance of memory application / release. In addition, the memory merging operation of the above method has the limitation that the first memory block address must be an integer multiple of 2. SUMMARY
[0007] Therefore, the present application provides a memory management method and device, a computer device and a storage medium to solve the problem of low efficiency of the current memory management method based on the buddy algorithm.
[0008] In a first aspect, the present application provides a memory management method, which comprises:
[0009] According to the usage state of each atomic memory block in the physical memory information, a state information matrix is generated; each element in the state information matrix is used to indicate whether each atomic memory block is used or not;
[0010] An index table array is generated based on the state information matrix; the index table array includes an intra-row index table array and a cross-row index table array; the index table array is used to indicate the usage of memory blocks of different specifications; the memory blocks of different specifications are used to indicate continuous unused atomic memory blocks of different lengths in the state information matrix;
[0011] Based on the index table array, a target memory block corresponding to the memory application request is determined;
[0012] Based on the target memory block, the state information matrix and the index table array are updated.
[0013] The memory management method provided by the embodiments of the present application forms a state information matrix corresponding to the usage state of each atomic memory block, and generates an index table array based on the information state matrix; the design of the index table array enables the continuous unused memory block to be quickly found and allocated, reduces memory fragmentation, and thus improves the overall memory utilization; that is, through the index table, the system can quickly locate the memory block of a suitable specification without traversing the entire memory space, which greatly shortens the memory allocation and recycling time and improves the system performance.
[0014] In an optional implementation, generating the index table array based on the state information matrix includes:
[0015] Generating the intra-row index table array and the cross-row index table array based on the state information matrix; the number of columns of the intra-row index table array and the cross-row index table array is equal to the number of memory block specifications, the number of rows of the intra-row index table array is equal to the number of rows of the state information matrix, and the number of rows of the cross-row index table array is less than the number of rows of the intra-row index table array by 1.
[0016] The memory management method provided by the embodiments of the present application can quickly locate the memory block of a suitable specification by converting the state information matrix into the index table array including the intra-row index table array and the cross-row index table array; the index table array not only records the usage of the memory block, but also classifies the memory block according to the specification, thereby reducing the time for searching the unused memory block in the entire state information matrix. This index mode accelerates the memory allocation process and improves the response speed and overall performance of the system. At the same time, the complex memory state information is simplified into the structured index table array, which makes the logic of memory management clearer and easier to maintain.
[0017] In an optional implementation, determining the target memory block corresponding to the memory application request based on the index table array includes:
[0018] determining a target region in the state information matrix in the index table array based on the memory application request;
[0019] selecting a target memory block corresponding to the memory application request in the target region.
[0020] The memory management method provided by the embodiments of the present application can quickly locate a region in the state information matrix that may contain a continuous unused memory block, i.e., a target memory block, satisfying the request size, by setting the intra-row index table array and the cross-row index table array. This fast positioning mechanism avoids purposeless or linear search in the entire physical memory space, thereby significantly improving the efficiency of memory allocation.
[0021] In an optional embodiment, the determining of the target region in the state information matrix in the index table array based on the memory application request comprises:
[0022] If there is a free state memory block with the same size as the memory application request in the index table array, a region in the state information matrix corresponding to the free state memory block is confirmed as the target region.
[0023] If there is no free state memory block with the same size as the memory application request in the index table array, a region in the state information matrix corresponding to a free state memory block with the smallest size greater than the memory application request is confirmed as the target region.
[0024] The memory management method provided by the embodiments of the present application can maximize the satisfaction of the memory request demand and reduce the generation of memory fragmentation by first checking whether there is a free memory block with the same size as the memory application request in the index table array, and if there is, directly determining the target region for the allocation of the memory block. If there is no completely matched memory block, a memory block with the smallest size greater than the request size is selected to determine the target region, which ensures the effective use of memory and avoids unnecessary memory waste.
[0025] In an optional embodiment, the selecting of the target memory block corresponding to the memory application request in the target region comprises:
[0026] The target memory block corresponding to the memory application request with the smallest address in the target region is selected.
[0027] The memory management method provided by the embodiments of the present application selects the memory block with the smallest address for allocation, which helps to maintain the continuity of the memory space, and at the same time, can simplify the complexity of memory management.
[0028] In an optional embodiment, the method further comprises:
[0029] If the memory application request is successful, the service layer is replied with a memory application success information and an address of the target memory block, otherwise, the service layer is replied with a memory application failure information.
[0030] The memory management method provided by the embodiments of the present application can make the service layer know the processing result of the memory request in time by replying the service layer with the success or failure information of the memory application. If the memory application is successful, the service layer can obtain the address of the target memory block and continue to perform subsequent operations; if the memory application fails, the service layer can take remedial measures in time, such as releasing part of the memory no longer needed, trying a smaller memory request, or notifying the user of the insufficient memory resources. Such instant feedback helps to enhance the stability of the program and the user experience.
[0031] In an alternative embodiment, the method further comprises:
[0032] In response to the memory release request, the state information matrix and the index table array are updated.
[0033] The memory management method provided by the embodiments of the present application can ensure that the memory blocks are correctly marked as free and reused in subsequent memory allocation requests when the memory blocks are released. This helps to improve the reusability of memory resources and reduce memory waste.
[0034] In an alternative embodiment, the method further comprises:
[0035] If the memory release request is successful, the service layer is replied with a memory release success information, otherwise, the service layer is replied with a memory release failure information.
[0036] The memory management method provided by the embodiments of the present application can make the service layer release the related resources faster when it receives the reply of the memory release success, and take appropriate remedial measures such as retrying the release operation, recording error logs, or notifying the user if the memory release fails, which helps to enhance the stability of the program and the user experience.
[0037] In a second aspect, the present application provides a memory management device, the device comprising:
[0038] The generating matrix module is configured to generate a state information matrix according to the usage state of each atomic memory block in the physical memory information, wherein each element in the state information matrix is used to indicate whether each atomic memory block is used or not;
[0039] The generating array module is configured to generate an index table array based on the state information matrix; the index table array comprises an intra-row index table array and a cross-row index table array; the index table array is used to indicate the usage of memory blocks of different specifications; the memory blocks of different specifications are used to indicate continuous atomic memory blocks of different lengths in the state information matrix which are not used;
[0040] The determining module is configured to determine a target memory block corresponding to the memory application request based on the index table array;
[0041] The updating module is configured to update the state information matrix and the index table array based on the target memory block.
[0042] In a third aspect, the present application provides a computer device, comprising a memory and a processor, the memory and the processor are communicatively connected with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the memory management method in the first aspect or any of the corresponding embodiments.
[0043] In a fourth aspect, the present application provides a computer readable storage medium, which stores computer instructions, and the computer instructions are used to make a computer execute the memory management method in the first aspect or any of the corresponding embodiments.
[0044] In a fifth aspect, the present application provides a computer program product, which comprises computer instructions, and the computer instructions are used to make a computer execute the memory management method in the first aspect or any of the corresponding embodiments. BRIEF DESCRIPTION OF DRAWINGS
[0045] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the specific embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.
[0046] FIG. 1 is a flow diagram of a memory management method according to an embodiment of the present application;
[0047] FIG. 2 is a transformation process diagram of a state information matrix and an intra-row index table array according to an embodiment of the present application;
[0048] FIG. 3 is a flow diagram of another memory management method according to an embodiment of the present application;
[0049] FIG. 4 is a flow diagram of still another memory management method according to an embodiment of the present application;
[0050] FIG. 5 is a structural block diagram of a memory management device according to an embodiment of the present application;
[0051] FIG. 6 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present application. DETAILED DESCRIPTION
[0052] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.
[0053] At present, the memory buddy algorithm is usually used to meet various memory size requirements and to avoid memory fragmentation as much as possible. The algorithm divides all free memory blocks into a plurality of block linked lists, each of which contains continuous memory blocks of a specific size, thereby achieving fine management of the memory. However, according to the process of memory application and release, the memory iteration splitting / merging operation and the traversal of the linked list, the above-mentioned memory management method will generate a large time overhead, which will affect the performance of memory application / release.
[0054] According to the embodiments of the present application, a memory management method embodiment is provided. It should be noted that the steps shown in the flowchart of the drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described herein can be executed in an order different from that shown herein.
[0055] In the present embodiment, a memory management method is provided. FIG. 1 is a flowchart of the memory management method according to an embodiment of the present application. As shown in FIG. 1, the flow includes the following steps:
[0056] In step S101, a state information matrix is generated according to the usage state of each atomic memory block in the physical memory information.
[0057] Specifically, first, all information of the current physical memory is obtained, including total capacity, available capacity, allocated capacity, etc. Then, the physical memory is divided into a plurality of atomic memory blocks of the same size. The size of the atomic memory block can be predefined, for example, it can be 4KB. These atomic memory blocks are the basic units of memory allocation and recovery.
[0058] Further, the whole memory is divided into a plurality of smaller atomic memory blocks. The state information of each atomic memory block is mapped to 1 bit to represent its current state information, so as to create a two-dimensional matrix state information matrix of M rows and N columns, and each element in the state information matrix is used to respectively indicate whether each atomic memory block is used or not. The atomic memory blocks have two states: idle and used. Specifically, the idle state means that the memory block management module is initialized after the memory block is released by the service layer, and the used state means that the memory block has been applied by the service layer and has not been released.
[0059] Optionally, 0 represents that the use state of the atomic memory block is "unused", and 1 represents that the use state of the atomic memory block is "used".
[0060] In step S102, an index table array is generated based on the state information matrix.
[0061] Specifically, the index table array includes an intra-row index table array and a cross-row index table array, and the index table array is used to indicate the distribution of different lengths of continuous and same state elements in the state information matrix. Different specifications of memory blocks are used to indicate different lengths of continuous unused atomic memory blocks in the state information matrix, wherein the smallest specification is 1 idle atomic memory block, and the largest specification is K continuous idle atomic memory blocks, and K can be predefined.
[0062] Further, the higher the memory block specification is, the longer the length of the continuous idle atomic memory block is. One idle atomic memory block can only belong to one memory block specification.
[0063] In some optional embodiments, the above step S102 includes:
[0064] generating the intra-row index table array and the cross-row index table array based on the state information matrix; the column number of the intra-row index table array and the cross-row index table array is equal to the number of memory block specifications, the row number of the intra-row index table array is equal to the row number of the state information matrix, and the row number of the cross-row index table array is less than the row number of the intra-row index table array by 1.
[0065] Specifically, for the intra-row index table, the row number of the intra-row index table array is determined according to the row number of the state information matrix, that is, when the state information matrix is M rows and N columns, the intra-row index table is also M rows, and the number of memory block specifications, that is, the number of continuous lengths of unused atomic memory blocks, is determined to determine the column number of the intra-row index table array.
[0066] Further, in order to ensure the boundary continuity between M rows, i.e. between two adjacent rows in the state matrix, a cross-row index table is designed as a supplement to the in-row index table, and the number of rows of the cross-row index table is one less than that of the in-row index table array, so the cross-row index table matrix corresponding to the state information matrix of M rows should be M-1 rows, and the number of columns of the cross-row index table is also equal to the number of memory block specifications.
[0067] Further, through the in-row index table array and the cross-row index table array, the entire memory is divided into 2M-1 local memories, and each time memory management only needs to select one or two local memories for operation, and the global continuity of the entire memory is ensured.
[0068] Step S103, determining a target memory block corresponding to the memory application request based on the index table array.
[0069] Specifically, first, the size of the memory block required by the request is obtained by parsing the memory application request. Then, according to the size of the memory block of the application request, the available free state memory block in the corresponding specification column is searched, and the first row with available free state memory block is confirmed as the valid row. Since each row of the index table array corresponds to a row in the state information matrix, the specific position of the target memory block in the information state matrix can be determined based on this.
[0070] Further, if no available free state memory block is found in the row index table array, the next row is searched until all columns and rows of the index table array are traversed.
[0071] In some optional embodiments, the above step S103 includes:
[0072] Step S1031, determining a target area in the state information matrix based on the memory application request in the index table array;
[0073] Step S1032, selecting a target memory block corresponding to the size of the memory application request in the target area.
[0074] Specifically, according to the memory application request, the in-row index table array and the cross-row index table array are searched in parallel. If an idle state memory block that can meet the current memory application is found through the index table array, the index value obtained from the index table is used to detect the accurate position of the memory block in the local state information matrix to determine the corresponding target area in the state information matrix. Then, according to the memory application request, a memory block of the required size is selected as the target memory block in the target area in the information state matrix, and the address of the memory block is obtained.
[0075] Step S104, updating the state information matrix and the index table array based on the target memory block.
[0076] Specifically, when the target memory block is determined through step S103, in the state information matrix, the start position and length of the target memory block are found, and the element at the corresponding position is changed from the "free" state (usually represented by 0 or False) to the "used" state (usually represented by 1 or True).
[0077] Further, the in-row index table array and the cross-row index table array are updated based on the updated state information matrix.
[0078] In summary, the memory management method provided by the embodiments of the present application divides the entire physical memory into a plurality of smaller atomic memory blocks for the convenience of memory management, and maps the state information of each atomic memory block to 1 bit to represent the current state information thereof. The mapping is aggregated into a state information matrix (bitmap matrix) of M rows and N columns. In the bitmap matrix, the consecutive representation indicates the physical address continuity in the memory, the in-row continuity, and the cross-row continuity. If the free atomic memory blocks are in-row continuous, one possible state information matrix is shown in Table 1:
[0079] Table 1: Example of state information matrix
[0080] If the free atomic memory blocks are cross-row continuous, one possible state information matrix is shown in Table 2:
[0081] Table 2: Example of state information matrix
[0082] Therefore, corresponding to the two possible continuous free atomic block distribution situations, an in-row index table array and a cross-row index table array are generated respectively. The in-row index table array is shown in FIG. 2, which divides the memory into M local memories and represents the state of each in-row local memory through the in-row index table. The cross-row index table array is a supplement to the in-row index table array, and is used to ensure the boundary continuity between the M in-row local memories. Therefore, a cross-row index table array of M-1 rows is formed to represent the state of the M-1 cross-row local memories. The number of columns of the cross-row index table array is the same as that of the in-row index table.
[0083] When memory is applied, the in-line index table array and the cross-line index table array are searched in parallel according to the size of the applied memory block, specifically, according to the size of the applied memory, the corresponding column in the index table array is searched, and the first valid row in the column of the index table array is selected, and the region of the state information matrix corresponding to the row is taken as a target region, and then a target memory block is selected according to the memory application request; if the search in a column of the index table array fails, and the size of the currently searched memory block is not the maximum memory size, the memory size is upgraded and the search in the index table is performed again until the target memory block is determined according to the above process; if the search in a column of the index table array fails, and the size of the currently searched memory block is the maximum memory size, it indicates that the required memory block of the service layer cannot be allocated at present, and a response is directly performed.
[0084] After the target memory block is determined, the state information corresponding to the target memory block in the state information matrix is changed from "idle" to "in use", and the index table array is updated based on the updated state information matrix.
[0085] In some optional embodiments, the target region in the state information matrix is determined in the index table array, including:
[0086] If there is an idle state memory block with the same size as the memory application request in the index table array, the region in the state information matrix corresponding to the idle state memory block is confirmed as the target region.
[0087] If there is no idle state memory block with the same size as the memory application request in the index table array, the region in the state information matrix corresponding to the idle state memory block with the smallest size greater than the memory application request is confirmed as the target region.
[0088] First, the column in which the memory block size completely matching the memory application request is searched in the in-line index table array and the cross-line index table array in parallel, the first valid row in the column of the index table array is searched out, and the row in the information state matrix corresponding to the row in which the column is located is taken as a target region, if the optional idle state memory block is found in the in-line index table and the cross-line index table, the idle state memory block in the in-line index table is preferentially used to determine the corresponding row in the state information matrix as the target region.
[0089] If there is no idle state memory block with the same size as the memory application request, and the size of the currently searched memory block is not the maximum memory size, the memory size is upgraded and the search in the index table is performed again, if the size of the memory block at this time is the maximum memory block size in the index table array, it indicates that the required memory block of the service layer cannot be allocated at present, and the memory application request fails.
[0090] In some optional embodiments, the target memory block corresponding to the size of the memory application request is selected in the target region, including:
[0091] Selecting the target memory block corresponding to the size of the memory application request in the address of the target region.
[0092] When determining a target region in a row of the state information matrix according to the index table array, if there are more than one selectable target memory block corresponding to the memory application request in the row of the state information matrix, as shown in Table 3, assuming that the atomic memory block is 4 KB and the memory application request is 12 KB, the 3rd row of the state information matrix is located as the target region according to the index table array, but there are two selectable target memory blocks in the target region, then the memory block with smaller memory address is selected as the target memory block.
[0093] Table 3: Target region example table
[0094] In some optional embodiments, the method further comprises:
[0095] If the memory application request is successful, the service layer is replied with memory application success information and the address of the target memory block, otherwise the service layer is replied with memory application failure information.
[0096] Please refer to FIG. 3, the memory application process further comprises a reply to the service layer. If the target memory block is found according to the index table array and the state information matrix, and the state information matrix and the index table array are updated based on the target memory block, the service layer is replied with memory application success information and the address of the target memory block; if the target memory block corresponding to the memory application request cannot be found, the service layer is replied with memory application failure information.
[0097] In some optional embodiments, the method further comprises:
[0098] In response to the memory release request, the state information matrix and the index table array are updated.
[0099] Please refer to FIG. 4, after receiving the memory release operation sent by the service layer, the row of the memory block in the state information matrix is obtained according to the address decoding of the released memory, the state information of the corresponding atomic memory block position in the row of the released atomic memory block in the state information matrix is updated, and the index information in the index table array is updated based on the updated state information matrix.
[0100] In some optional embodiments, the method further comprises:
[0101] If the memory release request is successful, the service layer is replied with memory release success information, otherwise the service layer is replied with memory release failure information.
[0102] A memory management apparatus is also provided in the embodiments, which is configured to implement the above-described embodiments and preferred embodiments, and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
[0103] The embodiments provide a memory management apparatus, as shown in FIG. 5, comprising:
[0104] A generation matrix module 501 is configured to generate a state information matrix according to the usage state of each atomic memory block in the physical memory information; each element in the state information matrix is configured to indicate whether each atomic memory block is used or not;
[0105] A generation array module 502 is configured to generate an index table array based on the state information matrix; the index table array comprises an intra-row index table array and a cross-row index table array; the index table array is configured to indicate the usage of memory blocks of different specifications; the memory blocks of different specifications are configured to indicate continuous atomic memory blocks of different lengths in the state information matrix that are not used;
[0106] A determination module 503 is configured to determine a target memory block corresponding to the memory application request based on the index table array;
[0107] An update module 504 is configured to update the state information matrix and the index table array based on the target memory block.
[0108] In some optional embodiments, the generation array module 502 comprises:
[0109] A generation index table subunit is configured to generate the intra-row index table array and the cross-row index table array based on the state information matrix; the number of columns of the intra-row index table array and the cross-row index table array is equal to the number of memory block specifications; the number of rows of the intra-row index table array is equal to the number of rows of the state information matrix; and the number of rows of the cross-row index table array is less than the number of rows of the intra-row index table array by 1.
[0110] In some optional embodiments, the determination module 503 comprises:
[0111] A target region determination sub-module is configured to determine a target region in the state information matrix in the index table array based on the memory application request.
[0112] A selection sub-module is configured to select a target memory block corresponding to the size of the memory application request in the target region.
[0113] In some optional embodiments, the target region determination sub-module comprises:
[0114] The first unit for determining the target region is configured to determine the region in the state information matrix corresponding to the free memory block as the target region when the free memory block with the same size as the memory application request exists in the index table array.
[0115] The second unit for determining the target region is configured to determine the region in the state information matrix corresponding to the free memory block with the minimum size greater than the memory application request as the target region when the free memory block with the same size as the memory application request does not exist in the index table array.
[0116] In some optional embodiments, the selecting sub-module comprises:
[0117] The minimum address unit is configured to select the target memory block with the minimum address in the target region and corresponding to the memory application request.
[0118] In some optional embodiments, the apparatus further comprises:
[0119] The responding module is configured to respond to the service layer with the memory application success information and the address of the target memory block when the memory application request is successful, and otherwise respond to the service layer with the memory application failure information.
[0120] In some optional embodiments, the apparatus further comprises:
[0121] The release updating module is configured to update the state information matrix and the index table array in response to the memory release request.
[0122] Further function descriptions of the above-mentioned modules and units are the same as those of the corresponding embodiments, and will not be described here.
[0123] The memory management apparatus in the embodiment is presented in the form of functional units. The units herein refer to ASIC (Application Specific Integrated Circuit) circuits, processors and memories executing one or more software or fixed programs, and / or other devices that can provide the above functions.
[0124] The embodiment of the present application further provides a computer device with the memory management apparatus shown in Fig. 5.
[0125] Referring to FIG. 6, FIG. 6 is a structural diagram of a computer device according to an optional embodiment of the present application. As shown in FIG. 6, the computer device includes one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components communicate with each other using different buses, and can be mounted on a common main board or mounted in other manners as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple memory banks, if necessary. Also, multiple computer devices can be connected, each providing part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). One processor 10 is taken as an example in FIG. 6.
[0126] The processor 10 can be a central processor, a network processor, or a combination thereof. The processor 10 can further include a hardware chip. The hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic device, a general array logic, or any combination thereof.
[0127] The memory 20 stores instructions executable by the at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiments.
[0128] The memory 20 can include a program storage area and a data storage area. The program storage area can store an operating system and application programs required by at least one function; the data storage area can store data created according to the use of the computer device, etc. In addition, the memory 20 can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some optional embodiments, the memory 20 can optionally include a memory remotely arranged with respect to the processor 10, and these remote memories can be connected to the computer device through a network. Examples of the network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.
[0129] The memory 20 can include a volatile memory, such as a random access memory; the memory can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid-state disk; and the memory 20 can further include a combination of the above kinds of memories.
[0130] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 can be connected by a bus or other means, and are connected by a bus in FIG. 6 as an example.
[0131] The input device 30 can receive inputted digital or character information, and generate key signal input related to user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 can include a display device, an auxiliary lighting device (e.g., an LED), a tactile feedback device (e.g., a vibration motor), etc. The display device includes but is not limited to a liquid crystal display, a light emitting diode, a display, and a plasma display. In some optional embodiments, the display device can be a touch screen.
[0132] The embodiments of the present application also provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or be implemented as computer code stored in a remote storage medium or a non-transitory machine readable storage medium and stored in a local storage medium through network downloading, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer code, which, when accessed and executed by the computer, the processor, or the hardware, implements the method shown in the above embodiments.
[0133] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, the method and / or technical solutions according to the present application can be called or provided. Those skilled in the art should understand that the form of computer program instructions in a computer readable medium includes but is not limited to source files, executable files, installation package files, etc. Correspondingly, the way of executing the computer program instructions by the computer includes but is not limited to: the computer directly executes the instructions, or the computer executes the corresponding compiled program after compiling the instructions, or the computer reads and executes the instructions, or the computer executes the corresponding installed program after reading and installing the instructions. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.
[0134] While embodiments of the application have been described in connection with the preferred embodiments of the various figures, those of ordinary skill in the art will appreciate that various modifications and variations of the preferred embodiments can be employed without departing from the spirit and scope of the application.
Claims
1. A memory management method characterized by comprising: The method comprises: generating a state information matrix according to the use state of each atomic memory block in the physical memory information; each element in the state information matrix is used for respectively indicating whether each atomic memory block is used or not; generating an index table array based on the state information matrix; the index table array comprises an intra-row index table array and a cross-row index table array; the index table array is used for indicating the use state of memory blocks of different specifications; the memory blocks of different specifications are used for indicating continuous atomic memory blocks of different lengths in the state information matrix which are not used; determining a target memory block corresponding to a memory application request based on the index table array; updating the state information matrix and the index table array based on the target memory block.
2. The method of claim 1, wherein, The generating of the index table array based on the state information matrix comprises: generating the intra-row index table array and the cross-row index table array based on the state information matrix; the column number of the intra-row index table array and the cross-row index table array is the number of memory block specifications; the row number of the intra-row index table array is equal to the row number of the state information matrix; the row number of the cross-row index table array is less than the row number of the intra-row index table array by 1.
3. The method of claim 2, wherein, The determining of the target memory block corresponding to the memory application request based on the index table array comprises: determining a target region in the state information matrix in the index table array based on the memory application request; selecting a target memory block corresponding to the size of the memory application request in the target region.
4. The method of claim 3, wherein, The determining of the target region in the state information matrix in the index table array based on the memory application request comprises: if there is a free state memory block with the same size as the memory application request in the index table array, then confirming the region in the state information matrix corresponding to the free state memory block as the target region; if there is no free state memory block with the same size as the memory application request in the index table array, then confirming the region in the state information matrix corresponding to the free state memory block with the smallest specification greater than the memory application request as the target region.
5. The method of claim 4, wherein, The selecting of the target memory block corresponding to the size of the memory application request in the target region comprises: selecting the target memory block corresponding to the size of the memory application request with the smallest address in the target region.
6. The method according to any one of claims 1 to 5, characterized in that, The method further comprises: if the memory application request is successful, replying to the service layer with memory application success information and the address of the target memory block, otherwise replying to the service layer with memory application failure information.
7. The method of claim 6, wherein, The method further comprises: updating the state information matrix and the index table array in response to a memory release request.
8. A memory management device, characterized by The apparatus comprises: a generating matrix module, configured to generate a state information matrix according to the use state of each atomic memory block in the physical memory information; each element in the state information matrix is used for respectively indicating whether each atomic memory block is used or not; The generating array module is configured to generate an index table array based on the state information matrix; the index table array comprises an intra-row index table array and a cross-row index table array; the index table array is used to indicate the usage of memory blocks of different specifications; the memory blocks of different specifications are used to indicate the continuous unused atomic memory blocks of different lengths in the state information matrix; The determining module is configured to determine a target memory block corresponding to a memory application request based on the index table array; The updating module is configured to update the state information matrix and the index table array based on the target memory block.
9. A computer device, comprising: The memory and the processor are in communication connection with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the memory management method in any one of claims 1 to 7. The computer readable storage medium stores computer instructions, and the computer instructions are used to make the computer execute the memory management method in any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that,