Data processing method and related apparatus

Abstract

A data processing method, applied to the parameter tuning process of a processor, and comprising: determining a first instruction subset from a first program instruction set to be run; adjusting an operating parameter of the processor on the basis of the first instruction subset; determining a second instruction subset from a second program instruction set, wherein the first instruction subset and the second instruction subset have different numbers of contained instructions, or proportions of target-type instructions in the first instruction subset and the second instruction subset are different; and adjusting the operating parameter of the processor on the basis of the second instruction subset. In the present application, when a processor runs instructions of different services, instruction subsets of different specifications (having different numbers of contained instructions or different proportions of instructions of the same type) can be selected for parameter tuning of the processor, and an instruction subset that is more suitable for participating in parameter tuning of the processor can be selected, thereby improving the parameter tuning effect of the processor.

Description

Data processing method and related apparatus

[0001] The present application claims priority from the Chinese patent application No. 202411392377.6 filed on September 30, 2024, and entitled "A data processing method and related apparatus", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of computer, and in particular, to a data processing method and related apparatus. BACKGROUND

[0003] In order to realize parameter tuning of a processor (for example, a central processing unit (CPU)), in the prior art, a program slice (that is, a subset of instructions) is collected from a set of to-be-executed instructions, and the parameters of the processor are adjusted according to the program slice. Specifically, the CPU of an electronic device runs the program slice, the performance of the CPU can be evaluated, and thus the parameter tuning of the CPU is realized.

[0004] However, with the continuous enrichment of program instruction related business scenarios, the tuning effect is poor when using the program slice to tune the parameters of the processor in the prior art. SUMMARY

[0005] The present application provides a data processing method, apparatus and computing device, which can improve the effect of parameter tuning of a processor.

[0006] In a first aspect, a data processing method is provided. A first subset of instructions is determined from a first set of program instructions to be executed. The running parameters of a processor are adjusted according to the first subset of instructions. A second subset of instructions is determined from a second set of program instructions. The second set of program instructions is a set of program instructions to be executed after the first set of program instructions. The first subset of instructions and the second subset of instructions include different numbers of instructions, or the first subset of instructions and the second subset of instructions include different proportions of target type instructions. The running parameters of the processor are adjusted according to the second subset of instructions.

[0007] In the instruction set of different service scenarios, the characteristics of the instruction subset more suitable for participating in parameter tuning (including the number of instructions or the proportion of instructions of the same type) are often different. For example, in a big data service scenario, a large number of instruction sets may be needed to perform processor parameter tuning. When the processor runs different services, the instruction subset selected for processor parameter tuning may be different. In this application, when the processor runs different instructions, different specifications of instruction subsets (different number of instructions or different proportion of instructions of the same type) can be selected for processor parameter tuning. The instruction subset more suitable for participating in processor parameter tuning can be selected, thereby improving the effect of processor parameter tuning.

[0008] The proportion of instructions of the target type can be a preset proportion of instructions of a preset type, and the target type can be an instruction type corresponding to a hot function.

[0009] In a possible implementation, the first instruction subset is determined from the first program instruction set to be run, including:

[0010] A plurality of instruction subsets are determined from the first program instruction set to be run; wherein the number of instructions included between at least two instruction subsets in the plurality of instruction subsets in the first program instruction set is different, or the proportion of instructions of the target type is different, the first instruction subset is selected from the plurality of instruction subsets determined from the first program instruction set, or

[0011] The second instruction subset is determined from the second program instruction set to be run, including:

[0012] A plurality of instruction subsets are determined from the second program instruction set to be run; wherein the number of instructions included between at least two instruction subsets in the plurality of instruction subsets in the second program instruction set is different, or the proportion of instructions of the target type is different, the second instruction subset is selected from the plurality of instruction subsets determined from the second program instruction set.

[0013] The number of instructions included in the program slice constructed in the prior art and the proportion of instructions of the same type (for example, hot instructions, that is, instructions that require more computational or time overhead to execute by the processor) are fixed, while the number of instructions included in the plurality of instruction subsets determined from the first program instruction set in the embodiments of the present application or the proportion of instructions of the same type (for example, hot instructions) is not completely the same. The advantage of such processing is that the plurality of instruction subsets determined from the first program instruction set are candidates for the last application to processor parameter tuning. Compared with always selecting a fixed number and a fixed proportion of instructions of a preset category, the candidate set in the embodiments of the present application has more characteristics (including diversity in the number or diversity in the proportion of instructions of the same type), and the characteristics (the number of instructions included or the proportion of instructions of the same type) of the instruction subset that is more suitable for participating in parameter tuning are different in different business scenarios. For example, in a big data business scenario, a plurality of instruction sets may be required to include a large number of instructions for processor parameter tuning. From the candidate set determined based on the embodiments of the present application (that is, the plurality of instruction subsets determined from the first program instruction set), an instruction subset that is more suitable for participating in processor parameter tuning can be selected, thereby improving the effect of processor parameter tuning.

[0014] In a possible implementation, the first instruction subset is one of the at least two instruction subsets of the first program instruction set.

[0015] In a possible implementation, the first instruction subset is one of the at least two instruction subsets of the second program instruction set.

[0016] In a possible implementation, the adjustment of the running parameter of the processor is related to the number of instructions included in the first instruction subset or the proportion of instructions of a target type in the first instruction subset; or,

[0017] The adjustment of the running parameter of the processor is related to the number of instructions included in the second instruction subset or the proportion of instructions of a target type in the second instruction subset.

[0018] The parameter adjustment of the processor is related to the specification attribute of the selected program slice (for example, the first instruction subset or the second instruction subset). For a program slice, the size of the number of instructions included is a key influencing factor for whether it is more suitable for participating in processor parameter tuning, and thus when the size of the number of instructions included in the program slice is used to adjust the running parameter of the processor, a better tuning effect can be obtained.

[0019] The parameter adjustment of the processor is related to the specification attribute of the selected program slice (for example, the first instruction subset or the second instruction subset), and the proportion of the target type instruction of the program slice is a key influencing factor for whether the program slice is more suitable for participating in the parameter optimization of the processor, and then when the proportion of the target type instruction of the program slice is used to adjust the running parameter of the processor, a better optimization effect can be obtained.

[0020] The parameter adjustment of the processor is related to the specification attribute of the selected program slice (for example, the first instruction subset or the second instruction subset), and the proportion of the target type instruction of the program slice is a key influencing factor for whether the program slice is more suitable for participating in the parameter optimization of the processor, and then when the proportion of the target type instruction of the program slice is used to adjust the running parameter of the processor, a better optimization effect can be obtained.

[0021] In a possible implementation, the adjusting, according to the first instruction subset, of the running parameter of the processor running the first program instruction set comprises:

[0022] The running parameter of the processor is adjusted according to the number of instructions included in the first instruction subset through a first mapping relationship, and the first mapping relationship indicates the corresponding relationship between the running parameter of the processor and the number of instructions.

[0023] The mapping relationship between the number of instructions included in the instruction subset and the running parameter of the processor can be preconfigured, and after the instruction subset (that is, the first instruction subset) participating in the parameter optimization of the processor is determined, the adjustment manner of the running parameter of the processor can be determined according to the mapping relationship between the number of instructions included in the target instruction subset and the running parameter of the processor. Compared with the prior art in which the program slice needs to be processed to know the adjustment manner of the running parameter of the processor, in the embodiment of the present application, the adjustment manner of the running parameter of the processor can be determined from the first mapping relationship according to the number of instructions included in the target instruction subset, which reduces the processing complexity and improves the processing speed and real-time performance of the online processor optimization.

[0024] In a possible implementation, the adjusting, according to the first instruction subset, of the running parameter of the processor running the first program instruction set comprises:

[0025] The running parameter of the processor is adjusted according to the proportion of the target type instruction in the first instruction subset through a second mapping relationship, and the second mapping relationship indicates the corresponding relationship between the running parameter of the processor and the proportion of the target type instruction.

[0026] The mapping relationship between the proportion of the target type instructions in the instruction subset and the running parameters of the processor can be preconfigured. After the instruction subset participating in the parameter optimization of the processor (i.e., the first instruction subset) is determined, it can be determined how the running parameters of the processor should be adjusted according to the mapping relationship between the proportion of the target type instructions in the target instruction subset and the running parameters of the processor. Compared with the prior art in which the adjustment mode of the running parameters of the processor needs to be known through complex processing of the program slice, in the embodiment of the present application, the adjustment mode of the running parameters of the processor can be determined from the first mapping relationship according to the proportion of the target type instructions in the target instruction subset, thereby reducing the processing complexity and improving the processing speed and real-time performance of the online processor optimization.

[0027] In a possible implementation, the adjusting the running parameters of the processor running the first set of program instructions according to the first instruction subset comprises:

[0028] adjusting the running parameters of the processor according to the number of instructions included in the first instruction subset and the proportion of the target type instructions, by a third mapping relationship; the third mapping relationship indicates a corresponding relationship between the running parameters of the processor and the number of instructions and the proportion of the target type instructions.

[0029] The mapping relationship between the proportion of the target type instructions in the instruction subset and the running parameters of the processor can be preconfigured. After the instruction subset participating in the parameter optimization of the processor (i.e., the first instruction subset) is determined, it can be determined how the running parameters of the processor should be adjusted according to the mapping relationship between the proportion of the target type instructions in the target instruction subset and the running parameters of the processor. Compared with the prior art in which the adjustment mode of the running parameters of the processor needs to be known through complex processing of the program slice, in the embodiment of the present application, the adjustment mode of the running parameters of the processor can be determined from the first mapping relationship according to the proportion of the target type instructions in the target instruction subset, thereby reducing the processing complexity and improving the processing speed and real-time performance of the online processor optimization.

[0030] In a possible implementation, the adjusting the running parameters of the processor according to the second instruction subset comprises:

[0031] adjusting the running parameters of the processor according to the number of instructions included in the second instruction subset, by a first mapping relationship; the first mapping relationship indicates a corresponding relationship between the running parameters of the processor and the number of instructions.

[0032] The mapping relationship between the number of instructions included in the instruction subset and the running parameter of the processor can be preconfigured, and after the instruction subset participating in the parameter optimization of the processor (that is, the second instruction subset) is determined, it can be determined how the running parameter of the processor should be adjusted according to the mapping relationship between the number of instructions included in the target instruction subset and the running parameter of the processor. Compared with the prior art in which the adjustment mode of the running parameter of the processor needs to be known through complex processing of the program slice, in the embodiment of the present application, the adjustment mode of the running parameter of the processor can be determined from the first mapping relationship according to the number of instructions included in the target instruction subset, thereby reducing the processing complexity and improving the processing speed and real-time performance of the online processor optimization.

[0033] In a possible implementation, the adjusting the running parameter of the processor according to the second instruction subset comprises:

[0034] adjusting the running parameter of the processor according to the proportion of the target type instruction in the second instruction subset and through a second mapping relationship; the second mapping relationship indicates a corresponding relationship between the running parameter of the processor and the proportion of the target type instruction.

[0035] The mapping relationship between the proportion of the target type instruction in the instruction subset and the running parameter of the processor can be preconfigured, and after the instruction subset participating in the parameter optimization of the processor (that is, the second instruction subset) is determined, it can be determined how the running parameter of the processor should be adjusted according to the mapping relationship between the proportion of the target type instruction in the target instruction subset and the running parameter of the processor. Compared with the prior art in which the adjustment mode of the running parameter of the processor needs to be known through complex processing of the program slice, in the embodiment of the present application, the adjustment mode of the running parameter of the processor can be determined from the first mapping relationship according to the proportion of the target type instruction in the target instruction subset, thereby reducing the processing complexity and improving the processing speed and real-time performance of the online processor optimization.

[0036] In a possible implementation, the adjusting the running parameter of the processor according to the second instruction subset comprises:

[0037] adjusting the running parameter of the processor according to the number of instructions included in the second instruction subset and the proportion of the target type instruction and through a third mapping relationship; the third mapping relationship indicates a corresponding relationship between the running parameter of the processor and the number of instructions and the proportion of the target type instruction.

[0038] In a possible implementation, the number of instructions of the instruction subset and the mapping relationship between the proportion of target type instructions and the running parameters of the processor can be preconfigured. After the instruction subset participating in the optimization of the running parameters of the processor (that is, the third instruction subset) is determined, the adjustment manner of the running parameters of the processor can be determined according to the number of instructions of the target instruction subset and the mapping relationship between the proportion of target type instructions and the running parameters of the processor. Compared with the prior art in which the adjustment manner of the running parameters of the processor needs to be known through complex processing of the program slice, in the embodiment of the present application, the adjustment manner of the running parameters of the processor can be determined from the mapping relationship according to the number of instructions of the target instruction subset and the proportion of target type instructions, thereby reducing the processing complexity and improving the processing speed and real-time performance of the online processor optimization.

[0039] In a possible implementation, the first instruction subset is one of the at least two instruction subsets in the first program instruction set, or the second instruction subset is one of the at least two instruction subsets in the second program instruction set.

[0040] In a possible implementation, the first instruction subset is selected from the plurality of instruction subsets of the first program instruction set according to the optimizable degree of the processor when running the instruction subset, or the second instruction subset is selected from the plurality of instruction subsets of the second program instruction set according to the optimizable degree of the processor when running the instruction subset. The optimizable degree indicates the optimization amplitude of the performance of the processor by adjusting the parameters of the processor or the registers related to the processor when running the instruction subset.

[0041] The instruction subset more suitable for participating in the parameter optimization of the processor can be understood as follows: the optimizable degree of the processor when running instruction subset A is higher than that when running other instruction subsets, and therefore, "instruction subset A" is the instruction subset more suitable for participating in the parameter optimization of the processor. The optimizable degree indicates the optimization amplitude of the performance of the processor by adjusting the parameters of the processor or the registers related to the processor when running the instruction subset. For a certain code set, the optimization amplitude of the performance of the processor by adjusting the parameters of the processor or the registers related to the processor is usually higher (compared with other code sets). The code set with the above characteristics can be considered as a code set having a greater impact on the running performance of the processor. The parameter optimization of the processor according to the code set with the above characteristics can make the processor in a better state, that is, the running performance is higher.

[0042] In a possible implementation, the first instruction subset is selected from part of the plurality of instruction subsets included in the first program instruction set, and the part of the plurality of instruction subsets includes one or more instruction subsets in each category in a clustering result obtained by clustering the plurality of instruction subsets of the first program instruction set; or the second instruction subset is selected from part of the plurality of instruction subsets included in the second program instruction set, and the part of the plurality of instruction subsets includes one or more instruction subsets in each category in a clustering result obtained by clustering the plurality of instruction subsets of the second program instruction set.

[0043] To ensure that the finally selected target instruction subset is an instruction subset suitable for participating in parameter tuning of the processor, the number of candidate sets needs to be set to be large (the more candidate sets, the greater the probability of finally selecting a better instruction subset), however, when the number of instruction subsets included in the candidate sets (the plurality of instruction subsets) is too large (for example, thousands), a certain computing power overhead is required to evaluate whether each instruction subset is suitable for participating in parameter tuning of the processor, which can cause a large overall computing power overhead. Therefore, in the embodiments of the present application, the candidate sets need to be screened first, and the number of sets included in the candidate sets is reduced (that is, part of the plurality of instruction subsets is selected from the plurality of instruction subsets), and then only a smaller number of candidate sets need to be selected to participate in parameter tuning of the processor (that is, the first instruction subset or the second instruction subset is selected from the part of the plurality of instruction subsets), so that the overall computing power overhead can be reduced.

[0044] In a possible implementation, the performance is an instruction number per cycle (IPC).

[0045] In a possible implementation, the running parameter includes at least one of a working frequency and a working voltage of the processor.

[0046] In a second aspect, the present application provides a data processing method, including: determining a plurality of instruction subsets from a first program instruction set to be run, and the plurality of instruction subsets contain different numbers of instructions or different proportions of the same type of instructions (for example, hot instructions); then selecting an instruction subset (for example, a target instruction subset) more suitable for participating in parameter tuning of a processor from the plurality of determined instruction subsets, and adjusting a running parameter of the processor running the first program instruction set according to the target instruction subset.

[0047] In the prior art, the number of instructions included in the constructed program slice and the number of instructions of the same type (for example, hot instructions, that is, instructions that require more computational or time overhead to execute) are fixed. In the embodiment of the present application, the number of instructions included in the plurality of instruction subsets determined from the first program instruction set or the proportion of instructions of the same type (for example, hot instructions) is not completely the same. The advantage of such processing is that the plurality of instruction subsets determined from the first program instruction set are candidates for the last application to processor parameter tuning. Among these candidates, the instruction set with different instruction numbers or preset category instruction proportions has more diverse characteristics (including number diversity or same type instruction proportion diversity) than the code with fixed number and fixed preset category instruction proportion. In different business scenarios, the characteristics (instruction number or same type instruction proportion) of the instruction subset that is more suitable for participating in parameter tuning are often different. For example, in a big data business scenario, a larger number of instructions may be required to perform processor parameter tuning. From the candidate set determined based on the embodiment of the present application (that is, the plurality of instruction subsets determined from the first program instruction set), an instruction subset that is more suitable for participating in processor parameter tuning can be selected, thereby improving the effect of processor parameter tuning.

[0048] In a possible implementation, when the running parameters of the processor are adjusted according to the target instruction subset, the running parameters of the processor can be adjusted according to the number of instructions included in the target instruction subset. That is, when the processor is adjusted, the specific adjustment value is related to the number of instructions included in the target instruction subset.

[0049] The parameter adjustment of the processor is related to the specification attribute of the selected program slice (for example, the target instruction subset). For the program slice, the size of the number of instructions it contains is a key influencing factor for whether it is more suitable for participating in processor parameter tuning. Therefore, when the size of the number of instructions contained in the program slice is used to adjust the running parameters of the processor, a better tuning effect can be obtained.

[0050] In a possible implementation,

[0051] The adjustment of the running parameters of the processor is related to the number of instructions included in the target instruction subset; or

[0052] The adjustment of the running parameters of the processor is related to the proportion of target type instructions in the target instruction subset; or

[0053] The adjustment of the running parameter of the processor is related to the number of instructions included in the target instruction subset and the proportion of target type instructions.

[0054] The parameter adjustment of the processor is related to the specification attribute of the selected program slice (for example, the target instruction subset) itself. For the program slice, the proportion of target type instructions is a key influencing factor for whether it is more suitable for participating in the parameter tuning of the processor. Therefore, when the proportion of target type instructions of the program slice is used to adjust the running parameter of the processor, a better tuning effect can be obtained.

[0055] The parameter adjustment of the processor is related to the specification attribute of the selected program slice (for example, the target instruction subset) itself. For the program slice, the number of instructions included and the proportion of target type instructions are key influencing factors for whether it is more suitable for participating in the parameter tuning of the processor. Therefore, when the number of instructions included and the proportion of target type instructions of the program slice are used to adjust the running parameter of the processor, a better tuning effect can be obtained.

[0056] In a possible implementation, the running parameter of the processor can be adjusted according to the number of instructions included in the target instruction subset through a first mapping relationship. The first mapping relationship indicates the corresponding relationship between the running parameter of the processor and the number of instructions.

[0057] The mapping relationship between the number of instructions included in the instruction subset and the running parameter of the processor can be preconfigured. After the instruction subset (that is, the target instruction subset) participating in the parameter optimization of the processor is determined, the adjustment of the running parameter of the processor can be determined according to the mapping relationship between the number of instructions included in the target instruction subset and the running parameter of the processor. Compared with the prior art in which the program slice needs to be processed to know the adjustment mode of the running parameter of the processor, in the embodiment of the present application, the adjustment mode of the running parameter of the processor can be determined from the first mapping relationship according to the number of instructions included in the target instruction subset, which reduces the processing complexity and improves the processing speed and real-time performance of the online processor tuning.

[0058] In a possible implementation, the running parameter of the processor can be adjusted according to the proportion of target type instructions in the target instruction subset through a second mapping relationship. The second mapping relationship indicates the corresponding relationship between the running parameter of the processor and the proportion of target type instructions.

[0059] The mapping relationship between the proportion of the target type instructions in the instruction subset and the running parameters of the processor can be preconfigured, and after the instruction subset participating in the parameter optimization of the processor (i.e., the target instruction subset) is determined, the adjustment manner of the running parameters of the processor can be determined according to the mapping relationship between the proportion of the target type instructions in the target instruction subset and the running parameters of the processor. Compared with the prior art in which the adjustment manner of the running parameters of the processor needs to be known through complex processing of the program slice, in the embodiment of the present application, the adjustment manner of the running parameters of the processor can be determined from the first mapping relationship according to the proportion of the target type instructions in the target instruction subset, thereby reducing the processing complexity and improving the processing speed and real-time performance of the online processor optimization.

[0060] In a possible implementation, the running parameters of the processor can be adjusted according to the number of instructions included in the target instruction subset and the proportion of the target type instructions, through a third mapping relationship, the third mapping relationship indicating the corresponding relationship between the running parameters of the processor and the number of instructions and the proportion of the target type instructions.

[0061] In a possible implementation, the mapping relationship between the number of instructions of the instruction subset and the proportion of the target type instructions and the running parameters of the processor can be preconfigured, and after the instruction subset participating in the parameter optimization of the processor (i.e., the target instruction subset) is determined, the adjustment manner of the running parameters of the processor can be determined according to the mapping relationship between the number of instructions of the target instruction subset and the proportion of the target type instructions and the running parameters of the processor. Compared with the prior art in which the adjustment manner of the running parameters of the processor needs to be known through complex processing of the program slice, in the embodiment of the present application, the adjustment manner of the running parameters of the processor can be determined from the mapping relationship according to the number of instructions of the target instruction subset and the proportion of the target type instructions, thereby reducing the processing complexity and improving the processing speed and real-time performance of the online processor optimization.

[0062] In a possible implementation, the target instruction subset is selected from the plurality of instruction subsets according to the optimizable degree of the processor when running the instruction subset, and the optimizable degree indicates the optimization amplitude of the performance parameter of the processor by adjusting the parameters of the processor or the registers related to the processor when running the instruction subset.

[0063] The "instruction subset more suitable for participating in parameter tuning of the processor" can be understood as: the processor has a higher degree of optimization when running instruction subset A than when running other instruction subsets, and then "instruction subset A" is the instruction subset more suitable for participating in parameter tuning of the processor. The degree of optimization indicates the optimization amplitude of the performance parameter of the processor by adjusting the parameters of the processor or the registers related to the processor when running the instruction subset. For a certain code set, the optimization amplitude of the performance parameter of the processor is often higher (compared with other code sets) by adjusting the parameters of the processor or the registers related to the processor. The code set with the above characteristics can be considered as a code set that has a greater impact on the running performance of the processor. According to the code set with the above characteristics, the parameter tuning of the processor is performed, so that the processor is in a better state, that is, the running performance is higher.

[0064] In a possible implementation, the target instruction subset is one of the at least two instruction subsets.

[0065] In a possible implementation, the selecting the target instruction subset from the plurality of instruction subsets comprises: selecting a part of instruction subsets from the plurality of instruction subsets; and selecting the target instruction subset from the part of instruction subsets.

[0066] To ensure that the finally selected target instruction subset is the instruction subset suitable for participating in parameter tuning of the processor, the number of candidate sets needs to be set to be larger (the more candidate sets, the greater the probability of finally selecting a better instruction subset), however, when the number of instruction subsets included in the candidate set (the plurality of instruction subsets) is too large (for example, thousands), it needs a certain computing power overhead to evaluate whether each instruction subset is the instruction subset suitable for participating in parameter tuning of the processor, which will cause a large overall computing power overhead. Therefore, in the embodiment of the present application, the candidate set needs to be screened first, and the number of sets included in the candidate set is reduced (that is, a part of instruction subsets are selected from the plurality of instruction subsets), and then only a smaller number of candidate sets need to be selected for participating in parameter tuning of the processor (that is, the target instruction subset is selected from the part of instruction subsets), so as to reduce the overall computing power overhead.

[0067] In a possible implementation, the target instruction subset is selected from the part of instruction subsets according to the degree of optimization of the processor when running each instruction subset in the part of instruction subsets.

[0068] For a code set, the performance of the processor can be optimized by adjusting the parameters of the processor or the registers associated with the processor, and the optimization of the performance of the processor is higher for the code set (compared to other code sets). The code set having the above characteristics can be considered as a code set that has a greater impact on the running performance of the processor. Therefore, the target instruction subset is selected from the part of instruction subsets according to the degree of optimization of the processor when running each instruction subset in the part of instruction subsets, and the parameters of the processor are optimized according to the target instruction subset, so that the processor is in a better state, that is, the running performance is higher.

[0069] In a possible implementation, the part of instruction subsets is composed of one or more instruction subsets in each category in the clustering result obtained by clustering the plurality of instruction subsets.

[0070] In order to ensure that the number of instruction subsets included in the reduced candidate set is still able to select the instruction subsets suitable for participating in the parameter optimization of the processor after the number of instruction subsets included in the reduced candidate set is reduced (that is, part of the selection candidate set), it is necessary to ensure that the instruction subsets suitable for participating in the parameter optimization of the processor are not excluded when the number of instruction subsets included in the reduced candidate set (that is, part of the selection candidate set) is reduced. The idea of the embodiment of the present application is to identify a typical instruction subset in the plurality of instruction subsets as the reduced candidate set. The so-called "typical instruction subset" can be understood as an instruction subset that can represent other instruction subsets in a category in the plurality of instruction subsets, that is, some instruction subsets in the plurality of instruction subsets are similar to each other, for example, the IPC size, whether to read the register, and the like. In this case, it can be considered that these instruction subsets belong to the same category, and then an instruction subset (for example, the instruction subset located at the centroid) that can represent the category can be selected from the instruction subsets in the same category as the reduced candidate set. If at least one instruction subset is selected from each category, there is no missing instruction subset having certain characteristics in the reduced candidate set.

[0071] In a possible implementation, the method further includes: obtaining a plurality of candidate instruction features of each instruction subset and the performance of the processor when running the instruction subset; and selecting part of the instruction features in the plurality of candidate instruction features, so that there is a difference between the performance of the instruction subsets in different categories in the clustering result obtained by clustering the plurality of instruction subsets according to the part of the instruction features (for example, the difference between the performance of the instruction subsets in different categories is the largest, and the difference between the performance of the instruction subsets in the same category is the smallest).

[0072] The number of characteristics of the instruction subset can be large (e.g., 100), the clustering process can be a multi-round process, each round can filter the characteristics of the instruction subset (e.g., the last round filters 10), selecting different characteristics can cause the position distribution of the instruction subset in the characteristic space to be different, and the purpose of filtering is to select certain characteristics (i.e., part of the instruction characteristics in the embodiment of the application). When clustering is performed based on the selected characteristics, the performance of the instruction subsets in different categories in the clustering result is different (e.g., the performance of the instruction subsets in different categories is the most different, and the performance of the instruction subsets in the same category is the least different).

[0073] In a possible implementation, the performance parameter is instructions per cycle (IPC).

[0074] In a possible implementation, the running parameter includes at least one of a working frequency and a working voltage of the processor.

[0075] In a third aspect, the present application provides a data processing apparatus, comprising:

[0076] An instruction selection module is configured to determine a plurality of instruction subsets from a first program instruction set to be run, wherein the number of instructions included in at least two instruction subsets in the plurality of instruction subsets is different or the proportion of target type instructions is different, and select a target instruction subset from the plurality of instruction subsets.

[0077] A parameter adjustment module is configured to adjust a running parameter of the processor according to the target instruction subset.

[0078] In a possible implementation, the adjustment of the running parameter of the processor is related to the number of instructions included in the target instruction subset, or

[0079] The adjustment of the running parameter of the processor is related to the proportion of target type instructions in the target instruction subset, or

[0080] The adjustment of the running parameter of the processor is related to the number of instructions included in the target instruction subset and the proportion of target type instructions.

[0081] In a possible implementation, the parameter adjustment module is specifically configured to adjust the running parameter of the processor by a first mapping relationship according to the number of instructions included in the target instruction subset, and the first mapping relationship indicates a corresponding relationship between the running parameter of the processor and the number of instructions.

[0082] In a possible implementation, the parameter adjustment module is specifically configured to: according to the proportion of the target type instruction in the target instruction subset, adjust the running parameter of the processor by using a second mapping relationship; and the second mapping relationship indicates a corresponding relationship between the running parameter of the processor and the proportion of the target type instruction.

[0083] In a possible implementation, the parameter adjustment module is specifically configured to: according to the number of instructions included in the target instruction subset and the proportion of the target type instruction, adjust the running parameter of the processor by using a third mapping relationship; and the third mapping relationship indicates a corresponding relationship between the running parameter of the processor and the number of instructions and the proportion of the target type instruction.

[0084] In a possible implementation, the target instruction subset is one of the at least two instruction subsets.

[0085] In a possible implementation, the target instruction subset is selected from the plurality of instruction subsets according to an optimizable degree of the processor when running an instruction subset; and the optimizable degree indicates an optimization amplitude of a performance parameter of the processor by adjusting a parameter of the processor or a register related to the processor when running an instruction subset.

[0086] In a possible implementation, the instruction selection module is specifically configured to:

[0087] select a part of instruction subsets from the plurality of instruction subsets;

[0088] select a target instruction subset from the part of instruction subsets.

[0089] In a possible implementation, the selecting a target instruction subset from the part of instruction subsets comprises:

[0090] selecting a target instruction subset from the part of instruction subsets according to an optimizable degree of the processor when running each instruction subset in the part of instruction subsets.

[0091] In a possible implementation, the target instruction subset is selected from part of instruction subsets in the plurality of instruction subsets, and the part of instruction subsets includes one or more instruction subsets in each category in a clustering result obtained by clustering the plurality of instruction subsets.

[0092] In a possible implementation, the instruction selection module is specifically configured to:

[0093] obtain a plurality of candidate instruction features of each instruction subset and a performance of the processor when running the instruction subset;

[0094] The part of the plurality of candidate instruction features is selected so that there is a difference in performance between instruction subsets of different categories in a clustering result obtained by clustering the plurality of instruction subsets according to the part of the plurality of candidate instruction features.

[0095] In a possible implementation, the performance is instructions per cycle (IPC).

[0096] In a possible implementation, the running parameter includes at least one of a working frequency and a working voltage of the processor.

[0097] In a fourth aspect, the present application provides a data processing apparatus, which comprises:

[0098] An instruction selection module is configured to determine a first instruction subset from a first program instruction set, and determine a second instruction subset from a second program instruction set, wherein the second program instruction set is a program instruction set to be executed after the first program instruction set, the first instruction subset and the second instruction subset include different numbers of instructions, or the first instruction subset and the second instruction subset include different proportions of target type instructions.

[0099] A parameter adjustment module is configured to adjust a running parameter of the processor according to the first instruction subset, and adjust the running parameter of the processor according to the second instruction subset.

[0100] In a possible implementation, the instruction selection module is specifically configured to:

[0101] determine a plurality of instruction subsets from a first program instruction set to be executed, wherein at least two instruction subsets of the plurality of instruction subsets in the first program instruction set include different numbers of instructions or different proportions of target type instructions, select a first instruction subset from the plurality of instruction subsets determined from the first program instruction set, or

[0102] determine a plurality of instruction subsets from a second program instruction set to be executed, wherein at least two instruction subsets of the plurality of instruction subsets in the second program instruction set include different numbers of instructions or different proportions of target type instructions, and select a second instruction subset from the plurality of instruction subsets determined from the second program instruction set.

[0103] In a possible implementation, the adjustment of the running parameter of the processor is related to the number of instructions included in the first instruction subset or the proportion of target type instructions in the first instruction subset; or

[0104] The adjustment of the running parameter of the processor is related to the number of instructions included in the second instruction subset or the proportion of target type instructions in the second instruction subset.

[0105] In a possible implementation, the parameter adjustment module is configured to:

[0106] adjust, according to a number of instructions included in the first instruction subset, a running parameter of the processor by using a first mapping relationship; the first mapping relationship indicates a corresponding relationship between the running parameter of the processor and the number of instructions; or

[0107] adjust, according to a proportion of target type instructions in the first instruction subset, the running parameter of the processor by using a second mapping relationship; the second mapping relationship indicates a corresponding relationship between the running parameter of the processor and the proportion of target type instructions; or

[0108] adjust, according to the number of instructions included in the first instruction subset and the proportion of target type instructions, the running parameter of the processor by using a third mapping relationship; the third mapping relationship indicates a corresponding relationship between the running parameter of the processor and the number of instructions and the proportion of target type instructions.

[0109] In a possible implementation, the parameter adjustment module is configured to:

[0110] adjust, according to a number of instructions included in the second instruction subset, a running parameter of the processor by using a first mapping relationship; the first mapping relationship indicates a corresponding relationship between the running parameter of the processor and the number of instructions; or

[0111] adjust, according to a proportion of target type instructions in the second instruction subset, the running parameter of the processor by using a second mapping relationship; the second mapping relationship indicates a corresponding relationship between the running parameter of the processor and the proportion of target type instructions; or

[0112] adjust, according to the number of instructions included in the second instruction subset and the proportion of target type instructions, the running parameter of the processor by using a third mapping relationship; the third mapping relationship indicates a corresponding relationship between the running parameter of the processor and the number of instructions and the proportion of target type instructions.

[0113] In a possible implementation, the first instruction subset is one of the at least two instruction subsets in the first program instruction set; or

[0114] the second instruction subset is one of the at least two instruction subsets in the second program instruction set.

[0115] In a possible implementation, the first instruction subset is selected from the multiple instruction subsets of the first program instruction set according to an optimizability of the processor when running the instruction subset, or the second instruction subset is selected from the multiple instruction subsets of the second program instruction set according to an optimizability of the processor when running the instruction subset.

[0116] The optimizability indicates an optimization degree of performance of the processor by adjusting parameters of the processor or registers associated with the processor when running the instruction subset.

[0117] In a possible implementation, the first instruction subset is selected from part of the multiple instruction subsets included in the first program instruction set, and the part of the multiple instruction subsets includes one or more instruction subsets in each category in a clustering result obtained by clustering the multiple instruction subsets of the first program instruction set; or,

[0118] The second instruction subset is selected from part of the multiple instruction subsets included in the second program instruction set, and the part of the multiple instruction subsets includes one or more instruction subsets in each category in a clustering result obtained by clustering the multiple instruction subsets of the second program instruction set.

[0119] In a possible implementation, the performance is instructions per cycle (IPC).

[0120] In a possible implementation, the running parameter includes at least one of a working frequency and a working voltage of the processor.

[0121] In a fifth aspect, a computing device is provided, including a processor and a memory, and the memory is configured to store computer instructions, when the processor executes the instructions, the data processing apparatus executes the method in any of the aspects above.

[0122] In a sixth aspect, a computer readable storage medium is provided, and the computer readable storage medium stores instructions, when the instructions are executed on a computer, the computer can execute the method in any of the aspects above.

[0123] In a seventh aspect, a computer program product is provided, and the computer program product includes instructions, when the instructions are executed on a computer, the computer can execute the method in any of the aspects above.

[0124] In an eighth aspect, a chip system is provided, and the chip system includes a processor and a communication interface, the communication interface is configured to communicate with a module outside the chip, and the processor is configured to run a computer program or instructions, so that a device installed with the chip system can execute the method in any of the aspects above.

[0125] In a ninth aspect, a computing device cluster is provided, comprising at least one computing device, any one of the computing devices being configured to run computer programs or instructions such that the computing device cluster can perform the method of any one of the above aspects. Alternatively, some or all of the computing devices are collectively configured to run computer programs or instructions such that the computing device cluster can perform the method of any one of the above aspects.

[0126] On the basis of the implementation manners of the above aspects, the present application can be further combined to provide more implementation manners. BRIEF DESCRIPTION OF DRAWINGS

[0127] Fig. 1 is a schematic diagram of an application architecture of the present application;

[0128] Fig. 2 is a schematic diagram of a data processing method provided by the present application;

[0129] Fig. 3A is a schematic diagram of obtaining program slices provided by the present application;

[0130] Fig. 3B is a schematic diagram of processor parameter adjustment provided by the present application;

[0131] Fig. 4A is a schematic diagram of a data processing method provided by the present application;

[0132] Fig. 4B is a schematic diagram of obtaining program slices provided by the present application;

[0133] Fig. 5 is a schematic diagram of the structure of a data processing apparatus provided by the present application;

[0134] Fig. 6 is a schematic diagram of the structure of a computing device provided by the present application;

[0135] Fig. 7 is a schematic diagram of the structure of a computing device cluster provided by the present application;

[0136] Fig. 8 is a schematic diagram of the structure of another computing device cluster provided by the present application;

[0137] Fig. 9 is a schematic diagram of the structure of a computer readable storage medium provided by the present application. DETAILED DESCRIPTION

[0138] The embodiments of the present application will be described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. Those skilled in the art can know that as new application scenarios appear, the technical solutions provided by the present application are also applicable to similar technical problems.

[0139] The terms "first", "second", and the like in the description and in the claims of the present application and above drawings are used for distinguishing between similar objects and not necessarily for describing a specific sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the present application described herein are capable of operation in other sequences than described or otherwise illustrated herein. Furthermore, the terms "comprise", "include", "contain", and "have" and variations thereof when used in this description and in the claims of the present application shall be construed as disclosing the presence of the stated element or elements and not excluding the presence of one or more additional elements or steps. The naming or numbering of steps appearing in the present application does not imply that the steps must be performed in the time / logical order indicated by the naming or numbering, the named or numbered steps can be performed in a different order according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved. The division of units appearing in the present application is a logical division, and in actual application, there can be another division manner, for example, a plurality of units can be combined or integrated in another system, or some features can be ignored or not performed, in addition, the coupling or direct coupling or communication connection between the units shown or discussed can be through some interface, the indirect coupling or communication connection between the units can be electrical or other similar forms, which are not limited in the present application. In addition, the units or sub-units described as separate components can or can not be physically separated, can or can not be physical units, or can be distributed in a plurality of circuit units, and some or all of the units can be selected according to actual needs to achieve the purpose of the present application.

[0140] The electronic device 100 involved in implementing the method provided in the embodiments of the present application will be introduced first. The electronic device 100 can be a computer, a workstation, a smart terminal, a server, and other types of electronic devices capable of automatically and high-speed processing of a large amount of numerical calculation and various information processing according to a program stored in advance, and the like, which are not limited in the embodiments of the present application.

[0141] As shown in FIG. 1, the electronic device 100 includes a processor 101, a system memory 102, a non-volatile memory 103, a network interface 104, and an input / output device 105, and a bus 106 for coupling the processor 101, the system memory 102, the non-volatile memory 103, the network interface 104, and the input / output device 105.

[0142] The processor 101 is configured to execute the data processing method related to the embodiments of the present application, and to perform parameter tuning of the processor 101. It can be understood that the electronic device 100 can also include multiple processors, and the data processing method related to the embodiments of the present application is executed by the processor 101 to perform parameter tuning on the other multiple processors.

[0143] The system memory 102 can be used to temporarily store the instructions 107, and the non-volatile memory 103 can be used to permanently store the instructions 107. The system memory 102 can be used to temporarily store data files obtained from the electronic device 100 and parsing rules for parsing instructions from the data files, and the non-volatile memory 103 can be used to permanently store data files obtained from the electronic device 100 and parsing rules for parsing instructions from the data files.

[0144] The network interface 104 is configured to communicate with other devices, for example, the electronic device 100 can communicate with a server through the network interface 104.

[0145] The input / output device 105 can be used for user interaction with the electronic device 100.

[0146] To realize parameter tuning of a processor (for example, a central processing unit (CPU)), in the related art, a program slice (that is, a subset of instructions) is collected from a set of instructions to be run, and the parameters of the processor are adjusted according to the program slice. Specifically, the program slice refers to saving part of the instructions in the instruction set included in an application program, and optionally, restoring at least one executable program consistent with the original execution logic of the application program. Program slicing is widely used in CPU parameter tuning. By controlling the CPU of the electronic device to run the program slice, an evaluation result corresponding to the parameter tuning can be obtained, that is, the IPC (instruction per cycle), and the performance of the CPU can be evaluated, thereby realizing parameter tuning of the CPU.

[0147] However, in the prior art, when determining the program slice, the program slice is often a fixed-size slice randomly selected from the instruction set. As the business scenarios related to the program instructions continue to be enriched, the fixed-size program slice cannot be applied to each business scenario, and therefore, the slice determination method in the related art can result in low effectiveness of parameter tuning of the processor.

[0148] Based on this, the embodiment of the present application provides a data processing method. The data processing method provided by the embodiment of the present application is described in detail below based on the method flow diagram shown in FIG. 2. The method shown in FIG. 2 can be implemented by executing related instructions by the processor 101 of the electronic device 100 shown in FIG. 1. In some embodiments, the data processing method provided by the embodiment of the present application can be executed by the processor 101 of the electronic device 100 shown in FIG. 1 to optimize the parameters of the processor 101, or to optimize the parameters of other processors of the electronic device 100 or processors of other electronic devices in communication with the electronic device 100.

[0149] The method shown in FIG. 2 includes:

[0150] 201. The processor determines a plurality of instruction subsets from a first program instruction set to be executed; wherein the number of instructions included between at least two instruction subsets in the plurality of instruction subsets is different, or the proportion of target type instructions is different.

[0151] The execution subject (processor) of step 201 can be an object of subsequent parameter optimization, that is, a method of performing parameter optimization itself, and based on the execution result of the parameter optimization method, the processor can perform parameter optimization on itself, or the processor can perform parameter optimization on other processors.

[0152] The first program instruction set can be instructions included in an original program to be executed.

[0153] Exemplarily, the first program instruction set here can be an original program (original instruction stream data) including 90000 instructions as shown in FIG. 3A.

[0154] The same type of instruction can be a hot spot instruction, that is, an instruction that requires a large amount of computing power or time when the processor executes the instruction. For example, the running time of each type of instruction indicated in the flame chart can be used to determine the hot spot instruction, and the instruction with a longer running time can be the hot spot instruction. The flame chart is a visualization tool used to show the hierarchical structure and execution time of the instructions. Each instruction in the flame chart is displayed as a stripe, and the width of the stripe (of course, according to different presentation methods of the flame chart, it can also be height, length or other dimensions that can indicate the execution time) represents the length of the instruction execution time. Through the flame chart, the instructions and the execution time of the instructions can be seen very intuitively.

[0155] In the embodiments of the present application, a plurality of instruction subsets in the first set of program instructions can be selected to construct a program slice. In the prior art, the number of instructions and the same type of instructions (for example, hot instructions, that is, instructions that require more algorithmic or time overhead to execute) included in the constructed program slice are fixed. In the embodiments of the present application, a plurality of instruction subsets are determined from the first set of program instructions, and the number of instructions or the proportion of the same type of instructions (for example, hot instructions) included in the plurality of instruction subsets is not completely the same. Then, an instruction subset (for example, a target instruction subset) that is more suitable for participating in the parameter tuning of the processor can be selected from the plurality of determined instruction subsets to perform the parameter tuning of the processor.

[0156] The program slice can refer to saving part of the instructions (which can be understood as an instruction subset of the set of program instructions) included in an application program. For example, an application program has 100,000 instructions, and the 30,000th instruction to the 40,000th instruction is recorded, reassembled into a segment of an executable program, and referred to as a program slice.

[0157] The advantage of such processing is that the plurality of instruction subsets determined from the first set of program instructions are candidates for the last application to the parameter tuning of the processor. These candidates have instruction subsets with different numbers of instructions or different proportions of preset category instructions. Compared with always selecting a fixed number and a fixed proportion of preset category instructions, the candidate set in the embodiments of the present application has more characteristics (has diversity in the number of contained instructions or the proportion of the same type of instructions). In different business scenarios, the characteristics (the number of contained instructions or the proportion of the same type of instructions) of the instruction subset that is more suitable for participating in the parameter tuning are often different. For example, in a big data business scenario, a larger number of instruction sets can be required to perform the parameter tuning of the processor. From the candidate set determined based on the embodiments of the present application (that is, the plurality of instruction subsets determined from the first set of program instructions), an instruction subset that is more suitable for participating in the parameter tuning of the processor can be selected, thereby improving the effect of the parameter tuning of the processor.

[0158] For example, referring to FIG. 3A, the instruction set includes 90,000 instructions. Three instruction subsets are obtained by performing instruction selection on the instruction set, including instructions from 19,000 to 22,000, instructions from 50,000 to 60,000, and instructions from 61,000 to 80,000. The three instruction subsets include different numbers of instructions. An instruction subset that is more suitable for participating in the parameter tuning of the processor can be selected from the three instruction subsets, thereby improving the effect of the parameter tuning of the processor.

[0159] The code set includes a large number of instruction sets, and the business scenarios include, but are not limited to, data and graphics processing scenarios, memory database scenarios, KV storage scenarios, CPU and shared memory benchmark test scenarios, and the like.

[0160] It should be understood that the "instruction subset more suitable for participating in parameter tuning of the processor" in the embodiments of the present application can be understood as: the processor has a higher degree of optimization when running the instruction subset, and the degree of optimization indicates the optimization amplitude of the performance of the processor when running the instruction subset by adjusting the parameters of the processor or the processor-related registers. Next, a specific example is given to introduce the degree of optimization in the embodiments of the present application:

[0161] In the case that the parameter of the processor-related register is parameter A, the processor runs instruction subset A, and the value of the performance parameter of the processor when running instruction subset A is X. By tuning the parameters of the processor-related registers, for example, adjusting the parameter of the processor-related register from parameter A to parameter B (the adjustment of the parameter of the processor's register will affect the performance parameter of the processor), in this case, the processor re-runs instruction subset A, and the value of the performance parameter of the processor when re-running instruction subset A is Y. The difference between Y and X is the optimization amplitude (caused by the adjustment of the register parameter) of the performance parameter, and there is an optimal adjustment mode for the processor-related registers, which can maximize the optimization amplitude of Y compared with X. This maximum optimization amplitude can be considered as the performance optimization amplitude of the processor when running the instruction subset. For a plurality of instruction subsets, the greater the performance optimization amplitude of the processor when running the instruction subset, the higher the degree of optimization of the processor when running the instruction subset.

[0162] For a certain code set, by adjusting the parameters of the processor or the processor-related registers, the optimization amplitude of the performance parameter of the processor is often higher (compared with other code sets). The code set with the above characteristics can be considered as a code set that has a greater impact on the running performance of the processor. Therefore, according to the degree of optimization of the processor when running each instruction subset in the part of instruction subsets, a target instruction subset is selected from the part of instruction subsets, and the parameter tuning of the processor according to the target instruction subset will make the processor in a better state, that is, the running performance is higher.

[0163] Exemplarily, the multiple instruction subsets can be determined from the first set of program instructions to be executed based on a manner of instruction instrumentation. The instruction instrumentation can specifically include: performing an intercept operation on the set of instructions based on a load instruction stream, and adjusting an interval of instruction intercepting according to a requirement of a program slicing granularity (in an embodiment of the present application, the program slicing granularity can also be referred to as a number of instructions included in a program slice) or a typical instruction proportion (in an embodiment of the present application, the typical instruction proportion can also be referred to as a proportion of target type instructions).

[0164] In a possible implementation, the user can input indication information, the indication information being used to indicate a number of instructions included in each instruction subset obtained by performing program slicing on the set of instructions or a proportion of instructions of the same type, and then, when performing instruction instrumentation, the set of instructions can be sliced according to the indication information.

[0165] In a possible implementation, the number of instructions between the multiple instruction subsets can vary according to a certain gradient, for example, the number of instructions of the multiple instruction subsets can include multiple values between 1000-20000, which is equivalent to increasing the diversity of the number of instructions of the multiple instruction subsets.

[0166] In a possible implementation, the proportion of preset instructions between the multiple instruction subsets can vary according to a certain gradient, for example, the proportion of preset instructions of the multiple instruction subsets can include multiple values between 1% and 10%, which is equivalent to increasing the diversity of the proportion of preset instructions of the multiple instruction subsets.

[0167] 202. The processor selects a target instruction subset from the multiple instruction subsets.

[0168] In a possible implementation, an instruction subset that is more suitable for participating in parameter tuning of the processor can be selected from the multiple instruction subsets.

[0169] In order to ensure that the finally selected target instruction subset is the instruction subset suitable for participating in the parameter tuning of the processor, the number of the candidate set needs to be set to be large (the more the candidate sets, the greater the probability of finally selecting a better instruction subset), and when the number of the instruction subsets included in the candidate set (the plurality of instruction subsets) is too large (for example, thousands), since a certain computing resource overhead is required for evaluating whether each instruction subset is suitable for participating in the parameter tuning of the processor, the overall computing resource overhead is large. Therefore, in the embodiment of the present application, the candidate set needs to be filtered first, and the number of the instruction subsets included in the candidate set is reduced (that is, a part of the instruction subsets are selected from the plurality of instruction subsets), and then only the instruction subsets suitable for participating in the parameter tuning of the processor need to be selected from the candidate set including a smaller number of instruction subsets (that is, the target instruction subset is selected from the part of the instruction subsets), so that the overall computing resource overhead can be reduced.

[0170] In a possible implementation, the part of the instruction subsets is constituted by one or more instruction subsets in each category in the clustering result obtained by clustering the plurality of instruction subsets.

[0171] In order to ensure that the instruction subset suitable for participating in the parameter tuning of the processor can still be selected from the reduced candidate set after the number of the instruction subsets included in the candidate set is reduced, it is necessary to ensure that when the candidate range of the candidate set is reduced (that is, a part of the candidate set is selected), the instruction subset suitable for participating in the parameter tuning of the processor is not excluded. The idea of the embodiment of the present application is to identify a very typical instruction subset in the plurality of instruction subsets as the reduced candidate set, wherein the so-called "very typical instruction subset" can be understood as an instruction subset that can represent other instruction subsets in a category in the plurality of instruction subsets, that is, some instruction subsets in the plurality of instruction subsets are similar to each other in characteristics such as IPC size and whether a register needs to be read, and in this case, these instruction subsets can be considered to be in the same category, and then an instruction subset (for example, the instruction subset located at the centroid) that can represent the category can be selected from the instruction subsets in the same category as the reduced instruction set. If at least one instruction subset is selected from each category, there is no case that an instruction subset having certain characteristics is omitted in the reduced instruction set.

[0172] In one possible implementation, a plurality of candidate instruction features of each of the instruction subsets and performance of the processor when running the instruction subsets can be obtained; and some of the plurality of candidate instruction features can be selected so that there is a difference between performance of instruction subsets of different categories in a clustering result obtained by clustering the plurality of instruction subsets according to the some of the instruction features (for example, the difference between performance of instruction subsets of different categories is the largest, and the difference between performance of instruction subsets of the same category is the smallest).

[0173] The number of instruction features of an instruction subset can be large (for example, 100), the clustering process can be a multi-round process, and each round can screen instruction features of the instruction subset (for example, 10 in the last round). Selecting different features can result in a difference in the distribution of positions of instruction subsets in a feature space, and the purpose of screening is to select some features (that is, the some instruction features in the embodiments of the present application).

[0174] In determining the instruction subsets finally participating in parameter optimization of the processor, a target instruction subset can be selected from the plurality of instruction subsets to participate in parameter optimization of the processor according to an optimizable degree of the processor when running the instruction subsets.

[0175] When the compression of the candidate set (that is, the number of instruction subsets included in the candidate set is reduced) is combined, a target instruction subset can be selected from the some instruction subsets according to an optimizable degree of the processor when running each of the some instruction subsets.

[0176] For example, the performance parameter can be instructions per cycle (IPC), and the instructions per cycle (IPC) can be the number of instructions run by the processor per clock cycle.

[0177] In a possible implementation, when determining the optimizability of the instruction subset, the change range of the performance parameter of the processor running the instruction subset can be observed by adjusting the processor-related register parameter, for example, the greater the increase in IPC, the greater the optimizability. The processor-related register parameter is parameter A, in this case, the processor runs instruction subset A, and the value of the performance parameter of the processor running instruction subset A is X, by adjusting the processor-related register parameter, for example, adjusting to parameter B, in this case, the processor runs instruction subset A, and the value of the performance parameter of the processor running instruction subset A is Y, the difference between Y and X is the optimization range of the performance parameter, and there is an optimal adjustment mode for the processor-related register, which can maximize the optimization range of Y compared with X, and this maximum optimization range can be considered as the performance optimization range of the processor running the instruction subset. For a plurality of instruction subsets, the greater the performance optimization range of the processor running the instruction subset, the higher the optimizability of the processor running the instruction subset, for example, the greater the performance optimization range can be: the greater the increase in IPC.

[0178] 203. The processor adjusts a running parameter of the processor running the first set of program instructions according to the target instruction subset.

[0179] In a possible implementation, when adjusting the running parameter of the processor according to the target instruction subset, the running parameter of the processor can be adjusted according to the number of instructions included in the target instruction subset. That is, when adjusting the parameter of the processor, the specific adjustment value is related to the number of instructions included in the target instruction subset.

[0180] The parameter adjustment of the processor is related to the specification attribute of the selected program slice (for example, the target instruction subset) itself, and for the program slice, the size of the number of instructions included therein is a key influencing factor for whether it is more suitable for participating in the parameter tuning of the processor, and thus, when the size of the number of instructions included in the program slice is used to adjust the running parameter of the processor, a better tuning effect can be obtained.

[0181] In a possible implementation, when adjusting the running parameter of the processor according to the target instruction subset, the running parameter of the processor can be adjusted according to the proportion of the target type instruction in the target instruction subset. That is, when adjusting the parameter of the processor, the specific adjustment value is related to the proportion of the target type instruction in the target instruction subset.

[0182] The parameter adjustment of the processor is related to the specification attribute of the selected program slice (for example, the target instruction subset), and the proportion of the target type instruction in the program slice is a key influencing factor for whether the program slice is more suitable for participating in the parameter optimization of the processor, and thus, when the proportion of the target type instruction in the program slice is used to adjust the running parameter of the processor, a better optimization effect can be obtained.

[0183] In a possible implementation, when the running parameter of the processor is adjusted according to the target instruction subset, the running parameter of the processor can be adjusted according to the number of instructions included in the target instruction subset and the proportion of the target type instruction. That is, when the parameter of the processor is adjusted, the specific adjustment value is related to the number of instructions included in the target instruction subset and the proportion of the target type instruction in the target instruction subset.

[0184] The parameter adjustment of the processor is related to the specification attribute of the selected program slice (for example, the target instruction subset), and the number of instructions included in the program slice and the proportion of the target type instruction are key influencing factors for whether the program slice is more suitable for participating in the parameter optimization of the processor, and thus, when the number of instructions included in the program slice and the proportion of the target type instruction in the program slice are used to adjust the running parameter of the processor, a better optimization effect can be obtained.

[0185] In a possible implementation, the running parameter of the processor can be adjusted according to the number of instructions included in the target instruction subset through a first mapping relationship. The first mapping relationship indicates the corresponding relationship between the running parameter of the processor and the number of instructions.

[0186] The mapping relationship between the number of instructions included in the instruction subset and the running parameter of the processor can be preconfigured, and after the instruction subset (that is, the target instruction subset) participating in the parameter optimization of the processor is determined, the mapping relationship between the number of instructions included in the target instruction subset and the running parameter of the processor can be used to determine how the running parameter of the processor should be adjusted. Compared with the prior art in which the program slice needs to be processed to know the adjustment mode of the running parameter of the processor, in the embodiment of the present application, the adjustment mode of the running parameter of the processor can be determined from the first mapping relationship according to the number of instructions included in the target instruction subset, which reduces the processing complexity and improves the processing speed and real-time performance of the online processor optimization.

[0187] In a possible implementation, the running parameter of the processor can be adjusted according to the proportion of the target type instruction in the target instruction subset through a second mapping relationship. The second mapping relationship indicates the corresponding relationship between the running parameter of the processor and the proportion of the target type instruction.

[0188] The mapping relationship between the proportion of the target type instructions in the instruction subset and the running parameters of the processor can be preconfigured. After the instruction subset participating in the parameter optimization of the processor (i.e., the target instruction subset) is determined, the adjustment manner of the running parameters of the processor can be determined according to the mapping relationship between the proportion of the target type instructions in the target instruction subset and the running parameters of the processor. Compared with the prior art in which the adjustment manner of the running parameters of the processor needs to be known through complex processing of the program slice, in the embodiment of the present application, the adjustment manner of the running parameters of the processor can be determined from the first mapping relationship according to the proportion of the target type instructions in the target instruction subset, thereby reducing the processing complexity and improving the processing speed and real-time performance of the online processor optimization.

[0189] In a possible implementation, the running parameters of the processor can be adjusted according to the number of instructions included in the target instruction subset and the proportion of the target type instructions, through a third mapping relationship. The third mapping relationship indicates the corresponding relationship between the running parameters of the processor and the number of instructions and the proportion of the target type instructions.

[0190] In a possible implementation, the mapping relationship between the number of instructions of the instruction subset and the proportion of the target type instructions and the running parameters of the processor can be preconfigured. After the instruction subset participating in the parameter optimization of the processor (i.e., the target instruction subset) is determined, the adjustment manner of the running parameters of the processor can be determined according to the mapping relationship between the number of instructions of the target instruction subset and the proportion of the target type instructions and the running parameters of the processor. Compared with the prior art in which the adjustment manner of the running parameters of the processor needs to be known through complex processing of the program slice, in the embodiment of the present application, the adjustment manner of the running parameters of the processor can be determined from the mapping relationship according to the number of instructions of the target instruction subset and the proportion of the target type instructions, thereby reducing the processing complexity and improving the processing speed and real-time performance of the online processor optimization.

[0191] In a possible implementation, the running parameters include at least one of the working frequency and the working voltage of the processor.

[0192] For example, referring to FIG. 3B, after the target instruction subset is determined, the corresponding parameter C3 of the processor can be determined from the mapping relationship (table) shown in FIG. 3B according to the number A3 of instructions of the target instruction subset and the proportion B3 of the same type of instructions, and then the parameter of the processor can be adjusted according to C3.

[0193] Referring to FIG. 4A, FIG. 4A is another schematic of the data processing method provided by the embodiments of the present application, and different from FIG. 3A, FIG. 4A describes a process of twice parameter tuning of the processor, including:

[0194] 401. The processor determines a first instruction subset from the first program instruction set.

[0195] The determination process of the first instruction subset can refer to the determination process of the target instruction subset in the corresponding embodiment of FIG. 2.

[0196] 402. The processor adjusts the running parameter of the processor running the first program instruction set according to the first instruction subset.

[0197] 403. The processor determines a second instruction subset from the second program instruction set; wherein the second program instruction set is the program instruction to be run after the first program instruction set, and the first instruction subset and the second instruction subset include different number of instructions, or the target type instruction in the first instruction subset and the second instruction subset has different proportion.

[0198] The determination process of the second instruction subset can refer to the determination process of the target instruction subset in the corresponding embodiment of FIG. 2.

[0199] In a possible implementation, the second program instruction set and the first program instruction set can be the instructions of different application programs.

[0200] In a possible implementation, the second program instruction set and the first program instruction set can be different instruction sets in the same application program.

[0201] 404. The processor adjusts the running parameter of the processor according to the second instruction subset.

[0202] For example, referring to FIG. 4B, the first instruction subset determined from the first program instruction set includes different number of instructions than the second instruction subset determined from the second program instruction set.

[0203] In a possible implementation, the first instruction subset is one of the at least two instruction subsets of the first program instruction set.

[0204] In a possible implementation, the first instruction subset is one of the at least two instruction subsets of the second program instruction set.

[0205] In the instructions of different business scenarios, the characteristics of the instruction subset more suitable for participating in parameter tuning (including the number of instructions or the proportion of instructions of the same type) are often different. For example, in the big data business scenario, a larger number of instruction sets may be needed to perform parameter tuning of the processor. In different processor optimization processes, the present application can select instruction subsets of different specifications (different numbers of instructions or different proportions of instructions of the same type) to perform parameter tuning of the processor, and can select instruction subsets more suitable for participating in parameter tuning of the processor, thereby improving the effect of parameter tuning of the processor.

[0206] In a possible implementation, the first instruction subset is determined from the first program instruction set to be run, including: determining a plurality of instruction subsets from the first program instruction set to be run; wherein the number of instructions included in at least two instruction subsets in the plurality of instruction subsets is different or the proportion of target type instructions is different, and the first instruction subset is selected from the plurality of instruction subsets; or the second instruction subset is determined from the second program instruction set to be run by the processor, including: determining a plurality of instruction subsets from the second program instruction set to be run; wherein the number of instructions included in at least two instruction subsets in the plurality of instruction subsets is different or the proportion of target type instructions is different, and the second instruction subset is selected from the plurality of instruction subsets.

[0207] In the instructions of different business scenarios, the characteristics of the instruction subset more suitable for participating in parameter tuning (including the number of instructions or the proportion of instructions of the same type) are often different. For example, in the big data business scenario, a larger number of instruction sets may be needed to perform parameter tuning of the processor. In different processor optimization processes, the present application can select instruction subsets of different specifications (different numbers of instructions or different proportions of instructions of the same type) to perform parameter tuning of the processor, and can select instruction subsets more suitable for participating in parameter tuning of the processor, thereby improving the effect of parameter tuning of the processor.

[0208] In a possible implementation, the adjustment of the running parameter of the processor according to the first instruction subset includes: adjusting the running parameter of the processor according to the number of instructions included in the first instruction subset or the proportion of target type instructions; or the adjustment of the running parameter of the processor according to the second instruction subset includes: adjusting the running parameter of the processor according to the number of instructions included in the second instruction subset or the proportion of target type instructions. In a possible implementation, the selection of the first instruction subset from the plurality of instruction subsets includes: selecting a part of instruction subsets from the plurality of instruction subsets, and selecting the first instruction subset from the part of instruction subsets; or the selection of the second instruction subset from the plurality of instruction subsets includes: selecting a part of instruction subsets from the plurality of instruction subsets, and selecting the second instruction subset from the part of instruction subsets.

[0209] The adjustment of the parameter of the processor is related to the specification attribute of the selected program slice (for example, the first instruction subset or the second instruction subset). For the program slice, the size of the number of instructions included is a key influencing factor for whether the program slice is more suitable for participating in the parameter tuning of the processor. Therefore, when the size of the number of instructions included in the program slice is used to adjust the running parameter of the processor, a better tuning effect can be obtained.

[0210] The adjustment of the parameter of the processor is related to the specification attribute of the selected program slice (for example, the first instruction subset or the second instruction subset). For the program slice, the size of the number of instructions included and the proportion of target type instructions are key influencing factors for whether the program slice is more suitable for participating in the parameter tuning of the processor. Therefore, when the size of the number of instructions included in the program slice and the proportion of target type instructions are used to adjust the running parameter of the processor, a better tuning effect can be obtained.

[0211] The adjustment of the parameter of the processor is related to the specification attribute of the selected program slice (for example, the first instruction subset or the second instruction subset). For the program slice, the proportion of target type instructions is a key influencing factor for whether the program slice is more suitable for participating in the parameter tuning of the processor. Therefore, when the proportion of target type instructions of the program slice is used to adjust the running parameter of the processor, a better tuning effect can be obtained.

[0212] In a possible implementation, the number of instructions included in the first instruction subset can be used to adjust the running parameter of the processor through a first mapping relationship. The first mapping relationship indicates the corresponding relationship between the running parameter of the processor and the number of instructions.

[0213] The mapping relationship between the number of instructions included in the instruction subset and the running parameter of the processor can be preconfigured, and after the instruction subset participating in the parameter optimization of the processor (i.e., the first instruction subset) is determined, how the running parameter of the processor should be adjusted can be determined according to the mapping relationship between the number of instructions included in the target instruction subset and the running parameter of the processor. Compared with the prior art in which the adjustment mode of the running parameter of the processor needs to be known through complex processing of the program slice, in the embodiment of the present application, the adjustment mode of the running parameter of the processor can be determined from the first mapping relationship according to the number of instructions included in the target instruction subset, thereby reducing the processing complexity and improving the processing speed and real-time performance of the online processor optimization.

[0214] In a possible implementation, the running parameter of the processor can be adjusted according to the proportion of the target type instruction in the first instruction subset and through a second mapping relationship; the second mapping relationship indicates the corresponding relationship between the running parameter of the processor and the proportion of the target type instruction.

[0215] The mapping relationship between the proportion of the target type instruction in the instruction subset and the running parameter of the processor can be preconfigured, and after the instruction subset participating in the parameter optimization of the processor (i.e., the first instruction subset) is determined, how the running parameter of the processor should be adjusted can be determined according to the mapping relationship between the proportion of the target type instruction in the target instruction subset and the running parameter of the processor. Compared with the prior art in which the adjustment mode of the running parameter of the processor needs to be known through complex processing of the program slice, in the embodiment of the present application, the adjustment mode of the running parameter of the processor can be determined from the first mapping relationship according to the proportion of the target type instruction in the target instruction subset, thereby reducing the processing complexity and improving the processing speed and real-time performance of the online processor optimization.

[0216] In a possible implementation, the running parameter of the processor can be adjusted according to the number of instructions included in the first instruction subset and the proportion of the target type instruction and through a third mapping relationship; the third mapping relationship indicates the corresponding relationship between the running parameter of the processor and the number of instructions and the proportion of the target type instruction.

[0217] The mapping relationship between the proportion of the target type instructions in the target instruction subset and the running parameters of the processor can be preconfigured, and after the instruction subset participating in the parameter optimization of the processor (i.e., the first instruction subset) is determined, how the running parameters of the processor should be adjusted can be determined according to the mapping relationship between the proportion of the target type instructions in the target instruction subset and the running parameters of the processor. Compared with the prior art in which the adjustment mode of the running parameters of the processor needs to be known through complex processing of the program slice, in the embodiment of the present application, the adjustment mode of the running parameters of the processor can be determined from the first mapping relationship according to the proportion of the target type instructions in the target instruction subset, thereby reducing the processing complexity and improving the processing speed and real-time performance of the online processor optimization.

[0218] In a possible implementation, the running parameters of the processor can be adjusted according to the number of instructions included in the second instruction subset through the first mapping relationship, and the first mapping relationship indicates the corresponding relationship between the running parameters of the processor and the number of instructions.

[0219] The mapping relationship between the number of instructions included in the target instruction subset and the running parameters of the processor can be preconfigured, and after the instruction subset participating in the parameter optimization of the processor (i.e., the second instruction subset) is determined, how the running parameters of the processor should be adjusted can be determined according to the mapping relationship between the number of instructions included in the target instruction subset and the running parameters of the processor. Compared with the prior art in which the adjustment mode of the running parameters of the processor needs to be known through complex processing of the program slice, in the embodiment of the present application, the adjustment mode of the running parameters of the processor can be determined from the first mapping relationship according to the number of instructions included in the target instruction subset, thereby reducing the processing complexity and improving the processing speed and real-time performance of the online processor optimization.

[0220] In a possible implementation, the running parameters of the processor can be adjusted according to the proportion of the target type instructions in the second instruction subset through the second mapping relationship, and the second mapping relationship indicates the corresponding relationship between the running parameters of the processor and the proportion of the target type instructions.

[0221] The mapping relationship between the proportion of the target type instructions in the target instruction subset and the running parameters of the processor can be preconfigured. After the instruction subset participating in the parameter optimization of the processor (i.e., the second instruction subset) is determined, the adjustment manner of the running parameters of the processor can be determined according to the mapping relationship between the proportion of the target type instructions in the target instruction subset and the running parameters of the processor. Compared with the prior art in which the adjustment manner of the running parameters of the processor needs to be known through complex processing of the program slice, in the embodiment of the present application, the adjustment manner of the running parameters of the processor can be determined from the first mapping relationship according to the proportion of the target type instructions in the target instruction subset, thereby reducing the processing complexity and improving the processing speed and real-time performance of the online processor optimization.

[0222] In a possible implementation, the running parameters of the processor can be adjusted according to the number of instructions included in the second instruction subset and the proportion of the target type instructions, through a third mapping relationship. The third mapping relationship indicates the corresponding relationship between the running parameters of the processor and the number of instructions and the proportion of the target type instructions.

[0223] In a possible implementation, the mapping relationship between the number of instructions of the instruction subset, the proportion of the target type instructions, and the running parameters of the processor can be preconfigured. After the instruction subset participating in the parameter optimization of the processor (i.e., the third instruction subset) is determined, the adjustment manner of the running parameters of the processor can be determined according to the mapping relationship between the number of instructions of the target instruction subset, the proportion of the target type instructions, and the running parameters of the processor. Compared with the prior art in which the adjustment manner of the running parameters of the processor needs to be known through complex processing of the program slice, in the embodiment of the present application, the adjustment manner of the running parameters of the processor can be determined from the mapping relationship according to the number of instructions of the target instruction subset and the proportion of the target type instructions, thereby reducing the processing complexity and improving the processing speed and real-time performance of the online processor optimization.

[0224] In a possible implementation, the first instruction subset is one of the at least two instruction subsets in the first program instruction set; or the second instruction subset is one of the at least two instruction subsets in the second program instruction set.

[0225] In a possible implementation, the first instruction subset is selected from the multiple instruction subsets of the first program instruction set according to an optimizability of the processor when running the instruction subset, or the second instruction subset is selected from the multiple instruction subsets of the second program instruction set according to an optimizability of the processor when running the instruction subset, where the optimizability indicates an optimization degree of performance of the processor by adjusting parameters of the processor or registers related to the processor when running the instruction subset.

[0226] The instruction subset more suitable for participating in parameter tuning of the processor can be understood as follows: when the processor runs an instruction subset A, the processor has a higher optimizability than running other instruction subsets, and then the instruction subset A is the instruction subset more suitable for participating in parameter tuning of the processor. The optimizability indicates an optimization degree of a performance parameter of the processor by adjusting parameters of the processor or registers related to the processor when running the instruction subset. For a certain code set, by adjusting parameters of the processor or registers related to the processor, an optimization degree of a performance parameter of the processor is often higher (compared to other code sets). The code set with the above characteristics can be considered as a code set having a greater impact on the running performance of the processor. Parameter tuning of the processor according to the code set with the above characteristics can make the processor in a better state, that is, the running performance is higher.

[0227] In a possible implementation, the first instruction subset is selected from part of the multiple instruction subsets included in the first program instruction set, and the part of the multiple instruction subsets includes one or more instruction subsets in each category in a clustering result obtained by clustering the multiple instruction subsets of the first program instruction set; or the second instruction subset is selected from part of the multiple instruction subsets included in the second program instruction set, and the part of the multiple instruction subsets includes one or more instruction subsets in each category in a clustering result obtained by clustering the multiple instruction subsets of the second program instruction set.

[0228] To ensure that the finally selected target instruction subset is the instruction subset suitable for participating in the parameter tuning of the processor, the number of the candidate set needs to be set to be large (the more the candidate sets, the greater the probability of finally selecting a better instruction subset), however, when the number of the instruction subsets included in the candidate set (multiple instruction subsets) is too large (for example, thousands), the calculation power consumption of evaluating whether each instruction subset is suitable for participating in the parameter tuning of the processor is required, which leads to a large overall calculation power consumption. Therefore, in the embodiment of the present application, the candidate set needs to be screened first, and the number of the sets included in the candidate set is reduced (that is, a part of the instruction subsets are selected from the multiple instruction subsets), and then only a small number of candidate sets need to be selected to participate in the parameter tuning of the processor (that is, the first instruction subset or the second instruction subset is selected from the part of the instruction subsets), so that the overall calculation power consumption can be reduced.

[0229] Next, a data processing apparatus provided by an embodiment of the present application is introduced. Referring to FIG. 5, a data processing apparatus 500 provided by an embodiment of the present application includes:

[0230] An instruction selection module 501 is configured to determine multiple instruction subsets from a first program instruction set, wherein the number of instructions included between at least two instruction subsets in the multiple instruction subsets is different or the proportion of target type instructions is different, and a target instruction subset is selected from the multiple instruction subsets.

[0231] The specific description of the instruction selection module 501 can be referred to the introduction of steps 201 and 202 in the above embodiments, and the similar parts will not be described here.

[0232] A parameter adjustment module 502 is configured to adjust the running parameter of the processor running the first program instruction set according to the target instruction subset.

[0233] The specific description of the parameter adjustment module 502 can be referred to the introduction of step 203 in the above embodiments, and the similar parts will not be described here.

[0234] In a possible implementation, the adjustment of the running parameter of the processor is related to the number of instructions included in the target instruction subset; or,

[0235] The adjustment of the running parameter of the processor is related to the proportion of target type instructions according to the target instruction subset; or,

[0236] The adjustment of the running parameter of the processor is related to the number of instructions included in the target instruction subset and the proportion of target type instructions.

[0237] In a possible implementation, the parameter adjustment module 502 is specifically configured to: according to the number of instructions included in the target instruction subset, adjust the running parameter of the processor through a first mapping relationship; the first mapping relationship indicates a corresponding relationship between the running parameter of the processor and the number of instructions.

[0238] In a possible implementation, the parameter adjustment module 502 is specifically configured to: according to the proportion of target type instructions in the target instruction subset, adjust the running parameter of the processor through a second mapping relationship; the second mapping relationship indicates a corresponding relationship between the running parameter of the processor and the proportion of target type instructions.

[0239] In a possible implementation, the parameter adjustment module 502 is specifically configured to: according to the number of instructions included in the target instruction subset and the proportion of target type instructions, adjust the running parameter of the processor through a third mapping relationship; the third mapping relationship indicates a corresponding relationship between the running parameter of the processor and the number of instructions and the proportion of target type instructions.

[0240] In a possible implementation, the target instruction subset is one of the at least two instruction subsets.

[0241] In a possible implementation, the target instruction subset is selected from the plurality of instruction subsets according to an optimizable degree of the processor when running an instruction subset; wherein the optimizable degree indicates an optimization amplitude of a performance parameter of the processor by adjusting a parameter of the processor or a register related to the processor when running an instruction subset.

[0242] In a possible implementation, the instruction selection module 501 is specifically configured to:

[0243] select a part of instruction subsets from the plurality of instruction subsets;

[0244] select a target instruction subset from the part of instruction subsets.

[0245] In a possible implementation, the selecting a target instruction subset from the part of instruction subsets comprises:

[0246] selecting a target instruction subset from the part of instruction subsets according to an optimizable degree of the processor when running each instruction subset in the part of instruction subsets.

[0247] In a possible implementation, the target instruction subset is selected from part of instruction subsets in the plurality of instruction subsets, and the part of instruction subsets comprises one or more instruction subsets in each category of a clustering result obtained by clustering the plurality of instruction subsets.

[0248] In a possible implementation, the instruction selection module 501 is specifically configured to:

[0249] obtain a plurality of candidate instruction features of each of the instruction subsets and performance of the processor when the instruction subsets are executed;

[0250] select part of the plurality of candidate instruction features, so that there is a difference in performance between instruction subsets of different categories in a clustering result obtained by clustering the plurality of instruction subsets according to the part of the instruction features.

[0251] In a possible implementation, the performance is instructions per cycle (IPC).

[0252] In a possible implementation, the running parameter includes at least one of a working frequency and a working voltage of the processor. In a possible implementation, the instruction selection module 501 is configured to determine a first instruction subset from a first set of program instructions; and determine a second instruction subset from a second set of program instructions; wherein the second set of program instructions is a set of program instructions that needs to be executed after the first set of program instructions, the first instruction subset and the second instruction subset include different numbers of instructions, or the first instruction subset and the second instruction subset include different proportions of target type instructions.

[0253] For specific descriptions of the instruction selection module 501, refer to the descriptions of steps 401 and 403 in the above embodiments, and similar parts are not described herein.

[0254] The parameter adjustment module 502 is configured to adjust a running parameter of the processor according to the first instruction subset; and adjust the running parameter of the processor according to the second instruction subset.

[0255] For specific descriptions of the parameter adjustment module 502, refer to the descriptions of steps 402 and 404 in the above embodiments, and similar parts are not described herein.

[0256] In a possible implementation, the instruction selection module 501 is specifically configured to:

[0257] determine a plurality of instruction subsets from a first set of program instructions to be executed; wherein the plurality of instruction subsets include different numbers of instructions or different proportions of target type instructions between at least two of the plurality of instruction subsets in the first set of program instructions, and the first instruction subset is selected from the plurality of instruction subsets determined from the first set of program instructions, or

[0258] determine a plurality of instruction subsets from a second set of program instructions to be executed; wherein a number of instructions included between at least two instruction subsets of the plurality of instruction subsets of the second set of program instructions is different, or a proportion of target type instructions is different, select a second instruction subset from the plurality of instruction subsets determined from the second set of program instructions.

[0259] In a possible implementation, the adjustment of the running parameter of the processor is related to the number of instructions included in the first instruction subset or the proportion of target type instructions in the first instruction subset; or,

[0260] The adjustment of the running parameter of the processor is related to the number of instructions included in the second instruction subset or the proportion of target type instructions in the second instruction subset.

[0261] In a possible implementation, the parameter adjustment module 502 is configured to:

[0262] adjust the running parameter of the processor according to the number of instructions included in the first instruction subset by a first mapping relationship; the first mapping relationship indicates a corresponding relationship between the running parameter of the processor and the number of instructions; or,

[0263] adjust the running parameter of the processor according to the proportion of target type instructions in the first instruction subset by a second mapping relationship; the second mapping relationship indicates a corresponding relationship between the running parameter of the processor and the proportion of target type instructions; or,

[0264] adjust the running parameter of the processor according to the number of instructions included in the first instruction subset and the proportion of target type instructions by a third mapping relationship; the third mapping relationship indicates a corresponding relationship between the running parameter of the processor and the number of instructions and the proportion of target type instructions.

[0265] In a possible implementation, the parameter adjustment module 502 is configured to:

[0266] adjust the running parameter of the processor according to the number of instructions included in the second instruction subset by a first mapping relationship; the first mapping relationship indicates a corresponding relationship between the running parameter of the processor and the number of instructions; or,

[0267] adjust the running parameter of the processor according to the proportion of target type instructions in the second instruction subset by a second mapping relationship; the second mapping relationship indicates a corresponding relationship between the running parameter of the processor and the proportion of target type instructions; or,

[0268] According to the number of instructions included in the second instruction subset and the proportion of target type instructions, a third mapping relationship is used to adjust the running parameter of the processor, the third mapping relationship indicating a corresponding relationship between the running parameter of the processor and the number of instructions and the proportion of target type instructions.

[0269] In a possible implementation, the first instruction subset is one of the at least two instruction subsets in the first program instruction set, or

[0270] The second instruction subset is one of the at least two instruction subsets in the second program instruction set.

[0271] In a possible implementation, the first instruction subset is selected from the multiple instruction subsets of the first program instruction set according to an optimizability of the processor when running an instruction subset, or the second instruction subset is selected from the multiple instruction subsets of the second program instruction set according to the optimizability of the processor when running an instruction subset.

[0272] The optimizability indicates an optimization amplitude of performance of the processor when running an instruction subset by adjusting a parameter of the processor or a register related to the processor.

[0273] In a possible implementation, the first instruction subset is selected from part of the multiple instruction subsets included in the first program instruction set, the part of the multiple instruction subsets including one or more instruction subsets in each category in a clustering result obtained by clustering the multiple instruction subsets of the first program instruction set, or

[0274] The second instruction subset is selected from part of the multiple instruction subsets included in the second program instruction set, the part of the multiple instruction subsets including one or more instruction subsets in each category in a clustering result obtained by clustering the multiple instruction subsets of the second program instruction set.

[0275] In a possible implementation, the performance is instructions per cycle (IPC).

[0276] In a possible implementation, the running parameter includes at least one of a working frequency and a working voltage of the processor.

[0277] Referring to FIG. 6, FIG. 6 is a structural schematic diagram of a computing device provided in the present application. The computing device 600 shown in FIG. 6 can be used to execute the data processing method provided in the present application. As shown in FIG. 6, the computing device 600 includes a bus 602, a processor 604, a memory 606, and a communication interface 608. The processor 604, the memory 606, and the communication interface 608 communicate with each other through the bus 602. The computing device 600 can be a server or a terminal device. It should be understood that the number of processors, accelerators, and memories in the computing device 600 is not limited in the present application.

[0278] The bus 602 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one line is shown in FIG. 6, but it does not mean that there is only one bus or only one type of bus. The bus 602 can include a path for transmitting information between various components (for example, the memory 606, the processor 604, the communication interface 608) of the computing device 600.

[0279] The processor 604 can include any one or more of a central processing unit (CPU), a microprocessor (MP), or a digital signal processor (DSP), an accelerator (for example, a graphics processing unit (GPU), a neural network processing unit (NPU)), and the like.

[0280] The memory 606 can include a volatile memory (for example, a random access memory (RAM)). The processor 604 can also include a non-volatile memory (for example, a read-only memory (ROM), a flash memory, a mechanical hard disk drive (HDD), or a solid state drive (SSD)).

[0281] The executable program code is stored in the memory 606, and the processor 604 executes the executable program code to implement the data processing method described above. That is, the program code for executing the data processing method is stored on the memory 606.

[0282] The communication interface 608 uses a transceiving module such as, but not limited to, a network interface card and a transceiver to implement communication between the computing device 600 and other devices or communication networks.

[0283] It should be understood that the computing device 600 according to the present application is used to execute the data processing method as shown in FIGS. 2 to 4A, and can correspond to the respective subjects executing the method according to the present application. For the sake of brevity, details are not repeated here.

[0284] The present application also provides a computing device cluster. The computing device cluster includes a plurality of computing devices. The computing device can be a server, such as a central server, an edge server, or a local server in a local data center. In some embodiments, the computing device can also be a terminal device such as a desktop computer, a notebook computer, or a smart phone.

[0285] Referring to FIG. 7, FIG. 7 is a structural schematic diagram of a computing device cluster provided by the present application. As shown in FIG. 7, the computing device cluster includes a plurality of computing devices 600. The memories 606 in the plurality of computing devices 600 in the computing device cluster can store the same instructions for executing the data processing method. Among them, different computing devices 600 in the computing device cluster can be connected through a local area network.

[0286] In some possible implementations, the memories 606 of the plurality of computing devices 600 in the computing device cluster can also respectively store partial instructions for executing the data processing method. In other words, the combination of the plurality of computing devices 600 can collectively execute the instructions of the data processing method to adjust the parameters of one of the computing devices (which can be the processor of the execution subject of the data processing method, or other processors).

[0287] It should be noted that the memories 606 in different computing devices 600 in the computing device cluster can store different instructions, respectively used to execute part of the functions of the data processing method provided by the embodiments of the present application.

[0288] In some possible implementation, one or more of the computing devices 600 in the computing device cluster can execute the step of determining the adjustment parameter of the processor in the data processing method provided in the present application as a management node, and perform parameter tuning on one or more processors in the computing device cluster based on the execution result. For example, one or more of the computing devices 600 in the computing device cluster can obtain program instructions to be executed by one or more processors in the computing device cluster, determine a parameter adjustment strategy of the processor according to the program instructions, and perform parameter tuning on one or more processors in the computing device cluster based on the parameter adjustment strategy.

[0289] In some possible implementation, one or more of the computing devices in the computing device cluster can be connected through a network. The network can be a wide area network, etc. FIG. 8 shows a possible implementation. FIG. 8 is a structural schematic diagram of another computing device cluster provided in the present application. As shown in FIG. 8, in the computing device cluster 800, two computing devices 600A and 600B are connected through a network. Specifically, the computing devices are connected to the network through the communication interfaces in the computing devices.

[0290] It should be understood that the method in the embodiments of the present application can be completed by the processors of multiple computing devices, that is, distributed computing is used, for example, the functions of the computing device 600A shown in FIG. 8 can also be completed by multiple computing devices 600. Similarly, the functions of the computing device 600B can also be completed by multiple computing devices 600.

[0291] In some possible implementation, one or more of the computing devices (for example, 600A or 600B) in the computing device cluster can execute the step of determining the adjustment parameter of the processor in the data processing method provided in the present application as a management node, and perform parameter tuning on one or more processors in the computing device cluster based on the execution result. For example, one or more of the computing devices (for example, 600A or 600B) in the computing device cluster can obtain program instructions to be executed by one or more processors in the computing device cluster, determine a parameter adjustment strategy of the processor according to the program instructions, and perform parameter tuning on one or more processors in the computing device cluster based on the parameter adjustment strategy.

[0292] It should be understood that the computing device 600 in the present application, the computing device cluster in FIG. 7, or the computing device cluster 800 can correspond to the data processing apparatus in FIG. 6 of the present application, and can correspond to a corresponding subject that executes the data processing method in FIG. 2 of the present application. Moreover, the above and other operations and / or functions of each module in the computing device 600 or the computing device cluster 800 are respectively for realizing the corresponding processes of the data processing method in FIG. 2, and for brevity, will not be described herein again.

[0293] Referring to FIG. 9, a schematic diagram of a computer-readable storage medium is provided. The present application also provides a computer-readable storage medium, in some embodiments, the method disclosed in FIG. 3A above can be implemented as computer program instructions encoded on a computer-readable storage medium or on other non-transitory media or articles of manufacture in a machine-readable format.

[0294] FIG. 9 schematically shows a conceptual, partially diagrammatic plan view of an example computer-readable storage medium arranged in accordance with at least some embodiments shown and described herein, the example computer-readable storage medium including computer program for executing a computer process on a computing device.

[0295] In one embodiment, the computer-readable storage medium 900 is provided using a signal bearing medium 901. The signal bearing medium 901 can include one or more program instructions 902 that, when executed by one or more processors, can provide at least some of the functionality described above with respect to FIG. 3A.

[0296] In some examples, the signal bearing medium 901 can embody a computer-readable medium 903, such as, but not limited to, a hard disk drive, a compact disk (CD), a digital video disk (DVD), a digital tape, memory, ROM, RAM, or the like.

[0297] In some implementations, the signal bearing medium 901 can embody a computer- recordable medium 904, such as, but not limited to, memory, a read / write (R / W) CD, a R / W DVD, and the like. In some implementations, the signal bearing medium 901 can embody a communication medium 905, such as, but not limited to, a digital and / or an analog communication medium (e.g., a fiber optic cable, a waveguide, a wired communication link, a wireless communication link, and the like). Thus, for example, the signal bearing medium 901 can be conveyed by a wireless form of the communication medium 905 (e.g., a wireless communication medium complying with the IEEE 1202.X standard or another transmission protocol).

[0298] The one or more program instructions 902 can be, for example, computer-executable instructions or logic-implementing instructions. In some examples, a computing device of a computing device can be configured to provide various operations, functions, or actions in response to the program instructions 902 being conveyed to the computing device by one or more of the computer-readable medium 903, the computer-recordable medium 904, and / or the communication medium 905.

[0299] In addition, it should be noted that the apparatus embodiments described above are merely illustrative, and units described as separate components can or can not be physically separate, and components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment. In addition, the connection relationship between the modules in the apparatus embodiments provided in the present application indicates that there is a communication connection between them, which can be implemented as one or more communication buses or signal lines.

[0300] Through the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software and the necessary general hardware, and of course can also be implemented by special hardware including special integrated circuits, special CPUs, special memories, special components, etc. Generally, functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structure for implementing the same function can also be various, such as analog circuits, digital circuits or special circuits. However, for the present application, software program implementation is a better embodiment. Based on this understanding, the technical solutions of the present application or the parts that contribute to the related art can be embodied in the form of software products, which are stored in readable storage media, such as computer floppy disks, U disks, mobile hard disks, ROM, RAM, magnetic or optical disks, etc., including a number of instructions to make a computer device (which can be a personal computer, a training device, or a network device, etc.) execute the methods of various embodiments of the present application.

[0301] In the above embodiments, all or part can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in the form of a computer program product in whole or in part.

[0302] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from one website, computer, training device or data center to another website, computer, training device or data center through wired (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can store or be integrated into a data storage device such as a training device, a data center, etc. containing one or more available media sets. The available media can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)), etc.

[0303] The above is only a specific embodiment of the present application. Those skilled in the art can think of changes or replacements based on the specific embodiments provided by the present application, which should be covered within the protection scope of the present application.

Claims

A data processing method, characterized by, The method comprises: determining a first instruction subset from a first program instruction set to be executed; adjusting a running parameter of a processor running the first program instruction set according to the first instruction subset; determining a second instruction subset from a second program instruction set to be executed; wherein the second program instruction set is a program instruction to be executed after the first program instruction set, the first instruction subset and the second instruction subset comprise different numbers of instructions or different proportions of target type instructions; adjusting the running parameter of the processor according to the second instruction subset. The method of claim 1, wherein The determining of the first instruction subset from the first program instruction set to be executed comprises: determining a plurality of instruction subsets from the first program instruction set to be executed; wherein at least two instruction subsets among the plurality of instruction subsets comprise different numbers of instructions or different proportions of target type instructions in the first program instruction set, and the first instruction subset is selected from the plurality of instruction subsets determined from the first program instruction set, or The determining of the second instruction subset from the second program instruction set to be executed comprises: determining a plurality of instruction subsets from the second program instruction set to be executed; wherein at least two instruction subsets among the plurality of instruction subsets comprise different numbers of instructions or different proportions of target type instructions in the second program instruction set, and the second instruction subset is selected from the plurality of instruction subsets determined from the second program instruction set. According to the method of claim 1 or 2, wherein The adjustment of the running parameter of the processor is related to the number of instructions comprised in the first instruction subset or the proportion of target type instructions in the first instruction subset; or The adjustment of the running parameter of the processor is related to the number of instructions comprised in the second instruction subset or the proportion of target type instructions in the second instruction subset. The method according to any one of claims 1 to 3, characterized in that The adjusting of the running parameter of the processor running the first program instruction set according to the first instruction subset comprises: adjusting the running parameter of the processor according to the number of instructions comprised in the first instruction subset through a first mapping relationship; the first mapping relationship indicates a corresponding relationship between the running parameter of the processor and the number of instructions; or adjusting the running parameter of the processor according to the proportion of target type instructions in the first instruction subset through a second mapping relationship; the second mapping relationship indicates a corresponding relationship between the running parameter of the processor and the proportion of target type instructions; or adjusting the running parameter of the processor according to the number of instructions and the proportion of target type instructions comprised in the first instruction subset through a third mapping relationship; the third mapping relationship indicates a corresponding relationship between the running parameter of the processor and the number of instructions and the proportion of target type instructions. The method according to any one of claims 1 to 4, characterized in that The adjusting of the running parameter of the processor according to the second instruction subset comprises: adjust the running parameter of the processor according to the number of instructions included in the second instruction subset, by a first mapping relationship; the first mapping relationship indicates a corresponding relationship between the running parameter of the processor and the number of instructions; or adjust the running parameter of the processor according to the proportion of target type instructions in the second instruction subset, by a second mapping relationship; the second mapping relationship indicates a corresponding relationship between the running parameter of the processor and the proportion of target type instructions; or adjust the running parameter of the processor according to the number of instructions included in the second instruction subset and the proportion of target type instructions, by a third mapping relationship; the third mapping relationship indicates a corresponding relationship between the running parameter of the processor and the number of instructions and the proportion of target type instructions. The method according to any one of claims 2 to 5, characterized in that The first instruction subset is one of the at least two instruction subsets in the first program instruction set; or The second instruction subset is one of the at least two instruction subsets in the second program instruction set. The method according to any one of claims 1 to 6, characterized in that The first instruction subset is selected from the multiple instruction subsets of the first program instruction set according to an optimizable degree of the processor when running an instruction subset, or the second instruction subset is selected from the multiple instruction subsets of the second program instruction set according to an optimizable degree of the processor when running an instruction subset; The optimizable degree indicates an optimization amplitude of performance of the processor by adjusting a parameter of the processor or a register related to the processor when running an instruction subset. The method according to any one of claims 1 to 7, characterized in that The first instruction subset is selected from part of the multiple instruction subsets included in the first program instruction set, and the part of the multiple instruction subsets includes one or more instruction subsets in each category in a clustering result obtained by clustering the multiple instruction subsets of the first program instruction set; or The second instruction subset is selected from part of the multiple instruction subsets included in the second program instruction set, and the part of the multiple instruction subsets includes one or more instruction subsets in each category in a clustering result obtained by clustering the multiple instruction subsets of the second program instruction set. The performance is instructions per cycle (IPC). The method according to claim 7 or 8, characterized in that The running parameter includes at least one of a working frequency and a working voltage of the processor. The method according to any one of claims 1 to 9, characterized in that The method comprises: A data processing method, characterized by, determining multiple instruction subsets from a first program instruction set to be run; wherein the number of instructions included between at least two instruction subsets in the multiple instruction subsets is different or the proportion of target type instructions is different; selecting a target instruction subset from the multiple instruction subsets; adjusting a running parameter of a processor running the first program instruction set according to the target instruction subset. The method of claim 11, wherein the adjustment of the running parameter of the processor is related to the number of instructions included in the target instruction subset; or the adjustment of the running parameter of the processor is related to the proportion of target type instructions in the target instruction subset; or the adjustment of the running parameter of the processor is related to the number of instructions included in the target instruction subset and the proportion of target type instructions. The adjustment of the running parameter of the processor is related to the number of instructions included in the target instruction subset and the proportion of target type instructions. The method according to claim 11 or 12, characterized in that The adjustment of the running parameter of the processor running the first program instruction set according to the target instruction subset comprises: adjusting the running parameter of the processor according to the number of instructions included in the target instruction subset through a first mapping relationship; the first mapping relationship indicates the corresponding relationship between the running parameter of the processor and the number of instructions; or adjusting the running parameter of the processor according to the proportion of target type instructions in the target instruction subset through a second mapping relationship; the second mapping relationship indicates the corresponding relationship between the running parameter of the processor and the proportion of target type instructions; or adjusting the running parameter of the processor according to the number of instructions included in the target instruction subset and the proportion of target type instructions through a third mapping relationship; the third mapping relationship indicates the corresponding relationship between the running parameter of the processor and the number of instructions and the proportion of target type instructions. The method according to any one of claims 11 to 13, characterized in that The target instruction subset is selected from part of the instruction subsets in the plurality of instruction subsets, and the part of the instruction subsets comprises one or more instruction subsets in each category of a clustering result obtained by clustering the plurality of instruction subsets. The method of claim 14, wherein The method further comprises: obtaining a plurality of candidate instruction features of each of the instruction subsets and performance of the processor running the instruction subset; selecting part of the instruction features in the plurality of candidate instruction features so that there is a difference between instruction subsets of different categories in a clustering result obtained by clustering the plurality of instruction subsets according to the part of the instruction features. A data processing device, characterized by comprise: an instruction selection module configured to determine a first instruction subset from a first program instruction set; determine a second instruction subset from a second program instruction set; wherein the second program instruction set is a program instruction to be run after the first program instruction set, the number of instructions included in the first instruction subset and the second instruction subset is different, or the proportion of target type instructions in the first instruction subset and the second instruction subset is different; a parameter adjustment module configured to adjust the running parameter of the processor according to the first instruction subset and adjust the running parameter of the processor according to the second instruction subset. The apparatus of claim 16, wherein The instruction selection module is specifically configured to: determine a plurality of instruction subsets from a first program instruction set to be run; wherein the number of instructions included between at least two instruction subsets in the plurality of instruction subsets in the first program instruction set is different or the proportion of target type instructions is different, select a first instruction subset from the plurality of instruction subsets determined from the first program instruction set, or determine a plurality of instruction subsets from a second program instruction set to be run; wherein the number of instructions included between at least two instruction subsets in the plurality of instruction subsets in the second program instruction set is different or the proportion of target type instructions is different, select a second instruction subset from the plurality of instruction subsets determined from the second program instruction set. The apparatus according to claim 16 or 17, wherein The adjustment of the running parameter of the processor is related to the number of instructions included in the first instruction subset or the proportion of target type instructions in the first instruction subset; or The adjustment of the running parameter of the processor is related to the number of instructions included in the second instruction subset or the proportion of target type instructions in the second instruction subset. A computing device, characterized in that A computer device comprising a memory and a processor; the memory stores code, and the processor is configured to execute the code, and when the code is executed, the computer device executes the method according to any one of claims 1 to 15. A cluster of computing devices, characterized in that, One or more computer devices, each comprising a processor and a memory; The processor of the at least one computer device is configured to execute program code stored in the memory of the at least one computer device, so that the computer device cluster executes the operation steps of the method according to any one of claims 1 to 15. A computer program product, characterized in that The computer program product stores program code, and the instructions cause the computer to implement the method according to any one of claims 1 to 15 when executed by the computer.

Images