Power conversion device

Abstract

This power conversion device comprises: a first semiconductor switching element (51b) to which a diode is connected in an anti-parallel fashion; and second semiconductor switching elements (32a, 34b) disposed in the path of a current induced in association with the generation of a reverse recovery current flowing through the first semiconductor switching element. The power conversion device performs reverse recovery current suppression control in which the second semiconductor switching elements are operated in a saturation region by adjusting the drain-source voltages and gate-source voltages of the second semiconductor switching elements in accordance with bringing the first semiconductor switching element into an ON state from a state in which energization is performed in the forward direction of the diode and then the second semiconductor switching elements are brought into an ON state.

Description

Power conversion device

[0001] The present disclosure relates to a power conversion device.

[0002] An isolated DC / DC converter can provide electrical insulation between the input and output, protecting the operator and also protecting electrical equipment. In addition, the voltage ratio between the input and output can be easily varied according to the turns ratio of the isolation transformer. For these reasons, it is widely used in medical, industrial, communication fields, etc. On the other hand, the isolation transformer also hinders the miniaturization of the converter.

[0003] For example, when a full-bridge isolated DC / DC converter converts the input DC voltage to the output DC voltage, first, it is converted to AC once by alternately repeating the diagonal operation of the semiconductor switching elements configured in the full-bridge type on the primary side, and then rectified on the secondary side to be converted to a DC voltage. When this semiconductor switching element is turned on, the reverse recovery current of the secondary-side rectifying element becomes the switching loss of the primary-side semiconductor element, and the loss increases in proportion to the switching frequency. Therefore, although there is a possibility of miniaturizing magnetic components such as an isolation transformer if a high-frequency operation is realized, this has become an obstacle to its realization.

[0004] In the example of a non-isolated converter, in a circuit that continuously supplies or receives load power between the upper and lower arms, such as a one-switch boost chopper, buck chopper, inverter, etc., when switching from the state where the body diode is in the reverse recovery state to the state where the corresponding semiconductor switching element is turned on, switching loss due to the reverse recovery current occurs, which is a factor that reduces the efficiency of the power converter and hinders high-frequency operation. Furthermore, a high voltage is generated due to the recovery surge that occurs when the reverse recovery current ends, making it difficult to use low-voltage devices with low-loss characteristics.

[0005] In response to these challenges, prior art documents have described methods for reducing inverter recovery losses (for example, Patent Document 1). According to this document, a configuration is shown in which a MOSFET for the main current and a series configuration of a resistor and a MOSFET for suppressing reverse recovery current are connected in parallel in each arm of the inverter. In this configuration, during the initial recovery period when the arm turns on, only the MOSFET for suppressing reverse recovery current is turned on, and then the MOSFET for the main current is turned on while the MOSFET for suppressing reverse recovery current is turned off, thereby reducing the reverse recovery current.

[0006] Japanese Patent Publication No. 2008-148410

[0007] However, in the configuration shown in the above-mentioned literature, the MOSFET provided for suppressing reverse recovery current is in series with the resistor, and therefore this series configuration cannot function for power transmission and can only perform the single function of suppressing reverse recovery current. Consequently, it is necessary to provide a separate MOSFET for power transmission in parallel, which reduces implementation efficiency and prevents miniaturization of the power converter.

[0008] This disclosure was made to solve the above-mentioned problems, and aims to provide a compact power converter by suppressing the generation of reverse recovery current to reduce switching losses and improving mounting efficiency.

[0009] The power converter according to this disclosure is a power converter having a power converter in which a plurality of semiconductor switching elements are connected to each other, comprising: a first semiconductor switching element in which diodes are connected in antiparallel; a second semiconductor switching element arranged in the path of the current flowing through the first semiconductor switching element, or arranged in the path of the current induced by the generation of a reverse recovery current flowing through the first semiconductor switching element; and a control calculation unit that performs reverse recovery current suppression control to turn on the second semiconductor switching element after operating the second semiconductor switching element in the saturation region by adjusting the drain-source voltage and gate-source voltage of the second semiconductor switching element in conjunction with turning on the first semiconductor switching element from a state in which current is supplied in the forward direction of the diode.

[0010] The power conversion device of this disclosure includes a first semiconductor switching element in which diodes are connected in antiparallel, and a second semiconductor switching element arranged in the path of the current flowing through the first semiconductor switching element, or in the path of the current induced by the generation of a reverse recovery current flowing through the first semiconductor switching element. By performing reverse recovery current suppression control to turn on the second semiconductor switching element in a high-resistance saturation region in conjunction with turning on the first semiconductor switching element from a state in which the diode is energized in the forward direction, the reverse recovery current generated in the first semiconductor switching element can be suppressed and switching losses can be reduced.

[0011] Furthermore, instead of placing a resistor in series with the second semiconductor switching element, the drain-source voltage and gate-source voltage of the second semiconductor switching element are adjusted to operate the drain-source resistance in the saturation region, resulting in high resistance. By adjusting the drain-source voltage and gate-source voltage to operate in the linear region and achieve low resistance, the second semiconductor switching element can also be used for power transmission. Consequently, there is no need to separately provide a MOSFET for power transmission in parallel, and a compact power conversion device can be realized by improving mounting efficiency.

[0012] This is a diagram illustrating the configuration of a power converter according to Embodiment 1. This diagram shows the on / off states of each switching element of the DC / AC converter and the current path on the secondary side of the transformer in the power converter according to Embodiment 1. This diagram illustrates the current and switching loss generation in the power converter according to Embodiment 1, both when reverse recovery current is suppressed and when it is not. This diagram illustrates the structure of a planar nch MOSFET used in the power converter according to Embodiment 1. This diagram illustrates the characteristics of reverse recovery current and surge voltage in the power converter according to Embodiment 1. This diagram illustrates the definitions of saturation region operation and linear region operation of a MOSFET in the power converter according to Embodiment 1. This diagram illustrates the timing of saturation region operation and linear region operation of a MOSFET when reverse recovery current is suppressed in the power converter according to Embodiment 1. This diagram illustrates the operating timing of a MOSFET when reverse recovery current is not suppressed in the power converter according to Embodiment 1. This is a flowchart illustrating the control flow for switching between cases where reverse recovery current suppression control is performed and cases where it is not performed in the power converter according to Embodiment 1. This is a diagram illustrating the configuration of a power converter according to Embodiment 2. This figure illustrates the timing of the MOSFET's saturation region operation and linear region operation when reverse recovery current is suppressed in the power conversion device according to Embodiment 2. This figure illustrates the timing of the MOSFET's operation when reverse recovery current is not suppressed in the power conversion device according to Embodiment 2. This is a configuration diagram of the power conversion device according to Embodiment 3. This figure illustrates the timing of the MOSFET's saturation region operation and linear region operation when reverse recovery current is suppressed in the power conversion device according to Embodiment 3. This figure illustrates the timing of the MOSFET's operation when reverse recovery current is not suppressed in the power conversion device according to Embodiment 3. This figure shows the hardware configuration of the control calculation unit in the power conversion device according to Embodiments 1 to 3.

[0013] Hereinafter, preferred embodiments of the power conversion device according to this disclosure will be described with reference to the drawings. The same parts and components will be denoted by the same reference numerals, and their detailed descriptions will be omitted.

[0014] <Embodiment 1> <Circuit Configuration> Figure 1 is a diagram showing the circuit configuration of a power conversion device according to Embodiment 1 of the present disclosure. As shown in this figure, the DC voltage source 1 is input to the DC / AC converter 3 via the link capacitor 2. The DC / AC converter 3 is configured by connecting in parallel a plurality of switching legs (a series arrangement of upper and lower arms) in which switching elements with diodes connected in antiparallel are connected in series, and in Figure 1 it is configured with four switching legs 31 to 34.

[0015] Switching leg 31 has switching elements 31a and 31b connected in series, switching leg 32 has switching elements 32a and 32b connected in series, switching leg 33 has switching elements 33a and 33b connected in series, and switching leg 34 has switching elements 34a and 34b connected in series. Furthermore, the upper and lower arms of switching leg 31 and the upper and lower arms of switching leg 32 are connected to point A of the primary winding 41 of transformer 4. In addition, the upper and lower arms of switching leg 33 and the upper and lower arms of switching leg 34 are connected to point B, which is the other end of the primary winding 41 of transformer 4.

[0016] The AC / DC converter 5 consists of two bridge-type switching legs 51 and 52, each comprising switching elements with diodes connected in antiparallel and connected in series. Here, switching leg 51 has switching elements 51a and 51b connected in series, and switching leg 52 has switching elements 52a and 52b connected in series. Furthermore, the space between the upper and lower arms of switching leg 51 is connected to point C of the secondary winding 42 of the transformer 4, and the space between the upper and lower arms of switching leg 52 is connected to point D, which is the other end of the secondary winding 42 of the transformer 4.

[0017] The output of the AC / DC converter 5 is supplied to the output capacitor 7 and output load 8 via the reactor 6. In this configuration, the side from the primary winding 41 of the transformer 4 to the DC voltage source 1 is referred to as the primary side, and the side from the secondary winding 42 of the transformer 4 to the output load 8 is referred to as the secondary side.

[0018] The surge clamp circuit 10 installed on the secondary side will now be described. The surge clamp circuit 10 consists of a diode 10a, a capacitor 10b, and a resistor 10c. Here, one end of the capacitor 10b and one end of the resistor 10c are connected to the cathode terminal of the diode 10a. The anode of the diode 10a is connected between the positive terminal of the AC / DC converter 5 (the drain of the switching elements 51a and 52a) and the reactor 6. Furthermore, the other end of the capacitor 10b is connected to the negative terminal of the AC / DC converter 5 (the source of the switching elements 51b and 52b), and the other end of the resistor 10c is connected between the reactor 6, the output capacitor 7, and the output load 8.

[0019] As described above, when the surge clamp circuit 10 is configured, the surge current generated at the positive terminal of the AC / DC converter 5 is stored in the capacitor 10b through the diode 10a, and a voltage (clamp voltage) corresponding to the stored charge is generated between the two terminals of the capacitor, and this voltage is clamped (held). Subsequently, current flows from the capacitor 10b through the resistor 10c to the output load 8.

[0020] In this figure, the switching element is explained using a MOSFET (Metal-oxide-Semiconductor Field-Effect Transistor), which is an insulated-gate field-effect transistor with diodes connected in antiparallel. However, it may also be an IGBT (Insulated Gate Bipolar Transistor), which is an insulated-gate bipolar transistor with diodes connected in antiparallel, and the switching element can be monopolar or bipolar. Also, in this figure, the DC / AC converter 3 is composed of four parallel switching legs, and each arm is shown in a configuration of two in parallel, but it may be composed of three or more arms by increasing the number of parallel switching legs.

[0021] Furthermore, although the AC / DC converter 5 of the secondary circuit is shown as a synchronous rectification type full bridge example, it may also be a diode rectifier instead of synchronous rectification, and any rectifier circuit that converts AC to DC, such as a center-tapped circuit with an intermediate tap on the secondary winding 42 of the transformer 4, is acceptable.

[0022] The control calculation unit 9 takes the input voltage Vin and input current Iin from the DC voltage source 1, the output voltage Vout and output current Iout supplied to the output load 8, and the surge clamp voltage Vsrg of the surge clamp circuit 10 as inputs to perform gate control of the switching elements that make up the DC / AC converter 3 and the AC / DC converter 5.

[0023] <Reverse Recovery Current Generation Situation> Next, we will explain the reverse recovery current generated in the circuit configuration shown in Figure 1. In the power converter shown in Figure 1, the upper and lower arms of the switching legs 31, 32 and 33, 34 of the DC / AC converter 3 operate diagonally via the primary winding 41 of the transformer 4. As a result, the voltage from the DC voltage source 1 is alternately applied between A and B of the primary winding 41 of the transformer 4, and an AC voltage is generated between C and D of the secondary winding 42 of the transformer 4, corresponding to the turns ratio of the primary winding 41 and the secondary winding 42. This AC voltage is rectified by the AC / DC converter 5, smoothed by the reactor 6 and output capacitor 7, and DC power is supplied to the output load 8. In the DC / AC converter 3 shown in Figure 1, diagonal operation means that the switching elements positioned diagonally in Figure 1, which shows the configuration of the DC / AC converter 3, operate alternately in pairs, such as the operation of the switching element pair 31a and 33b in relation to the operation of the switching element pair 33a and 31b, and the operation of the switching element pair 32a and 34b in relation to the operation of the switching element pair 34a and 32b.

[0024] Next, the states of the switching elements constituting the DC / AC converter 3, the current path flowing on the secondary side of the transformer 4, and the reverse recovery current will be explained using Figure 2. For convenience, in Figure 2, "switching" is abbreviated as "SW," and only the symbols are shown for the switching elements 31a to 34b. Figure 2 is a table showing the on / off states of each switching element constituting the DC / AC converter 3, corresponding to each state of the DC / AC converter 3 from M1 to M7, and the state of the current path on the secondary side of the transformer 4 at that time. The states of each state from M1 to M7 will be explained below based on this figure.

[0025] In state M1, the DC / AC converter 3 has switching elements 31a, 32a, 33b, and 34b turned on, and switching elements 33a, 34a, 31b, and 32b turned off. Meanwhile, in the secondary circuit of the transformer 4, a voltage is generated at point C of the secondary winding 42, and the current returns from point C to point C via switching element 51a, reactor 6, output capacitor 7, output load 8, switching element 52b, and point D of the secondary winding 42 of the transformer 4.

[0026] In state M2, the DC / AC converter 3 has switching elements 31a, 32a, 33b, and 34b changing from on to off, with switching elements 33a, 34a, 31b, and 32b being in the off state. Meanwhile, in the secondary circuit of the transformer 4, the reactor 6 acts as the current source, and the current returns to point C from point C, passing through switching element 51a, reactor 6, output capacitor 7, output load 8, switching element 52b, and point D of the secondary winding 42 of the transformer 4, similar to state M1.

[0027] State M3 is the state in which the switching element 52b is in the reverse recovery state, and the DC / AC converter 3 has the switching elements 31a, 32a, 33b, and 34b in the off state, and the switching elements 33a, 34a, 31b, and 32b have switched from off to on. At this time, due to the induced voltage generated at point D of the secondary winding 42 of the transformer 4, the current follows a current path from point D of the secondary winding 42 of the transformer 4, through the switching elements 52b, 51b, and point C, and returns to point D, as the reverse recovery current of the body diode of the switching element 52b.

[0028] In state M4, the DC / AC converter 3 has switching elements 31a, 32a, 33b, and 34b in the off state, and switching elements 33a, 34a, 31b, and 32b in the on state. Meanwhile, in the secondary circuit of the transformer 4, the reverse recovery of the body diode of switching element 52b has finished, and the drain-source junction is no longer in a low impedance state. As a result, a voltage is generated at point D of the secondary winding 42, and the current returns from point D to point D via switching element 52a, reactor 6, output capacitor 7, output load 8, switching element 51b, and point C of the secondary winding 42 of the transformer 4.

[0029] In state M5, the DC / AC converter 3 has switching elements 31a, 32a, 33b, and 34b turned off, and switching elements 33a, 34a, 31b, and 32b switched from on to off. Meanwhile, in the secondary circuit of the transformer 4, the reactor 6 acts as the current source, and the current returns to point D from point D, passing through switching element 52a, reactor 6, output capacitor 7, output load 8, switching element 51b, and point C of the secondary winding 42 of the transformer 4, similar to state M4.

[0030] State M6 is the state in which the switching element 51b is reverse-recovered. In the DC / AC converter 3, the switching elements 33a, 34a, 31b, and 32b are in the off state, and the switching elements 31a, 32a, 33b, and 34b are switched from off to on. At this time, the induced voltage generated at point C of the secondary winding 42 of the transformer 4 causes the current to return to point C as the reverse recovery current of the body diode of the switching element 51b, following a current path from point C of the secondary winding 42 of the transformer 4, through the switching elements 51b, 52b, and point D, back to point C.

[0031] In state M7, the DC / AC converter 3 has switching elements 31a, 32a, 33b, and 34b turned on, and switching elements 33a, 34a, 31b, and 32b turned off. Meanwhile, in the secondary circuit of the transformer 4, the reverse recovery of the body diode of switching element 51b has finished, and the drain-source junction is no longer in a low impedance state. As a result, a voltage is generated at point C of the secondary winding 42, and the current returns from point C to point C via switching element 51a, reactor 6, output capacitor 7, output load 8, switching element 52b, and point D of the secondary winding 42 of the transformer 4.

[0032] As shown above, state M3 in Figure 2 is a state in which a reverse recovery current is generated in the switching element 52b of the lower arm of the secondary AC / DC converter 5, and state M4 is a state in which a reverse recovery current is generated in the switching element 51b. Furthermore, Figure 3 shows a schematic diagram of the switching loss generated in the secondary AC / DC converter 5 when the peak of this reverse recovery current is denoted as Irr1, and the current when this reverse recovery current is suppressed by the method described later is denoted as Irr2. Since the switching loss is the integral of the product of the voltage and current that are in a fluctuating process during switching, if the peak of the reverse recovery current is large, the recovery loss, which is the switching loss, will also be large.

[0033] Figure 4 shows a cross-sectional view of an n-channel MOSFET 100 having a typical planar structure. It has a configuration in which an n- drift layer 103, made by lowering the impurity concentration of the n-type semiconductor to approach that of an intrinsic semiconductor, is provided between a p-type semiconductor (p-layer) 101 and an n-type semiconductor (n+ layer) 102. When a voltage is applied to the gate 104, the p-layer 105 directly below the gate inverts to n, forming an n-channel from the drain 106 to the source 107, thus enabling conduction (drain-source current Ids: 108 when switched on).

[0034] At this time, as can be seen from the figure, a pn junction is formed between the source 107 and the drain 106, and a parasitic body diode 109 and a parasitic npn transistor 110 are formed, through which current flows from the source 107 to the drain 106. In Figure 4, state M2 in Figure 2 is the state in which a forward current flows through the body diode 109 of the switching element 52b, and the drift layer 103 is filled with holes and electrons, which are carriers. Also, state M3 in Figure 2 is when a voltage is applied to the drain 106 terminal of the switching element 52b, the body diode 109 is reverse-biased, and a reverse recovery current flows as carriers are released from the drift layer 103, and the reverse recovery operation continues until this current becomes zero.

[0035] The time process of this reverse recovery operation is shown in Figure 5. The upper part of Figure 5 shows the voltage between the drain 106 and source 107 of the MOSFET, and the lower part shows the current of the body diode 109. The solid line shows the time response when the reverse recovery current is not suppressed, and the dashed line shows the time response when the reverse recovery current is suppressed. The operation of the body diode 109 of the switching element 52b, which performs reverse recovery operation from state M2 to M3 in Figure 2, will be used as an example to explain the response in each section. Note that although several timing charts will be shown from here on, the symbols representing time or levels shown on the horizontal and vertical axes of these timing charts are, in principle, specific to that particular chart and do not necessarily show the same values ​​across multiple charts.

[0036] (Between t0 and t1) This is the period in which a forward voltage VF is applied to the body diode 109 and a forward current IF flows. (Between t1 and t2) At t1, the forward current IF decreases to zero at terminal D of the secondary winding 42 of the transformer 4 due to the induced voltage from the primary winding 41, with a slope of dIF1 / dt. This is the period in which the forward voltage VF of the body diode becomes zero as the current decreases.

[0037] (Between t2 and t3) The body diode 109 is reverse-biased, and of the carriers in the drift layer 103 in Figure 4, holes are discharged to the source 107 and electrons to the drain 106, so a reverse current flows through the body diode 109 from the cathode to the anode with a slope of dIF1 / dt. At this time, if the slope of dIF1 / dt is large, the movement of carriers is accelerated, the peak of the reverse current Irr1 becomes large, and at the same time the carrier discharge time is shortened, and the time of reverse recovery is shortened. As long as a certain amount of carriers in the drift layer 103 are not discharged, the impedance between the drain 106 and source 107 is low, so this is a section in which the voltage does not rise.

[0038] (Between t3 and t4) In Figure 4, carrier discharge from the drift layer 103 progresses, and the reverse recovery current decreases with a slope of dIR1 / dt. At the same time, the drain voltage begins to increase. This voltage causes a depletion layer to spread between the p layer 101 and the n- drift layer 103, and the voltage between the drain 106 and source 107 is maintained and rises. If the slope of the reverse recovery current is dIR1 / dt and the external inductance is L, then a recovery surge Vsrg1 is generated at the end of the reverse recovery current due to a back electromotive force of LdIR1 / dt.

[0039] (Between t4 and t5) This is the period during which carriers are discharged when residual carriers are generated locally due to reasons such as a short carrier discharge time. In the above explanation, during the period from t3 to t5, if a high voltage is applied between drain 106 and source 107 while residual carriers are present, a localized electric field concentration occurs, so suppressing recovery surges is a desirable state for the reliability of the semiconductor.

[0040] The reverse recovery period is influenced by the slopes of dIF1 / dt and dIR1 / dt. A larger slope in dIF1 / dt leads to a larger slope in dIR1 / dt, resulting in a larger recovery surge. Additionally, the recovery loss increases because Irr1, the peak current of reverse recovery, becomes larger. The high dV / dt characteristics associated with the recovery surge increase the likelihood of dV / dt breakdown, where the parasitic npn transistor 110 shown in Figure 4 turns on and short-circuits due to the displacement current flowing through the parasitic capacitance (Cds) 111. This is also undesirable for the noise performance of the converter.

[0041] <Reverse Recovery Current Suppression Status> The dashed curve in Figure 5 shows the voltage and current conditions when reverse recovery current is suppressed. To show the difference in characteristics with and without reverse recovery current suppression, the time corresponding to the operation when reverse recovery current is not suppressed is shown with an apostrophe ', and the time corresponding to the operation when reverse recovery current is suppressed is shown with an apostrophe '. Specifically, this means that t2 when reverse recovery current is not suppressed becomes t2' when reverse recovery current is suppressed, t3 becomes t3', t4 becomes t4', and t5 becomes t5'.

[0042] By suppressing the reverse recovery current, the slope of the reverse recovery current, dIF1 / dt, becomes smaller, becoming dIF2 / dt and dIR1 / dt becomes smaller, becoming dIR2 / dt. As shown in Figure 3, the peak current during recovery decreases, and the recovery loss, which is a switching loss, decreases. In addition, the recovery surge Vsrg1 becomes smaller, becoming Vsrg2, which mitigates localized electric field concentration on the semiconductor. Furthermore, as the slope of dV1 / dt becomes smaller, becoming dV2 / dt, the displacement current flowing through the parasitic capacitance 111 also decreases, making it more difficult for the parasitic npn transistor to turn on.

[0043] Next, Figure 6 shows the characteristics of the drain 106 / source 107 voltage Vds and drain 106 / source 107 current Ids of the MOSFET. The Vds-Ids characteristics of the MOSFET can be divided into three operating regions: the cutoff region, the linear region, and the saturation region.

[0044] The cutoff region operation is a region where the voltage Vgs between the gate 104 and the source 107 is smaller than the gate-source threshold voltage Vth (Vgs < Vth), and the p-layer 101 directly under the gate shown in FIG. 4 does not become the n-channel conduction layer 105, and only a small leakage current occurs between the drain 106 and the source 107.

[0045] The linear region operation is a region where the condition for the channel to conduct, Vgs > Vth, is satisfied, and as the voltage Vds between the drain 106 and the source 107 increases, the drain current Ids increases. In this region, the p-layer directly under the gate shown in FIG. 4 uniformly changes to the n-channel conduction layer 105, the change in Ids with respect to the change in Vds is large, and the on-resistance of the FET is small.

[0046] The saturation region operation is a region where the condition for the channel to conduct, Vgs > Vth, is satisfied. When the voltage Vds between the drain 106 and the source 107 becomes high, the depletion layer spreads from the drain 106 end, and the inverted n-layer 105 from the p-layer directly under the gate shown in FIG. 4 is pinched off and the conduction layer is interrupted. Therefore, the drain-source current Ids does not change with respect to the voltage Vds between the drain 106 and the source 107, and this region is where the current changes with the gate voltage, and it is an operating region with a high on-resistance.

[0047] Therefore, the linear region operation and the saturation region operation mean that when the condition for the channel to conduct, Vgs > Vth, is satisfied, the state of operating at a Vds voltage lower than the pinch-off voltage (Vp = Vgs - Vth) is the linear region operation, and the region of operating at a voltage higher than the pinch-off voltage is the saturation region operation. Using the drain-source voltage Vds, the gate-source threshold voltage Vth, the gate-source voltage Vgs, and the pinch-off voltage Vp, the definition of the saturation region operation of the MOSFET is shown in (Equations 1, 2), the definition of the linear region operation is shown in (Equations 3, 4), and the definition of the cutoff region operation is shown in (Equation 5).

[0048] Saturation region operation: - Vds > Vp = Vgs - Vth (condition for pinch-off) (Equation 1) - Vgs > Vth (condition for forming a conducting channel) (Equation 2) Linear region operation: - Vds < Vp = Vgs - Vth (Vgs > Vth) (Equation 3) - Vgs > Vth (Equation 4) Cut-off region operation: Vgs < Vth (only leakage current Ids occurs) (Equation 5)

[0049] Figure 6 shows the relationship between Vds and Ids for each Vgs by corresponding a plurality of curves to a plurality of different Vgs. Here, points A, B, and C are operating points in the saturation region, and D, E, and F are operating points in the linear region. When a constant voltage is applied between the gate and the source to switch on, due to the time constant of the charge charging to the gate, the voltage between the gate and the source gradually increases according to this time constant. That is, the gate-source voltage Vgs exceeds Vth and the voltage increases as A⇒B⇒C in the saturation region. Along with this, the drain-source current Ids increases and the drain-source voltage Vds decreases. After that, when Vgs further increases and Vgs > Vds + Vth and the drain voltage falls below the pinch-off voltage (Vp = Vgs - Vth), it becomes an operation in the linear region with a low on-resistance, and draws a locus from D through E to point F which is the steady value of Vgs.

[0050] To make dIF1 / dt of the reverse recovery current be dIF2 / dt with a small slope, the switching element of the DC / AC converter 3 in the primary side circuit may be operated in a high-resistance saturation region to perform current limiting. That is, the control of the drain-source current using the saturation region operation of this MOSFET means suppressing the amount of charge charging to the gate using a high-resistance gate resistance or the like, and performing time response control of Vgs in the saturation region operation. Here, operating the switching element in the saturation region means maintaining an operation in the saturation region with a high on-resistance to perform current limiting, and operating in the linear region means making the operation time in the saturation region as short as possible and operating the main current in the linear region with a low on-resistance.

[0051] <Control Method for Suppressing Reverse Recovery Current> Based on the reasons for the occurrence of reverse recovery current and the mechanisms by which it can be suppressed, a control method for suppressing reverse recovery current and reducing switching losses and recovery surges in the circuit configuration of Figure 1 will be explained using Figure 7. Figure 7 shows the timing relationship of the switching elements 31a, 31b, 32a, 32b, 33a, 33b, 34a, and 34b of the DC / AC converter 3 in the primary circuit, which operate with a duty cycle D relative to the carrier in order to maintain a constant relationship between the output voltage and the input voltage of the DC / AC converter 3 when reverse recovery current is suppressed. Figure 7 also shows the period in which the saturation region and linear region operations of each MOSFET are alternated.

[0052] The triangular wave carrier is used to determine the on-time of the switching elements of the DC / AC converter 3 based on the duty cycle D. Switching elements 31a and 33b turn on in the linear region between t2 and t4. On the other hand, switching elements 32a and 34b turn on in the saturation region at a timing corresponding to a level of D + ΔD (ΔD > 0). Due to this ΔD, they turn on at timing t1, which is before switching elements 31a and 33b turn on, and then turn off at timing t3, which is before t4, with a predetermined delay of Δt relative to t2. The reason for setting t3 to a timing before t4 is to suppress the increase in conduction loss due to high-resistance saturation region operation. Here, Dlimit_max is the upper limit of the level of the MOSFET operating in the saturation region, and the lower limit of the level of the MOSFET operating in the saturation region is D, so the relationship D < D + ΔD < Dlimit_max < 1 holds.

[0053] Switching elements 32a and 34b turn on in a high-resistance saturation region before switching elements 31a and 33b, which operate in a low-resistance linear region. Therefore, when a reverse recovery current attempts to flow through switching element 51b in the secondary circuit of the AC / DC converter 5, the high-resistance switching elements 32a and 34b are positioned in the path of the current induced on the primary side, thus suppressing the current induced on the primary side. Consequently, the slope of the reverse recovery current in switching element 51b of the AC / DC converter 5 in the secondary circuit can be suppressed, reducing the peak of the reverse recovery current, thereby suppressing surges and reducing switching losses. Furthermore, when switching elements 31a and 33b turn on, the drain-source voltage has already decreased because switching elements 32a and 34b are already on, thus reducing the turn-on losses of switching elements 31a and 33b.

[0054] Here, a predetermined voltage (referred to as the surge clamp voltage command value) is set so as to be below the breakdown voltage of the switching element, and the difference between the clamp voltage of the surge clamp circuit 10 in Figure 1 and this surge clamp voltage command value is set to ΔD. That is, if clamp voltage > surge clamp voltage command value, then ΔD > 0, and if clamp voltage < surge clamp voltage command value, then ΔD < 0. When the clamp voltage becomes larger than the surge clamp voltage command value, ΔD increases, and the circuit operates in a way that suppresses the recovery surge that occurs when switching in the linear region, while limiting the current in the high-resistance saturation region operation and bringing the reverse recovery state under control. However, since the upper and lower arms move complementaryally, the condition is that D + ΔD is less than 1.

[0055] Next, we will explain the operation of the pairs 33a and 31b and 34a and 32b, which are diagonal operations to the operation of the pairs 31a and 33b and 32a and 34b. Returning to Figure 7, the switching elements 33a and 31b turn on in the linear region between t7 and t9. On the other hand, the switching elements 34a and 32b operate in the saturation region and turn on at a timing corresponding to the level D + ΔD (ΔD > 0). Due to this ΔD, they turn on at a timing t6, which is before the switching elements 33a and 31b turn on, and then turn off at a timing t8, which is before t9, with a predetermined time Δt delay relative to t7. The reason for setting t8 to a timing before t9 is to suppress the increase in losses that would occur if the high-resistance saturation region operation time were long.

[0056] Switching elements 34a and 32b turn on in a high-resistance saturation region before switching elements 33a and 31b, which operate in a low-resistance linear region. Therefore, when a reverse recovery current attempts to flow through switching element 52b in the secondary circuit of the AC / DC converter 5, the high-resistance switching elements 34a and 32b are positioned in the path of the current induced on the primary side, thus suppressing the current induced on the primary side. Consequently, the slope of the reverse recovery current in switching element 52b of the AC / DC converter 5 in the secondary circuit can be suppressed, reducing the peak of the reverse recovery current, thereby suppressing surges and reducing switching losses. Furthermore, when switching elements 33a and 31b turn on, switching elements 34a and 32b are already on and the drain-source voltage has decreased, thus reducing the turn-on losses of switching elements 33a and 31b.

[0057] In the first half-cycle up to this point, switching elements 31a, 33b, 33a, and 31b were used for power transmission, and switching elements 32a, 34b, 34a, and 32b were used for suppressing reverse recovery current. In the next second half-cycle, switching elements 32a, 34b, 34a, and 32b were used for power transmission, and switching elements 31a, 33b, 33a, and 31b were used for suppressing reverse recovery current. By switching the operation of the switching elements in the saturation region and the linear region between the first and second half-cycles, the losses of the switching elements are leveled.

[0058] Switching elements 32a and 34b turn on in the linear region between t12 and t14. On the other hand, switching elements 31a and 33b operate in the saturation region and turn on at a timing corresponding to the level D + ΔD (ΔD > 0). Due to this ΔD, they turn on at timing t11, which is before switching elements 32a and 34b turn on, and then turn off at timing t13, which is before t14, with a predetermined time Δt delay relative to t12. The reason for setting t13 to a timing before t14 is to suppress the increase in losses that would occur if the high-resistance saturation region operation time were long.

[0059] Then, switching elements 34a and 32b turn on in the linear region between t17 and t19. On the other hand, switching elements 33a and 31b operate in the saturation region, turning on at a timing corresponding to the level D + ΔD (ΔD > 0). Due to this ΔD, they turn on at timing t16, which is before switching elements 34a and 32b turn on, and then turn off at timing t18, which is before t19, with a predetermined time Δt delay relative to t17. The reason for setting t18 to a timing before t19 is the same as for switching elements 31a and 33b.

[0060] The above describes a parallel arm configuration in which the switching element that turns on first operates in the saturation region, followed by the switching element that operates in the linear region, and how the modes for suppressing reverse recovery current and transmitting power are separated into different elements. The reason for separating the control operations for suppressing reverse recovery current and transmitting power into different elements is explained below. If the ratio of control time in the saturation region and the linear region were to be separated during the on-period of a single switching element, then reverse recovery current suppression and power transmission control would have to be performed during the same on-period, and the control accuracy of each would interfere with each other, resulting in a deterioration of control accuracy. However, by dividing the functions of the two operating modes into separate elements in this way, each can be controlled individually with high precision.

[0061] <Switching of Operating Modes Based on Clamp Voltage> Figure 8 shows the timing relationship of the switching elements 31a, 31b, 32a, 32b, 33a, 33b, 34a, and 34b of the DC / AC converter 3 in the primary circuit when the clamp voltage of the surge clamp circuit 10 in Figure 1 is below a predetermined voltage (surge clamp voltage command value) set to be below the withstand voltage of the switching elements, and reverse recovery current is not suppressed. When reverse recovery current is not suppressed, there is no need to set a level of D+ΔD to turn on the switching elements for surge suppression, and the maximum duty cycle can be set to be larger than when reverse recovery current suppression control is enabled, which has the advantage of enabling a wider range of input / output voltage control.

[0062] The switching elements 31a, 31b, 32a, 32b, 33a, 33b, 34a, and 34b of the DC / AC converter 3 in the primary circuit all operate in the low-resistance linear region, with switching elements 31a, 32a, 33b, and 34b turning on at t1 to t2, and switching elements 31b, 32b, 33a, and 34a turning on at t4 to t5. The above describes two modes: whether or not to suppress the reverse recovery current depending on the clamped voltage. The operation of switching between these modes will be explained using the flowchart in Figure 9.

[0063] In step S001, the control calculation unit 9 in Figure 1 reads the input voltage Vin, input current Iin, output voltage Vout, output current Iout, surge clamp voltage command value Vsrg_REF, and surge clamp voltage Vsrg of the DC voltage source 1 as the state of the DC / AC converter 3 and AC / DC converter 5. Next, it proceeds to step S002, where it determines the relationship between the clamped surge clamp voltage Vsrg and the surge clamp voltage command value Vsrg_REF. If the clamped surge clamp voltage Vsrg is smaller than the surge clamp voltage command value Vsrg_REF, it proceeds to step S003, where all parallel arms are operated in the linear region, and then returns to step S002.

[0064] If the surge clamp voltage Vsrg clamped in step S002 is greater than or equal to the surge clamp voltage command value Vsrg_REF, the process proceeds to step S004, where the parallel arms are operated in the linear region after the saturation region operation. Subsequently, the process proceeds to step S005, where the clamped surge clamp voltage Vsrg is greater than or equal to the surge clamp voltage command value Vsrg_REF, and the process proceeds to step S006, where the on-time of the saturation region operation is extended.

[0065] The process then proceeds to step S007, where it is determined whether D+ΔD, the level at which the switching element for suppressing reverse recovery current turns on, is less than or equal to the upper limit Dlimit_max (set to be less than 1, which is the upper limit for carriers). If it is less than the upper limit, the process proceeds to step S002. On the other hand, if D+ΔD is greater than or equal to the upper limit, the process proceeds to step S008, where it is determined that the saturation region operation cannot be extended any longer, and that some abnormal condition has occurred that prevents surge suppression, and the operation of DC / AC converter 3 and AC / DC converter 5 is stopped.

[0066] In step S005, if the clamped surge clamp voltage Vsrg is smaller than the surge clamp voltage command value Vsrg_REF, the process proceeds to step S009 to shorten the on-time of saturation region operation. Then, the process proceeds to step S010, where D+ΔD, the level at which the switching element for suppressing reverse recovery current turns on, is compared with the duty cycle D of the linear region operation, which is the lower limit. If D+ΔD is greater than the lower limit D, the process returns to step S005. If D+ΔD is less than or equal to the lower limit D, the process proceeds to step S003, where all parallel arms are operated in the linear region. By providing a mode switching function in accordance with the surge clamp voltage in this way, the control range of the duty cycle is expanded while suppressing recovery surges, allowing for support of a wider range of input and output voltages.

[0067] In Figure 7, where reverse recovery current suppression control is enabled, there are four carrier peaks and troughs per period (T), while in Figure 8, where reverse recovery current suppression control is disabled, there are two peaks and troughs per period (T). Assuming the same power in both modes, reverse recovery current suppression control, which uses fewer parallel power-transmitting elements, results in greater conduction losses in the linear-domain switching elements used for power transmission. Therefore, it is necessary to shorten the period to reduce the energy loss of the linear-domain switching elements and disperse the heat generated.

[0068] In this case, if the period during reverse recovery current suppression control is halved compared to when reverse recovery current suppression control is not applied, the conduction loss per period of a switching element operating in the linear region becomes approximately equal. This is equivalent to increasing the frequency of the switching element, and this operation enables miniaturization of magnetic components. Furthermore, by varying the switching frequency according to the input voltage and the reverse recovery current suppression mode, taking into account magnetic saturation of the magnetic components, characteristics that achieve both low loss and miniaturization can be obtained.

[0069] As described above, by suppressing the reverse recovery current, the recovery surge can be reduced, allowing for the use of low-voltage elements and achieving high-efficiency characteristics. This reduction in switching losses enables high-frequency operation, resulting in a power conversion device that allows for miniaturization of magnetic components.

[0070] <Effects of the power conversion device according to this embodiment> To summarize, the power conversion device according to this embodiment includes a first semiconductor switching element 51b in which diodes are connected in antiparallel, second semiconductor switching elements 32a and 34b arranged in the path of the current induced by the generation of reverse recovery current flowing through the first semiconductor switching element 51b, and a control calculation unit 9 that performs reverse recovery current suppression control to turn on the second semiconductor switching elements 32a and 34b by adjusting the drain-source voltage and gate-source voltage of the second semiconductor switching elements 32a and 34b in conjunction with turning on the first semiconductor switching element 51b from a state in which the diode is energized in the forward direction, thereby operating the second semiconductor switching elements 32a and 34b in the saturation region, and then turning on the second semiconductor switching elements 32a and 34b.

[0071] Because of the above configuration, the reverse recovery current generated in the first semiconductor switching element 51b can be suppressed, thereby reducing switching losses. Furthermore, instead of placing a resistor in series with the second semiconductor switching elements 32a and 34b, the drain-source voltage and gate-source voltage of the second semiconductor switching elements 32a and 34b are adjusted to operate the drain-source resistance in the saturation region, resulting in high resistance. By adjusting the drain-source voltage and gate-source voltage to operate in the linear region, resulting in low resistance, the second semiconductor switching elements 32a and 34b can also be used for power transmission. Therefore, there is no need to separately provide a MOSFET for power transmission in parallel, and a compact power conversion device can be realized by improving mounting efficiency.

[0072] Furthermore, the system includes third semiconductor switching elements 31a and 33b connected in parallel to the second semiconductor switching elements 32a and 34b. The control calculation unit 9 operates the third semiconductor switching elements 31a and 33b in the linear region by adjusting the drain-source voltage and gate-source voltage after reverse recovery current suppression control, and then performs power transmission control to turn on the third semiconductor switching elements 31a and 33b. As a result, when the third semiconductor switching elements 31a and 33b are turned on, the second semiconductor switching elements 32a and 34b are already turned on and the drain-source voltage has decreased, thus reducing the turn-on loss of the third semiconductor switching elements 31a and 33b.

[0073] Furthermore, as shown in this embodiment, if the control operation is divided into two separate elements—the second semiconductor switching elements 32a and 34b for suppressing reverse recovery current and the third semiconductor switching elements 31a and 33b for power transmission—then, if the ratio of control time in the saturation region and the linear region is divided during the ON period of a single switching element, then reverse recovery current suppression and power transmission control must be performed during the same ON period. As a result, the control accuracy of each will interfere with each other, leading to a deterioration in control accuracy. However, by dividing the functions of the two operating modes among separate elements in this way, each can be controlled individually with high precision.

[0074] Furthermore, the control calculation unit 9 is characterized by controlling the duration of the ON state of the second semiconductor switching elements 32a and 34b to be shorter than the duration of the ON state of the third semiconductor switching elements 31a and 33b. This makes it possible to suppress the increase in conduction loss due to high-resistance saturation region operation in the second semiconductor switching elements 32a and 34b.

[0075] Furthermore, the control calculation unit 9 is characterized by performing control to turn on the third semiconductor switching elements 31a and 33b before turning on the second semiconductor switching elements 32a and 34b and then turning them off. As a result, when the third semiconductor switching elements 31a and 33b are turned on, the second semiconductor switching elements 32a and 34b are already turned on and the drain-source voltage has decreased, so the turn-on loss of the third semiconductor switching elements 31a and 33b, which operate in the linear region, can be reduced.

[0076] Furthermore, the control calculation unit 9 is characterized by performing control to turn off the second semiconductor switching elements 32a and 34b before turning on the third semiconductor switching elements 31a and 33b and then turning them off. This makes it possible to suppress the increase in conduction loss due to high-resistance saturation region operation in the second semiconductor switching elements 32a and 34b.

[0077] Furthermore, the control calculation unit 9 is characterized by performing a control that alternately repeats the following: a first control period in which reverse recovery current suppression control is performed on the second semiconductor switching elements 32a and 34b, and then power transmission control is performed on the third semiconductor switching elements 31a and 33b; and a second control period in which reverse recovery current suppression control is performed on the third semiconductor switching elements 31a and 33b, and then power transmission control is performed on the second semiconductor switching elements 32a and 34b, in conjunction with turning on the first semiconductor switching elements from a state in which current is supplied in the forward direction of the diodes, by adjusting the drain-source voltage and gate-source voltage of the third semiconductor switching elements to operate the third semiconductor switching elements in the saturation region, and then turning on the third semiconductor switching elements, by adjusting the drain-source voltage and gate-source voltage of the third semiconductor switching elements to operate them in the linear region, and then turning on the third semiconductor switching elements. This makes it possible to equalize losses between the second semiconductor switching elements 32a and 34b and the third semiconductor switching elements 31a and 33b.

[0078] Furthermore, the control calculation unit 9 controls the output voltage of the DC / AC converter 3 to a set value by controlling the duty cycle of the third semiconductor switching elements 31a and 33b in power transmission control, and controls the timing of turning on the second semiconductor switching elements 32a and 34b by controlling the voltage level corresponding to the timing of turning on the second semiconductor switching elements 32a and 34b in reverse recovery current suppression control. In this way, by using separate semiconductor switching elements for the third semiconductor switching elements 31a and 33b that perform power transmission and the second semiconductor switching elements 32a and 34b that perform reverse recovery current suppression control, and controlling them at timings corresponding to their respective levels, it becomes possible to perform appropriate control according to the respective purposes of power transmission control to generate a desired output voltage and reverse recovery current control to suppress surges.

[0079] The AC / DC converter 5 is equipped with a surge clamp circuit 10 for measuring a surge clamp voltage obtained by accumulating the surge current generated in the AC / DC converter 5 in a capacitor 10b. The control calculation unit 9 adopts a first operating mode in which, when the surge clamp voltage exceeds a predetermined surge clamp voltage command value, reverse recovery current suppression control is performed on the second semiconductor switching elements 32a and 34b and the power transmission control is performed on the third semiconductor switching elements 31a and 33b. When the surge clamp voltage is less than or equal to the surge clamp voltage command value, a second operating mode is adopted in which the power transmission control is performed on the second semiconductor switching elements 32a and 34b and the third semiconductor switching elements 31a and 33b. By providing a mode switching function in accordance with the surge clamp voltage in this way, the control range of the duty cycle is widened while suppressing recovery surges, and a wider range of input and output voltages can be accommodated.

[0080] Furthermore, the control calculation unit 9 is characterized in that, when the first operating mode is adopted, the switching frequencies of the second semiconductor switching elements 32a, 34b and the third semiconductor switching elements 31a, 33b are set higher than the switching frequencies of the second semiconductor switching elements 32a, 34b and the third semiconductor switching elements 31a, 33b when the second operating mode is adopted. When the first operating mode is adopted, the recovery surge can be reduced by suppressing the reverse recovery current, so that high-efficiency characteristics can be obtained by using low-voltage elements. Since switching losses can be reduced in this way, higher frequency operation can be performed than in the second operating mode, and thereby the magnetic components can be miniaturized.

[0081] <Embodiment 2> <Circuit Configuration> Figure 10 is a diagram showing the circuit configuration of a power converter according to Embodiment 2. Figure 10 is a boost converter, and the DC voltage source 201 is connected via a link capacitor 202 and a reactor 206 to the upper and lower arms of a converter in which a plurality of switching legs (a series of upper and lower arms) are connected in parallel, with switching elements connected in series. In the figure, it is composed of two switching legs 221 and 222, with switching leg 221 having switching elements 221a and 221b connected in series, and switching leg 222 having switching elements 222a and 222b connected in series.

[0082] The surge clamp circuit 210 connects a capacitor 210b and a resistor 210c to the cathode terminal of the diode 210a, and connects the anode of the diode 210a to the drain terminal of the upper arm of the parallel-connected switching legs 221 and 222. Furthermore, the other end of the capacitor 210b is connected to the source terminal of the lower arm of the parallel-connected switching legs 221 and 222, and the output capacitor 207 and output load 208 are connected in parallel between the drain source of the parallel-connected switching legs 221 and 222. The control calculation unit 209 takes the input voltage Vin and input current Iin of the DC voltage source 201, the output voltage Vout and output current Iout supplied to the output load 208, and the surge clamp voltage Vsrg of the surge clamp circuit 210 as inputs to perform gate control of the switching elements constituting the switching legs 221 and 222.

[0083] Figure 10 illustrates a MOSFET (Metal-oxide-Semiconductor Field-Effect Transistor) with switching element diodes connected in antiparallel. However, an IGBT (Insulated Gate Bipolar Transistor) with diodes connected in antiparallel may also be used, and the configuration of the switching element (monopolar or bipolar) is not limited. Furthermore, while this figure uses two parallel switching legs, the number of parallel switching legs can be increased to create a configuration with two or more arms, and the upper arm may be rectified using a rectifier diode instead of synchronous rectification.

[0084] <Control Method for Suppressing Reverse Recovery Current> Next, using Figure 11, we will explain the operation to suppress reverse recovery current and reduce surge and switching losses. This figure shows the timing relationship of one period in which the switching elements 221a, 221b, 222a, and 222b of switching legs 221 and 222 operate with a duty cycle D relative to the carrier in order to maintain a constant relationship between the output voltage and the input voltage of the power converter when suppressing reverse recovery current. One period is the period in which one MOSFET alternates between linear region operation and saturation region operation, and is shown as T in Figure 11.

[0085] First, let's explain the operation of the first half-period (T / 2). The sawtooth-shaped carriers are carriers that determine the on-time of the switching elements of switching legs 221 and 222. The switching element 222b of the lower arm turns on in the linear region between t2 and t4 based on the duty cycle D. On the other hand, the switching element 221b is in the saturation region and turns on at a timing corresponding to the level D + ΔD (ΔD > 0). Because of this ΔD, it turns on at timing t1, which is before the switching element 222b turns on, and then turns off at timing t3, which is before t4, with a predetermined time Δt delay relative to t2. The upper arm elements 221a and 222a turn on during the period between t4 and t5, when both the lower arm elements 221b and 222b are off.

[0086] Switching element 221b turns on in a high-resistance saturation region before switching element 222b, which operates in a low-resistance linear region. Therefore, when a reverse recovery current attempts to flow through switching elements 221a and 222a, the high-resistance switching element 221b is positioned in this current path, suppressing the reverse recovery current. Consequently, the slope of the reverse recovery current in switching elements 221a and 222a is suppressed, reducing the peak of the reverse recovery current, thereby suppressing surges and reducing switching losses. Furthermore, when switching element 222b turns on, switching element 221b has already turned on, lowering the drain-source voltage, thus reducing the turn-on loss of switching element 222b.

[0087] ΔD is determined such that the difference between the clamp voltage of the surge clamp circuit 10 in Figure 1 and a predetermined voltage (surge clamp voltage command value) set so that the clamp voltage is less than or equal to the breakdown voltage of the switching element is ΔD. That is, if clamp voltage > surge clamp voltage command value, then ΔD > 0, and if clamp voltage < surge clamp voltage command value, then ΔD < 0. When the clamp voltage becomes greater than the predetermined voltage, ΔD increases, and the circuit operates in a way that suppresses the recovery surge that occurs when switching in linear region operation, while limiting the current in the high-resistance saturation region operation and bringing the reverse recovery state under control. However, since the upper and lower arms move complementaryly, D + ΔD must be less than 1, which is the upper limit of the carrier.

[0088] Next, we will explain the operation of the second half-period (T / 2). Switching element 221b turns on in the linear region between t6 and t8, and switching element 222b turns on in the saturation region at a timing corresponding to the level D + ΔD (ΔD > 0). Due to this ΔD, it turns on at timing t5, which is before switching element 221b turns on, and turns off at timing t7, which is before timing t8, with a predetermined time Δt delay relative to the subsequent timing t6. Timings t4, t5, and t8 are the switching points of the upper and lower arms. In reality, a dead timing is provided to prevent short circuits between the upper and lower arms, but this is omitted in the diagram for simplicity.

[0089] Switching element 222b turns on in a high-resistance saturation region before switching element 221b, which operates in a low-resistance linear region. When a reverse recovery current attempts to flow through switching elements 221a and 222a, the high-resistance switching element 222b is positioned in this current path, suppressing the reverse recovery current. Therefore, the slope of the reverse recovery current in switching elements 221a and 222a is suppressed, reducing the peak of the reverse recovery current, thereby suppressing surges and reducing switching losses. Furthermore, when switching element 221b turns on, switching element 222b is already on and the drain-source voltage has decreased, thus reducing the turn-on loss of switching element 221b.

[0090] In this way, by preventing the same switching element from operating in the saturation region within one cycle, the switching elements 221b and 222b share the responsibility of operating in the linear region and the saturation region, thereby enabling the leveling of switching losses.

[0091] <Switching of Operating Modes Based on Clamp Voltage> Figure 12 shows the timing relationship of the switching elements 221a, 221b, 222a, and 222b of switching legs 221 and 222 when the clamp voltage of the surge clamp circuit 210 in Figure 10 is below a predetermined voltage (surge clamp voltage command value) set to be below the withstand voltage of the switching elements, and reverse recovery current is not suppressed. This shows the timing relationship of the switching elements 221a, 221b, 222a, and 222b of switching legs 221 and 222 when they operate with a duty cycle D relative to the carrier in order to maintain a constant relationship between the output voltage and the input voltage of the power converter. When reverse recovery current is not suppressed, this is the operation when the clamp voltage of the surge clamp circuit 210 in Figure 10 is below the surge clamp voltage command value, and since the maximum duty cycle can be widened, there is an advantage in that a wider range of input and output voltage control is possible. The switching elements 221a, 221b, 222a, and 222b of switching legs 221 and 222 all operate in the low-resistance linear region, with switching elements 221a and 222a turning on from t0 to t1, and switching elements 221b and 222b turning on from t1 to t2.

[0092] In Embodiment 2, as in Embodiment 1, by monitoring the clamp voltage of the surge clamp circuit 210 in Figure 10, it is possible to switch between control modes, such as when reverse recovery current suppression is performed and when it is not, as shown in Figure 9 of Embodiment 1. This enables handling of a wide range of input and output voltages while suppressing surges.

[0093] <Effects of the power conversion device according to this embodiment> As described above, in Embodiment 2, the same effects can be obtained as in Embodiment 1 even if the converter configuration is changed from an isolated DC / DC converter to a non-isolated boost converter. That is, the power conversion device according to this embodiment includes first semiconductor switching elements 221a and 222a in which diodes are connected in antiparallel, a second semiconductor switching element 221b arranged in the current path of the first semiconductor switching elements 221a and 222a, and a control calculation unit 209 that performs reverse recovery current suppression control to turn on the second semiconductor switching element 221b by adjusting the drain-source voltage and gate-source voltage of the second semiconductor switching element 221b in conjunction with turning on the first semiconductor switching elements 221a and 222a from a state in which current is supplied in the forward direction of the diodes, thereby operating the second semiconductor switching element 221b in the saturation region, and then turning on the second semiconductor switching element 221b.

[0094] Because of the above configuration, the reverse recovery current generated in the first semiconductor switching elements 221a and 222a can be suppressed, thereby reducing switching losses. Furthermore, instead of placing a resistor in series with the second semiconductor switching element 221b, the drain-source voltage and gate-source voltage of the second semiconductor switching element 221b are adjusted to operate the drain-source resistance in the saturation region, resulting in high resistance. By adjusting the drain-source voltage and gate-source voltage to operate in the linear region, resulting in low resistance, the second semiconductor switching element 221b can also be used for power transmission. Therefore, there is no need to separately provide a MOSFET for power transmission in parallel, and a compact power conversion device can be realized by improving mounting efficiency.

[0095] Furthermore, the system includes a third semiconductor switching element 222b connected in parallel to the second semiconductor switching element 221b. The control calculation unit 9 performs power transmission control to turn on the third semiconductor switching element 222b after performing reverse recovery current suppression control, by adjusting the drain-source voltage and gate-source voltage of the third semiconductor switching element 222b to operate it in the linear region. As a result, when the third semiconductor switching element 222b is turned on, the second semiconductor switching element 221b is already turned on and the drain-source voltage has decreased, thus reducing the turn-on loss of the third semiconductor switching element 222b.

[0096] <Embodiment 3> <Circuit Configuration> Figure 13 is a diagram showing the circuit configuration of a power conversion device according to Embodiment 3. Figure 13 is a step-down converter, and the DC voltage source 301 is connected via a link capacitor 302 to the upper and lower arms of a converter in which a plurality of switching legs (upper and lower arms in series) are connected in parallel, with switching elements connected in series. In the figure, it is composed of two switching legs 321 and 322, with switching leg 321 having switching elements 321a and 321b connected in series, and switching leg 322 having switching elements 322a and 322b connected in series.

[0097] The points where switching elements 321a and 321b of switching leg 321 are connected in series are connected to the points where switching elements 322a and 322b of switching leg 322 are connected in series, and these points are connected to reactor 306. The output of reactor 306 is input to output capacitor 307 and output load 308, and the other ends of output capacitor 307 and output load 308 are connected to the source terminals of the lower arms of switching legs 321 and 322.

[0098] The surge clamp circuit 310 connects a capacitor 310b and a resistor 310c to the cathode terminal of the diode 310a, and connects the other end of the capacitor 310b to the source terminal of the lower arm of the switching legs 321 and 322, to the drain terminal of the upper arm of the switching legs 321 and 322, to which the anodes of the diodes 310a are connected in parallel. The control calculation unit 309 takes the input voltage Vin and input current Iin of the DC voltage source 301, the output voltage Vout and output current Iout supplied to the output load 308, and the surge clamp voltage Vsrg of the surge clamp circuit 310 as inputs to perform gate control of the switching elements constituting the switching legs 321 and 322.

[0099] In Figure 13, the switching element is explained using a MOSFET (Metal-oxide-Semiconductor Field-Effect Transistor), which is an insulated-gate field-effect transistor with diodes connected in antiparallel. However, it may also be an IGBT (Insulated Gate Bipolar Transistor), which is an insulated-gate bipolar transistor with diodes connected in antiparallel, and the monopolar or bipolar configuration of the switching element is not limited. Furthermore, although the number of parallel switching legs is shown as two, it may be configured with two or more arms by increasing the number of parallel switching legs, and rectifier diodes may be used instead of synchronous rectification.

[0100] <Control Method for Suppressing Reverse Recovery Current> Next, using Figure 14, we will explain the operation to suppress reverse recovery current and reduce surge and switching losses. This figure shows the timing relationship of one period in which the switching elements 321a, 321b, 322a, and 322b of switching legs 321 and 322 operate with a duty cycle D relative to the carrier in order to maintain a constant relationship between the output voltage and the input voltage of the power converter when suppressing reverse recovery current. One period is the period in which one MOSFET alternates between the linear region and the saturation region, and is shown as T in Figure 11.

[0101] First, let's explain the operation of the first half-period (T / 2). The sawtooth-shaped carriers are carriers that determine the on-time of the switching elements of switching legs 321 and 322. The switching element 322a of the upper arm turns on in the linear region between t2 and t4 based on the duty cycle D. On the other hand, the switching element 321a operates in the saturation region and turns on at a timing corresponding to the level D + ΔD (ΔD > 0). Because of this ΔD, it turns on at timing t1, which is before the switching element 322a turns on, and then turns off at timing t3, with a predetermined time Δt delay relative to t2. The lower arm elements 321b and 322b turn on during the period t4 to t5 when both the upper arm elements 321a and 322a are off.

[0102] The high-resistance switching element 321a, which operates in the saturation region, turns on before the low-resistance switching element 322a, which operates in the linear region. When a reverse recovery current attempts to flow through the switching elements 321b and 322b, the high-resistance switching element 321a is positioned in this current path, suppressing the reverse recovery current. Therefore, the slope of the reverse recovery current of the switching elements 321b and 322b can be suppressed, reducing the peak of the reverse recovery current and suppressing surges. In addition, when the switching element 322a turns on, the drain-source voltage has already decreased because the switching element 321a has turned on, thus reducing the turn-on loss of the switching element 322a.

[0103] ΔD is determined such that the difference between the clamp voltage of the surge clamp circuit 10 in Figure 1 and a predetermined voltage (surge clamp voltage command value) set so that the clamp voltage is less than or equal to the breakdown voltage of the switching element is ΔD. That is, if clamp voltage > surge clamp voltage command value, then ΔD > 0, and if clamp voltage < surge clamp voltage command value, then ΔD < 0. When the clamp voltage becomes greater than the predetermined voltage, ΔD increases, and the circuit operates in a way that suppresses the recovery surge that occurs when switching in the linear region, while limiting the current in the high-resistance saturation region operation and bringing the reverse recovery state under control. However, since the upper and lower arms move complementaryly, D + ΔD must be less than 1.

[0104] Next, we will explain the operation of the second half-period (T / 2). Switching element 321a turns on in the linear region between t6 and t8, and switching element 322a turns on in the saturation region at a timing corresponding to the level D + ΔD (ΔD > 0). Due to this ΔD, it turns on at timing t5, which is before switching element 321a turns on, and turns off at timing t7, which is before timing t8, with a predetermined time Δt delay relative to the subsequent timing t6. Timings t4, t5, and t8 are the switching points of the upper and lower arms. In reality, a dead timing is provided to prevent short circuits between the upper and lower arms, but this is omitted in the diagram for simplicity.

[0105] The high-resistance switching element 322a, which operates in the saturation region, turns on before the low-resistance switching element 321a, which operates in the linear region. When a reverse recovery current attempts to flow through the switching elements 321b and 322b, the high-resistance switching element 322a is positioned in this current path, suppressing the reverse recovery current. Therefore, the slope of the reverse recovery current of the switching elements 321b and 322b can be suppressed, reducing the peak of the reverse recovery current and suppressing surges. In addition, when the switching element 321a turns on, the switching element 322a has already turned on and the drain-source voltage has decreased, thus reducing the turn-on loss of the switching element 321a.

[0106] In this way, by preventing the same switching element from operating in the saturation region within one cycle, the switching elements 321a and 322a share the responsibility of operating in the linear region and the saturation region, thereby enabling the leveling of power losses generated by the switching elements.

[0107] <Switching of Operating Modes Based on Clamp Voltage> Figure 15 shows the timing relationship of the switching elements 321a, 321b, 322a, and 322b of switching legs 321 and 322 when the clamp voltage of the surge clamp circuit 310 in Figure 13 is below a predetermined voltage (surge clamp voltage command value) set to be below the breakdown voltage of the switching elements, and reverse recovery current is not suppressed. This shows the timing relationship of the switching elements 321a, 321b, 322a, and 322b of switching legs 321 and 322 when they operate with a duty cycle D relative to the carrier in order to maintain a constant relationship between the output voltage and the input voltage of the power converter. When reverse recovery current is not suppressed, this is the operation when the clamp voltage of the surge clamp circuit 310 in Figure 13 is below the surge clamp voltage command value, and since the maximum duty cycle can be widened, there is an advantage in that a wider range of input and output voltage control is possible. The switching elements 321a, 321b, 322a, and 322b of switching legs 321 and 322 all operate in the low-resistance linear region, with switching elements 321b and 322b turning on from t0 to t1, and switching elements 321a and 322a turning on from t1 to t2.

[0108] In Embodiment 3, as in Embodiment 1, by monitoring the clamp voltage of the surge clamp circuit 310 in Figure 13, it is possible to switch between control modes, such as when reverse recovery current suppression is performed and when it is not, as shown in Figure 9 of Embodiment 1. This enables handling a wide range of input and output voltages while suppressing surges.

[0109] <Effects of the power conversion device according to this embodiment> As described above, in Embodiment 3, the same effects can be obtained as in Embodiment 1 even if the converter configuration is changed from an isolated DC / DC converter to a non-isolated step-down converter. That is, the power conversion device according to this embodiment includes first semiconductor switching elements 321b and 322b in which diodes are connected in antiparallel, a second semiconductor switching element 321a arranged in the current path of the first semiconductor switching elements 321b and 322b, and a control calculation unit 309 that performs reverse recovery current suppression control to turn on the second semiconductor switching element 321a by adjusting the drain-source voltage and gate-source voltage of the second semiconductor switching element 321a in conjunction with turning on the first semiconductor switching elements 321b and 322b from a state in which the diodes are energized in the forward direction, thereby operating the second semiconductor switching element 321a in the saturation region, and then turning on the second semiconductor switching element 321a.

[0110] Because of the above configuration, the reverse recovery current generated in the first semiconductor switching elements 321b and 322b can be suppressed, thereby reducing switching losses. Furthermore, instead of placing a resistor in series with the second semiconductor switching element 321a, the drain-source voltage and gate-source voltage of the second semiconductor switching element 321a are adjusted to operate the drain-source resistance in the saturation region, resulting in high resistance. By adjusting the drain-source voltage and gate-source voltage to operate in the linear region, resulting in low resistance, the second semiconductor switching element 321a can also be used for power transmission. Therefore, there is no need to separately provide a MOSFET for power transmission in parallel, and a compact power conversion device can be realized by improving mounting efficiency.

[0111] Furthermore, the system includes a third semiconductor switching element 322a connected in parallel to the second semiconductor switching element 321a. The control calculation unit 9 performs power transmission control to turn on the third semiconductor switching element 322a after performing reverse recovery current suppression control, by adjusting the drain-source voltage and gate-source voltage of the third semiconductor switching element 322a to operate it in the linear region. As a result, when the third semiconductor switching element 322a is turned on, the second semiconductor switching element 321a is already turned on and the drain-source voltage has decreased, thus reducing the turn-on loss of the third semiconductor switching element 322a.

[0112] The control arithmetic units 9, 209, and 309 consist of a processor 400 and a storage device 401, as shown in Figure 16 as an example of the hardware. Although not shown, the storage device comprises a volatile storage device such as random access memory and a non-volatile auxiliary storage device such as flash memory. Alternatively, a hard disk may be provided as an auxiliary storage device instead of flash memory. The processor 400 executes the program input from the storage device 401. In this case, the program is input to the processor 400 from the auxiliary storage device via the volatile storage device. The processor 400 may also output data such as calculation results to the volatile storage device of the storage device 401, or it may save the data to the auxiliary storage device via the volatile storage device.

[0113] While this disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but are applicable individually or in various combinations to the embodiments. Accordingly, countless variations not illustrated are envisioned within the scope of the art disclosed in this specification. For example, these include modifying, adding or omitting at least one component, or extracting at least one component and combining it with a component from another embodiment.

[0114] 51b, 221a, 222a, 321b, 322b: First semiconductor switching elements; 32a, 34b, 221b, 321a: Second semiconductor switching elements; 9, 209, 309: Control calculation unit; 31a, 33b, 222b, 322a: Third semiconductor switching elements; 10b, 210b, 310b: Capacitors; 10, 210, 310: Surge clamp circuit

Claims

1. A power converter having a power converter in which a plurality of semiconductor switching elements are connected to each other, comprising: a first semiconductor switching element in which diodes are connected in antiparallel; a second semiconductor switching element arranged in the path of the current flowing through the first semiconductor switching element, or arranged in the path of the current induced by the generation of a reverse recovery current flowing through the first semiconductor switching element; and a control calculation unit that performs reverse recovery current suppression control to turn on the second semiconductor switching element by adjusting the drain-source voltage and gate-source voltage of the second semiconductor switching element in conjunction with turning on the first semiconductor switching element from a state in which the diode is energized in the forward direction, thereby operating the second semiconductor switching element in the saturation region, and then turning on the second semiconductor switching element.

2. The power conversion device according to claim 1, further comprising a third semiconductor switching element connected in parallel to the second semiconductor switching element, wherein the control calculation unit, following the reverse recovery current suppression control, adjusts the drain-source voltage and gate-source voltage of the third semiconductor switching element to operate it in the linear region, and then performs power transmission control to turn on the third semiconductor switching element.

3. The power conversion device according to claim 2, characterized in that the control calculation unit controls the duration of the ON state of the second semiconductor switching element to be shorter than the duration of the ON state of the third semiconductor switching element.

4. The power conversion device according to claim 2 or 3, characterized in that the control calculation unit performs control to turn on the third semiconductor switching element before turning on the second semiconductor switching element and then turning it off.

5. The power conversion device according to any one of claims 2 to 4, characterized in that the control calculation unit performs control to turn off the second semiconductor switching element before turning on the third semiconductor switching element and then turning it off.

6. The power conversion device according to any one of claims 2 to 5, characterized in that the control calculation unit alternately repeats the following control periods: a first control period in which the reverse recovery current suppression control is performed and then the power transmission control is performed; and a second control period in which, in conjunction with turning on the first semiconductor switching element from a state in which the diode is energized in the forward direction, the drain-source voltage and gate-source voltage of the third semiconductor switching element are adjusted to operate the third semiconductor switching element in the saturation region, and then the reverse recovery current suppression control is performed to turn on the third semiconductor switching element, and then the drain-source voltage and gate-source voltage of the second semiconductor switching element are adjusted to operate it in the linear region, and then the power transmission control is performed to turn on the second semiconductor switching element.

7. The power converter according to any one of claims 2 to 6, characterized in that the control calculation unit controls the output voltage of the power converter to a set value by controlling the duty cycle of the third semiconductor switching element in the power transmission control, and controls the timing of turning on the second semiconductor switching element by controlling the voltage level corresponding to the timing of turning on the second semiconductor switching element in the reverse recovery current suppression control.

8. The power converter according to any one of claims 2 to 7, comprising a surge clamp circuit for measuring a surge clamp voltage obtained by accumulating surge current generated in the power converter in a capacitor, wherein the control calculation unit adopts a first operating mode in which, when the surge clamp voltage exceeds a predetermined surge clamp voltage command value, the reverse recovery current suppression control is performed on the second semiconductor switching element and the power transmission control is performed on the third semiconductor switching element, and when the surge clamp voltage is less than or equal to the surge clamp voltage command value, the control calculation unit adopts a second operating mode in which the power transmission control is performed on the second semiconductor switching element and the third semiconductor switching element.

9. The power conversion device according to claim 8, characterized in that the control calculation unit sets the switching frequencies of the second semiconductor switching element and the third semiconductor switching element when the first operating mode is adopted to be higher than the switching frequencies of the second semiconductor switching element and the third semiconductor switching element when the second operating mode is adopted.

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