Power conversion device and program for power conversion device

Abstract

This power conversion device comprises a first rectifier circuit, a first snubber circuit, a second rectifier circuit, a second snubber circuit, and a control unit. The first snubber circuit has a first snubber capacitor and a first snubber switch. The second snubber circuit has a second snubber capacitor and a second snubber switch. The control unit controls the first snubber switch and the second snubber switch so that the first snubber switch and the second snubber switch are periodically turned on and off in synchronization repeatedly regardless of the inter-terminal voltage of the first snubber capacitor and the inter-terminal voltage of the second snubber capacitor.

Description

Power conversion device and program for power conversion device

[0001] The present disclosure relates to a power conversion device and a program for a power conversion device.

[0002] The DC / DC converter disclosed in Patent Document 1 includes an inverter, a transformer, and a rectifier circuit. The inverter converts the power from a DC power source into AC power and outputs it to the transformer. The transformer outputs the AC power supplied to the primary winding from the secondary winding. The rectifier circuit rectifies the AC power output from the secondary winding of the transformer into DC power and outputs it.

[0003] Further, the DC / DC converter disclosed in Patent Document 1 includes a snubber circuit connected to the rectifier circuit. The snubber circuit has a snubber capacitor and a snubber switch. The snubber capacitor is charged based on the surge voltage generated in the rectifier circuit. When the snubber switch is switched to the on state, the snubber capacitor discharges the stored energy.

[0004] Japanese Unexamined Patent Application Publication No. 2015-70716

[0005] In a DC / DC converter as disclosed in Patent Document 1, a configuration in which the primary windings of two transformers are connected in series to the inverter and separate rectifier circuits and snubber circuits are connected to the secondary windings of each transformer, respectively, can be considered. In such a circuit configuration, due to differences between the snubber circuits in the voltage between the terminals of the snubber capacitor of the snubber circuit, a difference occurs in the current flowing through the inductor of each rectifier circuit. As a result, a current that fluctuates at a high frequency flows between the two rectifier circuits, causing the voltage between the terminals of the transformer to fluctuate finely up and down. Such fine fluctuations in the voltage of the transformer cause power loss in the DC / DC converter.

[0006] One embodiment for solving the above problem is a first transformer having a pair of external output terminals, a primary winding and a secondary winding, a first rectifier circuit connected between the secondary winding of the first transformer and the external output terminals and having a first high-potential output terminal and a first low-potential output terminal, a first snubber circuit having a first snubber capacitor connected between the first high-potential output terminal and the first low-potential output terminal, and a first snubber switch connected between the high-potential terminal of the first snubber capacitor and the external output terminal, a second transformer having a primary winding and a secondary winding connected in series with the primary winding of the first transformer, and a second high-potential switch connected between the secondary winding of the second transformer and the external output terminal. The power conversion device comprises a second rectifier circuit having an output terminal and a second low-potential output terminal; a second snubber circuit having a second snubber capacitor connected between the second high-potential output terminal and the second low-potential output terminal, and a second snubber switch connected between the high-potential terminal of the second snubber capacitor and the external output terminal; and a control unit that controls the first snubber switch and the second snubber switch, wherein the control unit controls the first snubber switch and the second snubber switch so that they repeatedly turn on and off synchronously and periodically, regardless of the terminal voltages of the first snubber capacitor and the terminal voltages of the second snubber capacitor.

[0007] Furthermore, one embodiment for solving the above problem is a first transformer having a pair of external output terminals, a primary winding and a secondary winding, a first rectifier circuit connected between the secondary winding of the first transformer and the external output terminals and having a first high-potential output terminal and a first low-potential output terminal, a first snubber circuit having a first snubber capacitor connected between the first high-potential output terminal and the first low-potential output terminal, and a first snubber switch connected between the high-potential terminal of the first snubber capacitor and the external output terminal, a second transformer having a primary winding and a secondary winding connected in series with the primary winding of the first transformer, and a second high-potential output terminal and a second low-potential output terminal connected between the secondary winding of the second transformer and the external output terminal. This is a program for a power converter that includes a second rectifier circuit having an output terminal, a second snubber circuit having a second snubber capacitor connected between the second high-potential output terminal and the second low-potential output terminal, and a second snubber switch connected between the high-potential terminal of the second snubber capacitor and the external output terminal, and a control unit that controls the first snubber switch and the second snubber switch. The program causes the control unit to execute a process to control the first snubber switch and the second snubber switch so that they repeatedly turn on and off synchronously and periodically, regardless of the terminal voltages of the first snubber capacitor and the terminal voltages of the second snubber capacitor.

[0008] This can suppress the flow of high-frequency fluctuating current between the two rectifier circuits.

[0009] Figure 1 is a circuit diagram of the power converter. Figure 2 is a circuit diagram of the switching circuit. Figure 3 is a circuit diagram of the first snubber circuit. Figure 4 is a circuit diagram of the second snubber circuit. Figure 5 is a conceptual diagram showing the functional blocks of the control unit. Figure 6 is a diagram showing the voltage transition of the first snubber capacitor.

[0010] <An Embodiment of a Power Conversion Device and Program> An embodiment of a power conversion device and program will be described below. Note that in some cases, multiple electronic components may be grouped together and given a single circuit configuration name; however, this is merely a convenient way to describe the objects collectively. In other words, the classification and naming of circuit configurations are not limited to this. Furthermore, "terminal" includes so-called nodes and simply means an electrical connection point.

[0011] (Circuit configuration of the power converter) As shown in Figure 1, the power converter 10 includes a first external input terminal 11A, a second external input terminal 11B, a third external input terminal 11C, a first external output terminal 12A, and a second external output terminal 12B. The power converter 10 also includes a transformer circuit 40.

[0012] The power converter 10 is a so-called three-phase isolated AC-DC converter. The power converter 10 converts the three-phase AC power input to the three external input terminals into DC power, which can then be output from a pair of external output terminals. A transformer circuit 40 is interposed in the power path, electrically isolating the external input terminal side from the external output terminal side.

[0013] The three external input terminals are connected to a three-phase AC power supply PS. The three-phase AC power supply PS is a three-phase, three-wire commercial power system with three AC power sources connected in a Y-connection. Each external input terminal receives one-to-one input of the three phases of the three-phase AC power input from the three-phase AC power supply PS. Any load LD can be connected between the first external output terminal 12A and the second external output terminal 12B. The load LD is, for example, electronic equipment such as a server driven by DC power.

[0014] The power converter 10 includes an input-side noise filter 20 and a switching circuit 30. The input-side noise filter 20 is a so-called low-pass filter. The input-side noise filter 20 includes a first inductor L1, a second inductor L2, and a third inductor L3. The input-side noise filter 20 also includes a first capacitor C1, a second capacitor C2, and a third capacitor C3. The circuit of the input-side noise filter 20, composed of these elements, is sometimes referred to as a smoothing filter or smoothing circuit.

[0015] The first terminal of the first inductor L1 is connected to the first external input terminal 11A. The first terminal of the first capacitor C1 is connected to the second terminal of the first inductor L1. The first terminal of the second inductor L2 is connected to the second external input terminal 11B. The first terminal of the second capacitor C2 is connected to the second terminal of the second inductor L2. The second terminal of the second capacitor C2 is connected to the second terminal of the first capacitor C1.

[0016] The first end of the third inductor L3 is connected to the third external input terminal 11C. The first end of the third capacitor C3 is connected to the second end of the third inductor L3. The second end of the third capacitor C3 is connected to the second end of the first capacitor C1.

[0017] As shown in Figure 2, the switching circuit 30 includes a plurality of input terminals, a pair of output terminals, and a plurality of bidirectional switches TSW. In Figure 2, only some of the bidirectional switches TSW are labeled with reference numerals. The switching circuit 30 can convert three-phase AC power to single-phase AC power through control of each bidirectional switch TSW by the control unit 100, which will be described later.

[0018] As shown in Figure 1, the input terminals are a first input terminal 31A, a second input terminal 31B, and a third input terminal 31C. The first input terminal 31A is connected to the second end of the first inductor L1. The second input terminal 31B is connected to the second end of the second inductor L2. The third input terminal 31C is connected to the second end of the third inductor L3. Therefore, three-phase AC power is input to the input terminals of the switching circuit 30 via each external input terminal and the input-side noise filter 20. The pair of output terminals are a first output terminal 32A and a second output terminal 32B. Single-phase AC power converted by multiple bidirectional switches TSW is output from the pair of output terminals.

[0019] As shown in Figure 2, each bidirectional switch (TSW) has two switching elements. Each switching element is an n-channel field-effect transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor). That is, each switching element has a body diode. The bidirectional switch (TSW) is composed of two switching elements connected in series such that the anode terminals of the body diodes are connected to each other. In other words, the two switching elements constituting each bidirectional switch (TSW) are connected to each other such that the body diodes are in opposite directions. More specifically, each bidirectional switch (TSW) has two switching elements with their source terminals connected to each other.

[0020] The multiple bidirectional switches TSW are a first high-side bidirectional switch HS1, a first low-side bidirectional switch LS1, a second high-side bidirectional switch HS2, a second low-side bidirectional switch LS2, a third high-side bidirectional switch HS3, and a third low-side bidirectional switch LS3.

[0021] The first high-side bidirectional switch HS1 connects the first input terminal 31A and the first output terminal 32A. Specifically, the first high-side bidirectional switch HS1 has an eleventh switch element S11 and a twentieth switch element S21. The drain terminal of the eleventh switch element S11 is connected to the first input terminal 31A. The source terminal of the eleventh switch element S11 is connected to the source terminal of the twentieth switch element S21. The drain terminal of the twentieth switch element S21 is connected to the first output terminal 32A.

[0022] The first low-side bidirectional switch LS1 connects the first input terminal 31A and the second output terminal 32B. Specifically, the first low-side bidirectional switch LS1 includes a 24th switch element S24 and a 14th switch element S14. The drain terminal of the 24th switch element S24 is connected to the first input terminal 31A. The source terminal of the 24th switch element S24 is connected to the source terminal of the 14th switch element S14. The drain terminal of the 14th switch element S14 is connected to the second output terminal 32B.

[0023] The second high-side bidirectional switch HS2 connects the second input terminal 31B and the first output terminal 32A. Specifically, the second high-side bidirectional switch HS2 has a 13th switch element S13 and a 23rd switch element S23. The drain terminal of the 13th switch element S13 is connected to the second input terminal 31B. The source terminal of the 13th switch element S13 is connected to the source terminal of the 23rd switch element S23. The drain terminal of the 23rd switch element S23 is connected to the first output terminal 32A.

[0024] The second low-side bidirectional switch LS2 connects the second input terminal 31B and the second output terminal 32B. Specifically, the second low-side bidirectional switch LS2 has a 26th switch element S26 and a 16th switch element S16. The drain terminal of the 26th switch element S26 is connected to the second input terminal 31B. The source terminal of the 26th switch element S26 is connected to the source terminal of the 16th switch element S16. The drain terminal of the 16th switch element S16 is connected to the second output terminal 32B.

[0025] The third high-side bidirectional switch HS3 connects the third input terminal 31C and the first output terminal 32A. Specifically, the third high-side bidirectional switch HS3 has a 15th switch element S15 and a 25th switch element S25. The drain terminal of the 15th switch element S15 is connected to the third input terminal 31C. The source terminal of the 15th switch element S15 is connected to the source terminal of the 25th switch element S25. The drain terminal of the 25th switch element S25 is connected to the first output terminal 32A.

[0026] The third low-side bidirectional switch LS3 connects the third input terminal 31C and the second output terminal 32B. Specifically, the third low-side bidirectional switch LS3 has a 22nd switch element S22 and a 12th switch element S12. The drain terminal of the 22nd switch element S22 is connected to the third input terminal 31C. The source terminal of the 22nd switch element S22 is connected to the source terminal of the 12th switch element S12. The drain terminal of the 12th switch element S12 is connected to the second output terminal 32B.

[0027] As shown in Figure 1, the power converter 10 has a transformer circuit 40. The transformer circuit 40 also includes a fourth inductor L4, a first transformer 41, and a second transformer 42. The first end of the fourth inductor L4 is connected to the first output terminal 32A of the switching circuit 30.

[0028] The first transformer 41 comprises a primary winding 41A and a secondary winding 41B. In the first transformer 41, the primary winding 41A and the secondary winding 41B are electrically insulated. These primary windings 41A and the secondary winding 41B are capable of transmitting power by electromagnetic induction. The second transformer 42 similarly comprises a primary winding 42A and a secondary winding 42B. In the second transformer 42, the primary winding 42A and the secondary winding 42B are electrically insulated. These primary windings 42A and the secondary winding 42B are capable of transmitting power by electromagnetic induction.

[0029] The first end of the primary winding 41A of the first transformer 41 is connected to the second end of the fourth inductor L4. The second end of the primary winding 41A of the first transformer 41 is connected to the first end of the primary winding 42A of the second transformer 42. The second end of the primary winding 42A of the second transformer 42 is connected to the second output terminal 32B of the switching circuit 30. In this way, the primary winding 42A of the second transformer 42 is connected in series with the primary winding 41A of the first transformer 41.

[0030] As shown in Figure 1, the power converter 10 includes a first rectifier circuit 50, an output noise filter 60, and a first snubber circuit 70. The first rectifier circuit 50 has four semiconductor elements. These four semiconductor elements are a first switch element 51, a second switch element 52, a third switch element 53, and a fourth switch element 54. The first to fourth switch elements 51 to 54 are all n-channel type MOSFETs. The first rectifier circuit 50 can convert AC power applied from the secondary winding 41B into DC power by controlling each switch element by a control unit 100, which will be described later.

[0031] The source terminal of the first switch element 51 is connected to the first end of the secondary winding 41B of the first transformer 41. The drain terminal of the first switch element 51 is connected to the drain terminal of the third switch element 53. The source terminal of the third switch element 53 is connected to the second end of the secondary winding 41B of the first transformer 41 and the drain terminal of the fourth switch element 54. The source terminal of the fourth switch element 54 is connected to the source terminal of the second switch element 52. The drain terminal of the second switch element 52 is connected to the first end of the secondary winding 41B of the first transformer 41 and the source terminal of the first switch element 51.

[0032] The first rectifier circuit 50 includes a first high-potential output terminal 55A and a first low-potential output terminal 55B. DC power is output from the first high-potential output terminal 55A and the first low-potential output terminal 55B of the first rectifier circuit 50. In this embodiment, the first high-potential output terminal 55A is the connection point where the drain terminal of the first switch element 51 and the drain terminal of the third switch element 53 are connected. The first low-potential output terminal 55B is the connection point where the source terminal of the second switch element 52 and the source terminal of the fourth switch element 54 are connected. The first high-potential output terminal 55A is connected to the first external output terminal 12A via the output-side noise filter 60. The first low-potential output terminal 55B is connected to the second external output terminal 12B via the first snubber circuit 70. That is, the first rectifier circuit 50 is connected between the secondary winding 41B of the first transformer 41 and each external output terminal.

[0033] The output noise filter 60 is a so-called low-pass filter. The output noise filter 60 includes a fifth inductor L5 and a fourth capacitor C4. The first end of the fifth inductor L5 is connected to the first high-potential output terminal 55A of the first rectifier circuit 50. That is, the first end of the fifth inductor L5 is connected to the drain terminal of the first switch element 51 and the drain terminal of the third switch element 53. The second end of the fifth inductor L5 is connected to the first external output terminal 12A. The first end of the fourth capacitor C4 is connected to the second end of the fifth inductor L5. The second end of the fourth capacitor C4 is connected to the second external output terminal 12B. The circuit of the output noise filter 60 composed of these elements is sometimes referred to as a smoothing filter or smoothing circuit.

[0034] As shown in Figure 1, the first snubber circuit 70 includes a first connection terminal CT1, a second connection terminal CT2, a third connection terminal CT3, and a fourth connection terminal CT4. The first connection terminal CT1 is connected to the first high-potential output terminal 55A of the first rectifier circuit 50. Furthermore, the first connection terminal CT1 is connected to the first end of the fifth inductor L5. The second connection terminal CT2 is connected to the first low-potential output terminal 55B of the first rectifier circuit 50. The third connection terminal CT3 is connected to the second end of the fifth inductor L5, the first external output terminal 12A, and the first end of the fourth capacitor C4. The fourth connection terminal CT4 is connected to the second external output terminal 12B and the second end of the fourth capacitor C4.

[0035] As shown in Figure 3, the first snubber circuit 70 includes a first diode 71, a second diode 72, and a third diode 73. The first snubber circuit 70 also includes a first snubber capacitor 74, a first snubber switch 76, and a first snubber inductor 77.

[0036] The anode of the first diode 71 is connected to the first connection terminal CT1. The cathode of the first diode 71 is connected to the first terminal of the first snubber capacitor 74. Therefore, the first diode 71 allows current to flow from the first connection terminal CT1 to the first snubber capacitor 74. On the other hand, the first diode 71 does not allow current to flow from the first snubber capacitor 74 to the first connection terminal CT1.

[0037] The second end of the first snubber capacitor 74 is connected to the second connection terminal CT2 and the fourth connection terminal CT4. Therefore, the first snubber capacitor 74 is connected between the first high-potential output terminal 55A and the first low-potential output terminal 55B of the first rectifier circuit 50.

[0038] The first snubber switch 76 is an n-channel MOSFET. The drain terminal of the first snubber switch 76 is connected to the cathode of the first diode 71 and to the first terminal of the first snubber capacitor 74. The source terminal of the first snubber switch 76 is connected to the third connection terminal CT3 via the first snubber inductor 77. Therefore, the first snubber switch 76 is connected between the high-potential terminal of the first snubber capacitor 74 and the first external output terminal 12A.

[0039] The cathode of the second diode 72 is connected to the source terminal of the first snubber switch 76. The anode of the second diode 72 is connected to the second connection terminal CT2 and the fourth connection terminal CT4. In other words, the second diode 72 allows current to flow from the second connection terminal CT2 and the fourth connection terminal CT4 to the first snubber switch 76. On the other hand, the second diode 72 does not allow current to flow from the first snubber switch 76 to the second connection terminal CT2 and the fourth connection terminal CT4. Therefore, the second diode 72 is a so-called freewheeling diode.

[0040] The first end of the first snubber inductor 77 is connected to the source terminal of the first snubber switch 76 and the cathode of the second diode 72. The second end of the first snubber inductor 77 is connected to the anode of the third diode 73.

[0041] The cathode of the third diode 73 is connected to the third connection terminal CT3. Therefore, the third diode 73 allows current to flow from the first snubber inductor 77 to the third connection terminal CT3. On the other hand, the third diode 73 does not allow current to flow from the third connection terminal CT3 to the first snubber inductor 77.

[0042] As shown in Figure 1, the power converter 10 includes a second rectifier circuit 80, a sixth inductor L6, and a second snubber circuit 90. The second rectifier circuit 80 has four semiconductor elements. These four semiconductor elements are a fifth switch element 85, a sixth switch element 86, a seventh switch element 87, and an eighth switch element 88. The fifth to eighth switch elements 85 to 88 are all n-channel type MOSFETs. The second rectifier circuit 80 can convert AC power applied from the secondary winding 42B of the second transformer 42 into DC power through control of each switch element by the control unit 100, which will be described later.

[0043] The source terminal of the fifth switch element 85 is connected to the first end of the secondary winding 42B of the second transformer 42. The drain terminal of the fifth switch element 85 is connected to the drain terminal of the seventh switch element 87. The source terminal of the seventh switch element 87 is connected to the second end of the secondary winding 42B of the second transformer 42 and the drain terminal of the eighth switch element 88. The source terminal of the eighth switch element 88 is connected to the source terminal of the sixth switch element 86. The drain terminal of the sixth switch element 86 is connected to the first end of the secondary winding 42B of the second transformer 42 and the source terminal of the fifth switch element 85.

[0044] The second rectifier circuit 80 includes a second high-potential output terminal 89A and a second low-potential output terminal 89B. DC power is output from the second high-potential output terminal 89A and the second low-potential output terminal 89B of the second rectifier circuit 80. In the present embodiment, the second high-potential output terminal 89A is a connection point to which the drain terminals of the fifth switch element 85 and the seventh switch element 87 are connected. The second low-potential output terminal 89B is a connection point to which the source terminals of the sixth switch element 86 and the eighth switch element 88 are connected. The second high-potential output terminal 89A is connected to the first external output terminal 12A via the sixth inductor L6. The second low-potential output terminal 89B is connected to the second external output terminal 12B via the second snubber circuit 90. That is, the second rectifier circuit 80 is connected between the secondary winding 42B of the second transformer 42 and each external output terminal.

[0045] The first end of the sixth inductor L6 is connected to the second high-potential output terminal 89A of the second rectifier circuit 80. That is, the first end of the sixth inductor L6 is connected to the drain terminals of the fifth switch element 85 and the seventh switch element 87. The second end of the sixth inductor L6 is connected to the first external output terminal 12A. Also, the second end of the sixth inductor L6 is connected to the first end of the fourth capacitor C4 in the output-side noise filter 60 described above. Therefore, the sixth inductor L6 functions as a noise filter, more specifically a low-pass filter, together with the fourth capacitor C4. In other words, a noise filter is connected to the second rectifier circuit 80, and the noise filter shares the output-side noise filter 60 and the fourth capacitor C4.

[0046] As shown in FIG. 1, the second snubber circuit 90 includes a fifth connection terminal CT5, a sixth connection terminal CT6, a seventh connection terminal CT7, and an eighth connection terminal CT8. The fifth connection terminal CT5 is connected to the second high-potential output terminal 89A of the second rectifier circuit 80. Moreover, the fifth connection terminal CT5 is connected to the first end of the sixth inductor L6. The sixth connection terminal CT6 is connected to the second low-potential output terminal 89B of the second rectifier circuit 80. The seventh connection terminal CT7 is connected to the second end of the sixth inductor L6, the first external output terminal 12A, and the first end of the fourth capacitor C4. The eighth connection terminal CT8 is connected to the second external output terminal 12B and the second end of the fourth capacitor C4.

[0047] As shown in FIG. 4, the second snubber circuit 90 includes a fourth diode 91, a fifth diode 92, and a sixth diode 93. Further, the second snubber circuit 90 includes a second snubber capacitor 94, a second snubber switch 96, and a second snubber inductor 97.

[0048] The anode of the fourth diode 91 is connected to the fifth connection terminal CT5. The cathode of the fourth diode 91 is connected to the first end of the second snubber capacitor 94. Therefore, the fourth diode 91 allows current to flow from the fifth connection terminal CT5 to the second snubber capacitor 94. On the other hand, the fourth diode 91 does not allow current to flow from the second snubber capacitor 94 to the fifth connection terminal CT5.

[0049] The second end of the second snubber capacitor 94 is connected to the sixth connection terminal CT6 and the eighth connection terminal CT8. Therefore, the second snubber capacitor 94 is connected between the second high-potential output terminal 89A and the second low-potential output terminal 89B of the second rectifier circuit 80.

[0050] The second snubber switch 96 is an n-channel MOSFET. The drain terminal of the second snubber switch 96 is connected to the cathode of the fourth diode 91 and to the first terminal of the second snubber capacitor 94. The source terminal of the second snubber switch 96 is connected to the seventh connection terminal CT7 via the second snubber inductor 97. Therefore, the second snubber switch 96 is connected between the high-potential terminal of the second snubber capacitor 94 and the first external output terminal 12A.

[0051] The cathode of the fifth diode 92 is connected to the source terminal of the second snubber switch 96. The anode of the fifth diode 92 is connected to the sixth connection terminal CT6 and the eighth connection terminal CT8. In other words, the fifth diode 92 allows current to flow from the sixth connection terminal CT6 and the eighth connection terminal CT8 to the second snubber switch 96. On the other hand, the fifth diode 92 does not allow current to flow from the second snubber switch 96 to the sixth connection terminal CT6 and the eighth connection terminal CT8. Therefore, the fifth diode 92 is a so-called freewheeling diode.

[0052] The first end of the second snubber inductor 97 is connected to the source terminal of the second snubber switch 96 and the cathode of the fifth diode 92. The second end of the second snubber inductor 97 is connected to the anode of the sixth diode 93.

[0053] The cathode of the sixth diode 93 is connected to the seventh connection terminal CT7. Therefore, the sixth diode 93 allows current to flow from the second snubber inductor 97 to the seventh connection terminal CT7. On the other hand, the sixth diode 93 does not allow current to flow from the seventh connection terminal CT7 to the second snubber inductor 97.

[0054] (Regarding the control unit) As shown in Figure 1, the power converter 10 is equipped with a control unit 100. The control unit 100 has a storage device and an execution device (not shown). In other words, the control unit 100 is an MCU (Microcontroller Unit). The storage device of the control unit 100 stores various programs that are executed by the execution device. One of these programs is a program PG for controlling the first snubber switch 76 and the second snubber switch 96.

[0055] The execution device includes, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), an FPGA (Field Programmable Gate Array), a CPLD (Complex Programmable Logic Device), and an ASIC (Application Specific Integrated Circuit). In the following, the control by the execution device of the control unit 100 will simply be referred to as control by the control unit 100.

[0056] When power is supplied to the power converter 10 from the three-phase AC power supply PS, the control unit 100 executes a program stored in its memory. In accordance with this program, the control unit 100 controls each bidirectional switch TSW of the switching circuit 30, each switch element of the first rectifier circuit 50, and each switch element of the second rectifier circuit 80 in a predetermined switching pattern.

[0057] Specifically, the power converter 10 includes a gate drive circuit (not shown). The control unit 100 inputs a switching signal to the input terminal of the gate drive circuit. Based on this switching signal, the gate drive circuit outputs a switching signal as a gate drive voltage to the gate terminal of each switch element. In other words, the control unit 100 uses the gate drive circuit to control the on / off state of each switch element.

[0058] As shown in Figure 2, the switching signals for each bidirectional switch TSW of the switching circuit 30 are the 11th switching signal SG11 to the 16th switching signal SG16 and the 21st switching signal SG21 to the 26th switching signal SG26. The 11th switching signal SG11 to the 16th switching signal SG16 correspond one-to-one to the 11th switching element S11 to the 16th switching element S16, respectively. The 21st switching signal SG21 to the 26th switching signal SG26 correspond one-to-one to the 21st switching element S21 to the 26th switching element S26, respectively. By switching each bidirectional switch TSW on or off based on each switching signal, the switching circuit 30 can convert the three-phase AC power input to each input terminal into single-phase AC power. That is, single-phase AC power is applied to the primary winding 41A of the first transformer 41. When AC power is applied to the primary winding 41A as described above, single-phase AC power is also generated in the secondary winding 41B due to electromagnetic induction.

[0059] As shown in Figure 1, the switching signals for each switch element of the first rectifier circuit 50 and each switch element of the second rectifier circuit 80 are the first switching signal SG1, the second switching signal SG2, the third switching signal SG3, and the fourth switching signal SG4. The first to fourth switching signals SG1 to SG4 correspond one-to-one with the first to fourth switch elements 51 to 54 of the first rectifier circuit 50. Similarly, the first to fourth switching signals SG1 to SG4 correspond one-to-one with the fifth to eighth switch elements 85 to 88 of the second rectifier circuit 80. Therefore, each switch element of the first rectifier circuit 50 and each switch element of the second rectifier circuit 80 are switched on and off in a similar manner.

[0060] When current flows from the second end to the first end of the secondary winding 41B of the first transformer 41, the control unit 100 switches the first switch element 51 and the fourth switch element 54 to the ON state. Furthermore, the control unit 100 switches the second switch element 52 and the third switch element 53 to the OFF state. This ON / OFF state of the switch elements is called the first switching pattern. In this first switching pattern, current flows from the first end of the secondary winding 41B to the first external output terminal 12A via the first switch element 51. As described above, the primary winding 41A of the first transformer 41 and the primary winding 42A of the second transformer 42 are connected in series. Therefore, when current flows from the second end to the first end of the secondary winding 41B of the first transformer 41, current also flows from the second end to the first end of the secondary winding 42B of the second transformer 42.

[0061] When current flows from the first end to the second end of the secondary winding 41B of the first transformer 41, the control unit 100 switches the second switch element 52 and the third switch element 53 to the ON state. Furthermore, the control unit 100 switches the first switch element 51 and the fourth switch element 54 to the OFF state. This ON / OFF state of the switch elements is called the second switching pattern. In this second switching pattern, current flows from the second end of the secondary winding 41B to the first external output terminal 12A via the third switch element 53. Therefore, the control unit 100 converts the AC power generated in the secondary winding 41B into DC power in the first rectifier circuit 50. As a result, while the power converter 10 is running, the potential of the first high-potential output terminal 55A of the first rectifier circuit 50 is higher than the potential of the first low-potential output terminal 55B.

[0062] (Regarding the control of each snubber switch) Next, the control of the first snubber switch 76 and the second snubber switch 96 by the control unit 100 will be described.

[0063] As shown in Figure 3, the control unit 100 generates a first control signal CS1 as a gate drive signal for the first snubber switch 76 of the first snubber circuit 70 and outputs it to the gate terminal of the first snubber switch 76. Also, as shown in Figure 4, the control unit 100 generates a second control signal CS2 as a gate drive signal for the second snubber switch 96 of the second snubber circuit 90 and outputs it to the gate terminal of the second snubber switch 96. The control unit 100 controls the first snubber circuit 70 in a so-called discontinuous mode. The discontinuous mode is a mode in which the first snubber switch 76 is controlled such that there is a period of time when no current flows through the first snubber inductor 77 of the first snubber circuit 70. Similarly, the control unit 100 controls the second snubber circuit 90 in a discontinuous mode as well.

[0064] Specifically, the control unit 100 performs the functions of the following functional blocks by executing the program PG stored in the memory device. Note that the term "circuit" in the following description of the control unit 100 is for convenience only and does not indicate that it is configured as an analog circuit.

[0065] As shown in Figure 5, the control unit 100 functions as a first control circuit 101, a second control circuit 102, a pulse signal generation circuit 103, a first OR circuit 106, and a second OR circuit 107.

[0066] The first control circuit 101 acquires a first upper limit value UL1, a first lower limit value DL1, and a first capacitor voltage VC1. The first upper limit value UL1 and the first lower limit value DL1 are pre-stored in the memory of the control unit 100. The first upper limit value UL1 is defined as a value less than or equal to the positive peak voltage of the first high-potential output terminal 55A while the power converter 10 is in operation. The first lower limit value DL1 is defined as a value less than the first upper limit value UL1. The first capacitor voltage VC1 is the terminal voltage of the first snubber capacitor 74 in the first snubber circuit 70. The first capacitor voltage VC1 is detected by a voltage detection circuit (not shown) and acquired by the first control circuit 101.

[0067] The first control circuit 101 outputs a first intermediate signal IS1 that indicates either an H level or an L level. When the first control circuit 101 is outputting an L level first intermediate signal IS1, it compares the first capacitor voltage VC1 with a first upper limit value UL1. Then, when the first capacitor voltage VC1 becomes greater than or equal to the first upper limit value UL1, the first control circuit 101 switches the first intermediate signal IS1 to an H level. Also, when the first control circuit 101 is outputting an H level first intermediate signal IS1, it compares the first capacitor voltage VC1 with a first lower limit value DL1. Then, when the first capacitor voltage VC1 becomes less than or equal to the first lower limit value DL1, the first control circuit 101 switches the first intermediate signal IS1 to an L level. In this way, the first control circuit 101 is a hysteresis comparator that uses the first upper limit value UL1 and the first lower limit value DL1, which are different from each other, as thresholds.

[0068] The second control circuit 102 acquires the second upper limit value UL2, the second lower limit value DL2, and the second capacitor voltage VC2. The second upper limit value UL2 and the second lower limit value DL2 are pre-stored in the memory of the control unit 100. The second upper limit value UL2 is defined as a value less than or equal to the positive peak voltage of the second high-potential output terminal 89A while the power converter 10 is in operation. The second lower limit value DL2 is defined as a value less than the second upper limit value UL2. In this embodiment, the second upper limit value UL2 and the second lower limit value DL2 are the same values ​​as the first upper limit value UL1 and the first lower limit value DL1, respectively. The second capacitor voltage VC2 is the terminal voltage of the second snubber capacitor 94 in the second snubber circuit 90. The second capacitor voltage VC2 is detected by a voltage detection circuit (not shown) and acquired by the second control circuit 102.

[0069] The second control circuit 102 outputs a second intermediate signal IS2 that indicates either an H level or an L level. When the second control circuit 102 is outputting an L level second intermediate signal IS2, it compares the second capacitor voltage VC2 with the second upper limit value UL2. Then, when the second capacitor voltage VC2 becomes greater than or equal to the second upper limit value UL2, the second control circuit 102 switches the second intermediate signal IS2 to an H level. Also, when the second control circuit 102 is outputting an H level second intermediate signal IS2, it compares the second capacitor voltage VC2 with the second lower limit value DL2. Then, when the second capacitor voltage VC2 becomes less than or equal to the second lower limit value DL2, the second control circuit 102 switches the second intermediate signal IS2 to an L level. In this way, the second control circuit 102 is a hysteresis comparator that uses the second upper limit value UL2 and the second lower limit value DL2, which are different from each other, as thresholds.

[0070] The pulse signal generation circuit 103 outputs a pulse signal PWM that alternately repeats high and low levels. In this embodiment, the proportion of high levels in one cycle of the pulse signal PWM, i.e., the on-duty cycle, is constant. The pulse signal generation circuit 103 changes the frequency of the pulse signal PWM based on the AC input voltage to the first transformer 41. Specifically, the pulse signal generation circuit 103 acquires the voltage between a pair of output terminals of the switching circuit 30. This voltage is acquired by a voltage detection circuit (not shown) and output to the pulse signal generation circuit 103. The pulse signal generation circuit 103 then calculates the effective value of the output voltage of the switching circuit 30 based on the amplitude of the voltage between the pair of output terminals. The pulse signal generation circuit 103 treats the calculated effective value as the AC input voltage to the first transformer 41. The pulse signal generation circuit 103 increases the frequency of the pulse signal PWM as the AC input voltage to the first transformer 41 increases.

[0071] Here, the AC input voltage to the first transformer 41 is an arbitrary first value, and the length of one cycle of on / off for the first snubber switch 76 and the second snubber switch 96 at this time is defined as the first period. Also, the AC input voltage to the first transformer 41 is a second value smaller than the first value, and the length of one cycle of on / off for the first snubber switch 76 and the second snubber switch 96 at this time is defined as the second period. According to the control of the pulse signal PWM frequency by the pulse signal generation circuit 103 described above, the first period becomes shorter than the second period. In particular, in this embodiment, the larger the AC input voltage to the first transformer 41, the shorter one cycle of on / off for the first snubber switch 76 and the second snubber switch 96 becomes.

[0072] The first OR circuit 106 acquires the first intermediate signal IS1 from the first control circuit 101. The first OR circuit 106 also acquires the pulse signal PWM from the pulse signal generation circuit 103. The first OR circuit 106 then outputs the logical OR of the first intermediate signal IS1 and the pulse signal PWM as the first control signal CS1. Therefore, the first control signal CS1 becomes high when at least one of the first intermediate signal IS1 and the pulse signal PWM is high. The first control signal CS1 becomes low when both the first intermediate signal IS1 and the pulse signal PWM are low.

[0073] The second OR circuit 107 acquires the second intermediate signal IS2 from the second control circuit 102. The second OR circuit 107 also acquires the pulse signal PWM from the pulse signal generation circuit 103. The second OR circuit 107 then outputs the OR of the second intermediate signal IS2 and the pulse signal PWM as the second control signal CS2. Therefore, the second control signal CS2 is at a high level when at least one of the second intermediate signal IS2 and the pulse signal PWM is at a high level. The second control signal CS2 is at a low level when both the second intermediate signal IS2 and the pulse signal PWM are at a low level.

[0074] (Regarding the operation of the first snubber circuit) First, we assume that the first intermediate signal IS1 output by the first control circuit 101 is input to the first snubber switch 76 as the gate drive signal for the first snubber switch 76 of the first snubber circuit 70. Also, under this assumption, the terminal voltage of the first snubber capacitor 74 is taken as the virtual capacitor voltage VVC.

[0075] As shown in Figure 6, when the virtual capacitor voltage VVC of the first snubber capacitor 74 exceeds the first lower limit DL1 and is less than the first upper limit UL1, the first intermediate signal IS1 is basically at the L level. At this time, the first snubber switch 76 is off, so no discharge occurs from the first snubber capacitor 74 to the third connection terminal CT3.

[0076] On the other hand, while the power converter 10 is in operation, the potential of the first high-potential output terminal 55A of the first rectifier circuit 50 is higher than the potential of the first low-potential output terminal 55B. Also, the voltage at the first high-potential output terminal 55A fluctuates periodically as each switch element of the first rectifier circuit 50 switches on and off. As a result, the virtual capacitor voltage VVC of the first snubber capacitor 74 increases in steps according to the period in which the voltage at the first high-potential output terminal 55A reaches a positive peak value.

[0077] Then, at time T1, when the virtual capacitor voltage VVC of the first snubber capacitor 74 becomes greater than or equal to the first upper limit value UL1, the first intermediate signal IS1 switches to the H level at the same time T1. Consequently, the first snubber switch 76 turns on, and discharge occurs from the first snubber capacitor 74 to the third connection terminal CT3. As a result, the virtual capacitor voltage VVC of the first snubber capacitor 74 drops sharply.

[0078] At time T2, following time T1, when the virtual capacitor voltage VVC of the first snubber capacitor 74 falls below the first lower limit value DL1, the first intermediate signal IS1 switches to L level at the same time T2. Consequently, the first snubber switch 76 turns off, and discharge from the first snubber capacitor 74 to the third connection terminal CT3 ceases. As a result, similar to the above, the virtual capacitor voltage VVC of the first snubber capacitor 74 gradually increases.

[0079] Assume that the second intermediate signal IS2 output by the second control circuit 102 is input as the gate drive signal for the second snubber switch 96 of the second snubber circuit 90. While a detailed explanation is omitted, in this case, the terminal voltage of the second snubber capacitor 94 changes in the same way as the virtual capacitor voltage VVC of the first snubber capacitor 74.

[0080] Here, it is preferable that the timing at which the first snubber switch 76 of the first snubber circuit 70 turns on and the timing at which the second snubber switch 96 of the second snubber circuit 90 turns on are perfectly synchronized. However, due to individual differences in each element, detection errors in the terminal voltage of each snubber capacitor, etc., the two snubber switches do not necessarily turn on simultaneously. For example, suppose the second snubber switch 96 turns on earlier than the first snubber switch 76 turns on. In this case, the second capacitor voltage VC2 of the second snubber capacitor 94 becomes smaller than the first capacitor voltage VC1 of the first snubber capacitor 74. As a result, the voltage applied to the sixth inductor L6 becomes smaller than the voltage applied to the fifth inductor L5, creating a difference in the magnitude of the current flowing through both inductors. Due to the effect of this difference in the magnitude of the current, a high-frequency fluctuating current flows between the first rectifier circuit 50 and the second rectifier circuit 80. As a result, the voltage in the transformer circuit 40 fluctuates rapidly, increasing the overall power loss in the power conversion device 10.

[0081] In the above embodiment, the first control signal CS1 is input to the first snubber switch 76 as a gate drive signal for the first snubber circuit 70. The first control signal CS1 is a logical OR signal of the pulse signal PWM and the first intermediate signal IS1. Therefore, when the first intermediate signal IS1 is at an L level, the waveform of the first control signal CS1 is the same as that of the pulse signal PWM.

[0082] When a first control signal CS1, which has the same waveform as the pulse signal PWM, is input to the first snubber switch 76, the first snubber switch 76 repeatedly turns on and off at a frequency corresponding to the switching frequency between the H level and L level of the pulse signal PWM. At this time, the magnitude of the first capacitor voltage VC1 of the first snubber capacitor 74 does not affect the on / off operation of the first snubber switch 76. That is, the first snubber switch 76 repeatedly turns on and off regardless of the first capacitor voltage VC1. As a result of the first snubber switch 76 repeatedly turning on and off, the first snubber capacitor 74 repeatedly discharges and charges at a frequency corresponding to the switching frequency between the H level and L level of the pulse signal PWM. As a result, as shown in Figure 6, the first capacitor voltage VC1 of the first snubber capacitor 74 fluctuates slightly up and down, with a voltage exceeding the first lower limit DL1 and below the first upper limit UL1. Note that the value of the first capacitor voltage VC1 fluctuates finely at a frequency corresponding to the switching frequency between the high and low levels of the pulse signal PWM, but in Figure 6, it is simplified and illustrated as if it were a constant voltage. Also, although a detailed explanation is omitted, the second snubber switch 96 of the second snubber circuit 90 is also controlled by the second control signal CS2, which has the same waveform as the pulse signal PWM. Therefore, the second snubber switch 96 repeatedly turns on and off periodically in synchronization with the first snubber switch 76. As a result, the second capacitor voltage VC2 of the second snubber circuit 90 also changes in the same way as the first capacitor voltage VC1.

[0083] The length of one period of the H level and L level of the pulse signal PWM can be determined as follows. As described above, assume that the first intermediate signal IS1 is input as the gate drive signal to the first snubber switch 76. Then, as shown in Figure 6, under this assumption, the length of one period from the first lower limit DL1 to the first upper limit UL1 of the virtual capacitor voltage VVC is defined as the specific period ST. In this case, it is preferable that the length of one period of the pulse signal PWM is kept sufficiently short of the specific period ST, for example, one-tenth or less of the length.

[0084] Furthermore, the on-duty cycle of the pulse signal PWM can be defined as follows: Assume that the voltage range from the first lower limit DL1 to the first upper limit UL1 is divided into three equal parts. Then, when the first control signal CS1, which has the same waveform as the pulse signal PWM, is input to the first snubber switch 76, it is preferable to define the on-duty cycle of the pulse signal PWM such that the first capacitor voltage VC1 is maintained within the middle range of the three divided ranges.

[0085] <Effects of the Embodiment> The above embodiment provides the following effects. In addition, the effects of the first rectifier circuit 50 and the first snubber circuit 70 described below can also be said to apply to the second rectifier circuit 80 and the second snubber circuit 90.

[0086] (1) In the above embodiment, when the first control signal CS1, which has the same waveform as the pulse signal PWM, is output to the first snubber switch 76, the first snubber switch 76 and the second snubber switch 96 repeatedly turn on and off in sync. As a result, the difference between the first capacitor voltage VC1 of the first snubber capacitor 74 and the second capacitor voltage VC2 of the second snubber capacitor 94 does not tend to become large. As a result, even if a high-frequency fluctuating current flows between the two rectifier circuits, the magnitude of that current becomes small. As a result, power loss in the power converter 10 is reduced.

[0087] (2) In the above embodiment, the control unit 100 controls the first snubber circuit 70 in discontinuous mode. When the first snubber circuit 70 is controlled in discontinuous mode, the first capacitor voltage VC1 of the first snubber capacitor 74 depends not only on the on-duty cycle of the first snubber switch 76, but also on the length of one on / off cycle of the first snubber switch 76.

[0088] In the above embodiment, when the AC input voltage to the first transformer 41 is a first value, the cycle of the first snubber switch 76 becomes shorter compared to when it is a second value which is smaller than the first value. That is, the number of times the first snubber capacitor 74 discharges per unit time increases. As a result, the first capacitor voltage VC1 of the first snubber capacitor 74 becomes smaller. By keeping the first capacitor voltage VC1 small in this way, there is room to charge the first snubber capacitor 74 with the surge voltage generated in the first rectifier circuit 50.

[0089] (3) In the above embodiment, due to some malfunction, the first capacitor voltage VC1 of the first snubber capacitor 74 may exceed the first upper limit value UL1. For example, if the pulse signal generation circuit 103 is unable to generate the pulse signal PWM and the pulse signal PWM is lost, the control unit 100 will be unable to periodically turn the first snubber switch 76 on and off. At this time, the first capacitor voltage VC1 will change in the same way as the virtual capacitor voltage VVC described above. In the above embodiment, in such a case, the first snubber switch 76 is controlled by the first control signal CS1 which has the same waveform as the first intermediate signal IS1. That is, the first snubber switch 76 is switched to the ON state when the first capacitor voltage VC1 of the first snubber capacitor 74 exceeds the first upper limit value. Therefore, it is possible to prevent the first capacitor voltage VC1 of the first snubber capacitor 74 from rising excessively when the pulse signal PWM is lost.

[0090] (4) In the above embodiment, after switching the first snubber switch 76 to the ON state as described above, the control unit 100 switches the first snubber switch 76 to the OFF state when the first capacitor voltage VC1 of the first snubber capacitor 74 falls below the first lower limit value DL1. This allows the first snubber capacitor 74 to be charged with the surge voltage generated in the first rectifier circuit 50 even when the pulse signal PWM is lost.

[0091] (5) In the above embodiment, when the first control signal CS1 having the same waveform as the pulse signal PWM is output to the first snubber switch 76, the first capacitor voltage VC1 of the first snubber capacitor 74 is maintained at a considerably low level relative to the first upper limit value UL1. Therefore, even when the first snubber switch 76 is ON and the second snubber switch 96 is OFF, there is little risk of high voltage being applied to the second snubber circuit 90 and the second rectifier circuit 80.

[0092] <Examples of Modifications> The above embodiment can be implemented with the following modifications. The above embodiment and the following examples of modifications can be combined with each other to the extent that they do not contradict each other technically.

[0093] The configuration of the power converter 10 is not limited to the examples of the above embodiment. For example, the power converter 10 does not need to include one or more selected from the input-side noise filter 20, the switching circuit 30, and the output-side noise filter 60. Furthermore, the power converter 10 may include elements and circuits other than those exemplified in the above embodiment.

[0094] The three-phase AC power supply PS connected to the three external input terminals is not limited to a three-phase three-wire system; it may also be a three-phase four-wire system or a delta-connected three-phase three-wire system. The configuration of the power converter 10 can be appropriately changed to correspond to the type of three-phase AC power supply PS.

[0095] The switch elements constituting the bidirectional switch TSW, the switch elements constituting the first rectifier circuit 50, the switch elements constituting the second rectifier circuit 80, the first snubber switch 76, and the second snubber switch 96 are not limited to the examples of the above embodiment. The two switch elements of the bidirectional switch TSW can be transistors that can conduct current in both the forward and reverse directions. For example, the two switch elements of the bidirectional switch TSW may be P-channel type MOSFETs. In this case, the drain terminals of the two switch elements of the bidirectional switch TSW are connected to each other. Alternatively, the switch elements constituting the bidirectional switch TSW may be gallium nitride high electron mobility transistors (GaN-High Electron Mobility Transistor, GaN-HEMT), etc. In this case, the two switch elements are connected in series so that their source terminals are connected to each other.

[0096] The transformer circuit 40 does not necessarily have to include the fourth inductor L4. In this case, the leakage inductance of the first transformer 41 and the second transformer 42 can be used for resonance instead of the fourth inductor L4.

[0097] The specific circuit configurations of the first rectifier circuit 50 and the second rectifier circuit 80 are not limited to the examples of the above embodiment. For example, these rectifier circuits may be half-wave rectifier circuits or the like. Also, these rectifier circuits may be circuits consisting of four rectifier diodes.

[0098] The first snubber circuit 70 may include at least a second diode 72, a first snubber capacitor 74, a first snubber switch 76, and a first snubber inductor 77. For example, in the above embodiment, a third diode 73 is not essential. That is, the first snubber circuit 70 may not include a third diode 73. The same applies to the second snubber circuit 90.

[0099] In the above embodiment, the control unit 100 is not limited to the configuration of the functional block shown in Figure 5, as long as it can generate control signals equivalent to the first control signal CS1 and the second control signal CS2. Furthermore, the behavior of the H level and L level of the first control signal CS1 and the second control signal CS2 may be changed depending on the type of switch element to be controlled. In addition, the control unit 100 may have an analog circuit for generating the first control signal CS1 and the second control signal CS2. Thus, the configuration of the control unit 100 is not limited as long as the first snubber switch 76 and the second snubber switch 96 can be periodically turned on and off.

[0100] - Of the functional blocks of the control unit 100 in the above embodiment, the first control circuit 101 and the second control circuit 102 may be omitted. In addition, the first OR circuit 106 and the second OR circuit 107 may be omitted accordingly. In this case, the pulse signal PWM will be output directly as the first control signal CS1 and the second control signal CS2.

[0101] In the above embodiment, the pulse signal generation circuit 103 treated the effective value of the voltage between the pair of output terminals of the switching circuit 30 as the AC input voltage to the first transformer 41, but it is not limited to this. For example, the voltage input to the power converter 10 from the three-phase AC power supply PS, that is, the effective value of the voltage at each external input terminal, may be treated as the AC input voltage to the first transformer 41. In this way, even without directly detecting and acquiring the terminal voltage of the first transformer 41, any voltage that is linked to the terminal voltage of the first transformer 41 can be treated as the AC input voltage to the first transformer 41.

[0102] In the above embodiment, the on-duty cycle of the pulse signal PWM may be changed in place of or in addition to the frequency of the pulse signal PWM. Specifically, the control unit 100 may increase the on-duty cycle of the pulse signal PWM as the AC input voltage to the first transformer 41 increases. When the first control signal CS1, which has the same waveform as the pulse signal PWM, is input to the first snubber switch 76, the first capacitor voltage VC1 becomes lower as the on-duty cycle of the pulse signal PWM increases. In other words, the power output by the first snubber circuit 70 increases.

[0103] In the above embodiment, the pulse signal generation circuit 103 changes the frequency of the pulse signal PWM based on the AC input voltage to the first transformer 41. Alternatively, or in addition to this, the pulse signal generation circuit 103 may change the frequency of the pulse signal PWM based on the power output from each external output terminal. Specifically, the pulse signal generation circuit 103 acquires the output current from the external output terminal. This output current is acquired by a current detection circuit (not shown) and output to the pulse signal generation circuit 103. The pulse signal generation circuit 103 lowers the frequency of the pulse signal PWM as the output current decreases. Here, the output current is an arbitrary third value, and the length of one cycle of on / off for the first snubber switch 76 and the second snubber switch 96 at this time is defined as the third period. Also, the output current is a fourth value greater than the third value, and the length of one cycle of on / off for the first snubber switch 76 and the second snubber switch 96 at this time is defined as the fourth period. According to the control of the pulse signal PWM frequency by the pulse signal generation circuit 103 described above, the third period becomes longer than the fourth period. In particular, in this modified example, the smaller the output current from the external output terminal, the longer the on / off cycle of the first snubber switch 76 and the second snubber switch 96 becomes. Here, an example of directly detecting the output current from the external output terminal is given, but the output current may also be estimated based on other values. Other values ​​include, for example, the input current from the three-phase AC power supply PS and the current flowing through the fourth inductor L4.

[0104] In the above modification example, when the output current from the external output terminal is the third value, the cycle of the first snubber switch 76 becomes longer compared to when it is the fourth value, which is greater than the third value. That is, the number of times the first snubber capacitor 74 discharges per unit time decreases. As a result, the power output by the first snubber switch 76 to the pair of external output terminals becomes smaller. Therefore, in situations where the terminal voltage between the pair of external output terminals is small, the risk of a large amount of energy being discharged from the first snubber capacitor 74 and the terminal voltage between the pair of external output terminals becoming unstable can be reduced. In this modification example, instead of or in addition to lowering the frequency of the pulse signal PWM as the output current decreases, the on-duty cycle of the pulse signal PWM may be reduced as the output current decreases.

[0105] <Note> The technical concepts that can be understood from the above embodiments and modified examples are described below. [1] A first transformer having a pair of external output terminals, a primary winding and a secondary winding, a first rectifier circuit connected between the secondary winding of the first transformer and the external output terminals and having a first high-potential output terminal and a first low-potential output terminal, a first snubber circuit having a first snubber capacitor connected between the first high-potential output terminal and the first low-potential output terminal, and a first snubber switch connected between the high-potential terminal of the first snubber capacitor and the external output terminal, a second transformer having a primary winding and a secondary winding connected in series with the primary winding of the first transformer, and a second high-potential output terminal connected between the secondary winding of the second transformer and the external output terminal A power conversion device comprising: a second rectifier circuit having a second low-potential output terminal; a second snubber circuit having a second snubber capacitor connected between the second high-potential output terminal and the second low-potential output terminal, and a second snubber switch connected between the high-potential terminal of the second snubber capacitor and the external output terminal; and a control unit that controls the first snubber switch and the second snubber switch, wherein the control unit controls the first snubber switch and the second snubber switch so that they repeatedly turn on and off synchronously and periodically, regardless of the terminal voltage of the first snubber capacitor and the terminal voltage of the second snubber capacitor.

[0106] [2] The power conversion device according to [1], wherein when the AC input voltage is a first value, the on / off cycle of the first snubber switch and the second snubber switch is shortened compared to when it is a second value which is smaller than the first value.

[0107] [3] The power conversion device according to [1] or [2], wherein when the power output to the external output terminal is a third value, the on / off cycle of the first snubber switch and the second snubber switch is made longer compared to when the power is a fourth value which is greater than the third value.

[0108] [4] The power conversion device according to any one of [1] to [3], wherein the control unit switches the first snubber switch to the ON state when the terminal voltage of the first snubber capacitor exceeds a predetermined first upper limit while the first snubber switch cannot be periodically switched on and off, and switches the second snubber switch to the ON state when the terminal voltage of the second snubber capacitor exceeds a second upper limit while the second snubber switch cannot be periodically switched on and off.

[0109] [5] The power conversion device according to [4], wherein the control unit switches the first snubber switch to the ON state when the terminal voltage of the first snubber capacitor becomes equal to or greater than the first upper limit, and then switches the first snubber switch to the OFF state when the terminal voltage of the first snubber capacitor becomes equal to or less than a predetermined first lower limit value which is less than the first upper limit, and switches the second snubber switch to the ON state when the terminal voltage of the second snubber capacitor becomes equal to or greater than the second upper limit, and then switches the second snubber switch to the OFF state when the terminal voltage of the second snubber capacitor becomes equal to or less than a predetermined second lower limit value which is less than the second upper limit.

[0110] [6] The power conversion device according to [5], wherein the first snubber switch is an n-channel field-effect transistor, and the control unit outputs to the gate of the first snubber switch the logical OR of a pulse signal that alternately repeats high level and low level and a signal that becomes high level when the terminal voltage of the first snubber capacitor becomes above the first upper limit and becomes low level when the terminal voltage of the first snubber capacitor becomes below the first lower limit.

[0111] [7] A pair of external output terminals, a first transformer having a primary winding and a secondary winding, a first rectifier circuit connected between the secondary winding of the first transformer and the external output terminals and having a first high-potential output terminal and a first low-potential output terminal, a first snubber circuit having a first snubber capacitor connected between the first high-potential output terminal and the first low-potential output terminal, and a first snubber switch connected between the high-potential terminal of the first snubber capacitor and the external output terminal, a second transformer having a primary winding and a secondary winding connected in series with the primary winding of the first transformer, and a second high-potential output terminal and a second low-potential output terminal connected between the secondary winding of the second transformer and the external output terminal A program for a power converter comprising: a second rectifier circuit; a second snubber circuit having a second snubber capacitor connected between the second high-potential output terminal and the second low-potential output terminal, and a second snubber switch connected between the high-potential terminal of the second snubber capacitor and the external output terminal; and a control unit that controls the first snubber switch and the second snubber switch, wherein the program causes the control unit to execute a process to control the first snubber switch and the second snubber switch so that the first snubber switch and the second snubber switch repeatedly turn on and off synchronously, regardless of the terminal voltage of the first snubber capacitor and the terminal voltage of the second snubber capacitor.

[0112] 10...Power converter 12A...First external output terminal 12B...Second external output terminal 41...First transformer 42...Second transformer 50...First rectifier circuit 55A...First high-potential output terminal 55B...First low-potential output terminal 70...First snubber circuit 74...First snubber capacitor 76...First snubber switch 80...Second rectifier circuit 89A...Second high-potential output terminal 89B...Second low-potential output terminal 90...Second snubber circuit 94...Second snubber capacitor 96...Second snubber switch 100...Control unit

Claims

1. A first transformer having a pair of external output terminals, a primary winding and a secondary winding, a first rectifier circuit connected between the secondary winding of the first transformer and the external output terminals and having a first high-potential output terminal and a first low-potential output terminal, a first snubber circuit having a first snubber capacitor connected between the first high-potential output terminal and the first low-potential output terminal, and a first snubber switch connected between the high-potential terminal of the first snubber capacitor and the external output terminal, a second transformer having a primary winding and a secondary winding connected in series with the primary winding of the first transformer, and a second rectifier circuit connected between the secondary winding of the second transformer and the external output terminals and having a second high-potential output terminal and a second low-potential output terminal, A power conversion device comprising: a second snubber circuit having a second snubber capacitor connected between the second high-potential output terminal and the second low-potential output terminal, and a second snubber switch connected between the high-potential terminal of the second snubber capacitor and the external output terminal; and a control unit that controls the first snubber switch and the second snubber switch, wherein the control unit controls the first snubber switch and the second snubber switch so that they repeatedly turn on and off synchronously and periodically, regardless of the terminal voltage of the first snubber capacitor and the terminal voltage of the second snubber capacitor.

2. The power conversion device according to claim 1, wherein the control unit shortens the on / off cycle of the first snubber switch and the second snubber switch when the AC input voltage is a first value compared to when it is a second value smaller than the first value.

3. The power conversion device according to claim 1 or 2, wherein the control unit lengthens the on / off cycle of the first snubber switch and the second snubber switch when the power output to the external output terminal is a third value, compared to when it is a fourth value which is greater than the third value.

4. The power conversion device according to any one of claims 1 to 3, wherein the control unit switches the first snubber switch to the ON state when the terminal voltage of the first snubber capacitor exceeds a predetermined first upper limit while the first snubber switch cannot be periodically switched on and off, and switches the second snubber switch to the ON state when the terminal voltage of the second snubber capacitor exceeds a predetermined second upper limit while the second snubber switch cannot be periodically switched on and off.

5. The power conversion device according to claim 4, wherein the control unit switches the first snubber switch to the ON state when the terminal voltage of the first snubber capacitor becomes equal to or greater than the first upper limit, and then switches the first snubber switch to the OFF state when the terminal voltage of the first snubber capacitor becomes equal to or less than a predetermined first lower limit value which is less than the first upper limit, and then switches the second snubber switch to the OFF state when the terminal voltage of the second snubber capacitor becomes equal to or greater than the second upper limit, and then switches the second snubber switch to the ON state when the terminal voltage of the second snubber capacitor becomes equal to or less than a predetermined second lower limit value which is less than the second upper limit.

6. A pair of external output terminals, a first transformer having a primary winding and a secondary winding, a first rectifier circuit connected between the secondary winding of the first transformer and the external output terminals and having a first high-potential output terminal and a first low-potential output terminal, a first snubber circuit having a first snubber capacitor connected between the first high-potential output terminal and the first low-potential output terminal, and a first snubber switch connected between the high-potential terminal of the first snubber capacitor and the external output terminal, a second transformer having a primary winding and a secondary winding connected in series with the primary winding of the first transformer, a second rectifier circuit connected between the secondary winding of the second transformer and the external output terminals and having a second high-potential output terminal and a second low-potential output terminal, A power converter comprising: a second snubber circuit having a second snubber capacitor connected between the second high-potential output terminal and the second low-potential output terminal, and a second snubber switch connected between the high-potential terminal of the second snubber capacitor and the external output terminal; and a control unit that controls the first snubber switch and the second snubber switch, wherein the control unit executes a process to control the first snubber switch and the second snubber switch so that the first snubber switch and the second snubber switch repeatedly turn on and off synchronously, regardless of the terminal voltage of the first snubber capacitor and the terminal voltage of the second snubber capacitor.

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