Cascode amplifier circuit

Abstract

In the present invention, a high-frequency signal is input into a first transistor. A plurality of second transistors are cascode-connected to the first transistor. A bias circuit supplies a bias to each of the plurality of second transistors. A power supply wiring applies a voltage-variable power supply voltage to a cascode connection circuit including the first transistor and the plurality of second transistors. The bias circuit includes at least one voltage regulator, and supplies a bias voltage, which is generated on the basis of the voltage of the power supply wiring and the voltage of a voltage control node of which the voltage is controlled by the voltage regulator, to at least one of the plurality of second transistors.

Description

Cascode amplifier circuit

[0001] This invention relates to a cascode amplifier circuit.

[0002] An envelope tracking amplifier is known that modulates the power supply voltage of a cascode amplifier circuit based on an input signal (Patent Document 1). In the cascode amplifier circuit disclosed in Patent Document 1, the power supply voltage modulated based on the input signal is divided by a resistor voltage divider circuit to generate a bias voltage. This bias voltage is supplied to the cascode transistor.

[0003] Special table 2016-530845 publication

[0004] When the power supply voltage is reduced, the bias voltage generated based on the reduced power supply voltage also decreases. If the bias voltage of the cascode transistor drops excessively, the cascode transistor may turn off, and the gain may decrease. The object of the present invention is to provide a cascode amplifier circuit in which the decrease in gain is suppressed even when the power supply voltage is reduced.

[0005] According to one aspect of the present invention, a cascode amplifier circuit is provided comprising: a first transistor to which a high-frequency signal is input; a plurality of second transistors cascode-connected to the first transistor; a bias circuit that supplies a bias to each of the plurality of second transistors; and a power supply wiring that applies a variable power supply voltage to the cascode connection circuit including the first transistor and the plurality of second transistors, wherein the bias circuit includes at least one voltage regulator and supplies a bias voltage generated based on the voltage of a voltage control node whose voltage is controlled by the voltage regulator and the voltage of the power supply wiring to at least one of the plurality of second transistors.

[0006] The bias voltage of the second transistor changes according to the voltage of the voltage control node. By controlling the voltage of the voltage control node with a voltage regulator, the bias voltage of the second transistor can be optimized. By optimizing the bias voltage, the decrease in gain can be suppressed even when the power supply voltage is reduced.

[0007] FIG. 1 is an equivalent circuit diagram of a cascode amplifier circuit according to the first embodiment. FIG. 2 is a graph showing an example of the relationship between the power supply voltage Vdd and the bias voltage Vg of the cascode amplifier circuit according to the first embodiment. FIG. 3 is a graph showing another example of the relationship between the power supply voltage Vdd and the bias voltage Vg of the cascode amplifier circuit according to the first embodiment. FIG. 4 is an equivalent circuit diagram of a cascode amplifier circuit according to the first comparative example. FIG. 5 is a graph showing the relationship between the power supply voltage Vdd and the bias voltage Vg of the cascode amplifier circuit according to the first comparative example. FIG. 6 is an equivalent circuit diagram of a cascode amplifier circuit according to the second comparative example. FIG. 7 is a graph showing the relationship between the power supply voltage Vdd and the bias voltage Vg of the cascode amplifier circuit according to the second comparative example. FIG. 8 is an equivalent circuit diagram of a cascode amplifier circuit according to the second embodiment. FIG. 9 is an equivalent circuit diagram of a cascode amplifier circuit according to the third embodiment. FIG. 10 is an equivalent circuit diagram of a cascode amplifier circuit according to the fourth embodiment. FIG. 11 is an equivalent circuit diagram of a cascode amplifier circuit according to the fifth embodiment. FIG. 12 is a graph showing an example of the relationship between the power supply voltage Vdd and the bias voltage Vg of the cascode amplifier circuit according to the fifth embodiment.

[0008] [First Embodiment] The cascode amplifier circuit according to the first embodiment will be described with reference to FIGS. 1, FIGS. 2, and FIGS. 3. FIG. 1 is an equivalent circuit diagram of a cascode amplifier circuit according to the first embodiment. A high-frequency input signal Pin is input to the gate of the first transistor Q １ through an impedance matching circuit 60. A bias voltage Vg １ is supplied to the gate of the first transistor Q １ through a resistor element R １ .

[0009] Four second transistors Q ２ connected in series are cascode-connected to the first transistor Q １ . Note that the number of the second transistors Q ２ is not limited to four, and may be two, three, or five or more.

[0010] The first transistor Q １ and the second transistor Q ２An NMOSFET is used as the first transistor Q. １ The source is connected to the reference potential (grounded), and the first transistor Q １ Multiple second transistors Q are connected to the drain of ２ A series circuit consisting of the following is connected. First transistor Q １ and four second transistors Q ２ Then, sequentially numbering is assigned from the reference potential side, for the first transistor Q. １ and four second transistors Q ２ We will distinguish between them. First transistor Q １ This is the first stage transistor, and there are four second-stage transistors Q ２ They are assigned sequential numbers from 2 to 5. Multiple second transistors Q ２ The gates are connected to capacitor C. ２ It is grounded via AC through this.

[0011] The bias circuit 20 has multiple second transistors Q ２ A resistor R is placed at each gate. ２ The bias voltage is supplied via this. Second transistor Q from the second to fifth stages ２ The bias voltage supplied to each gate is Vg ２ , Vg ３ , Vg ４ , Vg ５ This is how it is written.

[0012] Transistor Q (first transistor) １ and four second transistors Q ２ A variable power supply voltage Vdd is supplied to the cascode connection circuit including the first transistor Q via power supply wiring 50 and choke coil L. １ and four second transistors Q ２ A high-frequency output signal, Output, is output from the connection point between the cascode connection circuit and the choke coil L via the impedance matching circuit 61.

[0013] The power supply voltage Vdd is modulated according to the high-frequency input signal Pin using techniques such as envelope tracking (ET) and average power tracking (APT). In other words, the power supply voltage Vdd is variable within a set operating range.

[0014] Four second transistors Q ２ A bias circuit consisting of a voltage regulator 22 and a first resistor voltage divider circuit 23 is connected to each of the gates. Each of the voltage regulators 22 controls the voltage of voltage control node Nv so that the voltage of voltage control node Nv reaches the voltage target value. Voltage control node Nv corresponds to, for example, the output node of the voltage regulator 22.

[0015] Multiple first resistor voltage divider circuits 23 are each connected between the power supply wiring 50 and the voltage control node Nv. The bias circuit 20 generates a bias voltage based on the voltage Vc of the voltage control node Nv and the power supply voltage Vdd applied to the power supply wiring 50, which is then passed through multiple second transistors Q ２ It supplies power to each of them. For example, the voltage divided by the first resistor voltage divider circuit 23 is used as the bias voltage for the second transistor Q ２ It is supplied to the gate. The bias voltage is determined by the voltage of the voltage control node Nv, the power supply voltage Vdd, and the voltage division ratio of the first resistor voltage divider circuit 23.

[0016] If we denote the resistance of the resistor element on the voltage control node Nv side of the first resistor voltage divider circuit 23 as Ra, the resistance of the resistor element on the power supply wiring 50 side as Rb, and the voltage at the voltage control node Nv as Vc, then the bias voltage Vg is expressed by the following formula: Vg = Vdd - (Vdd - Vc) × Rb / (Ra + Rb) ... (1) As can be seen from formula (1), when the power supply voltage Vdd is higher than the voltage Vc at the voltage control node Nv, the bias voltage Vg will be lower than the power supply voltage Vdd. Conversely, when the power supply voltage Vdd is lower than the voltage Vc at the voltage control node Nv, the bias voltage Vg will be higher than the power supply voltage Vdd.

[0017] Next, with reference to Figure 2, the preferred relationship between the power supply voltage Vdd and the bias voltage Vg will be explained.

[0018] Figure 2 is a graph showing an example of the relationship between the power supply voltage Vdd and the bias voltage Vg. The horizontal axis represents the normalized value of the power supply voltage Vdd, and the vertical axis represents the normalized value of the bias voltage Vg. Note that the power supply voltage Vdd and bias voltage Vg are equal to the upper limit value Vdd of the operating range WR of the power supply voltage Vdd. Ｕ The value was normalized to 1. The solid line Vg in the graph in Figure 2. ２ , Vg ３ , Vg ４ , Vg ５ These are the second transistor Q from the second to the fifth stage. ２ This shows the bias voltage supplied to the system. The dashed line in the graph represents the bias voltage Vg, which is equal to the power supply voltage Vdd.

[0019] First, when the normalized value of the power supply voltage Vdd is 1, that is, when the power supply voltage Vdd is the upper limit value Vdd of the operating range WR Ｕ When adjusted to this, the power supply voltage Vdd is the first transistor Q １ and four second transistors Q ２ The bias voltage Vg is distributed almost evenly. ２ , Vg ３ , Vg ４ , Vg ５ This determines the four second transistors Q. ２ The voltage between the source and drain of the second transistor Q ２ This makes it possible to keep the voltage below the withstand voltage. (Four second transistors Q) ２ If the voltage between the source and drain of each transistor exceeds the withstand voltage, the second transistor Q ２ You just need to increase the number of them.

[0020] Next, the power supply voltage Vdd is the lower limit of the operating range WR Vdd Ｌ (For example, when the normalized value of the power supply voltage Vdd is 0.09), the second transistor Q ２ The voltage between each gate and drain is the withstand voltage Vds Ｅ The bias voltage Vg is determined so as not to exceed a certain value. For example, the second transistor Q of the fifth stage. ２ The drain has the lower limit value of the power supply voltage Vdd. Ｌ Because a bias voltage Vg is applied, ５The lower limit Vdd Ｌ The withstand voltage Vds between the gate and drain. Ｅ It is best to set it to a value less than or equal to the added value. Second transistor Q from the second to fourth stages. ２ Similarly, the bias voltage Vg ２ , Vg ３ , Vg ４ It is possible to make a decision.

[0021] Upper limit of power supply voltage Vdd Ｕ The bias voltage Vg and the lower limit Vdd in this case. Ｌ Once the bias voltage Vg is determined, the voltage Vc of the voltage control node Nv and the voltage division ratio Rb / (Ra+Rb) of the first resistor voltage divider circuit 23 can be determined from equation (1).

[0022] Figure 3 is a graph showing another example of the relationship between the power supply voltage Vdd and the bias voltage Vg. The horizontal and vertical axes of the graph in Figure 3 are the same as those of the graph shown in Figure 2. In the example shown in Figure 2, the power supply voltage Vdd is the lower limit Vdd Ｌ Bias voltage Vg ２ , Vg ３ , Vg ４ , Vg ５ However, although they increase in this order, as shown in Figure 3, it is not necessary to follow this order. In this case as well, the second transistor Q ２ The bias voltage Vg is determined so that the voltage between each gate and drain does not exceed the withstand voltage.

[0023] Next, the superior effects of the first embodiment will be described in comparison with the first comparative example shown in Figures 4 and 5.

[0024] Figure 4 is an equivalent circuit diagram of the cascode amplifier circuit according to the first comparative example. In the first comparative example, the bias circuit includes a multi-stage resistive voltage divider circuit 30 connected between the power supply voltage Vdd and the reference potential. The voltage divided by the resistive voltage divider circuit 30 is the bias voltage Vg ２ , Vg ３ , Vg ４ , Vg ５ Four second transistors Q ２ It is supplied to.

[0025] FIG. 5 is a graph showing the relationship between the power supply voltage Vdd and the bias voltage Vg of the cascode amplifier circuit according to the first comparative example. The horizontal axis of the graph in FIG. 5 represents the normalized value of the power supply voltage Vdd, and the vertical axis represents the normalized value of the bias voltage Vg.

[0026] In the modified example shown in FIG. 4, the bias voltage Vg is generated by dividing the power supply voltage Vdd. ２ , Vg ３ , Vg ４ , Vg ５ Therefore, when the power supply voltage Vdd is 0V, the bias voltage Vg ２ , Vg ３ , Vg ４ , Vg ５ also becomes 0V. Also, throughout the operating range WR of the power supply voltage Vdd, the bias voltage Vg ２ , Vg ３ , Vg ４ , Vg ５ is lower than the power supply voltage Vdd.

[0027] In this configuration, the gain deviation in the vicinity of the lower limit value Vdd Ｕ of the power supply voltage Vdd when the gain at the upper limit value Vdd of the operating range WR is used as a reference is large. Specifically, when the power supply voltage Vdd is in the vicinity of the lower limit value Vdd Ｌ of the operating range WR, the gain significantly decreases. This is due to the fact that the bias voltage Vg Ｌ is too low. ２ , Vg ３ , Vg ４ , Vg ５ of the operating range WR.

[0028] On the other hand, in the first embodiment, as shown in FIGS. 2 and 3, in the vicinity of the lower limit value Vdd Ｌ of the power supply voltage Vdd within the operating range WR, the bias voltage Vg ２ , Vg ３ , Vg ４ , Vg ５ can be set to be larger than the power supply voltage Vdd. Therefore, when the power supply voltage Vdd is at the lower limit value Vdd ＬEven when the gain is reduced to near the threshold, the decrease in gain can be suppressed. This is achieved by setting the bias voltage Vg higher than the power supply voltage Vdd, which suppresses the decrease in gain of the second transistor Q. ２ This is because each of them turns on, resulting in a low resistance value, roughly equivalent to the on-resistance.

[0029] Next, the superior effects of the first embodiment will be explained in comparison with the second comparative example shown in Figures 6 and 7.

[0030] Figure 6 is an equivalent circuit diagram of a cascode amplifier circuit according to the second comparative example. In the second comparative example, the bias circuit includes a multi-stage resistive voltage divider circuit 30 connected between a fixed voltage Vsup and a reference potential. The voltage divided by the resistive voltage divider circuit 30 is the bias voltage Vg ２ , Vg ３ , Vg ４ , Vg ５ Four second transistors Q ２ It is supplied to.

[0031] Figure 7 is a graph showing the relationship between the power supply voltage Vdd and the bias voltage Vg of a cascode amplifier circuit according to the second comparative example. In the graph of Figure 7, the horizontal axis represents the normalized value of the power supply voltage Vdd, and the vertical axis represents the normalized value of the bias voltage Vg. Because a fixed voltage Vsup is applied to the resistor voltage divider circuit 30, the bias voltage Vg remains constant even when the power supply voltage Vdd changes. ２ , Vg ３ , Vg ４ , Vg ５ It is constant.

[0032] Power supply voltage Vdd is the lower limit of the operating range Vdd Ｌ With the bias voltage Vg decreasing to near that level, ３ , Vg ４ , Vg ５ This becomes considerably higher than the power supply voltage Vdd. Therefore, the second transistor Q in the fifth stage in particular... ２ In this case, the voltage between the gate and drain exceeds the withstand voltage. This reduces the reliability of the cascode amplifier circuit.

[0033] In contrast, in the first embodiment, as shown in Figures 2 and 3, when the power supply voltage Vdd is low, the bias voltage Vg２ , Vg ３ , Vg ４ , Vg ５ Because the Q of the second transistor also decreases, ２ The voltage between each gate and drain becomes less likely to exceed the withstand voltage. This suppresses the decrease in reliability of the cascode amplifier circuit.

[0034] Furthermore, the digital arithmetic circuit generates a bias voltage Vg as shown in Figures 2 and 3. ２ , Vg ３ , Vg ４ , Vg ５ It is also possible to change the bias voltage Vg. In this configuration, AD conversion by an AD converter that detects the power supply voltage Vdd, digital calculations, and DA conversion by a DA converter that generates the bias voltage are required. For this reason, the bias voltage Vg in response to changes in the power supply voltage Vdd. ２ , Vg ３ , Vg ４ , Vg ５ The tracking speed will become slower.

[0035] It is also possible to use an analog arithmetic circuit using an operational amplifier instead of a digital arithmetic circuit. In this configuration as well, the bias voltage Vg in response to changes in the power supply voltage Vdd ２ , Vg ３ , Vg ４ , Vg ５ The tracking speed is limited by the operating speed of the operational amplifier.

[0036] In contrast, in the first embodiment, the bias voltage Vg is determined by the first resistor voltage divider circuit 23 (Figure 1) connected to the power supply voltage Vdd. ２ , Vg ３ , Vg ４ , Vg ５ Because it generates a bias voltage Vg in response to changes in the power supply voltage Vdd ２ , Vg ３ , Vg ４ , Vg ５ There is almost no delay in the changes.

[0037] As described above, in the first embodiment, the gain deviation when the power supply voltage Vdd changes is suppressed, high reliability is maintained, and the bias voltage Vg is controlled by the change in the power supply voltage Vdd. ２ , Vg ３ , Vg ４ , Vg ５ This enables a sufficiently fast tracking speed.

[0038] Furthermore, in the first embodiment, as shown in equation (1), the slope of the change in bias voltage Vg with respect to the change in power supply voltage Vdd can be adjusted by the voltage division ratio of the first resistor voltage divider circuit 23. Moreover, once the voltage division ratio of the first resistor voltage divider circuit 23 is determined, the bias voltage Vg can be increased or decreased while keeping the slope of the change in bias voltage Vg with respect to the change in power supply voltage Vdd constant, by the voltage Vc of the voltage control node Nv. In this way, in the first embodiment, the bias voltage can be flexibly set according to various requirements.

[0039] Next, we will describe the preferred range of the voltage Vc generated at the voltage control node Nv. When the voltage Vc generated at the voltage control node Nv is 0V, the power supply voltage Vdd is the lower limit Vdd of the operating range WR (Figure 2). Ｌ When set to a value near this range, the bias voltage Vg drops excessively, similar to the comparative example shown in Figure 5. By making the voltage Vc generated at the voltage control node Nv greater than 0V, the excessive drop in the bias voltage Vg can be suppressed.

[0040] The bias voltage Vg is the second transistor Q ２ The drain voltage of the second transistor Q ２ It is preferable to set the voltage within a range less than or equal to the sum of the withstand voltages between the gate and drain of the second transistor Q. ２ The maximum value of the drain voltage is the upper limit of the operating range Vdd when the power supply voltage Vdd is Vdd Ｕ The bias voltage Vg is equal to the power supply voltage Vdd, and the upper limit of the operating range is Vdd. Ｕ Next, the second transistor Q ２It is undesirable from a reliability standpoint for the voltage Vc of the voltage control node Nv to exceed the sum of the withstand voltages between the gate and drain. Therefore, the voltage Vc of the voltage control node Nv should be set to the upper limit of the operating range of the power supply voltage Vdd. Ｕ The second transistor Q ２ It is preferable to set the voltage to be less than or equal to the sum of the withstand voltages between the gate and drain.

[0041] Next, an example of setting the voltage Vc of the voltage control node Nv of the voltage regulator 22 and the voltage division ratio of the first resistor voltage divider circuit 23 will be described. The first transistor Q that constitutes the cascode connection circuit １ and multiple second transistors Q ２ The stacking stage is N stages, and the second transistor Q is the Nth stage. ２ The bias voltage supplied to is Vg Ｎ This is how it is written.

[0042] Second Transistor Q ２ The gate threshold voltage is Vgs Ｔ It is labeled as follows: Second transistor Q ２ The overdrive voltage is V ＯＶ This is how it is written.

[0043] Power supply voltage Vdd is the upper limit of the operating range Vdd Ｕ When adjusting, the upper limit of the power supply voltage Vdd is Vdd Ｕ The first transistor Q of the N stage １ and the second transistor Q ２ Assuming that the voltage is applied equally, the second transistor Q of the Nth stage ２ Source voltage Vs Ｎ It is expressed by the following formula: Vs Ｎ =((N-1) / N)×Vdd Ｕ ... (2) As an example, bias voltage Vg Ｎ It is preferable to set it as follows: Vg Ｎ = Vs Ｎ +Vgs Ｔ +V ＯＶ ... (3)

[0044] Power supply voltage Vdd is the upper limit of the operating range Vdd Ｕ When adjusting it, the second transistor Q of the Nth stage ２Bias voltage Vg Ｎ The second transistor Q in the Nth stage should be such that the value obtained by equation (3) is obtained. ２ It is advisable to determine the voltage Vc of the voltage control node Nv of the voltage regulator 22 that supplies the bias voltage, and the voltage division ratio of the first resistor voltage divider circuit 23.

[0045] Next, a modified example of the first embodiment will be described. In the first embodiment, four second transistors Q ２ A voltage regulator 22 is inserted into each of the bias circuits, but multiple second transistors Q ２ Among some of the second transistor Q ２ The voltage regulator 22 may be inserted only into the bias circuit. The other second transistor Q ２ The bias circuit does not require the insertion of a voltage regulator 22; instead, the first resistor voltage divider circuit 23 can be connected to the reference potential.

[0046] Note that there are multiple second transistors Q ２ Among some of the second transistor Q ２ When inserting the voltage regulator 22 into the bias circuit, the second transistor Q on the side closer to the power supply wiring 50 ２ It is preferable to insert the voltage regulator 22 into the bias circuit.

[0047] Multiple second transistors Q ２ Of these, the second transistor Q is the one closest to the power supply wiring 50. ２ As the source voltage increases, the second transistor Q ２ It is prone to being turned off. The second transistor Q is on the side closer to the power supply wiring 50. ２ By inserting the voltage regulator 22 into the bias circuit and increasing the bias voltage, the second transistor Q ２ This makes it less likely that the system will be turned off.

[0048] In the first embodiment, the first transistor Q １ and four second transistors Q ２Although a MOSFET was used, a bipolar transistor may also be used. If a bipolar transistor is used, the source, drain, and gate in the above explanation should be read as emitter, collector, and base, respectively. Also, the power supply voltage Vdd applied to the drain should be read as the power supply voltage Vcc applied to the collector.

[0049] [Second Embodiment] Next, a cascode amplifier circuit according to the second embodiment will be described with reference to Figure 8. The following description will omit details of components common to the cascode amplifier circuit according to the first embodiment, which was described with reference to Figures 1, 2, and 3.

[0050] Figure 8 is an equivalent circuit diagram of a cascode amplifier circuit according to the second embodiment. In the first embodiment (Figure 1), each output node of the four voltage regulators 22 is used as a voltage control node Nv. In contrast, in the second embodiment, the bias circuit 20 includes a multi-stage second resistor voltage divider circuit 24 that divides the output voltage of one voltage regulator 22, and multiple voltage division points of the second resistor voltage divider circuit 24 each constitute multiple voltage control nodes Nv. The first resistor voltage divider circuit 23 is provided for each of the voltage control nodes Nv, similar to the first embodiment (Figure 1).

[0051] Capacitors C are placed between each of the voltage control nodes Nv and the reference potential, and between the output node of the voltage regulator 22 and the reference potential. ３ , C ４ Capacitor C is connected. ３ , C ４ It has the function of grounding the AC component.

[0052] The resistance values ​​of the resistors constituting the first resistor voltage divider circuit 23 are sufficiently greater than the resistance values ​​of the resistors constituting the second resistor voltage divider circuit 24. Therefore, the current flowing into the second resistor voltage divider circuit 24 via the first resistor voltage divider circuit 23 is sufficiently smaller than the current flowing from the output node of the voltage regulator 22 to the reference potential. As a result, the voltages generated at each of the multiple voltage control nodes Nv, which are divided by the second resistor voltage divider circuit 24, are substantially unaffected by the current flowing through the first resistor voltage divider circuit 23. Consequently, the voltages generated at the voltage control nodes Nv can be considered to be controlled to a nearly constant voltage by the voltage regulator 22.

[0053] Next, the excellent effects of the second embodiment will be described. In the second embodiment, as in the first embodiment, the gain deviation when the power supply voltage Vdd changes is suppressed, high reliability is maintained, and the bias voltage Vg in response to changes in the power supply voltage Vdd is maintained. ２ , Vg ３ , Vg ４ , Vg ５ This enables a sufficiently fast tracking speed. Furthermore, the second embodiment offers the excellent advantage of reducing the number of voltage regulators 22 compared to the first embodiment.

[0054] Next, a modified version of the second embodiment will be described. In the second embodiment (Figure 8), one end of the second resistor voltage divider circuit 24 is connected to a reference potential, and the other end is connected to a voltage regulator 22, and the output voltage of the voltage regulator 22 is divided. Alternatively, both ends of the second resistor voltage divider circuit 24 may be connected to a reference potential, and one of the division points may be connected to the voltage regulator 22.

[0055] [Third Embodiment] Next, a cascode amplifier circuit according to the third embodiment will be described with reference to Figure 9. Hereinafter, the configuration common to the cascode amplifier circuit according to the first embodiment, described with reference to Figures 1, 2, and 3, will not be explained.

[0056] Figure 9 is an equivalent circuit diagram of a cascode amplifier circuit according to the third embodiment. In the first embodiment (Figure 1), the voltage of the voltage control node Nv, which is the output node of each of the four voltage regulators 22, and the voltage division ratio of the first resistor voltage divider circuit 23 are fixed. In contrast, in the third embodiment, the output voltage of each of the voltage regulators 22, i.e., the voltage of each of the voltage control nodes Nv, are variable, and the voltage division ratio of each of the first resistor voltage divider circuits 23 is also variable.

[0057] The output node of the cascode amplifier circuit is connected to the input contact of the band selector switch 46 via the impedance matching circuit 61. Multiple output contacts of the band selector switch 46 are each connected to a filter 47 corresponding to a specific band frequency range.

[0058] The control circuit 45 controls the selection of the output contacts of the band selection switch 46, the output voltages of the voltage regulator 22, and the voltage division ratios of the first resistor voltage divider circuit 23. The control circuit 45 controls the band selection switch 46 according to the operating frequency band of the cascode amplifier circuit, and also controls the bias voltage Vg of the second transistor Q to be optimal for amplifying high-frequency signals in the operating frequency band. ２ The bias circuit 20 is controlled so that it is supplied to the target.

[0059] Next, the excellent effects of the third embodiment will be described. In the third embodiment, as in the first embodiment, the gain deviation when the power supply voltage Vdd changes is suppressed, high reliability is maintained, and the bias voltage Vg in response to changes in the power supply voltage Vdd is maintained. ２ , Vg ３ , Vg ４ , Vg ５ This enables a sufficiently fast tracking speed. Furthermore, in the third embodiment, an optimal bias voltage can be supplied according to the operating frequency band.

[0060] Next, a modification of the third embodiment will be described. In the third embodiment, the function of adjusting the respective output voltages of the voltage regulator 22 and the respective voltage division ratios of the first resistor voltage divider circuit 23 is used to optimize the bias voltage Vg according to the operating frequency band, but it can also be used for other purposes. For example, this function can be used for the purpose of calibrating the bias voltage to compensate for variations in the manufacturing process.

[0061] If a cascode amplifier circuit can operate in either high-power or low-power mode, this function can also be used to optimize the bias voltage Vg according to the power mode.

[0062] [Fourth Embodiment] Next, a cascode amplifier circuit according to the fourth embodiment will be described with reference to Figure 10. The following description will omit details of components common to the cascode amplifier circuit according to the second embodiment, which was described with reference to Figure 8.

[0063] Figure 10 is an equivalent circuit diagram of a cascode amplifier circuit according to the fourth embodiment. In the second embodiment (Figure 8), the output voltage of the voltage regulator 22 is constant. Furthermore, the voltage division ratio of the second resistor voltage divider circuit 24 is also constant. Therefore, the voltage Vc of each of the multiple voltage control nodes Nv is almost constant. Also, the voltage division ratio of each of the first resistor voltage divider circuits 23 is also constant. In contrast, in the fourth embodiment, the output voltage of the voltage regulator 22, the voltage division ratio of the first resistor voltage divider circuit 23, and the voltage division ratio of the second resistor voltage divider circuit 24 are variable. Therefore, as in the case of the third embodiment (Figure 9), the voltage Vc of the multiple voltage control nodes Nv can be changed.

[0064] Next, the excellent effects of the fourth embodiment will be described. In the fourth embodiment, as in the second embodiment, the gain deviation when the power supply voltage Vdd changes is suppressed, high reliability is maintained, and the bias voltage Vg in response to changes in the power supply voltage Vdd is maintained. ２ , Vg ３ , Vg ４ , Vg ５This enables a sufficiently fast tracking speed. Furthermore, in the fourth embodiment, similar to the third embodiment (Figure 9), an optimal bias voltage can be supplied according to the operating frequency band, power mode, etc. In addition, it is possible to calibrate the bias voltage to compensate for variations in the manufacturing process.

[0065] [Fifth Embodiment] Next, a cascode amplifier circuit according to the fifth embodiment will be described with reference to Figures 11 and 12. Hereinafter, the configuration common to the cascode amplifier circuit according to the first embodiment, described with reference to Figures 1, 2, and 3, will not be explained.

[0066] Figure 11 is an equivalent circuit diagram of a cascode amplifier circuit according to the fifth embodiment. In the fifth embodiment, the fifth stage is the second transistor Q ２ The configuration of the bias circuit is the second transistor Q in the fifth stage of the first embodiment (Figure 1). ２ This differs from the configuration of the bias circuit.

[0067] The second transistor Q in the fifth stage ２ The bias circuit includes a voltage regulator 22, a third resistor voltage divider circuit 25, and a diode 26. The third resistor voltage divider circuit 25 is connected between the power supply wiring 50 and the reference potential, and a bias voltage Vg is applied to the voltage divider point 25P. ５ This generates the following. The output node of the voltage regulator 22 corresponds to the voltage control node Nv. The diode 26 is connected between the voltage control node Nv and the voltage divider point 25P in a direction where the direction from the voltage control node Nv towards the voltage divider point 25P is the forward direction.

[0068] Figure 12 is a graph showing an example of the relationship between the power supply voltage Vdd and the bias voltage Vg. The horizontal axis represents the normalized value of the power supply voltage Vdd, and the vertical axis represents the normalized value of the bias voltage Vg. Note that the power supply voltage Vdd and bias voltage Vg are equal to the upper limit value Vdd of the operating range WR of the power supply voltage Vdd. Ｕ The value was normalized to 1. The solid line Vg in the graph of Figure 12. ２ , Vg ３ , Vg ４ , Vg ５ These are the second transistor Q from the second to the fifth stage. ２This shows the bias voltage supplied to the system. The dashed line in the graph represents the bias voltage Vg, which is equal to the power supply voltage Vdd.

[0069] Bias voltage Vg ２ , Vg ３ , Vg ４ The relationship between the power supply voltage Vdd and the power supply voltage Vdd is the same as the relationship in the cascode amplifier circuit according to the first embodiment shown in Figure 2. The power supply voltage Vdd is the upper limit value Vdd of the operating range WR. Ｕ As it decreases from, the bias voltage Vg ５ The voltage also decreases. The voltage at the voltage divider point 25P is the voltage V obtained by subtracting the forward voltage of diode 26 from the voltage Vc of voltage control node Nv. １ When it drops to this point, even if the power supply voltage Vdd drops further, the voltage at the voltage divider point 25P will be voltage V １ It is maintained.

[0070] Next, the excellent effects of the fifth embodiment will be described. In the fifth embodiment, even if the power supply voltage Vdd drops below a predetermined value, the bias voltage Vg ５ Voltage V １ Maintained at voltage V １ It will not fall below a certain value. Therefore, a significant drop in gain when the power supply voltage Vdd decreases can be suppressed.

[0071] Next, a modified example of the fifth embodiment will be described. In the fifth embodiment, the bias circuit, which includes a voltage regulator 22, a diode 26, and a third resistor voltage divider circuit 25, is replaced by the fifth stage second transistor Q ２ It is applied to the other second transistor Q ２ It may be applied to this.

[0072] The embodiments described above are illustrative, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. Similar effects and benefits from similar configurations in multiple embodiments will not be mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the embodiments described above. For example, it will be obvious to those skilled in the art that various modifications, improvements, and combinations are possible.

[0073] 20 Bias circuit 22 Voltage regulator 23 First resistor voltage divider circuit 24 Second resistor voltage divider circuit 25 Third resistor voltage divider circuit 25P Voltage divider point 26 Diode 30 Resistor voltage divider circuit 40 Cascode connection circuit 45 Control circuit 46 Band selection switch 47 Filter 50 Power supply wiring 60, 61 Impedance matching circuit Nv Voltage control node Vg １ , Vg ２ , Vg ３ , Vg ４ , Vg ５ Bias voltage Q １ First transistor Q ２ Second transistor Q ２１ First stage, second transistor Q ２２ Second stage, second transistor Q ２３ Third stage, second transistor Q ２４ The second transistor in the fourth stage

Claims

1. A cascode amplifier circuit comprising: a first transistor to which a high-frequency signal is input; a plurality of second transistors cascode-connected to the first transistor; a bias circuit that supplies a bias to each of the plurality of second transistors; and a power supply wiring that applies a variable power supply voltage to the cascode connection circuit including the first transistor and the plurality of second transistors, wherein the bias circuit includes at least one voltage regulator and supplies a bias voltage generated based on the voltage of a voltage control node whose voltage is controlled by the voltage regulator and the voltage of the power supply wiring to at least one of the plurality of second transistors.

2. The cascode amplifier circuit according to claim 1, wherein the voltage regulator has a function to change the output voltage by external control, and further comprises a control circuit for changing the output voltage of the voltage regulator.

3. The cascode amplifier circuit according to claim 1 or 2, wherein the bias circuit includes a first resistor voltage divider circuit connected between the voltage control node and the power supply wiring, and the voltage divided by the first resistor voltage divider circuit is supplied to the second transistor as the bias voltage.

4. The cascode amplifier circuit according to claim 3, wherein the voltage regulator and the first resistor voltage divider circuit are provided for each of the second transistors.

5. The cascode amplifier circuit according to claim 3, wherein the bias circuit further includes three or more second resistor voltage divider circuits that divide the output voltage of the voltage regulator, and each of the multiple voltage divider points of the second resistor voltage divider circuit constitutes a plurality of voltage control nodes, and the first resistor voltage divider circuit is provided for each of the voltage control nodes.

6. The cascode amplifier circuit according to claim 3, wherein the bias circuit includes a third resistor voltage divider circuit connected between the power supply wiring and a reference potential and generating the bias voltage at the voltage divider point, and a diode connected between the voltage control node and the voltage divider point in a direction such that the direction from the voltage control node toward the voltage divider point is the forward direction.

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