Vertical cavity surface emitting laser device system and vertical cavity surface emitting laser device array

Abstract

In one embodiment, the present invention provides a VCSEL device system comprising a plurality of laser beams individually emitted from a VCSEL device configured with an in-plane light source. This system provides a plurality of synchronized laser emissions indiviudally having aligned parameters.

Description

Vertical Cavity Surface Emitting Laser Device System and Vertical Cavity Surface Emitting Laser Device Array

[0001] According to the present invention, a technique for manufacturing a vertical-cavity surface-emitting laser is provided. Background of the Invention

[0002] Vertical-cavity surface-emitting lasers (VCSELs) are a type of semiconductor laser that emits light perpendicular to the surface of the manufactured wafer, unlike edge-emitting lasers where light propagates along the plane of the wafer. Due to their efficient and compact design, VCSELs are gaining popularity for their applications in data communications, sensing, 3D imaging, and optical mice.

[0003] Conventional VCSELs consist of multiple semiconductor layers, including mirrors and an active region where light is generated. A conventional VCSEL includes an active region, which is a gain medium where electron-hole recombination occurs to generate light. The VCSEL also includes a distributed Bragg reflector (DBR), which consists of highly reflective mirrors on either side of the active region, ensuring that light travels perpendicularly back and forth to amplify the laser radiation. Oxide layers confine the current and optical modes, improving efficiency.

[0004] Various types of conventional VCSELs include single-mode VCSELs. Such single-mode VCSELs emit light in a single transverse mode with a narrow spectral width. In one embodiment, such VCSELs are desirable for high-precision sensing and high-speed communication due to their low divergence and well-defined emission wavelength. Other types include multimode VCSELs. Such multimode VCSELs emit light in multiple transverse optical modes, have a wider spectral output and higher output power, and are suitable for short-distance data communication and low-cost applications such as fiber optic networks. Tunable VCSELs are another example of VCSELs. Tunable devices often feature a mechanism for dynamically adjusting the emission wavelength, using a micro-electromechanical system (MEMS). Other types of VCSELs include polarization-locked VCSELs and long-wavelength VCSELs, which operate at wavelengths around approximately 1.3–1.55 μm, for example, and are commonly used in long-distance telecommunications due to their low absorption and low dispersion in optical fibers.

[0005] Unfortunately, conventional VCSELs have limitations. Specifically, conventional VCSELs have limited power output. Conventional VCSELs typically have lower output power compared to end-emitting lasers. Such VCSELs are not well-suited for long-distance applications requiring high power levels. Also, conventional VCSELs have narrow spectral tuning. In most conventional VCSELs, the emission wavelength is fixed by the structure, limiting the tuning range, which can be a constraint in certain applications such as spectroscopy. Other limitations include thermal sensitivity. The performance of VCSELs can degrade with temperature fluctuations. Wavelengths tend to drift as the temperature rises, which can affect the accuracy of the laser output in temperature-sensitive environments. In addition, conventional VCSELs often exhibit poor polarization control, limiting their use in applications requiring a stable and well-defined polarization state. These and other limitations exist in conventional VCSELs.

[0006] From the above, it is clear that improved technology for VCSEL is highly desirable.

[0007] This invention relates to laser devices and systems. In one embodiment, the invention provides a vertical-cavity surface-emitting laser ("VCSEL") device configured with an in-plane light source. In one embodiment, the in-plane light source is configured to synchronize one or more parameters of a plurality of VCSEL devices with each other and with the in-plane light source. As just one example, the invention can be applied to a variety of applications including lighting, industry, biology, communications, automotive, atomic clocks, games, chemistry, energy including fusion, finance, and more. Of course, other examples exist.

[0008] For example, the present invention provides a vertical cavity surface-emitting laser (VCSEL) device. In one embodiment, the device has a semiconductor substrate containing a compound semiconductor material. In one embodiment, the device has a plurality of VCSEL devices arranged in an array on a first portion of the semiconductor substrate. Each VCSEL device has a first DBR stack and a second DBR stack facing the first DBR stack. Each VCSEL device has a cavity region formed between the first DBR stack and the second DBR stack. In one embodiment, the cavity region has a length of 5 microns (μm) or more to facilitate in-plane propagation of light, such as a laser beam. In one embodiment, the cavity region includes a multiple quantum well region characterized by laser emission and having a first emission spectrum. The cavity region also has an n-type region formed between the multiple quantum well region and the second DBR stack and a p-type region formed between the multiple quantum well region and the first DBR stack.

[0009] In one embodiment, the device has a waveguide that couples each of a plurality of VCSEL devices. In one embodiment, the device has an in-plane light source located in a second portion of a semiconductor substrate. The in-plane light source is characterized by a second emission spectrum such that each of the first emission spectra is included in the second emission spectrum.

[0010] In one embodiment, the device has a free-space gap between a first portion of a semiconductor substrate and a second portion of a semiconductor substrate to isolate multiple VCSEL devices from an in-plane light source. The in-plane light source is characterized by a first parameter, and each VCSEL device is characterized by a second parameter. The first parameter interacts with the second parameter in the waveguide to exhibit the properties of the first parameter, thereby characterizing each VCSEL device by the first parameter.

[0011] In one embodiment, the CBC apparatus has a combiner that is coupled to each of the laser beams emitted from the VCSEL device, coherently coupling each of the laser beams together to form a single coherently coupled laser beam. In one embodiment, the combiner is a lens apparatus, a fiber apparatus comprising multiple fibers operablely coupled to focus each of the laser beams, or is constructed in free space by bending a semiconductor substrate. Naturally, variations are possible.

[0012] In one embodiment, the method includes providing a semiconductor substrate containing a compound semiconductor material. In one embodiment, the semiconductor substrate includes a surface region.

[0013] In one embodiment, the method includes forming an n-type GaN (gallium nitride) material located on a surface region and forming a multiple quantum well region having a first emission spectrum characterized by laser emission in the range of, for example, 400 to 550 nm. In one embodiment, the method includes forming a p-type GaN material located on a multiple quantum well region. The method includes subjecting the p-type GaN material to an injection treatment containing a boron-containing entity.

[0014] In one embodiment, the method includes forming a transparent electrode material located on a p-type GaN material. The method also includes forming a p-type contact pad located on the transparent electrode material.

[0015] In one embodiment, the method includes forming an opening region that penetrates a p-type contact pad in order to expose a portion of the transparent electrode material, and forming an n-contact region by removing a portion of the p-type GaN material and a portion of the multiple quantum well region to expose a portion of the n-type GaN.

[0016] In one embodiment, the method includes forming an n-type contact pad located on an exposed portion of n-type GaN, and then forming a filler material located on the n-type contact pad. In another embodiment, the method includes forming a multilayer substrate by joining the filler material and a support substrate located on the p-type contact pad, as shown in the figure.

[0017] In one embodiment, the method includes inverting a multilayer substrate. The method includes removing a certain thickness from the semiconductor substrate to leave a thin film on the semiconductor substrate, and polishing the back surface of the thin film on the semiconductor substrate.

[0018] In one embodiment, the method includes forming a lens structure from a thin film of a semiconductor substrate using patterning and etching steps. In one embodiment, the method includes forming a first DBR stack located on the surface of a lens structure such that the first DBR stack, lens structure, multiple quantum wells, n-type contact pads, and p-type contact pads correspond to one of a plurality of VCSEL devices formed in an array.

[0019] Depending on the example, the present invention can achieve one or more of these benefits and / or advantages. In one embodiment, the present invention provides a VCSEL array and associated method configured with an in-plane light source. In one embodiment, the present invention provides the advantage of using the VCSEL laser in the claimed embodiment to generate a synchronized laser source through efficient size, weight, and cost. These and other benefits and / or advantages are achievable by the device and associated method. Further details of these benefits and / or advantages can be found throughout this specification, in particular below.

[0020] The properties and advantages of the present invention can be further understood by referring to the latter part of the specification and the accompanying drawings.

[0021] To better understand the present invention, refer to the accompanying drawings. With understanding that these drawings should not be considered limitations of the scope of the present invention, the embodiments described herein and the best mode of the present invention as understood herein will be described in further detail through the use of the accompanying drawings.

[0022] This is a simplified diagram of a VCSEL device according to an embodiment of the present invention. This is a simplified diagram of a VCSEL device according to an embodiment of the present invention. This is a simplified diagram of a VCSEL device according to an embodiment of the present invention.

[0023] These are simplified diagrams of various coupling devices configured using VCSEL devices according to embodiments of the present invention. These are simplified diagrams of various coupling devices configured using VCSEL devices according to embodiments of the present invention. These are simplified diagrams of various coupling devices configured using VCSEL devices according to embodiments of the present invention.

[0024] This is a simplified diagram showing various cavity regions, including the epitaxial configuration of a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing various cavity regions, including the epitaxial configuration of a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing various cavity regions, including the epitaxial configuration of a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing various cavity regions, including the epitaxial configuration of a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing various cavity regions, including the epitaxial configuration of a VCSEL device according to one embodiment of the present invention.

[0025] This is a simplified diagram showing a VCSEL device according to an embodiment of the present invention. This is a simplified diagram showing a VCSEL device according to an embodiment of the present invention. This is a simplified diagram showing a VCSEL device according to an embodiment of the present invention. This is a simplified diagram showing a VCSEL device according to an embodiment of the present invention. This is a simplified diagram showing a VCSEL device according to an embodiment of the present invention. This is a simplified diagram showing a VCSEL device according to an embodiment of the present invention. This is a simplified diagram showing a VCSEL device according to an embodiment of the present invention. This is a simplified diagram showing a VCSEL device according to an embodiment of the present invention. This is a simplified diagram showing a VCSEL device according to an embodiment of the present invention. This is a simplified diagram showing a VCSEL device according to an embodiment of the present invention. This is a simplified diagram showing a VCSEL device according to an embodiment of the present invention.

[0026] This is a simplified diagram showing the spectral width of an in-plane device along with multiple VCSEL devices according to one embodiment of the present invention.

[0027] This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention.

[0028] This is a simplified diagram illustrating a method for manufacturing a VCSEL device together with an in-plane device according to one embodiment of the present invention. This is a simplified diagram illustrating a method for manufacturing a VCSEL device together with an in-plane device according to one embodiment of the present invention. This is a simplified diagram illustrating a method for manufacturing a VCSEL device together with an in-plane device according to one embodiment of the present invention. This is a simplified diagram illustrating a method for manufacturing a VCSEL device together with an in-plane device according to one embodiment of the present invention.

[0029] This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. This is a simplified diagram showing a method for manufacturing a VCSEL device according to one embodiment of the present invention.

[0030] This is a simplified diagram illustrating a method for manufacturing a VCSEL device having a saturable absorbent material according to one embodiment of the present invention.

[0031] The present invention provides technology relating to laser devices and systems. In one embodiment, the present invention provides a vertical-cavity surface-emitting laser ("VCSEL") device configured with an in-plane light source. In one embodiment, the in-plane light source is configured to synchronize one or more parameters of a plurality of VCSEL devices with each other and with the in-plane light source. As just one example, the present invention can be applied to a variety of applications including lighting, industrial, biological, telecommunications, automotive, gaming, chemistry, energy, finance, and more. Of course, other examples exist.

[0032] The following description is provided to enable those skilled in the art to construct and use the invention and to incorporate it into the context of a particular application. Various modifications and various uses in various applications will be readily apparent to those skilled in the art, and the general principles defined herein may apply to a wide range of embodiments. Accordingly, the invention is not limited to the embodiments presented, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

[0033] The following detailed description includes numerous specific details to provide a more detailed understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without necessarily being limited to these specific details. In other examples, well-known structures and apparatus are shown in block diagram form rather than in detail, in order to avoid obscuring the present invention.

[0034] The reader's attention is directed to all papers and documents submitted concurrently with this Specified and published for verification together with this Specified, and the contents of all such papers and documents are incorporated herein by reference. All features disclosed herein (including the attached claims, abstract, and drawings) may be replaced by alternative features that serve the same, equivalent, or similar purpose unless otherwise expressly stated. Thus, unless otherwise expressly stated, each feature disclosed is merely an example of a comprehensive set of equivalent or similar features.

[0035] Furthermore, no element in a claim that does not explicitly state a “means for” or a “step” for performing a particular function should be construed as a “means” or “step” clause as defined in Section 112, paragraph 6 of the U.S. Patent Act. In particular, the use of “step” or “act” in the claims herein is not intended to evoke the provisions of Section 112, paragraph 6 of the U.S. Patent Act.

[0036] Where an element is referred to herein as being "connected" or "joined" to another element, it should be understood that the elements are either directly connected to the other element or that intervening elements may exist between them. In contrast, where an element is referred to as being "directly connected" or "directly joined" to another element, it should be understood that there are no intervening elements in a "direct" connection between the elements. However, the existence of a direct connection does not preclude other connections in which intervening elements may exist.

[0037] Similarly, where it is referred herein that one element is “joined” to another, it should be understood that those elements may be directly joined to the other (without intervening elements), or that intervening elements may exist between the joined elements. In contrast, where it is referred to that one element is “directly joined” to another, it should be understood that there are no intervening elements in the “direct” joining between those elements. However, the existence of direct joining does not preclude other forms of joining in which intervening elements may be present.

[0038] Similarly, it should be understood that when an element is referred to as a "layer" in this specification, the layer may be a single layer or may include a plurality of layers. For example, a conductive layer may include a plurality of different conductive materials or a plurality of layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or a plurality of layers of dielectric materials. When it is described that one layer is bonded or connected to another layer, it should be understood that the bonded or connected layers may include intervening elements present between the bonded or connected layers. In contrast, when it is referred to that one layer is "directly" connected or bonded to another layer, it should be understood that there are no intervening elements between those layers. However, the presence of directly bonded or connected layers does not exclude other connections where intervening elements may be present.

[0039] Further, the terms left, right, front, back, top, bottom, forward direction, reverse direction, clockwise and counterclockwise are used for purposes of illustration only and are not limited to any fixed direction or orientation. Rather, they are used only to indicate the relative positions and / or directions between various parts and / or components of an object.

[0040] Further, the methods and processes described in this specification may be described in a particular order for ease of explanation. However, unless the context indicates otherwise, intervening processes may be performed before and / or after any part of the described processes, and various additional procedures may be rearranged, added, and / or omitted according to various embodiments.

[0041] Unless otherwise indicated, all numerical values used in this specification to represent quantities, dimensions, etc. should be understood as being modified by the term "about" in all cases. In this application, the use of the singular form includes the plural unless otherwise specified, and the use of the terms "and" and "or" means "and / or" unless otherwise specified. Further, the terms "including" and "having", as well as the use of other forms such as "includes", "included", "has", "have", and "had", should be regarded as non-exclusive. Also, terms such as "element" or "component" include both elements and components containing one unit and elements and components containing multiple units unless otherwise specified.

[0042] As used herein, the phrase "at least one of" preceding a series of items and separating any of those items with "and" or "or" modifies the entire list rather than each member (i.e., each item) of the enumeration. The phrase "at least one of" does not require a selection of at least one of each of the enumerated items; rather, the phrase allows for the meaning of including at least one of any one of those items and / or at least one of any combination of those items. By way of example, the phrases "at least one of A, B, and C" or "at least one of A, B, or C" each refer to only A, only B, or only C, as well as / or any combination of A, B, and C. If the selection is intended to be "at least one of each of A, B, and C", or "at least one of A, at least one of B, and at least one of C", it will be explicitly stated as such.

[0043] Further details of the present invention can be found throughout this specification, particularly as follows.

[0044] For example, the present invention provides a vertical-cavity surface-emitting laser device (VCSEL). In one embodiment, the device has a semiconductor substrate containing a compound semiconductor material, such as GaN. In one embodiment, the device has a plurality of VCSEL devices arranged in an array on a first portion of the semiconductor substrate. In one embodiment, the compound semiconductor material is selected from at least gallium nitride, gallium arsenide, gallium phosphide, or an organic semiconductor material, or other suitable material. The material may also be layered, stepped, homogeneous, heterogeneous, and others.

[0045] Each VCSEL device has a first DBR (Distributed Bragg Reflector) stack (e.g., multilayer) and a second DBR stack facing the first DBR stack. Each VCSEL device has a cavity region formed between the first DBR stack and the second DBR stack. In one embodiment, the cavity region has a length of, for example, 5 microns or more to facilitate in-plane propagation of light. Preferably, the cavity region is longer than 10 microns. In one embodiment, the cavity region includes a multiple quantum well region characterized by laser emission and having a first emission spectrum. The cavity region also has an n-type region formed between the multiple quantum well region and the second DBR stack, and a p-type region formed between the multiple quantum well region and the first DBR stack.

[0046] In one embodiment, the multiple quantum well region includes, in particular, two to seven well layers. Each well layer is located between a pair of barrier layers or alternative layers.

[0047] In one embodiment, the device has a waveguide that connects each of a plurality of VCSEL devices. In one embodiment, the waveguide is, in particular, a slab waveguide.

[0048] In one embodiment, the device has an in-plane light source located in a second portion of a semiconductor substrate. The in-plane light source is a light source that emits light containing a component that propagates in a direction along a plane (plane, surface) perpendicular to the stacking direction of the semiconductor substrate. The device also includes a light source that emits light containing a component that propagates after being reflected by a DBR, as shown in Figure 3. The in-plane light source is characterized by a second emission spectrum such that each of the first emission spectra is included in a second emission spectrum that contains multiple spectra.

[0049] In one embodiment, the in-plane light source is selected from, among other things, an end-face emitting laser, a light-emitting diode, and a superluminescent diode. In one embodiment, the in-plane light source is a superluminescent diode having an anti-reflective coating on the side surface. In one embodiment, the in-plane light source is an end-face emitting laser comprising a pair of DBR stacks. In one embodiment, the in-plane light source includes a ridge structure. In one embodiment, the in-plane light source comprises a ridge structure coupled to an electrode pair, each of which is coupled to a power supply. Further details of the light source can be found throughout this specification, in particular below.

[0050] In one embodiment, the device has a free-space gap between a first portion of a semiconductor substrate and a second portion of a semiconductor substrate in order to separate multiple VCSEL devices from an in-plane light source.

[0051] In a preferred embodiment, the in-plane light source is characterized by a first parameter, and each VCSEL device is characterized by a second parameter. The first parameter interacts with the second parameter in the waveguide so that each VCSEL device exhibits the properties of the first parameter, and thereby each VCSEL device is characterized by the first parameter.

[0052] In one embodiment, the first parameter is at least one of phase, frequency, polarization, timing, or pulse timing. The second parameter is the same as the first parameter. In one embodiment, each of the second parameters of the VCSEL device is synchronized with the first parameter. In one embodiment, the interaction between the first and second parameters is an injection locking process. Of course, other variations may exist depending on the application.

[0053] In one embodiment, the cavity is characterized by a length ranging from 5 microns to 200 microns in order to again confine the in-plane light source. A variety of other characteristics may exist.

[0054] In one embodiment, the device is configured with an emission range of 400 to 550 nm, particularly in infrared and ultraviolet light.

[0055] In one embodiment, the first DBR stack includes an oxide and a nitride stack. In one embodiment, the first DBR stack includes two or more different refractive indices.

[0056] In one embodiment, the free space gap includes a trench structure. The free space gap includes a trench structure, and the trench structure includes a passivation material located inside the trench structure.

[0057] In one embodiment, the VCSEL device array includes 2 million to 10 million devices. Other examples may include more than 10 million devices.

[0058] In one embodiment, the free-space gap includes an anti-reflective coating (AR coating) covering it. In one embodiment, the free-space gap separates a first portion of the semiconductor substrate from a second portion of the semiconductor substrate. In one embodiment, the free-space gap separates a first portion of the semiconductor substrate from a second portion of the semiconductor substrate so that the first portion is a separate substrate from the second portion. In one embodiment, the free-space gap includes a trench region having angled sidewalls configured, for example, between about 0 and 45 degrees, from a direction perpendicular to the plane of the semiconductor substrate. In one embodiment, the free-space gap is filled to connect the first portion of the semiconductor substrate to the second portion of the semiconductor substrate or is monolithic.

[0059] Figures 1 to 3 are simplified diagrams of VCSEL devices according to embodiments of the present invention. These figures show multiple VCSEL devices arranged in an array. Each VCSEL device is configured together with an in-plane light source. Each VCSEL device has multiple n-type layers and multiple p-type layers. The MQW is configured between the n-type and p-type layers. A slab waveguide configured below the MQW is shown.

[0060] As shown in the figure, a similar structure is included in the in-plane light source. The free-space gap separates multiple VCSEL devices from the in-plane light source.

[0061] Each emission from the VCSEL device is in phase with the others and therefore synchronized.

[0062] The cavity region is also shown. The cavity region has a length suitable for enabling in-plane light propagation to each of the VCSEL devices.

[0063] Referring to Figure 2, it is shown that light emitted from an in-plane light source propagates from the in-plane light source through free space to each of the VCSEL devices using a slab waveguide. In one embodiment, one or more parameters from the in-plane light source are configured to synchronize such one or more parameters with each of the VCSEL devices, as will be further described.

[0064] Referring to Figure 3, the light emitted from the in-plane light source is shown to propagate between the DBR stacks, as indicated. A certain thickness of the semiconductor substrate is configured as a waveguide for propagating the light emitted from the in-plane light source to each VCSEL device.

[0065] Figures 4 to 6 are simplified diagrams of various coupling devices configured using VCSEL devices according to embodiments of the present invention. In one embodiment, the present invention provides a coherent beam-coupled ("CBC") vertical-cavity surface-emitting laser device (VCSEL). Note: Here, Figures 4 to 6 show specific elements. The device comprises a semiconductor substrate containing a compound semiconductor material and a plurality of VCSEL devices arranged in an array in a first portion of the semiconductor substrate.

[0066] In one embodiment, each VCSEL device has a first DBR stack, a second DBR stack facing the first DBR stack, and a cavity region formed between the first DBR stack and the second DBR stack. In one embodiment, the cavity region has a length of 5 microns or more to facilitate in-plane propagation of light. In one embodiment, the cavity region includes a multiple quantum well ("MQW") region characterized by laser emission having a first emission spectrum, ranging from a first wavelength to a second wavelength.

[0067] In one embodiment, the VCSEL has an n-type region configured between the multiple quantum well region and the second DBR stack, and a p-type region configured between the multiple quantum well region and the first DBR stack.

[0068] In one embodiment, the VCSEL has waveguides that couple each of a plurality of VCSEL devices. In one embodiment, the VCSEL has an in-plane light source located in a second portion of a semiconductor substrate, the in-plane light source being characterized by a second emission spectrum such that each of the first emission spectra is included in the second emission spectrum.

[0069] In one embodiment, the device has a free-space gap between a first portion of a semiconductor substrate and a second portion of a semiconductor substrate to isolate multiple VCSEL devices from an in-plane light source. In one embodiment, the in-plane light source is characterized by a first parameter, each VCSEL device is characterized by a second parameter, the first parameter interacts with the second parameter in a waveguide to exhibit the properties of the first parameter, thereby characterizing each VCSEL device by the first parameter, and each VCSEL device is synchronized.

[0070] In one embodiment, the VCSEL device is coupled using one or more elements.

[0071] In one embodiment, the CBC apparatus has a combiner that couples to each of the laser beams emitted from the VCSEL device, coherently coupling each of the laser beams together to form a single coherently coupled laser beam.

[0072] In one embodiment, the combiner is a lens device as shown in Figure 4. In another embodiment, the combiner is a fiber device comprising a plurality of fibers operably coupled to focus each of the laser beams, as shown in Figure 5. In yet another embodiment, the combiner is constructed in free space by bending a semiconductor substrate, as shown in Figure 6.

[0073] In one embodiment, the wavelength is, for example, in the range of 400 nm (nanometers) to 550 nm. Other wavelength ranges for infrared and ultraviolet light may also be included in various examples.

[0074] Figures 7 to 11 are simplified diagrams showing various cavity regions, including an epitaxial stacked configuration of a VCSEL device according to one embodiment of the present invention.

[0075] Referring to Figure 7, the cavity region has an n-type region including an n-GaN layer located on top of the first DBR stack. The p-type region includes a p++GaN contact layer, p-type AlGaN; and further includes a GaN barrier region formed between the multiple quantum well region and the p-type region. In one embodiment, the device has a p-type electrode region including a transparent electrode and a phase-shift region.

[0076] Figure 8 is a simplified diagram of the refractive index, absorption coefficient, and electric field strength of a cavity structure having the structure shown in Figure 7. The vertical axis represents these values, and the horizontal axis represents the vertical distance. The cavity region is covered by two DBRs that form standing waves of resonant light. The standing waves form nodes and antinodes at intervals proportional to the reciprocal of the wavelength and refractive index. The structure of the cavity region is preferably designed so that the absorption layer and gain layer are located near the nodes and antinodes. This configuration suppresses absorption and amplification by the absorption layer and gain layer, respectively. The ITO layer and MQW layer are the absorption layer and gain layer, respectively. The structure shown in Figure 7 has a structure suitable for satisfying this criterion.

[0077] In the example shown in Figure 9, the device further includes n-type GaN, n++-type GaN, and p++-type InGaN. Referring again to Figure 9, the cavity region includes n-type GaN, n++-type GaN, p++-type InGaN, p-type GaN, p-type AlGaN, GaN barrier, multiple quantum well region, optionally n-type AlGaN, and n-type GaN, coupled between the first DBR stack and the second DBR stack.

[0078] Figure 10 is a simplified diagram of the refractive index, absorption coefficient, and electric field strength of the cavity structure in the structure shown in Figure 9. The cavity structure includes n-type GaN, n++-type GaN, and p++-type InGaN, and is called a tunnel junction, where the p++-type InGaN electrically bridges the n++-type GaN and p-type GaN, allowing current to flow from the n-type layer to the p-type. The cavity structure meets the criteria described. In one embodiment, the InGaN layer is an absorbing material located at the nodes of the standing wave. Since the InGaN layer can be thinner than ITO, the absorption caused by these layers is lower when using a tunnel junction instead of ITO, as long as it is located near the nodes.

[0079] Referring to Figure 11, the cavity region comprises n-type GaN, n++-type GaN, p++-type InGaN, p-type GaN, p-type AlGaN, GaN barrier, multiple quantum well region, optionally n-type AlGaN, and n-type GaN, coupled between the first DBR stack and the second DBR stack.

[0080] Figures 12 to 23 are simplified diagrams showing a VCSEL device according to an embodiment of the present invention.

[0081] Figures 12 to 23 are simplified diagrams showing VCSEL devices according to embodiments of the present invention. These figures illustrate various VCSEL devices according to the present invention.

[0082] Figure 12 shows a VCSEL device in one embodiment of the present invention in which a free-space gap completely isolates an in-plane light source from the VCSEL array. In one embodiment, the in-plane light source can be held on the side of the VCSEL array by some support structure so that light generated from the in-plane light source can easily enter the VCSEL array from the side of the VCSEL array. In one embodiment, the introduced in-plane light propagates in a trajectory that bounces between two pairs of DBRs, and the structure comprising the cavity region and DBRs forms a waveguide for the light to propagate in the in-plane direction. In one embodiment, the sidewall of the free-space gap can be tilted, for example, between 0 and 45 degrees from the normal direction (direction perpendicular to the plane) of the wafer containing the VCSEL array. Such a tilt enhances the light emitted in the tilt direction, thereby improving the bounce trajectory and increasing the coupling effect between tilt propagation and the perpendicular VCSEL mode. Thus, in one embodiment, the VCSELs are synchronized with each other. In one embodiment, the device structure of the cavity region of the VCSEL and the cavity structure of the in-plane emitter may be the same or slightly different.

[0083] Figure 13 is a simplified diagram showing a VCSEL device similar to the VCSEL device shown in Figure 12, according to an embodiment of the present invention. In one embodiment, the sidewalls of the free-space gap are vertical, facilitating in-plane propagation of light emitted from an in-plane light source. Such a structure improves the propagation of light over longer distances and synchronizes VCSELs located at more distant spatial positions within the wafer (or chip) for manufacturing. In a preferred embodiment, a larger number of VCSELs or all VCSELs are synchronized to the parameters of the in-plane light source. In one embodiment, the device reduces the power consumption required to operate the in-plane light source.

[0084] Figure 14 is a simplified diagram of a VCSEL device configured with a slab waveguide according to an embodiment of the present invention. The slab waveguide further enhances the in-plane propagation of light emitted from an in-plane light source. As a result, the light travels further, which helps to synchronize VCSELs located at greater distances on the wafer or chip for device manufacturing. This further reduces the power consumption required to operate the in-plane light source. Figure 15 shows an example of in-plane propagation.

[0085] Figure 16 is a simplified diagram showing a VCSEL device according to one embodiment of the present invention, with a free-space gap that is shallower than a certain thickness in the cavity region. Such a device leaves a portion of the n-GaN or GaN substrate as a common stage for the VCSEL array and the in-plane light source. In one embodiment, two of these devices are fabricated monolithically. In one embodiment, the two elements have the same structure with respect to the cavity region. This structure allows for a simpler manufacturing process that reduces manufacturing costs. This structure improves manufacturing costs and yield because it does not require alignment between the two elements. In one embodiment, the free-space gap may have an anti-reflective coating on each side as an interface with the element. Such a coating facilitates the incidence of light generated from the in-plane light source into the VCSEL array without back reflection. Preferably, the propagating light traverses further, synchronizing VCSELs located at more distant spatial positions on the wafer (or chip) for device manufacturing and reducing the power consumption required to operate the in-plane light source.

[0086] Figure 17 is a simplified diagram of a VCSEL device according to one embodiment of the present invention, in which the free-space gap is filled with the same structure in the cavity region of the VCSEL array and in-plane light source. This structure does not suffer from backscattering or reflection of the interface to the free-space gap. Therefore, this structure has the same kind of advantages as those given by AR coating. Furthermore, this structure eliminates the need for the steps of removing material to form a free-space gap and depositing an AR coating, which leads to reduced manufacturing costs and improved yield.

[0087] Figure 18 is a simplified diagram of a VCSEL device according to one embodiment of the present invention, in which the in-plane light source is an end-face emitting laser. This device has two DBRs at each end and a ridge waveguide in the upper region. In one embodiment, a structure including such a device is required to achieve laser oscillation. In one embodiment, the light emitted from the laser is more powerful and highly directional, and the light propagates to a greater spatial region in the VCSEL array. In addition, in one embodiment, more VCSELs or all VCSELs in the array are synchronized.

[0088] Figure 19 is a simplified diagram of a VCSEL device according to one embodiment of the present invention, in which the in-plane light source is an end-face emitting laser under pulsed current injection. The end-face emitting laser is configured to synchronize the timing of light emission from the VCSEL array.

[0089] Figure 20 is a simplified diagram of a VCSEL device according to one embodiment of the present invention, in which the in-plane light source is an end-emitting laser containing a saturable absorber (SA material) in a cavity. The absorber and light source passively pulse the end-emitting laser. In one embodiment, such an end-emitting laser synchronizes the timing of light emission from the VCSEL array.

[0090] Figure 21 is a simplified diagram of a VCSEL device according to one embodiment of the present invention, in which the in-plane light source is an end-face emitting laser including a diode configured in reverse bias. Since the diode under reverse bias acts as a saturable absorber (SA element), the light source and diode pulse the end-face emitting laser. In one embodiment, such a light source can be configured to synchronize the timing of emission for the entire VCSEL array. In one embodiment, the pulse interval and peak output can be controlled by changing the reverse bias voltage.

[0091] Figure 22 is a simplified diagram of a VCSEL device according to one embodiment of the present invention, in which the VCSEL array includes a saturable absorber material within the cavity region. Such a device is configured to enable pulsed operation of the VCSEL. In one embodiment, the peak output and pulse energy are enhanced in the VCSEL array.

[0092] Figure 23 is a simplified diagram of a VCSEL device according to one embodiment of the present invention, in which the VCSEL array includes a saturable absorber material and a half-mirror (in-cavity mirror) within the cavity region. Such a device can enable pulsed operation of the VCSEL. In one embodiment, such a device enhances the peak output of the VCSEL array. By setting the reflectivity of the half-mirror, the photon density in the saturable absorber can be controlled, and the pulse interval, peak output, and pulse energy can be controlled.

[0093] None of the aforementioned approaches are mutually exclusive. Such approaches can be combined, separated, modified, or changed.

[0094] Figure 24 is a simplified diagram showing the spectral width of an in-plane device with multiple VCSEL devices according to one embodiment of the present invention. As shown, the vertical axis is relative to normalized intensity, and the horizontal axis is relative to wavelength. The solid line (curve, see range A) is the spectrum of the emission wavelength of the in-plane light source (see range C) encompassing each emission spectrum from each VCSEL device. The spectrum from each VCSEL device is represented by a dashed line (each of the five curves, see range B). This configuration allows photons emitted from the in-plane light source to control the parameters of the VCSELs. In one embodiment, the parameters are, for example, emission wavelength, phase, polarization, and pulse emission timing. Therefore, by configuring such a structure, each VCSEL will have the same parameters and at least a 99.5% coefficient of determination. This is a physical phenomenon called synchronization of each VCSEL element.

[0095] In one embodiment, a method for fabricating a VCSEL device is briefly described below. 1. A bulk GaN substrate is provided; 2. The surface of the substrate is cleaned; 3. The substrate is loaded into an organometallic vapor deposition (MOCVD) reactor configured with a precursor gas; 4. The substrate is heated to a temperature higher than, for example, 800 degrees Celsius, or another selected temperature, which can be higher than 800 degrees Celsius, and more preferably higher than 1000 degrees Celsius ("°C"); 5. In order to grow an epitaxial structure on the substrate, in particular among variations, one or more gases of an organometallic (MO) mixture are introduced, for example, among variations, one or more gases such as trimethylgallium, trimethylaluminum, trimethylindium, ammonium, hydrogen, silane, and cyclopentanemagnesium; 6. An epitaxial structure including n-type GaN, multiple quantum well layers, and p-type GaN, as well as other layers, is formed on the substrate to form an epitaxial wafer; 7. 11. Remove the epitaxial wafer from the reactor; 8. Clean the wafer and heat it to a temperature higher than 500°C, for example, to remove hydrogen from the wafer; 9. Mask the surface of the wafer with a resin (e.g., photoresist) disk having a diameter in the range of 2 to 10 micrometers, for example, and implant ions as boron entities; 10. Form one or more unimplanted patterned (e.g., circular) regions, which are VCSEL aperture regions, where the resin disk can be photoresist patterned by photolithography; 11. Deposit a transparent electrode (e.g., indium tin oxide), and wet etch the exposed regions after patterning to leave the transparent electrode covering at least the VCSEL aperture and in-plane emitter, where the deposition of indium tin oxide ("ITO") can be done using a vacuum evaporator; 12. A p-type pad metal is deposited so as to cover a portion of the ITO without covering the opening, where the thickness of the ITO is preferably between 10 and 100 nanometers, and the p-type pad can be a metal layer containing, among other suitable materials, gold, platinum, titanium, etc.13. Optionally, reactive ion etching (RIE) may be applied to etch the GaN, masking at least a portion of the area covered by ITO and p-pads, thereby exposing the n-GaN, where the etching gas may include, for example, chloride, and the mask material may be a photoresist patterned by lithography techniques; an n-pad may be deposited on the area where the n-GaN is exposed to form a contact, the n-pad may be a metal layer such as gold, platinum, or titanium; 14. The top surface of the wafer may be bonded to a support substrate such as sapphire via a filler such as wax, one or more metals, or adhesive tape, among other preferred materials; 15. The wafer and support substrate may be inverted to expose the back surface of the wafer facing upwards; 16. 17. The back surface of the wafer is lapped to thin the substrate to a thickness of, for example, between 5 and 200 micrometers, and a cavity region of a similarly short length is formed, where the lapping process can be performed with a grinder, and the cavity region may include the epitaxial layer and a portion of the wafer; 18. The back surface of the wafer is polished, where the polishing process can be performed using a polisher with a rotating tape; 19. A resin disk is formed by photolithography, where the diameter and thickness of the disk are in the range of, for example, 10 to 200 μm and, for example, 0.5 to 10 μm, respectively, and the center of the disk is positioned and aligned above the opening region; 10. The wafer is heated to change the dimensions of the resin from a disk to droplets; 21. Reactive ion etching (RIE) is applied to remove the resin droplets as a sacrificial layer and to etch the back surface of the GaN, transferring the dimensions of the droplets to the back surface of the GaN while the etching gas contains chloride; 22. A back-side DBR is deposited using two materials with different refractive indices, for example, SiO; ２ and Ta ２ O ５ 22. Remove the sapphire substrate; 23. Clean and remove the filler material, e.g., wax; 24. Deposit a top surface DBR having two materials with different refractive indices, e.g., SiO ２ and ZrO ２25. It can be used and deposition can be done by sputtering; 26. Optionally, a portion of the bottom DBR can be removed to expose the bottom surface of n-GaN. An n-pad metal can be deposited there to establish a current path from the bottom surface; 27. Perform other steps as needed.

[0096] In one embodiment, the above-described series of steps provides a method according to the present invention. Depending on the embodiment, one or more steps may be added, one or more steps may be modified, one or more steps may be combined, or the order of one or more steps may be changed. Naturally, those skilled in the art will understand other modifications, improvements, and variations.

[0097] Further details of this method can be found throughout this specification, in particular below.

[0098] Figures 25 to 36 are simplified diagrams illustrating a method for manufacturing a VCSEL device according to one embodiment of the present invention. For example, the present invention provides a method for manufacturing a vertical-cavity surface-emitting laser device (VCSEL). In one embodiment, this method can be combined with any of the above and / or the following methods and device technologies.

[0099] Referring again to the drawings, this method includes providing a semiconductor substrate containing a compound semiconductor material. Please refer to Figure 25. In one embodiment, the semiconductor substrate includes a surface region.

[0100] Referring to Figure 26, the method includes forming an n-type GaN material located on a surface region and forming a multiple quantum well region having a first emission spectrum characterized by laser emission in the range of, for example, 400 to 550 nm. In one embodiment, the method includes forming a p-type GaN material located on a multiple quantum well region. The method includes subjecting the p-type GaN material to an implantation treatment containing a boron-containing entity. Please refer to Figure 27.

[0101] In one embodiment, the method includes forming a transparent electrode material located on a p-type GaN material. The method also includes forming a p-type contact pad located on the transparent electrode material.

[0102] Furthermore, as shown, the method forms an opening region, for example, a circle, so as to expose a portion of the p-type GaN region. A p-type semiconductor region is realized by doping this opening with boron impurities. In one embodiment, the method includes forming an opening region that penetrates a p-type contact pad so as to expose a portion of the transparent electrode material (see Figure 28), and forming an n-contact region by removing a portion of the p-type GaN material and a portion of the multiple quantum well region so as to expose a portion of the n-type GaN (see Figure 29).

[0103] In one embodiment, the method includes forming an n-type contact pad (see also Figure 29) located on the exposed portion of n-type GaN, and then forming a filler material located on the n-type contact pad. In one embodiment, the filler material may be wax, adhesive tape, or other suitable material.

[0104] Referring to Figure 30, this method includes forming a multilayer substrate by bonding a filler material and a support substrate located on a p-type contact pad, as shown in the figure.

[0105] In one embodiment, the method includes a lapping step as shown in Figure 31 to remove a portion of the semiconductor substrate.

[0106] In one embodiment, the method includes inverting a multilayer substrate. The method includes removing a certain thickness from the semiconductor substrate (see Figure 32) to leave a thin film on the semiconductor substrate, and polishing the back surface of the thin film on the semiconductor substrate.

[0107] In one embodiment, the method includes forming a lens structure from a thin film of a semiconductor substrate using patterning and etching steps. In one embodiment, the method includes forming a first DBR stack located on the surface of a lens structure such that the first DBR stack, lens structure, multiple quantum wells, n-type contact pads, and p-type contact pads correspond to one of a plurality of VCSEL devices formed in an array.

[0108] In one embodiment, the method includes: forming a photoresist material located on a thin film of a semiconductor substrate (see Figure 33); shaping the photoresist material to form a lens shape (see Figure 34); and using the photoresist material to form a lens structure (see Figure 35).

[0109] In one embodiment, each of the multiple VCSELs is formed monolithically on a semiconductor substrate.

[0110] In one embodiment, the method includes forming a free-space gap to separate a plurality of VCSELs formed on a first portion of a semiconductor substrate from an in-plane light source located on a second portion of the semiconductor substrate.

[0111] In one embodiment, the method includes removing the support substrate, as shown in Figure 36.

[0112] In one embodiment, the method includes forming a second DBR stack configured to be located on a transparent electrode material (see also Figure 36). In one embodiment, the method includes forming a second DBR stack configured to be located on a transparent electrode material and forming a phase-shift layer coupled to the second DBR stack.

[0113] In one embodiment, the compound semiconductor material is selected from at least gallium nitride, gallium arsenide, gallium phosphide, or an organic semiconductor material. In one embodiment, the VCSEL device is characterized by a cavity length in the range of, for example, 5 microns to 200 microns. In one embodiment, each VCSEL device is synchronized to a parameter. In one embodiment, the first DBR stack includes oxide and nitride stacks. In one embodiment, the first DBR stack includes two or more different refractive indices. In one embodiment, the free-space gap includes a trench structure, and the trench structure includes a passivation material located inside the trench structure. In one embodiment, the array of VCSEL devices includes 2 million to 10 million devices. In one embodiment, the multiple quantum well region includes 2 to 7 well layers, each well layer being configured between a pair of barrier layers.

[0114] In one embodiment, the method includes forming a waveguide optically coupled to a multiple quantum well region.

[0115] Figures 37 to 40 are simplified diagrams illustrating a method for manufacturing a VCSEL device with an in-plane device according to one embodiment of the present invention. In one embodiment, for an in-plane optical element, the manufacturing steps described below can be performed simultaneously with the above-described steps for VCSEL manufacturing (see also Figure 37). Accordingly, one or more differences will be described below. In one embodiment, the steps for forming the cavity region, transparent electrode, p-pad and n-pad are performed simultaneously with the steps for VCSEL manufacturing. In one embodiment, an additional difference is the formation of a free-space gap located between the VCSEL array and the in-plane optical element (see Figures 38, 39, and 40). The formation of the free-space gap can be performed by etching n-GaN, either as a simultaneous process as described above or as an additional process performed between the above steps. In one embodiment, the formation of the anti-reflective coating and DBR is performed after the formation of the free-space gap. The formation of these materials can be performed by any process, such as reactive sputtering or vacuum deposition.

[0116] In one embodiment, the free-space gap includes an anti-reflective coating covering it. In one embodiment, the free-space gap separates a first portion of the semiconductor substrate from a second portion of the semiconductor substrate. In one embodiment, the free-space gap includes a trench region having angled sidewalls, configured, for example, at an angle between approximately 0 and 45 degrees from a direction perpendicular to the plane of the semiconductor substrate. In one embodiment, the free-space gap is filled to connect the first portion of the semiconductor substrate to the second portion of the semiconductor substrate or is monolithic.

[0117] Naturally, it can take on different forms.

[0118] Figures 41 to 51 are simplified diagrams showing a method for manufacturing a VCSEL device according to one embodiment of the present invention. In the embodiment referring to Figure 41, the method includes providing a substrate, for example, a GaN substrate. The method includes forming an n-type GaN region, an MQW region, and a p-type GaN region in Figure 42. In one embodiment, the method includes forming a transparent conductive material in a boron implantation and an opening region, which is shown in Figure 43. In one embodiment, the method includes forming a p-type pad having, for example, a circular, patterned opening, as shown in Figure 44.

[0119] In one embodiment, a DBR stack is formed on a transparent conductive material, as shown in Figure 45. In another embodiment, an adhesive or filler area, such as solder, adhesive, wax, or conductive paste, is formed to bond a support substrate to a VCSEL substrate, as shown in Figure 46, to form a multilayer substrate.

[0120] In the embodiment shown in Figure 47, the method inverts the multilayer substrate. The method also wraps the back side of the GaN substrate, as shown.

[0121] In one embodiment, the method forms a lens structure. The lens structure involves forming a photoresist disk (see Figure 48), which is patterned to form a curved resist structure in Figure 49. In one embodiment, the method uses reactive ion etching to transfer the resist structure onto a portion of an n-type GaN substrate to form the lens shown in Figure 50.

[0122] Referring to Figure 51, the method includes forming a DBR stack, as shown in the figure. Other steps may be included.

[0123] Figures 52 and 53 are simplified diagrams illustrating a method for manufacturing a VCSEL device using a saturable absorber material according to one embodiment of the present invention. As shown, the saturable absorber (SA) can be formed in the cavity region in one embodiment. The formation of the SA can be performed before the formation of the DBR in Figure 52. In one embodiment, the saturable absorber can be placed on either side of the cavity region, or, in one embodiment, inside the cavity region.

[0124] In one embodiment, the VCSEL device is configured using a saturable absorber material coupled to an in-plane light source. In one embodiment, the VCSEL device has a saturable absorber apparatus including a pulsed laser. In one embodiment, as shown in Figure 53, the device has a saturable absorber coupled to one or more of the first DBR stacks or the second DBR stacks.

[0125] In one embodiment, the saturable absorber is bonded to one or more VCSEL devices. In one embodiment, the saturable absorber is CdSe (cadmium selenide), ZnO (zinc oxide), ZnS (zinc sulfide), graphene oxide (GO), MoS ２ (Molybdenum disulfide), fullerene (C ６０ The absorbers are selected from polymer dyes, Ti:sapphire (titanium-doped sapphire), and Ce:YAG (cerium-doped yttrium aluminum garnet). In preferred examples, the saturable absorber contains Ce:YAG. Of course, other materials can also be used depending on the application.

[0126] As used herein, the terms “first,” “second,” and “nth” are not intended to imply any order or limitation of the claims. In one embodiment, these terms, including variations, substitutions, and modifications, are used according to those skilled in the art.

[0127] While the above is a sufficient description of a particular embodiment, various modifications, alternative structures, and equivalents may be used. Therefore, the above description and examples should not be construed as limiting the scope of the invention as defined by the claims.

[0128] The various aspects of this disclosure are summarized below as an appendix. (Note 1) A vertical-cavity surface-emitting laser (VCSEL) device comprising a semiconductor substrate containing a compound semiconductor material, and a plurality of VCSEL devices arranged in an array in a first portion of the semiconductor substrate, each of the VCSEL devices comprising a first DBR stack, a second DBR stack facing the first DBR stack, and a cavity region formed between the first DBR stack and the second DBR stack, the cavity region having a length of 5 microns or more to facilitate in-plane propagation of light, the cavity region comprising a multiple quantum well region characterized by laser emission and having a first emission spectrum, each of the VCSEL devices further comprising an n-type region formed between the multiple quantum well region and the second DBR stack, and a p-type region formed between the multiple quantum well region and the first DBR stack, and the vertical-cavity surface-emitting laser device further comprising a waveguide coupling each of the plurality of VCSEL devices, A vertical-cavity surface-emitting laser device comprising an in-plane light source disposed in a second portion of the semiconductor substrate, wherein the in-plane light source is characterized by a second emission spectrum, each of the first emission spectra is included in the second emission spectrum, and the vertical-cavity surface-emitting laser device further comprises a free-space gap between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate that separates the plurality of VCSEL devices from the in-plane light source, wherein the in-plane light source is characterized by a first parameter, each of the VCSEL devices is characterized by a second parameter, the first parameter interacts with the second parameter in the waveguide to exhibit the properties of the first parameter, thereby each of the VCSEL devices is characterized by the first parameter. (Note 2) The device according to Note 1, wherein the compound semiconductor material is selected from at least gallium nitride, gallium arsenide, gallium phosphide, or an organic semiconductor material. (Note 3) The device as described in Note 1, wherein the length is in the range of 5 microns to 200 microns and the luminescence is in the range of 400 to 550 nm.(Note 4) The device according to Note 1, wherein the first parameter is at least one of phase, frequency, polarization, timing, or pulse timing. (Note 5) The device according to Note 1, wherein each of the VCSEL devices is synchronized to the first parameter. (Note 6) The device according to Note 1, wherein the first DBR stack comprises an oxide and a nitride stack. (Note 7) The device according to Note 1, wherein the first DBR stack comprises two or more different refractive indices. (Note 8) The device according to Note 1, wherein the free-space gap comprises a trench structure. (Note 9) The device according to Note 1, wherein the free-space gap comprises a trench structure, and the trench structure comprises a passivation material located inside the trench structure. (Note 10) The device according to Note 1, wherein the interaction between the first parameter and the second parameter is an injection locking process. (Note 11) The device according to Note 1, wherein the array of the VCSEL device comprises 2 million to 10 million devices. (Note 12) The device according to Note 1, wherein the multiple quantum well region comprises 2 to 7 well layers, each of which is configured between a pair of barrier layers. (Note 13) The device according to Note 1, wherein the in-plane light source is selected from an end-face emitting laser, a light-emitting diode, and a superluminescent diode. (Note 14) The device according to Note 1, wherein the waveguide is a slab waveguide. (Note 15) The device according to Note 1, wherein the free-space gap includes an anti-reflective coating covering it. (Note 16) The device according to Note 1, wherein the free-space gap separates the first portion of the semiconductor substrate from the second portion of the semiconductor substrate. (Note 17) The device according to Note 1, wherein the free-space gap separates the first portion of the semiconductor substrate from the second portion of the semiconductor substrate, so that the first portion is a separate substrate from the second portion. (Note 18) The device according to Note 1, wherein the in-plane light source is a superluminescent diode, and the superluminescent diode is provided with an anti-reflective coating on the side surface of the superluminescent diode.(Supplementary Note 19) The device according to Supplementary Note 1, wherein the free space gap includes a trench region having angled sidewalls configured at an angle between about 0 to 45 degrees from a direction perpendicular to the plane of the semiconductor substrate. (Supplementary Note 20) The device according to Supplementary Note 1, wherein the free space gap is filled or monolithic so as to connect the first portion of the semiconductor substrate to the second portion of the semiconductor substrate. (Supplementary Note 21) The device according to Supplementary Note 1, wherein the in-plane light source is an edge-emitting laser including a pair of DBR stacks. (Supplementary Note 22) The device according to Supplementary Note 1, wherein the in-plane light source includes a ridge structure. (Supplementary Note 23) The device according to Supplementary Note 1, wherein the in-plane light source includes a ridge structure coupled to a pair of electrodes, each of the electrodes being coupled to a power source. (Supplementary Note 24) The device according to Supplementary Note 1, further comprising a saturable absorber material coupled to the in-plane light source. (Supplementary Note 25) The device according to Supplementary Note 1, further comprising a saturable absorption device including a pulsed laser. (Supplementary Note 26) The device according to Supplementary Note 1, further comprising a saturable absorber coupled to one or more of the first DBR stack or the second DBR stack. (Supplementary Note 27) The device according to Supplementary Note 1, further comprising a saturable absorber coupled to one or more of the VCSEL devices, and the saturable absorber is CdSe (cadmium selenide), ZnO (zinc oxide), ZnS (zinc sulfide), graphene oxide (GO), MoS. ２ (molybdenum disulfide), fullerene (C ６０The device according to Appendix 1, further comprising a polymer dye, Ti:sapphire (titanium-doped sapphire), and Ce:YAG (cerium-doped yttrium aluminum garnet). (Appendix 28) The device according to Appendix 1, further comprising a saturable absorber containing Ce:YAG. (Appendix 29) The device according to Appendix 1, wherein the n-type region comprises an n-GaN layer located on the first DBR stack, and the p-type region comprises a p++GaN contact layer, p-type AlGaN, and further comprises a GaN barrier region formed between the multiple quantum well region and the p-type region. (Appendix 30) The device according to Appendix 30, further comprising a p-type electrode region including a transparent electrode and a phase-shift region. (Appendix 31) The device according to Appendix 1, further comprising n-type GaN, n++-type GaN, and p++-type inGaN. (Note 32) A vertical-cavity surface-emitting laser (VCSEL) device comprising a semiconductor substrate containing a compound semiconductor material, and a plurality of VCSEL devices arranged in an array in a first portion of the semiconductor substrate, each of the VCSEL devices comprising a first DBR stack, a second DBR stack facing the first DBR stack, and a cavity region formed between the first DBR stack and the second DBR stack, the cavity region having a length of 5 microns or more to facilitate in-plane propagation of light, the cavity region comprising a multiple quantum well region having a first emission spectrum characterized by laser emission in the range of 400 to 550 nm, and the vertical-cavity surface-emitting laser device further comprising a waveguide coupling each of the plurality of VCSEL devices, The vertical cavity surface-emitting laser device comprises an in-plane light source disposed in a second portion of the semiconductor substrate, wherein the in-plane light source is characterized by a second emission spectrum, and each of the first emission spectra is included in the second emission spectrum, and the vertical cavity surface-emitting laser device further comprises a free-space gap between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate that separates the plurality of VCSEL devices from the in-plane light source.Vertical cavity surface-emitting laser device, wherein the in-plane light source is characterized by a first parameter, each of the VCSEL devices is characterized by a second parameter, the first parameter interacts with the second parameter in the waveguide to exhibit the properties of the first parameter, and thereby each of the VCSEL devices is characterized by the first parameter. (Note 33) The device according to Note 32, wherein the cavity region is coupled between the first DBR stack and the second DBR stack and includes n-type GaN, n++-type GaN, p++-type InGaN, p-type GaN, p-type AlGaN, a GaN barrier, the multiple quantum well region, optionally n-type AlGaN, and n-type GaN. (Note 34) The device according to Note 32, wherein the cavity region is coupled between the first DBR stack and the second DBR stack and includes a phase shift layer, a transparent electrode region, p++-type GaN, p-type GaN, p-type AlGaN, a GaN barrier, the multiple quantum well region, optionally n-type AlGaN, and n-type GaN. (Note 35) A coherent beam-coupled vertical cavity surface-emitting laser (VCSEL) device comprising a semiconductor substrate containing a compound semiconductor material, and a plurality of VCSEL devices spatially arranged in an array on a first portion of the semiconductor substrate, each of the VCSEL devices comprising: a first DBR stack, a second DBR stack facing the first DBR stack, and a cavity region formed between the first DBR stack and the second DBR stack, the cavity region having a length of 5 microns or more to facilitate in-plane propagation of light, the cavity region comprising a multiple quantum well region having a first emission spectrum characterized by laser emission ranging from a first wavelength to a second wavelength, each of the VCSEL devices further comprising: an n-type region formed between the multiple quantum well region and the second DBR stack, and a p-type region formed between the multiple quantum well region and the first DBR stack, the coherent beam-coupled vertical cavity surface-emitting laser device further comprises: A waveguide connecting each of the plurality of VCSEL devices,The coherent beam-coupled vertical cavity surface-emitting laser device further comprises an in-plane light source located in a second portion of the semiconductor substrate, wherein the in-plane light source is characterized by a second emission spectrum, and each of the first emission spectra is included in the second emission spectrum, and the coherent beam-coupled vertical cavity surface-emitting laser device further comprises a free-space gap between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate that separates the plurality of VCSEL devices from the in-plane light source, wherein the in-plane light source is characterized by a first parameter, each of the VCSEL devices is characterized by a second parameter, the first parameter interacts with the second parameter in the waveguide to exhibit the characteristics of the first parameter, thereby each of the VCSEL devices is characterized by the first parameter, each of the VCSEL devices is synchronized, and the coherent beam-coupled vertical cavity surface-emitting laser device further comprises A coherent beam-coupled vertical cavity surface-emitting laser device comprising a combiner that couples to each of the laser beams emitted from the VCSEL device and coherently couples each of the laser beams together to form a single coherent coupled laser beam. (Note 36) A method for manufacturing a vertical cavity surface-emitting laser (VCSEL) device, comprising providing a semiconductor substrate containing a compound semiconductor material, wherein the semiconductor substrate includes a surface region, and the method further comprises: forming an n-type GaN material located on the surface region; forming a multiple quantum well region having a first emission spectrum characterized by laser emission in the range of 400 to 550 nm; forming a p-type GaN material located on the multiple quantum well region; subjecting the p-type GaN material to an injection treatment including a boron-containing entity; forming a transparent electrode material located on the p-type GaN material; forming a p-type contact pad located on the transparent electrode material; forming an opening region penetrating the p-type contact pad in order to expose a portion of the transparent electrode material; and forming an n-contact region by removing a portion of the p-type GaN material and a portion of the multiple quantum well region to expose a portion of n-type GaN.A method for manufacturing a vertical-cavity surface-emitting laser (VCSEL) device, comprising: forming an n-type contact pad located on the exposed portion of the n-type GaN; forming a filler material located on the n-type contact pad; joining the filler material and a support substrate located on the p-type contact pad to form a multilayer substrate; inverting the multilayer substrate; removing a certain thickness from the semiconductor substrate to leave a thin film of the semiconductor substrate; polishing the back surface of the thin film of the semiconductor substrate; forming a lens structure from the thin film of the semiconductor substrate using patterning and etching steps; and forming the first DBR stack located on the surface of the lens structure such that the first DBR stack, the lens structure, the multiple quantum wells, the n-type contact pad, and the p-type contact pad correspond to one of a plurality of VCSEL devices formed in an array. (Note P1) A vertical-cavity surface-emitting laser (VCSEL) device system comprising: a semiconductor substrate containing a compound semiconductor material; and a plurality of VCSEL devices arranged in an array in a first portion of the semiconductor substrate, each of the VCSEL devices comprising: a first DBR stack; a second DBR stack facing the first DBR stack; and a cavity region formed between the first DBR stack and the second DBR stack, the cavity region having a cavity length of 5 microns or more; the cavity region including a multiple quantum well region capable of laser emission; the VCSEL device being capable of emitting first light of a first emission spectrum; the cavity region comprising: an n-type region formed between the multiple quantum well region and the second DBR stack; and a p-type region formed between the multiple quantum well region and the first DBR stack; the VCSEL device system further comprising: a waveguide coupling each of the plurality of VCSEL devices; The semiconductor substrate comprises an in-plane light source disposed in a second portion thereof, wherein the in-plane light source is capable of emitting a second light of a second emission spectrum,VCSEL device system wherein each of the first emission spectra is included in the range of the second emission spectrum, the VCSEL device system further comprises the second light of the second emission spectrum having a first parameter, each of the first light of the first emission spectrum having a second parameter, and each of the VCSEL devices is characterized by the first parameter, the first parameter interacting with the second parameter in the waveguide. (Note P2) The VCSEL device system according to Note P1, wherein a free-space gap is provided between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate, separating the plurality of VCSEL devices from the in-plane light source. (Note P3) The VCSEL device system according to Note P1, wherein there is no free-space gap between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate, or the first portion and the second portion have a continuous structure. (Note P4) The VCSEL device system according to any one of Notes P1 to P3, wherein the first parameter is at least one of phase, frequency, polarization, timing, or pulse timing. (Note P5) The VCSEL device system according to any one of Notes P1 to P4, wherein each of the VCSEL devices is synchronized to the first parameter. (Note P6) The VCSEL device system according to any one of Notes P2 to P5, wherein the free-space gap includes a trench structure. (Note P7) The VCSEL device system according to any one of Notes P1 to P6, wherein the multiple quantum well region includes 2 to 7 well layers, each of which is configured between a pair of barrier layers. (Note P8) The VCSEL device system according to any one of Notes P1 to P7, wherein the in-plane light source is selected from an end-emitting laser, a light-emitting diode, and a superluminescent diode. (Note P9) The waveguide is a slab waveguide, as described in any one of Notes P1 to P8 of the VCSEL device system. (Note P10)The VCSEL device system according to any one of Appendix P2 to P9, wherein the free-space gap includes an anti-reflective coating covering the free-space gap. (Appendix P11) The VCSEL device system according to any one of Appendix P2 to P10, wherein the free-space gap separates the first portion of the semiconductor substrate from the second portion of the semiconductor substrate so that the first portion is a separate substrate from the second portion. (Appendix P12) The VCSEL device system according to any one of Appendix P2 to P11, wherein the in-plane light source is a superluminescent diode, and the superluminescent diode has an anti-reflective coating on its side surface. (Appendix P13) The VCSEL device system according to any one of Appendix P2 to P12, wherein the free-space gap includes a trench region having angled sidewalls configured at an angle of about 0 to 45 degrees from a direction perpendicular to the plane of the semiconductor substrate. (Appendix P14) The device further comprises a saturable absorber material coupled to the light source, or a saturable absorber device including a pulsed laser, or a saturable absorber coupled to one or more of the first DBR stack or the second DBR stack, or a saturable absorber coupled to one or more of the VCSEL devices, wherein the saturable absorber is CdSe (cadmium selenide), ZnO (zinc oxide), ZnS (zinc sulfide), graphene oxide (GO), MoS ２ (Molybdenum disulfide), fullerene (C ６０A VCSEL device system according to any one of appendices P1 to P13, further comprising a polymer dye, Ti: sapphire (titanium-doped sapphire), and Ce: YAG (cerium-doped yttrium aluminum garnet). (Appendix P15) A VCSEL device system according to any one of appendices P1 to P14, wherein the n-type region comprises an n-GaN layer located on the first DBR stack, and the p-type region comprises a p++GaN contact layer, p-type AlGaN, and further comprises a GaN barrier region formed between the multiple quantum well region and the p-type region. (Appendix P16) A VCSEL device system according to appendix P15, further comprising a p-type electrode region including a transparent electrode and a phase-shift region. (Appendix P17) A VCSEL device system according to any one of the appendices P1 to P16, further comprising n-type GaN, n++-type GaN, and p++-type inGaN. (Appendix P18) The VCSEL device system according to any one of the appendices P1 to P14, wherein the cavity region is coupled between the first DBR stack and the second DBR stack and includes n-type GaN, n++-type GaN, p++-type InGaN, p-type GaN, p-type AlGaN, a GaN barrier, the multiple quantum well region, optionally n-type AlGaN, and n-type GaN, or the cavity region is coupled between the first DBR stack and the second DBR stack and includes a phase shift layer, a transparent electrode region, p++-type GaN, p-type GaN, p-type AlGaN, a GaN barrier, the multiple quantum well region, optionally n-type AlGaN, and n-type GaN. (Appendix P19) A coherent beam-coupled vertical cavity surface-emitting laser (VCSEL) device system comprising a semiconductor substrate containing a compound semiconductor material, and a plurality of VCSEL devices arranged in an array in a first portion of the semiconductor substrate, wherein each of the VCSEL devices comprises a first DBR stack, a second DBR stack facing the first DBR stack,The VCSEL device system further comprises a cavity region formed between the first DBR stack and the second DBR stack, the cavity region having a length of 5 microns or more to facilitate in-plane propagation of light, the cavity region comprising a multiple quantum well region having a first emission spectrum characterized by laser emission ranging from a first wavelength to a second wavelength, each of the VCSEL devices further comprises an n-type region formed between the multiple quantum well region and the second DBR stack, and a p-type region formed between the multiple quantum well region and the first DBR stack, the VCSEL device system further comprises a waveguide coupling each of the plurality of VCSEL devices, and an in-plane light source disposed in a second portion of the semiconductor substrate, the in-plane light source being characterized by a second emission spectrum, each of the first emission spectra being included in the second emission spectrum, and the VCSEL device system further comprises a free-space gap between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate separating the plurality of VCSEL devices from the in-plane light source. The in-plane light source is characterized by a first parameter, each of the VCSEL devices is characterized by a second parameter, the first parameter interacts with the second parameter in the waveguide to exhibit the characteristics of the first parameter, thereby each of the VCSEL devices is characterized by the first parameter, each of the VCSEL devices is synchronized, and the VCSEL device system further comprises a combiner which is coupled to each of the laser beams emitted from the VCSEL devices and coherently couples each of the laser beams together to form a single coherently coupled laser beam. (Appendix P20) A vertical-cavity surface-emitting laser (VCSEL) device array comprising a semiconductor substrate containing a compound semiconductor material, and a plurality of VCSEL devices arranged in an array on the semiconductor substrate, each of the VCSEL devices comprising a first DBR stack, a second DBR stack facing the first DBR stack,The VCSEL device includes a cavity region formed between the first DBR stack and the second DBR stack, the cavity region having a cavity length of 5 microns or more, the cavity region including a multiple quantum well region capable of laser emission, the VCSEL device is capable of emitting first light of a first emission spectrum, each of the VCSEL devices further includes an n-type region formed between the multiple quantum well region and the second DBR stack, and a p-type region formed between the multiple quantum well region and the first DBR stack, the VCSEL device array further includes a waveguide coupling each of the plurality of VCSEL devices, each of the first emission spectra is included in the range of the second emission spectrum of second light incident on the waveguide, the two light of the second emission spectrum has a first parameter, and each of the first light of the first emission spectrum has a second parameter. Each of the VCSEL devices is a VCSEL device array characterized by the first parameter, the first parameter interacting with the second parameter in the waveguide.

Claims

1. A vertical-cavity surface-emitting laser (VCSEL) device system comprising: a semiconductor substrate containing a compound semiconductor material; and a plurality of VCSEL devices spatially arranged in an array on a first portion of the semiconductor substrate, each of the VCSEL devices including: a first DBR stack; a second DBR stack facing the first DBR stack; and a cavity region formed between the first DBR stack and the second DBR stack, the cavity region having a cavity length of 5 microns or more; the cavity region including a multiple quantum well region capable of laser emission; the VCSEL device being capable of emitting first light of a first emission spectrum; the cavity region including an n-type region formed between the multiple quantum well region and the second DBR stack; and a p-type region formed between the multiple quantum well region and the first DBR stack; the VCSEL device system further comprising: a waveguide coupling each of the plurality of VCSEL devices; A VCSEL device system comprising an in-plane light source disposed in a second portion of the semiconductor substrate, wherein the in-plane light source is capable of emitting a second light of a second emission spectrum, each of the first emission spectra is included in the range of the second emission spectrum, the VCSEL device system further comprises the second light of the second emission spectrum having a first parameter, each of the first light of the first emission spectrum having a second parameter, and each of the VCSEL devices being characterized by the first parameter, the first parameter interacting with the second parameter in the waveguide.

2. The VCSEL device system according to claim 1, wherein a free-space gap is provided between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate for separating the plurality of VCSEL devices from the in-plane light source.

3. The VCSEL device system according to claim 1, wherein there is no free space gap between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate, or the first portion and the second portion have a continuous structure.

4. The VCSEL device system according to any one of claims 1 to 3, wherein the first parameter is at least one of phase, frequency, polarization, timing, or pulse timing.

5. The VCSEL device system according to any one of claims 1 to 4, wherein each of the VCSEL devices is synchronized with the first parameter.

6. The VCSEL device system according to any one of claims 2 to 5, wherein the free space gap includes a trench structure.

7. The VCSEL device system according to any one of claims 1 to 6, wherein the multiple quantum well region comprises two to seven well layers, and each of the well layers is configured between a pair of barrier layers.

8. The VCSEL device system according to any one of claims 1 to 7, wherein the in-plane light source is selected from an end-face emitting laser, a light-emitting diode, and a superluminescent diode.

9. The VCSEL device system according to any one of claims 1 to 8, wherein the waveguide is a slab waveguide.

10. The VCSEL device system according to any one of claims 2 to 9, wherein the free space gap includes an anti-reflective coating covering the free space gap.

11. The VCSEL device system according to any one of claims 2 to 10, wherein the free space gap separates the first portion of the semiconductor substrate from the second portion of the semiconductor substrate, so that the first portion is a separate substrate from the second portion.

12. The VCSEL device system according to any one of claims 2 to 11, wherein the in-plane light source is a superluminescent diode, and the superluminescent diode is provided with an anti-reflective coating on its side surface.

13. The VCSEL device system according to any one of claims 2 to 12, wherein the free space gap includes a trench region having angled sidewalls configured at an angle of about 0 to 45 degrees from a direction perpendicular to the plane of the semiconductor substrate.

14. The device further comprises a saturable absorber material coupled to the light source, or a saturable absorber device including a pulsed laser, or a saturable absorber coupled to one or more of the first DBR stack or the second DBR stack, or a saturable absorber coupled to one or more of the VCSEL devices, wherein the saturable absorber is CdSe (cadmium selenide), ZnO (zinc oxide), ZnS (zinc sulfide), graphene oxide (GO), MoS ２ (Molybdenum disulfide), fullerene (C ６０ A VCSEL device system according to any one of claims 1 to 13, comprising a polymer dye, Ti: sapphire (titanium-doped sapphire), and Ce: YAG (cerium-doped yttrium aluminum garnet).

15. The VCSEL device system according to any one of claims 1 to 14, wherein the n-type region includes an n-GaN layer located on the first DBR stack, and the p-type region includes a p++GaN contact layer, p-type AlGaN, and further includes a GaN barrier region formed between the multiple quantum well region and the p-type region.

16. The VCSEL device system according to claim 15, further comprising a p-type electrode region including a transparent electrode and a phase-shift region.

17. The VCSEL device system according to any one of claims 1 to 16, further comprising n-type GaN, n++-type GaN, and p++-type inGaN.

18. The VCSEL device system according to any one of claims 1 to 14, wherein the cavity region is coupled between the first DBR stack and the second DBR stack and includes n-type GaN, n++-type GaN, p++-type InGaN, p-type GaN, p-type AlGaN, a GaN barrier, the multiple quantum well region, optionally n-type AlGaN, and n-type GaN, or the cavity region is coupled between the first DBR stack and the second DBR stack and includes a phase shift layer, a transparent electrode region, p++-type GaN, p-type GaN, p-type AlGaN, a GaN barrier, the multiple quantum well region, optionally n-type AlGaN, and n-type GaN. 19.A coherent beam-coupled vertical cavity surface-emitting laser (VCSEL) device system comprising: a semiconductor substrate containing a compound semiconductor material; and a plurality of VCSEL devices spatially arranged in an array on a first portion of the semiconductor substrate, each of the VCSEL devices comprising: a first DBR stack; a second DBR stack facing the first DBR stack; and a cavity region formed between the first DBR stack and the second DBR stack, the cavity region having a length of 5 microns or more to facilitate in-plane propagation of light, the cavity region comprising a multiple quantum well region having a first emission spectrum characterized by laser emission ranging from a first wavelength to a second wavelength; each of the VCSEL devices further comprising: an n-type region formed between the multiple quantum well region and the second DBR stack; and a p-type region formed between the multiple quantum well region and the first DBR stack; the VCSEL device system further comprising: a waveguide coupling each of the plurality of VCSEL devices; A VCSEL device system comprising: an in-plane light source disposed in a second portion of the semiconductor substrate, wherein the in-plane light source is characterized by a second emission spectrum, and each of the first emission spectra is included in the second emission spectrum; the VCSEL device system further comprises a free-space gap between the first portion and the second portion of the semiconductor substrate separating the plurality of VCSEL devices from the in-plane light source; the in-plane light source is characterized by a first parameter, each of the VCSEL devices is characterized by a second parameter, the first parameter interacts with the second parameter in the waveguide to exhibit the characteristics of the first parameter, thereby characterizing each of the VCSEL devices by the first parameter, and each of the VCSEL devices is synchronized; and the VCSEL device system further comprises a combiner that is coupled to each of the laser beams emitted from the VCSEL devices, and coherently couples each of the laser beams together to form a single coherently coupled laser beam.

20. A vertical-cavity surface-emitting laser (VCSEL) device array comprising a semiconductor substrate containing a compound semiconductor material, and a plurality of VCSEL devices arranged spatially on the semiconductor substrate in an array, wherein each of the VCSEL devices includes a first DBR stack, a second DBR stack facing the first DBR stack, and a cavity region formed between the first DBR stack and the second DBR stack, the cavity region having a cavity length of 5 microns or more, the cavity region including a multiple quantum well region capable of laser emission, the VCSEL device being capable of emitting first light of a first emission spectrum, each of the VCSEL devices further including an n-type region formed between the multiple quantum well region and the second DBR stack, and a p-type region formed between the multiple quantum well region and the first DBR stack, and the VCSEL device array further comprising a waveguide coupling each of the plurality of VCSEL devices. Each of the first emission spectra is included in the range of the second emission spectrum of a second light incident on the waveguide, the two light of the second emission spectrum has a first parameter, each of the first light of the first emission spectrum has a second parameter, and each of the VCSEL devices is characterized by the first parameter, with the first parameter interacting with the second parameter in the waveguide.

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