Model tuning agent using reinforcement learning technology with global performance

Abstract

A method of tuning a machine learning model associated with a lithography patterning process is disclosed. More particularly, a method of using a reinforcement learning tuning engine to accurately adjust a deep learning-trained lithography model and enable global view of a training dataset is disclosed. In the reinforcement learning process, the reward can be defined as a function of global metrics derived from model predictions. Given the reward, the accuracy agent can determine actions corresponding to delta variables of the model.

Description

MODEL TUNING AGENT USING REINFORCEMENT LEARNING TECHNOLOGY WITH GLOBAL PERFORMANCECROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of US application 63 / 702,996 which was filed on October 3, 2024 and which is incorporated herein in its entirety by reference.FIELD

[0002] The embodiments provided herein disclose a method of tuning a model associated with a lithography patterning process.BACKGROUND

[0003] A lithographic apparatus is a machine that applies a desired pattern onto a target portion of a substrate. The lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). An IC chip in a smart phone can be as small as a person’s thumbnail and may include over 2 billion transistors. Making an IC is a complex and time-consuming process, with circuit components in different layers and including hundreds of individual steps. Errors in even one step may potentially result in problems with the final IC and may cause device failure. Therefore, in manufacturing processes of ICs, unfinished or finished circuit components are inspected to ensure that they are manufactured according to design and are free of defects. Inspection systems utilizing optical microscopes or charged particle (e.g., electron) beam microscopes, such as a scanning electron microscope (SEM) can be employed. As the physical sizes of IC components continue to shrink, accuracy and yield in IC inspection become increasingly important. High process yield and high wafer throughput can be impacted by the presence of defects, especially if operator intervention is required for reviewing the defects. Therefore, modeling lithographic conditions that may accurately predict the formation of defects in ICs before fabrication occurs is desired.SUMMARY

[0004] The embodiments provided herein disclose a method of tuning a model associated with a lithography patterning process and predicting a wafer fabricated by the lithography patterning process.

[0005] Some embodiments of the present disclosure provide a method for tuning a machine learning model associated with a lithography process. The method comprises obtaining a trained model, wherein the trained model is trained by a deep learning process, wherein the deep learning process comprises a plurality of iterative training steps, and wherein an iterative training step of the plurality of iterative training steps uses a respective portion of a training dataset; applying the trained model to trained dataset to generate a plurality of prediction results; determining a reward based onthe generated plurality of prediction results; determining a model tuning action based on the determined reward; and adjusting the trained model based on the determined model tuning action.

[0006] Other advantages of the present disclosure will become apparent from the following description taken in conjunction with the accompanying drawings wherein are set forth, by way of illustration and example, certain embodiments of the present disclosure.BRIEF DESCRIPTION OF FIGURES

[0007] The above and other aspects of the present disclosure will become more apparent from the description of exemplary embodiments, taken in conjunction with the accompanying drawings.

[0008] FIG. 1 is a schematic diagram illustrating an example lithographic projection assembly to fabricate an IC, consistent with embodiments of the present disclosure.

[0009] FIG. 2 is a schematic diagram illustrating an example workflow for simulating lithography in a lithographic projection apparatus, consistent with embodiments of the present disclosure.

[0010] FIG. 3 is a schematic diagram illustrating an example artificial intelligence architecture, consistent with some embodiments of the present disclosure.

[0011] FIG. 4 is an example flow diagram for training a model associated with a lithography patterning process according to a conventional deep learning method.

[0012] FIG. 5A is an example block diagram for generating input data, consistent with embodiments of the present disclosure.

[0013] FIG. 5B is an example block diagram of a system for processing image data, consistent with embodiments of the present disclosure.

[0014] FIG. 6 is an example illustration of tuning a deep learning-trained model associated with a lithography process using a tuning engine, consistent with embodiments of the present disclosure.

[0015] FIG. 7 is an example workflow illustrating a method, consistent with embodiments of the present disclosure.DETAILED DESCRIPTION

[0016] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of exemplary embodiments do not represent all implementations consistent with the disclosure. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the disclosure as recited in the appended claims.

[0017] The enhanced computing power of electronic devices, while reducing the physical size of the devices, can be accomplished by significantly increasing the packing density of circuitcomponents such as transistors, capacitors, diodes, etc. on an IC chip. Semiconductor IC manufacturing is a complex and time-consuming process, with hundreds of individual steps. Errors in even one step have the potential to dramatically affect the functioning of the final product. Even one “killer defect” can cause device failure. The goal of the manufacturing process is to improve the overall yield of the process.

[0018] ICs may be manufactured using lithography, which is a fabrication process involving creating complex circuit patterns drawn on a mask deposited onto a substrate. Lithography may be performed by a lithographic apparatus, which is a machine that applies a source of radiation (e.g., light or X-ray) onto a target portion of the substrate to form a desired pattern. The target portion of the substrate may be covered with a pattern device (e.g., mask) that may be either eliminated or developed after exposure to the radiation source. This process of transferring the desired pattern to the substrate is called a patterning process. The patterning process may include a patterning step to transfer a pattern from a pattern device (e.g., a mask) to the substrate. There can also be one or more related pattern processing steps, such as mask development by a development apparatus, baking of the substrate using a bake tool, etching the pattern onto the substrate using an etch apparatus, or other chemical and physical processing steps involved in fabricating a pattern onto the substrate. Variations in experimental parameters (e.g., stochastic variations, errors, or noise due to an inspection tool or pattern processing tool) can potentially limit lithography implementation for high volume manufacturing (HVM), or process yield, of ICs and introduce defects into IC structures.

[0019] In the manufacture of ICs using a lithographic apparatus, typically many lithographic patterning steps are performed, thereby forming functional features in successive layers on the substrate. A critical aspect of performance of the lithographic apparatus is therefore the ability to place the applied pattern correctly and accurately in relation to features laid down in previous layers. For this purpose, the substrate is provided with one or more sets of alignment marks. Each mark is a structure having a position that can be measured later using, for example, an electron beam inspection tool. Defects may occur in which an applied pattern structure or pattern layer is incorrectly placed in relation to a reference mark, or when the fabrication conditions are suboptimal. A reference mark or layout defines the desired structure, structure dimensions, and the distance between IC structures (such as gates, capacitors, etc.) or interconnect lines. This may ensure that the IC devices or lines do not interact with one another in an undesirable way. The structure limitations provided by the reference layouts are typically referred to as critical dimensions. A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the critical dimension determines the overall size and packing density of the designed IC. A goal in IC fabrication is to faithfully reproduce the original IC design on the substrate. If an error occurs during fabrication where the created IC design pattern does not match the reference design, this may result in a defect in the IC structure and render the IC inoperable.

[0020] As semiconductor manufacturing processes continue to advance, the dimensions of functional elements have continually been reduced while the number of functional elements, such as transistors, per device has been steadily increasing over decades, following a trend commonly referred to as “Moore's law.” At the current state of technology, layers of devices are manufactured using lithographic projection apparatuses that project a design layout onto a substrate using illumination from a deep-ultraviolet illumination source, creating individual functional elements having dimensions well below 100 nm, i.e., less than half the wavelength of the radiation from the illumination source (e.g., a 193 nm illumination source). This process in which features with dimensions smaller than the classical resolution limit of a lithographic projection apparatus are printed, is commonly known as low-ki lithography, according to the resolution formula critical dimension (CD)=ki / Z / NA. where Z is the wavelength of radiation employed (currently in most cases 248 nm or 193 nm), NA is the numerical aperture of projection optics in the lithographic projection apparatus and ki is an empirical resolution factor. In general, the smaller ki the more difficult it becomes to reproduce a pattern on the substrate that resembles the shape and dimensions planned by a designer in order to achieve particular electrical functionality and performance. To overcome these difficulties, simulated or computational lithography models are applied to the lithographic projection apparatus, the design layout, or the patterning device. These include, for example, but not limited to, optimization of NA and optical coherence settings, customized illumination schemes, use of phase shifting patterning devices, optical proximity correction (OPC, sometimes also referred to as “optical and process correction”) in the design layout, or other methods generally defined as “resolution enhancement techniques” (RET).

[0021] In computational lithography, patterning process models related to different aspects of the patterning process such as a mask model, an optical model, a resist model, or a post-exposure model may be employed to predict a pattern that will be printed on the substrate. The patterning process models when properly trained (e.g., using measurement data associated with a printed wafer) can produce accurate prediction of patterns dimensions output from the patterning processes. For example, a patterning process model of post-exposure processes may be trained based on empirical measurements. The training process involves exposing test substrates by varying different process parameters (e.g., dose, focus, etc.), measuring resulting critical dimensions printed patterns after postexposure processes, and calibrating the patterning process models to the measured results. In practice, faster and more accurate models may serve to improve lithography performance (e.g., yield), enhance process windows, patterning recipes, or enabled increased complexity of a design pattern.

[0022] A lithography patterning process is a complex process and not all aspects may be modeled based on physics / chemistry involved in the lithography patterning process. For example, some effects of the post-exposure processes are well understood and can be modelled with mathematical expressions of physical terms (e.g., parameters associated with a resist process) that describe the physics / chemistry of the process. For example, an acid-base diffusion after the exposurecan be modelled by a Gaussian filter on the aerial image. Additionally, some of physical terms (e.g., associated with dose, focus, intensity, pupil, etc.) are associated with and tunable via tunable parameters (e.g., tunable knobs) of the lithographic apparatus, thereby enabling real-time control of the patterning process. Some physical terms may not be directly tunable via tuning knobs but may be explained by the physics / chemistry of a process (e.g., aerial image formation, resist image formation, etc.). For example, a resist model may comprise a Gaussian filter on the aerial image for modelling an acid-base diffusion in the resist after the exposure. This sigma term is generally not tunable via tunable knobs. Even so, the values of such physical terms (e.g., sigma) may be determined based on empirical equations or physics-based equations that model effects of a process (e.g., resist formation).

[0023] However, several aspects or effects of a lithography patterning process are not well understood, and thus difficult to model using physics / chemistry-based equations. Conventional modeling methods and systems train and use deep-learning (DL) convolutional neural networks (CNNs) for modeling less-understood aspects of the lithography patterning process (e.g., postexposure). A conventional DL CNN modeling approach involves iteratively training a model to predict a wafer pattern and calculate a corresponding loss function and gradient. In each iterative training step, the DL CNN model uses only a fraction of a training dataset. Therefore, the calculated loss function for each training step only represents the performance of an individual training sample in the fraction of the training dataset (e.g., a minibatch). Accordingly, any loss function calculated using a conventional DL modeling approach may not accurately reflect the worst performance of the entire training dataset. A modeling approach that can tune a DL model using an entire training dataset, avoid a multiple-queue configuration, and obviate selection of hyperparameters is thus desired.

[0024] Embodiments of the present disclosure provide a method to predict a lithography patterning process by tuning a DL-trained model to previously unobtainable accuracy through a reinforcement learning process using an entire training dataset. Some embodiments of the present disclosure may provide a method to train a model tuning engine, in which the trained model tuning engine may be used to tune a DL-trained model associated with a lithography patterning process using an entire training dataset. In some embodiments, a DL-trained model associated with a lithography patterning process and a training dataset (e.g., a plurality of images or patterns) are inputted to the tuning engine, in which the tuning engine calculates a reward and updates the DL-trained model based on the reward. The tuning engine may calculate a plurality of error values associated with applying the training dataset to the DL-trained model, and a largest error value above a threshold value is selected. The threshold value may be a user specified value. In some embodiments, the threshold value may be a maximum allowed error value for a model associated with a lithography patterning process (e.g., max model error, max grid dependency, max room mean square, max error range, max wiggle, or any other model error value). In some embodiments, the tuning engine may calculate a tuning action based on the reward and use the tuning action to adjust the DL-trained model. The tuning action may be weight or bias applied to a variable of the DL-trained model. In someembodiments, the DL-trained model may be cycled through the tuning engine to minimize a calculated error associated with the DL-trained model until a largest calculated error associated with the DL-trained model is below the threshold value. In some embodiments, the tuning agent may be optimized using a gradient optimization algorithm (e.g., a proximal policy optimization) and thus reduce a number of cycling the DL-trained through the tuning engine to obtain a minimized calculated error value. The tuned DL-trained model may then be used in modeling a lithography patterning process with improved accuracy. Thus, some embodiments of the present disclosure may increase throughput of IC manufacturing and confidence in predicting lithographic fabrication conditions to manufacture defect-free ICs.

[0025] Relative dimensions of components in drawings may be exaggerated for clarity. Within the following description of drawings the same or like reference numbers refer to the same or like components or entities, and only the differences with respect to the individual embodiments are described. As used herein, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a database can include A or B, then, unless specifically stated otherwise or infeasible, the database can include A, or B, or A and B. As a second example, if it is stated that a database can include A, B, or C, then, unless specifically stated otherwise or infeasible, the database can include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0026] Reference is now made to FIG. 1, which is a schematic diagram illustrating an exemplary lithographic projection apparatus 100. Lithographic projection apparatus 100 may include an emission source 101, which may be a charged-particle emission source, deep-ultraviolet excimer laser source or other type of source including an extreme ultraviolet (EUV) source, and emits a beam 108.Illumination optics which may include illumination optics components 102 and 103 that shape radiation from the radiation source 101; a patterning device 104; and transmission optics 105 that project an image of the patterning device pattern onto a substrate 106. An adjustable filter or aperture 107 at the pupil plane of the projection optics may restrict the range of beam angles that impinge on substrate 106, where the largest possible angle defines the numerical aperture of the projection optics NA=sin(0mazon substrate 106 where beam 108 impacts is called a target portion 109, in which the beam impacts the top layer or mask (not shown).

[0027] Illumination optics components 102 and 103 may direct and shape beam 108 via patterning device 104 onto substrate 106 and may include any optical component that may alter the wavefront of beam 108. A resist layer on substrate 106 may be exposed and a radiation intensity distribution at substrate 106 (i.e., an aerial image) may be transferred to the resist layer. Optical properties of the lithographic projection apparatus (e.g., properties of the source, the patterning device, and the projection optics) dictate this process. The resist layer may be removed and the applied pattern from beam 108 may then be applied to the substrate as discussed above.

[0028] A resist model can be used to calculate a resist image from the aerial image. The resist model is related to properties of the resist layer (e.g., effects of chemical processes that occur during exposure, post-exposure bake (PEB) and development). Optical properties of the lithographic projection apparatus (e.g., properties of the illumination, the patterning device, or the projection optics) may dictate the aerial image and can be defined in an optical model. Since the patterning device used in the lithographic projection apparatus can be changed, it is desirable to separate the optical properties of the patterning device from the optical properties of the rest of the lithographic projection apparatus including the source and the projection optics. Details of techniques and models that may be used to transform a design layout into various lithographic images (e.g., an aerial image or a resist image), to apply OPC using those techniques and models, and to evaluate performance are described in U.S. Patent Application Publication Nos. US 2008-0301620, 2007-0050749, 2007- 0031745, 2008-0309897, 2010-0162197, and 2010-0180251, the disclosure of each being hereby incorporated herein by reference in their entireties.

[0029] It may be desirable to use one or more tools to produce results that, for example, can be used to design, control, monitor, etc. the patterning process. One or more tools used in computationally controlling, designing, etc. one or more aspects of the patterning process, such as the pattern design for a patterning device (including, for example, adding sub-resolution assist features or optical proximity corrections), the illumination for the patterning device, etc., may be provided. Accordingly, in a system for computationally controlling, designing, etc. a manufacturing process involving patterning, the manufacturing system components or processes can be described by various functional modules or models. In some embodiments, one or more electronic (e.g., mathematical, parameterized, etc.) models may be provided that describe one or more steps or apparatuses of the patterning process (e.g., etching). In some embodiments, a simulation of the patterning process can be performed using one or more electronic models to simulate how the patterning process forms a patterned substrate using a pattern provided by a patterning device.

[0030] Although reference may be made in the present disclosure to ICs, it is appreciated that the present disclosure may be applicable to other possible applications or designs. For example, the present disclosure may be applied to integrated optical systems, magnetic domain memories, liquidcrystal display panels, thin-film magnetic heads, and other nanoscale structures. It is further appreciated that the terms “reticle”, “wafer”, or “die” may be used interchangeably with the terms “mask”, “substrate” or “sample”, and “target portion”, respectively.

[0031] FIG. 2 illustrates an example workflow for simulating lithography in a lithographic projection apparatus. An illumination model 231 represents optical characteristics (including radiation intensity distribution or phase distribution) of the illumination. A projection optics model 232 represents optical characteristics (including changes to the radiation intensity distribution or the phase distribution caused by the projection optics) of the projection optics. A design layout model 235 represents optical characteristics (including changes to the radiation intensity distribution or the phasedistribution caused by a given design layout) of a design layout, which is the representation of an arrangement of features on or formed by a patterning device. An aerial image 236 can be simulated using the illumination model 231, the projection optics model 232, and the design layout model 235. A resist image 238 can be simulated from the aerial image 236 using a resist model 237. Simulation of lithography can, for example, predict contours or CDs in the resist image.

[0032] More specifically, illumination model 231 can represent the optical characteristics of the illumination that include, but are not limited to, NA-sigma (o) settings as well as any particular illumination shape (e.g., off-axis illumination such as annular, quadrupole, dipole, etc.). The projection optics model 232 can represent the optical characteristics of the of the projection optics, including, for example, aberration, distortion, a refractive index, a physical size or dimension, etc. The design layout model 235 can also represent one or more physical properties of a physical patterning device, as described, for example, in U.S. Patent No. 7,587,704, which is incorporated herein by reference in its entirety. Optical properties associated with the lithographic projection apparatus (e.g., properties of the illumination, the patterning device, and the projection optics) dictate the aerial image. Since the patterning device used in the lithographic projection apparatus can be changed, it is desirable to separate the optical properties of the patterning device from the optical properties of the rest of the lithographic projection apparatus including at least the illumination and the projection optics (hence design layout model 235).

[0033] The resist model 237 can be used to calculate the resist image from the aerial image, an example of which can be found in U.S. Patent No. 8,200,468, which is hereby incorporated herein by reference in its entirety. The resist model is typically related to properties of the resist layer (e.g., effects of chemical processes which occur during exposure, post-exposure bake or development).

[0034] One of the objectives of the full simulation is to accurately predict, for example, edge placements, aerial image intensity slopes or CDs, which can then be compared against an intended design. The intended design is generally defined as a pre-OPC design layout which can be provided in a standardized digital file format such as GDS, GDSII, OASIS, or other file formats.

[0035] From the design layout, one or more portions may be identified, which are referred to as “clips.” In some embodiments, a set of clips is extracted, which represents the complicated patterns in the design layout (typically about 50 to 1000 clips, although any number of clips may be used). It is appreciated that these patterns or clips represent small portions (e.g., circuits, cells, etc.) of the design and especially the clips represent small portions for which particular attention or verification is needed. In other words, clips may be the portions of the design layout or may be similar or have a similar behavior of portions of the design layout where critical features are identified either by experience (including clips provided by a customer), by trial and error, or by running a full-chip simulation. Clips often contain one or more test patterns or gauge patterns. An initial larger set of clips may be provided a priori by a customer based on known critical feature areas in a design layout that require particular image optimization. Alternatively, in some embodiments, the initial larger setof clips may be extracted from the entire design layout by using an automated (such as, machine vision) or manual algorithm that identifies the critical feature areas.

[0036] For example, the simulation and modeling can be used to configure one or more features of the patterning device pattern (e.g., performing optical proximity correction), one or more features of the illumination (e.g., changing one or more characteristics of a spatial / angular intensity distribution of the illumination, such as change a shape), or one or more features of the projection optics (e.g., numerical aperture, etc.). Such a configuration can be generally referred to as, respectively, mask optimization, source optimization, and projection optimization. Such optimization can be performed on their own or combined in different combinations. One such example is source-mask optimization (SMO), which involves the configuring of one or more features of the patterning device pattern together with one or more features of the illumination. The optimization techniques may focus on one or more of the clips. The optimizations may use the machine learning model described herein to predict values of various parameters (including images, etc.).

[0037] Similar modelling techniques may be applied for optimizing an etching process, for example, or other processes. In some embodiments, illumination model 231, projection optics model 232, design layout model 235, resist model 237, or other models may be used in conjunction with an etch model, for example. For example, output from an after-development inspection (ADI) model (e.g., included as some or all of design layout model 235, resist model 237, or other models) may be used to determine an ADI contour, which may be provided to an effective etch bias (EEB) model to generate a predicted after etch inspection (AEI) contour.

[0038] In some embodiments, an optimization process of a system may be represented as a cost function. The optimization process may comprise finding a set of parameters (design variables, process variables, etc.) of the system that minimizes the cost function. The cost function can have any suitable form depending on the goal of the optimization. For example, the cost function can be weighted root mean square (RMS) of deviations of certain characteristics (evaluation points) of the system with respect to the intended values (e.g., ideal values) of these characteristics. The cost function can also be the maximum of these deviations (e.g., worst deviation). The term “evaluation points” should be interpreted broadly to include any characteristics of the system or fabrication method. The design or process variables of the system can be confined to finite ranges or be interdependent due to practicalities of implementations of the system or method. In the case of a lithographic projection apparatus, the constraints are often associated with physical properties and characteristics of the hardware such as tunable ranges, or patterning device manufacturability design rules. The evaluation points can include physical points on a resist image on a substrate, as well as non-physical characteristics such as one or more etching parameters, dose and focus, etc., for example.

[0039] In some embodiments, illumination model 231, projection optics model 232, design layout model 235, resist model 237, an etch model, or other models associated with or included in anintegrated circuit manufacturing process may be an empirical or other simulation model that performs at least some of the operations of the method described herein. The empirical model may predict outputs based on correlations between various inputs (e.g., one or more characteristics of a pattern such as curvature, one or more characteristics of the patterning device, one or more characteristics of the illumination used in the lithographic process such as the wavelength, etc.). As an example, the empirical model may be a machine learning model or any other parameterized model. In some embodiments, the machine learning model (for example) may be or include mathematical equations, algorithms, plots, charts, networks (e.g., neural networks), or other tools and machine learning model components. For example, the machine learning model may be or include one or more neural networks having an input layer, an output layer, and one or more intermediate or hidden layers. In some embodiments, the one or more neural networks may be or include deep neural networks (e.g., neural networks that have one or more intermediate or hidden layers between the input and output layers). As an example, the one or more neural networks may be based on a large collection of neural units (or artificial neurons). The one or more neural networks may loosely mimic the manner in which a biological brain works (e.g., via large clusters of biological neurons connected by axons). Each neural unit of a neural network may be connected with many other neural units of the neural network. Such connections can be enforcing or inhibitory in their effect on the activation state of connected neural units. In some embodiments, each individual neural unit may have a summation function that combines the values of all its inputs together. In some embodiments, each connection (or the neural unit itself) may have a threshold function such that a signal must surpass the threshold before it is allowed to propagate to other neural units. These neural network systems may be self-learning and trained, rather than explicitly programmed, and can perform significantly better in certain areas of problem solving, as compared to traditional computer programs. In some embodiments, the one or more neural networks may include multiple layers (e.g., where a signal path traverses from front layers to back layers). In some embodiments, back propagation techniques may be utilized by the neural networks, where forward stimulation is used to reset weights on the “front” neural units. In some embodiments, stimulation and inhibition for the one or more neural networks may be freer flowing, with connections interacting in a more chaotic and complex fashion. In some embodiments, the intermediate layers of the one or more neural networks include one or more convolutional layers, one or more recurrent layers, or other layers.

[0040] The one or more neural networks may be trained (e.g., parameters are determined) using a set of training information. The training information may include a set of training samples. Each sample may be a pair comprising an input object (typically a vector, which may be called a feature vector) and a desired output value (also called the supervisory signal). A training algorithm analyzes the training information and adjusts the behavior of the neural network by adjusting the parameters (e.g., weights of one or more layers) of the neural network based on the training information. For example, given a set of N training samples of the form {(xi, yi), (x2, y2), . . . ,(xN,y )} such that Xi is the featurevector of the i-th example and y; is its supervisory signal, a training algorithm seeks a neural network g: X -> Y, where X is the input space and Y is the output space. A feature vector is an n-dimensional vector of numerical features that represent some object (e.g., a simulated aerial image, a wafer design, a clip, etc.). The vector space associated with these vectors is often called the feature space. After training, the neural network may be used for making predictions using new samples.

[0041] In some embodiments, the present systems and methods include (or use) an empirical simulation model that comprises one or more algorithms. The one or more algorithms comprise one or more non-linear, linear, or quadratic functions representative of the physical parameters of a lithography patterning process. In some embodiments, the one or more algorithms comprise a curvature term configured to, alone or in combination with other algorithm terms, correlate curvatures with bias amounts or directions.

[0042] As one example practical application of the present disclosure, optical proximity correction involves adjusting a desired or target pattern or placing appropriate assist features around the desired pattern such that a difference between a predicted pattern and a desired pattern is reduced. Optical proximity correction often requires an optical model, a mask model, a resist model, and an etch model to the simulate the lithography process for mask design optimization. The resist model is configured to generate a resist image. The etch model (e.g., an effective etch bias model) is configured to simulate etch effects and generate an etch contour determined based on a resist contour. In some embodiments, the etch model calculates after-etching- image (AEI) contours by directly biasing after development image (ADI) contours. During etch model calibration, an etch biasing value and an etch bias direction are determined and used to configure the model. The etch bias value (e.g., a scalar magnitude) is determined for a location of interest on a contour. An etch bias direction may be determined based on an ADI feature characteristic (e.g., a curvature) or pattern density of the ADI contour.

[0043] Metrology data may be collected and provided to embodiments of the present disclosure (e.g., a simulation model) using any number of metrology tools or measurements. Embodiments of the present disclosure are not limited to the metrology tool used to collect metrology. Non-limiting examples of metrology tools include a charged particle beam tool (e.g., electron beam tool), an aerial imaging measurement tool, an optical microscope, or any other metrology tool may be used to collect metrology measurements.

[0044] Although reference may be made in the present disclosure to ICs, it is appreciated that the present disclosure may be applicable to other possible applications or designs. For example, the present disclosure may be applied to integrated optical systems, magnetic domain memories, liquidcrystal display panels, thin-film magnetic heads, and other nanoscale structures. It is further appreciated that the terms “die”, “structure”, and “IC structure” are used interchangeably in this disclosure.

[0045] In some embodiments, a machine learning model may comprise a neural network. For example, a model may be a deep neural network with a set of weights that model according to the data that it has been fed to train it.

[0046] Neural networks typically consist of multiple layers, and the signal path traverses from front to back. The goal of the neural network is to solve problems in the same way that the human brain would, although several neural networks are much more abstract. Modem neural network projects typically work with a few thousand to a few million neural units and millions of connections. The neural network may have any suitable architecture and / or configuration known in the art.

[0047] A neural network, as used herein, may refer to a computing model for analyzing underlying relationships in a set of input data by way of mimicking human brains. Similar to a biological neural network, the neural network may include a set of connected units or nodes (referred to as “neurons”), structured as different layers, where each connection (also referred to as an “edge”) may obtain and send a signal between neurons of neighboring layers in a way similar to a synapse in a biological brain. The signal may be any type of data (e.g., a real number). Each neuron may obtain one or more signals as an input and output another signal by applying a non-linear function to the inputted signals. Neurons and edges may typically be weighted by corresponding weights to represent the knowledge the neural network has acquired. During a training process (similar to a learning process of a biological brain), the weights may be adjusted (e.g., by increasing or decreasing their values) to change the strengths of the signals between the neurons to improve the performance accuracy of the neural network. Neurons may apply a thresholding function (referred to as an “activation function”) to its output values of the non-linear function such that a signal is outputted only when an aggregated value (e.g., a weighted sum) of the output values of the non-linear function exceeds a threshold determined by the thresholding function. Different layers of neurons may transform their input signals in different manners (e.g., by applying different non-linear functions or activation functions). The output of the last layer (referred to as an “output layer”) may output the analysis result of the neural network, such as, for example, a categorization of the set of input data (e.g., as in image recognition cases), a numerical result, or any type of output data for obtaining an analytical result from the input data.

[0048] During the training of a neural network, a loss function may be used to evaluate the output data. The loss function, as used herein, may map output data of a machine learning model (e.g., the neural network) onto a real number (referred to as a “loss”) that intuitively represents a loss or an error (e.g., representing a difference between the output data and target output data) associated with the output data. The training of the neural network may seek to maximize or minimize the loss function (e.g., by pushing the loss towards a local maximum or a local minimum in a loss curve). For example, one or more parameters of the neural network may be adjusted or updated purporting to maximize or minimize the loss function. After adjusting or updating the one or more parameters, theneural network may obtain new input data in a next iteration of its training. When the loss function is maximized or minimized, the training of the neural network may be terminated.

[0049] Reference is now made to FIG. 3, which is a schematic diagram illustrating an example artificial intelligence architecture, consistent with some embodiments of the present disclosure. For example, FIG. 3 illustrates a neural network 300. As depicted in FIG. 3, neural network 300 may include an input layer 320 that receives inputs, including input 310-1, . . ., input 310-m (m being an integer). For example, an input of neural network 300 may include any structure or unstructured data (e.g., an image). In some embodiments, neural network 300 may obtain a plurality of inputs simultaneously. For example, in FIG. 3, neural network 300 may obtain m inputs simultaneously. In some embodiments, input layer 320 may obtain m inputs in succession such that input layer 320 receives input 310-1 in a first cycle (e.g., in a first inference) and pushes data from input 310-1 to a hidden layer (e.g., hidden layer 430-1), then receives a second input in a second cycle (e.g., in a second inference) and pushes data from the second input to the hidden layer, and so on. Input layer 320 may obtain any number of inputs in the simultaneous manner, the successive manner, or any manner of grouping the inputs.

[0050] Input layer 320 may include one or more nodes, including node 320-1, node 320-2, . . ., node 320-a (a being an integer). A node (also referred to as a “machine perceptron” or a “neuron”) may model the functioning of a biological neuron. Each node may apply an activation function to received inputs (e.g., one or more of input 310-1, . . ., input 310-m). An activation function may include a Heaviside step function, a Gaussian function, a multiquadratic function, an inverse multiquadratic function, a sigmoidal function, a rectified linear unit (ReLU) function (e.g., a ReLU5 function or a Leaky ReLU function), a hyperbolic tangent (“tanh”) function, or any non-linear function. The output of the activation function may be weighted by a weight associated with the node. A weight may include a positive value between 0 and 1, or any numerical value that may scale outputs of some nodes in a layer more or less than outputs of other nodes in the same layer.

[0051] As further depicted in FIG. 3, neural network 300 includes multiple hidden layers, including hidden layer 330-1, . . ., hidden layer 330-n (n being an integer). When neural network 300 includes more than one hidden layer, it may be referred to as an “artificial neural network” (ANN). An ANN encompasses a “deep neural network” (DNN) and a “recurrent neural network” (RNN). Each hidden layer may include one or more nodes. For example, in FIG. 3, hidden layer 330-1 includes node 330- 1-1, node 330-1-2, node 330-1-3, . . ., node 330-1-b (b being an integer), and hidden layer 330-n includes node 330-n-l, node 330-n-2, node 330-n-3, . . ., node 330-n-c (c being an integer). Similar to nodes of input layer 320, nodes of the hidden layers may apply the same or different activation functions to outputs from connected nodes of a previous layer, and weight the outputs from the activation functions by weights associated with the nodes.

[0052] As further depicted in FIG. 3, neural network 300 may include an output layer 340 that finalizes outputs, including output 350-1, output 350-2, . . ., output 350-d (d being an integer). Outputlayer 340 may include one or more nodes, including node 340-1, node 340-2, . . ., node 340-d. Similar to nodes of input layer 320 and of the hidden layers, nodes of output layer 340 may apply activation functions to outputs from connected nodes of a previous layer and weight the outputs from the activation functions by weights associated with the nodes.

[0053] Although nodes of each hidden layer of neural network 300 are depicted in FIG. 3 to be connected to each node of its previous layer and next layer (referred to as “fully connected”), the layers of neural network 300 may use any connection scheme. For example, one or more layers (e.g., input layer 320, hidden layer 330-1, . . ., hidden layer 330-n, or output layer 340) of neural network 300 may be connected using a convolutional scheme, a sparsely connected scheme, or any connection scheme that uses fewer connections between one layer and a previous layer than the fully connected scheme as depicted in FIG. 3.

[0054] Moreover, although the inputs and outputs of the layers of neural network 300 are depicted as propagating in a forward direction (e.g., being fed from input layer 320 to output layer 340, referred to as a “feedforward network”) in FIG. 3, neural network 300 may additionally or alternatively use backpropagation (e.g., feeding data from output layer 340 towards input layer 320) for other purposes. In some embodiments, neural network 300 may use backpropagation to evaluate and minimize a loss function. Neural network 300 may evaluate and minimize a loss function to improve a weight or bias of neutral network 300 to improve a feedforward network. In some embodiments, neural network 300 may minimize a loss function by applying a mean squared error loss function, a cross-entropy loss function, a mean absolute percentage error loss function, or a stability related loss function (e.g., a grid dependency loss or a trend loss). Accordingly, although neural network 300 is depicted similar to a deep neural network (DNN), neural network 300 may include a recurrent neural network (RNN) or any other neural network.

[0055] Reference is now made to FIG. 4, which is a flow diagram of an example conventional deeplearning modeling method 400 to model a lithography patterning process. Step S401 involves obtaining (i) image data 402 associated with a desired pattern, (ii) measured pattern data 404 of the substrate, associated with the desired pattern, (iii) a first model associated with an aspect (e.g., having effects that can be accurately modelled by physics / chemistry based equations) of the patterning process, the first model comprising a first set of parameters 407, and (iv) a machine learning model associated with another aspect (e.g., having effects that may not be accurately modelled by physics / chemistry based equations) of the patterning process, the machine learning model comprising a second set of parameters 408.

[0056] Image data 402 may refer to any input to the patterning process model configured to predict effects of an aspect of the patterning process or a final pattern that will be printed on the substrate. Image data 402 may be an aerial image, a mask image, a resist image, or other outputs related to one or more aspects of the patterning process. Obtaining the aerial image, mask image, resist image, etc. comprises simulating a patterning process, as discussed in FIG. 2.

[0057] The paterning process model comprises the first model coupled to a second model (e.g., a machine learning model). The first model may be connected to the machine learning model in a series or in a parallel combination. A series combination of the models involves providing output of the first model as an input to the machine learning model. A series combination of the models involves providing output of the machine learning model as an input to the first model. A parallel combination of the models involves providing the same input to the first model and the machine learning model, combining output of the first model and the machine learning model, and determining the predicted printed patern based on the combined outputs of the respective models. The paterning process model may be configured to include both series and parallel arrangement of the first model, a machine learning model, or another physics-based or machine learning model.

[0058] The first model is an empirical model comprising physical terms that accurately describes effects of a first aspect of the paterning process. In some embodiments, the first model may correspond to a first aspect related to an acid-based diffusion after exposure of the substrate. In some embodiments, a first model is a resist model. The first set of parameters of the resist model may correspond to at least one of the following physical terms: an initial acid distribution; an acid diffusion; an image contrast; a long range patern loading effect; a long range patern loading effect; an acid concentration after neutralization; a base concentration after neutralization; a diffusion due to high acid concentration; a diffusion due to high base concentration; a resist shrinkage; a resist development; or two-dimensional convex curvature effects.

[0059] The machine learning model may be a neural network that models a second aspect of the paterning process having a relatively less physics-based understanding. The second set of parameters includes weights and bias of one or more layers of the neural network. During the training process (e.g., involving processes S403, S407), the weights and biases are adjusted in cooperation with the first set of parameters such that a difference between the predicted patern and the measured patern is reduced. The paterning process model may correspond to the second aspect of a post-exposure process of the paterning process.

[0060] Method 400 further involves iteratively determining values of the first set of parameters 407 and the second set of parameters 408 to train the paterning process model. The iteration involves executing steps S403, S405, and S407.

[0061] Step S403 involves executing, using the image data 402, the first model and the machine learning model to cooperatively predict a patern of the substrate. Step S405, involves determining a difference between the measured patern 404 and the predicted patern 405 of the paterning process model and further determining whether the difference is reduced or minimized. Step S407 involves modifying the values of the first set of parameters 407 and the second set of parameters 408 such that a difference between the measured patern 404 and the predicted patern 405 of the paterning process model is reduced.

[0062] The modified values are determined based on an optimization technique such as a gradient descent method that guides how to modify the values of the first set of parameters and the second set of parameters such that a gradient of the difference with respect to the respective parameters is reduced. After several iterations, a global or a local optimum value of the parameters is obtained such that the difference in prediction and measurements is minimized Thus, the patterning process model is calibrated (or trained) and can be further employed for improving the patterning process via OPC, defect detection, hot spot ranking, or other known applications of the patterning process model.

[0063] As discussed above, a conventional DL CNN modeling approach involves iteratively training a model to predict a wafer pattern and calculate a corresponding loss function and gradient. In each iterative training step, the DL CNN model uses only a fraction of a training dataset. Therefore, the calculated loss function for each training step only represents the performance of an individual training sample in the fraction of the training dataset (e.g., a minibatch). Accordingly, any loss function calculated using a conventional DL modeling approach may not accurately reflect the worst performance of the entire training dataset.

[0064] To train a tuning engine configured to tune and adjust a DL-trained model associated with a lithography patterning process, a system to collect and process data following one or more certain lithographic processing steps is desired. Reference is now made to FIG. 5A, which is an example block diagram for obtaining input data, consistent with embodiments of the present disclosure. Input data may be collected as illustrated in FIG. 5A. A lithographic projection apparatus 501 (e.g., lithographic projection apparatus 100 in FIG. 1) may be used to fabricate a wafer according to a lithographic processing condition (e.g., a focus and dose for a radiation source). A metrology tool 502 may be used to measure metrology information of structures formed on the wafer that was generated by lithographic projection apparatus 501. Metrology information may include, but is not limited to, critical dimension, edge placement, and overlay. In some embodiments, a controller 503 with a memory may be communicatively connected to metrology tool 502 to store the measured metrology information.

[0065] In some embodiments, controller 503 may be a generic or specific electronic device capable of manipulating or processing information. For example, controller 503 may include any combination of any number of a central processing unit (or “CPU”), a graphics processing unit (or “GPU”), a neural processing unit (or “NPU”), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PLA), a Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), and any type circuit capable of data processing. Controller 503 may also be a virtual processor that includes one or more processors distributed across multiple machines or devices coupled via a network.

[0066] In some embodiments, controller 503 may further include one or more memories (not shown). A memory may be a generic or specific electronic device capable of storing codes and data accessible by the processor (e.g., via a bus). For example, the memory may include any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, or any type of storage device. The codes and data may include an operating system (OS) and one or more application programs (or “apps”) for specific tasks. The memory may also be a virtual memory that includes one or more memories distributed across multiple machines or devices coupled via a network.

[0067] In some embodiments, an offline computing system (e.g., offline from high volume manufacturing) may be used to collect input data, input the data and DL-trained model to a tuning engine, adjust the DL-trained model via a calculated reward, and cycle the adjusted DL-trained model to determine an optimized tuning engine configured to tune the DL-trained model to a minimized error value. Reference is now made to FIG. 5B, which is a block diagram of an example computing system for training a tuning engine for tuning a DL-trained model associated with a lithography patterning process, consistent with embodiments of the present disclosure. For example, computing system 504 may be a preprocessor, an encoder, or a decoder. In some embodiments, computing system 504 may comprise a memory 506 storing a set of instructions and at least one processor 505 configured to execute the set of instructions to cause computing system 504 to perform operations or manipulations on data for processing. As shown in FIG. 5B, computing system 504 can include processor 505. When processor 505 executes instructions described herein, computing system 504 can become a specialized machine for preprocessing, encoding, or decoding image data. Processor 505 can be any type of circuitry capable of manipulating or processing information. For example, processor 505 can include any combination of any number of a central processing unit (or “CPU”), a graphics processing unit (or “GPU”), a neural processing unit (“NPU”), a microcontroller unit (“MCU”), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PLA), a Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), a System On Chip (SoC), an Application- Specific Integrated Circuit (ASIC), or the like. In some embodiments, processor 505 can also be a set of processors grouped as a single logical component. For example, as shown in FIG. 5B, processor 505 can include multiple processors, including processor 505a, processor 505b, and processor 505n.

[0068] Computing system 504 can also include memory 506 configured to store data (e.g., a set of instructions, computer codes, intermediate data, or the like). For example, as shown in FIG. 5B, the stored data can include program instructions (e.g., program instructions for calibrating a tuning engine) and data for processing (e.g., metrology data). Processor 505 can access the programinstructions and data for processing (e.g., via bus 507), and execute the program instructions to perform an operation or manipulation on the data for processing. Memory 506 can include a highspeed random -access storage device or a non-volatile storage device. In some embodiments, memory 506 can include any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, or the like. Memory 506 can also be a group of memories (not shown in FIG. 5B) grouped as a single logical component.

[0069] Bus 507 can be a communication device that transfers data between components included in computing system 504, such as an internal bus (e.g., a CPU-memory bus), an external bus (e.g., a universal serial bus port, a peripheral component interconnect express port), or the like.

[0070] For ease of explanation without causing ambiguity, processor 505 and other data processing circuits are collectively referred to as a “data processing circuit” in this disclosure. The data processing circuit can be implemented entirely as hardware, or as a combination of software, hardware, or firmware. In addition, the data processing circuit can be a single independent module or can be combined entirely or partially into any other component of computing system 504.

[0071] Computing system 504 can further include network interface 508 to provide wired or wireless communication with a network (e.g., the Internet, an intranet, a local area network, a mobile communications network, or the like). In some embodiments, network interface 508 can include any combination of any number of a network interface controller (NIC), a radio frequency (RF) module, a transponder, a transceiver, a modem, a router, a gateway, a wired network adapter, a wireless network adapter, a Bluetooth adapter, an infrared adapter, a near-field communication (“NFC”) adapter, a cellular network chip, or the like.

[0072] In some embodiments, optionally, computing system 504 can further include peripheral interface 509 to provide a connection to one or more peripheral devices. As shown in FIG. 5B, the peripheral device can include, but is not limited to, a cursor control device (e.g., a mouse, a touchpad, or a touchscreen), a keyboard, a display (e.g., a cathode-ray tube display, a liquid crystal display, or a light-emitting diode display), an input device (e.g., a computing device), or the like.

[0073] Reference is now made to FIG. 6, which is an example flow diagram of using a tuning engine to tune a DL-trained model associated with a lithography patterning process, consistent with embodiments of the present disclosure. FIG. 6 illustrates inputting a DL-trained model 601 and a training dataset 602 into tuning engine 603. Tuning engine 603 may update DL-trained model 601 by using a gradient optimization algorithm (e.g., proximal policy optimization). DL-trained model 601 may be trained as described above using a DL-CNN. In some embodiments, DL-trained model 601 may comprise an OPC model operable to generate an OPC mask pattern with given target patterns, a mask model, an optical model, a resist model, an etch model, or any other simulation model associated with a lithography patterning process. Training dataset 602 may comprise a plurality of data corresponding to DL-trained model 601.

[0074] In some embodiments, DL-trained model 601 comprises a mask model configured to predict a mask image from polygon data, and training dataset 602 comprises a plurality of polygon representations of a mask contour or a mask pattern. In some embodiments, the mask model may be a thin mask model or a thick mask model. In some embodiments, DL-trained model 601 comprises a thin mask model and training dataset 602 comprises a plurality of polygon representations of a thin mask contour or a thin mask pattern (e.g., does not consider a thickness of a mask contour or a mask pattern). In some embodiments, DL-trained model 601 comprises a thick mask model and training dataset 602 comprises a plurality of polygon representations of a thick mask contour or a thick mask pattern (e.g., a 3D representation of a mask contour or a mask pattern).

[0075] In some embodiments, DL-trained model 601 comprises an optical model configured to predict an aerial image from mask data, and training dataset 602 comprises a plurality of mask images or mask patterns. In some embodiments, DL-trained model 601 comprises a resist model configured to predict a resist image from aerial data, and training dataset 602 comprises a plurality of aerial images or aerial patterns. In some embodiments, DL-trained model 601 comprises an etch model configured to predict an etch image from resist data, and training dataset 602 comprises a plurality of resist images or resist patterns.

[0076] In some embodiments, DL-trained model 601 and a training dataset 602 are provided to an environment 604 in tuning engine 603. In some embodiments, environment 604 may comprise a function to calculate an output from DL-trained model 601 and training dataset 602 and a plurality of error values, where an error value of the plurality of error values corresponds to DL-trained model 601 from each training example in training dataset 602. As a non -limiting example, if DL-trained model 601 comprises a resist model and training dataset 602 comprises a plurality of aerial images or aerial patterns, then environment 604 may output a calculated resist image and a plurality of error values corresponding to the resist model. Tuning engine 603 may then calculate a reward 605 based on the calculated plurality of error values. In some embodiments, reward 605 may be calculated by determining a largest error value of the plurality of calculated error values. In some embodiments, reward 605 may be calculated by determining the largest error value of the plurality of calculated error values that is above a threshold value. The threshold value may be a user-specified value. In some embodiments, reward 605 may be defined as a function of global metrics derived from output by inputting training dataset 602 into DL-trained model 601. In some embodiments, reward 605 may comprise a maximum model error, a maximum grid dependency, a room mean square value, a maximum error range, a maximum wiggle value, a maximum weef value, or a maximum wiggle value. Tuning engine 603 may then calculate a tuning action 607 based on reward 605. In some embodiments, tuning action 607 may comprise a delta variable (e.g., a weight or bias) to add to a variable in DL-trained model 601. In some embodiments, tuning engine 603 may determine that reward 605 is above a threshold value, and thus adjust DL-trained model 601 with tuning action 607 and cycle the adjusted DL-trained model 601 back through tuning engine 603 with training dataset602. In some embodiments, tuning engine 603 may determine that reward 605 is below a threshold value, and thus add tuning action 607 to DL-trained model 601 to output a tuned DL-trained model 608. In some embodiments, tuned DL-trained model 608 may be configured to more accurately model a lithography patterning process compared to DL-trained model 601. In some embodiments, tuned DL-trained model 608 may be used to more accurately model and predict a result in a lithography patterning process.

[0077] Reference is now made to FIG. 7, which is an example workflow illustrating a method 700 of tuning a DL-trained model associated with a lithography patterning process, consistent with embodiments of the present disclosure. The steps of method 700 may be performed by a computing device that includes, e.g., controller 503 of FIG. 5A or computing system 504 of FIG. 5B. It is appreciated that the illustrated method 700 may be altered to modify the order of steps and to include the additional steps.

[0078] In step 701, atrained model is obtained. The trained model may be trained by a deep learning process, where the deep learning process comprises a plurality of iterative training steps. A training step of the iterative training steps uses a portion of a training dataset used to train the trained model. In some embodiments, the trained model may be a mask model, an optical model, a resist model, or an etch model. In some embodiments, the training dataset may be a plurality of polygon representations of a mask contour or a mask pattern, a plurality of mask images or mask patterns, a plurality of aerial images or aerial patterns, or a plurality of resist images or resist patterns.

[0079] In step 702, the trained model and the training dataset are applied to a tuning engine.

[0080] In step 703, a plurality of prediction results and a plurality of error values associated with the plurality of prediction results are calculated from the trained model and the training dataset. In some embodiments, the plurality of predictions results is calculated from applying each training example of the training dataset to the trained model. In some embodiments, the plurality of error values is calculated from applying each training example of the training dataset to the trained model. In some embodiments, the plurality of prediction results comprises a predicted mask image, predicted mask pattern, predicted aerial image, predicted aerial pattern, predicted resist image, predicted resist pattern, predicted etch image, or predicted etch pattern. In some embodiments, the plurality of error values comprises a plurality of model error values, a plurality of grid dependency values, a plurality of root mean square values, a plurality of error range values, a plurality of wiggle values, a plurality of weef values, or a plurality of wiggle values.

[0081] In step 704, a reward is determined based on the calculated plurality of prediction results. In some embodiments, the reward is determined based on a maximum calculated error value. In some embodiments, the reward is determined based on a maximum calculated error value that is above a threshold value. The threshold value may be a user-specified value. In some embodiments, the reward may comprise a maximum model error, a maximum grid dependency, a room mean square value, amaximum error range, a maximum wiggle value, a maximum weef value, or a maximum wiggle value.

[0082] In step 705, a model tuning action is determined based on the determined reward. In some embodiments, the model tuning action comprises a delta variable for a variable of the DL-trained model. In some embodiments, the model tuning action comprises a weight or a bias to be applied to the DL-trained model.

[0083] In step 706, the trained model is adjusted based on the determined model tuning action.

[0084] Benefits of the present disclosure include providing a method to tune and improve the accuracy of a DL-trained model associated with a lithography process using a global view of a training dataset. In some embodiments, the present disclosure provides a method to more accurately and quickly determine a model’s performance in predicting a wafer feature formation during a lithography process.

[0085] A non-transitory computer readable medium may be provided that may store instructions for a processor of a lithographic projection apparatus (e.g., lithographic projection apparatus 100 of FIG.1), a computing device (e.g., controller 503 of FIG. 5A or computing system 504 of FIG. 5B) to train or apply a tuning engine, method 700 of FIG. 7, and other executable functions relating to the tuning of a DL-trained model associated with a lithography patterning process. Common forms of non- transitory media include, for example, a floppy disk, a flexible disk, hard disk, solid state drive, magnetic tape, or any other magnetic data storage medium, a Compact Disc Read Only Memory (CD- ROM), any other optical data storage medium, any physical medium with patterns of holes, a Random Access Memory (RAM), a Programmable Read Only Memory (PROM), and Erasable Programmable Read Only Memory (EPROM), a FLASH-EPROM or any other flash memory, Non-Volatile Random Access Memory (NVRAM), a cache, a register, any other memory chip or cartridge, and networked versions of the same.

[0086] The embodiments may further be described using the following clauses:1. A method for tuning a machine learning model associated with a lithography process, the method comprising: obtaining a trained model, wherein the trained model is trained by a deep learning process, wherein the deep learning process comprises a plurality of iterative training steps, and wherein an iterative training step of the plurality of iterative training steps uses a respective portion of a training dataset; applying the trained model to the training dataset to generate a plurality of prediction results; determining a reward based on the generated plurality of prediction results; determining a model tuning action based on the determined reward; and adjusting the trained model based on the determined model tuning action.2. The method of clause 1, wherein determining the reward based on the generated plurality of prediction results comprises: generating a plurality of error values associated with the plurality of generated prediction results; andselecting a generated error value from the generated plurality of error values that surpasses a threshold value.3. The method of clause 2, wherein the selected error value comprises a largest absolute error value of the generated plurality of error values.4. The method of clause 2 or 3, wherein the generated plurality of error values represents a performance of the trained model.5. The method of any one of clauses 3 to 4, wherein the generated plurality of error values comprises model error values, grid dependency error values, root mean square values, trend-aware loss values, hinge values, error value ranges, wiggle values, weef values, or ripple values.6. The method of any one of clauses 1 to 5, wherein the trained model comprises a mask model, an optical model, a resist model, or an etch model.7. The method of any one of clauses 1 to 6, wherein the generated plurality of prediction results comprises a predicted mask image, predicted mask pattern, predicted aerial image, predicted aerial pattern, predicted resist image, predicted resist pattern, predicted etch image, or predicted etch pattern.8. The method of any one of clauses 1 to 7, wherein the training dataset comprises a plurality of polygon representations of a mask contour or a mask pattern, a plurality of mask images or mask patterns, a plurality of aerial images or aerial patterns, or a plurality of resist images or resist patterns.9. The method of any one of clauses 1 to 8, wherein the training dataset comprises a design data or collected images of a plurality of polygon representations of a mask contour or a mask pattern, a plurality of mask images or mask patterns, a plurality of aerial images or aerial patterns, or a plurality of resist images or resist patterns.10. The method of clause 9, wherein the design data or the collected images comprise a critical dimension, a contour, a curvature, or an edge placement.11. The method of clause 9 or 10, wherein the design data comprises a design image, a design pattern, a golden image, a simulated image, a simulated pattern, an averaged image, or an averaged pattern.12. The method of clause 11, wherein the design image or the design pattern comprise a graphic design system (GDS) fde.13. The method of any one of clauses 1 to 12, wherein determining the model tuning action comprises: generating a delta variable based on the determined reward, wherein the delta variable comprises a weight or a bias for a variable of the trained model.14. The method of clause 13, further comprising: generating a gradient of the delta variable to optimize the calculated delta variable; and using the generated gradient to update the delta variable of the model tuning action.15. The method of any one of clauses 1 to 14, wherein the machine learning model is tuned using an offline system or server.16. A non-transitory computer readable medium comprising a set of instructions that is executable by one or more processors of a computing device to cause the computing device to perform operations for tuning a machine learning model associated with a lithography process, the operations comprising the method of any one of clauses 1-15.17. A system for tuning a machine learning model associated with a lithography process, comprising: a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the system to perform operations comprising the method of any one of clauses 1-15.18. A method for tuning a machine learning model associated with a lithography process, the method comprising: obtaining a trained model, wherein the trained model is trained by a deep learning process, wherein the deep learning process comprises a plurality of iterative training steps, and wherein an iterative training step of the plurality of iterative training steps uses a portion of a training dataset; applying the trained model and the training dataset to a tuning engine; generating a plurality of prediction results from the trained model and the training dataset; determining a reward based on the generated plurality of prediction results; determining a model tuning action based on the determined reward; and adjusting the trained model based on the determined model tuning action.19. The method of clause 18, wherein determining the reward based on the generated plurality of prediction results comprises: generating a plurality of error values associated with the plurality of generated prediction results; and selecting a calculated error value from the generated plurality of error values that surpasses a threshold value.20. The method of clause 19, wherein the selected error value comprises a largest absolute error value of the generated plurality of error values.21. The method of clause 19 or 20, wherein the generated plurality of error values represents a performance of the trained model.22. The method of any one of clauses 19 to 21, wherein the generated plurality of error values comprises model error values, grid dependency error values, root mean square values, trend-aware loss values, hinge values, error value ranges, wiggle values, weef values, or ripple values.23. The method of any one of clauses 18 to 22, wherein the trained model comprises a mask model, an optical model, a resist model, or an etch model.24. The method of any one of clauses 18 to 23, wherein the generated plurality of prediction results comprises a predicted mask image, predicted mask pattern, predicted aerial image, predicted aerial pattern, predicted resist image, predicted resist pattern, predicted etch image, or predicted etch pattern.25. The method of any one of clauses 18 to 24, wherein the training dataset comprises a plurality of polygon representations of a mask contour or a mask pattern, a plurality of mask images or mask patterns, a plurality of aerial images or aerial patterns, or a plurality of resist images or resist patterns.26. The method of any one of clauses 18 to 25, wherein the training dataset comprises design data or collected images of a plurality of polygon representations of a mask contour or a mask pattern, a plurality of mask images or mask patterns, a plurality of aerial images or aerial patterns, or a plurality of resist images or resist patterns.27. The method of clause 26, wherein the design data or the collected images comprise a critical dimension, a contour, a curvature, or an edge placement.28. The method of clause 26 or 27, wherein the design data comprises a design image, a design pattern, a golden image, a simulated image, a simulated pattern, an averaged image, or an averaged pattern.29. The method of clause 28, wherein the design image or the design pattern comprise a graphic design system (GDS) fde.30. The method of any one of clauses 18 to 29, wherein determining the model tuning action comprises: generating a delta variable based on the determined reward, wherein the delta variable comprises a weight or a bias for a variable of the trained model.31. A non-transitory computer readable medium comprising a set of instructions that is executable by one or more processors of a computing device to cause the computing device to perform operations for tuning a machine learning model associated with a lithography process, the operations comprising the method of any one of clauses 18-30.32. A system for tuning a machine learning model associated with a lithography process, comprising: a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the system to perform operations comprising the method of any one of clauses 18-30.

[0087] It will be appreciated that the embodiments of the present disclosure are not limited to the exact construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof. The present disclosure has been described in connection with various embodiments, other embodiments of the disclosure will be apparent from consideration of the specification and practice of the technology disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

CLAIMS1. A method for tuning a machine learning model associated with a lithography process, the method comprising: obtaining a trained model, wherein the trained model is trained by a deep learning process, wherein the deep learning process comprises a plurality of iterative training steps, and wherein an iterative training step of the plurality of iterative training steps uses a respective portion of a training dataset; applying the trained model to the training dataset to generate a plurality of prediction results; determining a reward based on the generated plurality of prediction results; determining a model tuning action based on the determined reward; and adjusting the trained model based on the determined model tuning action.

2. The method of claim 1, wherein determining the reward based on the generated plurality of prediction results comprises: generating a plurality of error values associated with the plurality of generated prediction results; and selecting a generated error value from the generated plurality of error values that surpasses a threshold value.

3. The method of claim 2, wherein the selected error value comprises a largest absolute error value of the generated plurality of error values.

4. The method of claim 2, wherein the generated plurality of error values represents a performance of the trained model.

5. The method of claim 3, wherein the generated plurality of error values comprises model error values, grid dependency error values, root mean square values, trend-aware loss values, hinge values, error value ranges, wiggle values, weef values, or ripple values.

6. The method claim 1, wherein the trained model comprises a mask model, an optical model, a resist model, or an etch model.

7. The method claim 1, wherein the generated plurality of prediction results comprises a predicted mask image, predicted mask pattern, predicted aerial image, predicted aerial pattern, predicted resist image, predicted resist pattern, predicted etch image, or predicted etch pattern.

8. The method of claim 1, wherein the training dataset comprises a plurality of polygon representations of a mask contour or a mask pattern, a plurality of mask images or mask patterns, a plurality of aerial images or aerial patterns, or a plurality of resist images or resist patterns.

9. The method of claim 1, wherein the training dataset comprises a design data or collected images of a plurality of polygon representations of a mask contour or a mask pattern, a plurality of mask images or mask patterns, a plurality of aerial images or aerial patterns, or a plurality of resist images or resist patterns.

10. The method of claim 9, wherein the design data or the collected images comprise a critical dimension, a contour, a curvature, or an edge placement.

11. The method of claim 9, wherein the design data comprises a design image, a design pattern, a golden image, a simulated image, a simulated pattern, an averaged image, or an averaged pattern.

12. The method of claim 11, wherein the design image or the design pattern comprise a graphic design system (GDS) fde.

13. The method of claim 1, wherein determining the model tuning action comprises: generating a delta variable based on the determined reward, wherein the delta variable comprises a weight or a bias for a variable of the trained model.

14. The method of claim 13, further comprising: generating a gradient of the delta variable to optimize the calculated delta variable; and using the generated gradient to update the delta variable of the model tuning action.

15. The method of claim 1, wherein the machine learning model is tuned using an offline system or server.

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