Ultra efficient front-end rectifier

Abstract

A front-end rectifier configured for converting three-phased AC voltage to DC voltage while maintaining unity power factor is disclosed, wherein the rectifier is configured as a two-level converter, in which six active switches (S1-S6) are arranged so that each of the three AC phases (Ph A, Ph B, Ph C) is connected to a positive side and a negative side of a DC-link through a top switch (S1, S3, S5) and a bottom switch (S2, S4, S5), respectively, and wherein the three top switches (S1, S3, S5) and the three bottom switches (S2, S4, S6) are controlled according to a modulation strategy so that, at any given time, for the AC phase (Vmax), for which the voltage is the highest, the top switch is on and the bottom switch is off; for the AC phase (Vmin), for which the voltage is the lowest, the top switch is off and the bottom switch is on; and for the AC phase (Vmin) with the middle voltage value, i.e. the AC phase for which the voltage is neither the highest nor the lowest, the top switch (Sm-T) and the bottom switch (SmB) are modulated at a predefined modulation frequency. Furthermore, a method for controlling active switches (S1-S6) of such a rectifier is disclosed.

Description

[0001] P7251 PC00

[0002] 1

[0003] ULTRA EFFICIENT FRONT-END RECTIFIER

[0004] Field of the disclosure

[0005] The present disclosure relates to a front-end rectifier, in particular to a front-end rectifier, which is configured and controlled to reduce power losses and maintain unity power factor.

[0006] Background of the disclosure

[0007] In modern power electronics, rectifiers are essential components used to convert alternating current (AC) to direct current (DC) in various applications, such as motor drives, power supplies, and renewable energy systems. One of the most common types of rectifiers used in such applications is the three-phase two-level rectifier. This type of rectifier typically utilizes six active switches to convert the three-phase AC input into a stable DC output. While this technology is widely adopted, it is associated with significant power losses, which can negatively impact the efficiency of the entire system.

[0008] While converters in general have a broader range of operations including, for instance, the modification of waveform or frequency and stepping up or down of voltage, the expression “rectifier” is used throughout the present disclosure for describing a converter that deals with AC to DC conversion only.

[0009] Power losses in rectifiers can generally be divided into two main categories: conduction losses and switching losses. Conduction losses occur when the active switches are in the "on" state, while switching losses occur during the transition between "on" and "off" states. In conventional systems, all six switches in a three-phase rectifier are required to switch at every switching period, leading to substantial switching losses. These losses can result in increased heat generation, reduced overall efficiency, and higher operational costs due to the need for enhanced cooling systems.

[0010] Several approaches have been explored to reduce these power losses. For instance, modifications to the inverter topology can reduce the voltage stress in each switching transition and, thereby, the power loss during transition, or the sampling frequency can P7251 PC00

[0011] 2 be decreased. A notable example is the use of a three-level inverter topology, which can reduce the voltage stress across the device by 50%. Other techniques to enhance rectifier efficiency include the use of advanced control methods like space vector pulse width modulation (SVPWM) and employing components made from silicon carbide, which lowers the internal resistance of power devices and consequently reduces conduction losses. However, these solutions still involve the frequent switching of multiple switches, resulting in persistent switching losses.

[0012] It is therefore an objective of the present disclosure to provide a rectifier with a novel configuration and modulation strategy that reduces power losses compared to power conversion applications known in the art, while maintaining unity power factor.

[0013] Summary

[0014] In a first aspect of the present disclosure, it relates to a front-end rectifier configured for converting three-phase AC voltage to DC voltage while maintaining unity power factor, wherein the rectifier is configured as a two-level converter, in which six active switches are arranged so that each of the three AC phases is connected to a positive side and a negative side of a DC-link through a top switch and a bottom switch, respectively. The three top switches and the three bottom switches are controlled or at least configured to be controlled according to a modulation strategy so that, at any given time, for the AC phase with the highest voltage, the top switch is on and the bottom switch is off; for the AC phase with the lowest voltage, the top switch is off and the bottom switch is on; and for the AC phase with the middle voltage value, the top switch and the bottom switch are modulated or at least configured to be modulated at a predefined modulation frequency.

[0015] Preferably, the front-end rectifier further comprises a dedicated controller, which is configured for controlling and modulating the relevant switches of the front-end rectifier according to a desired modulation strategy.

[0016] This configuration significantly reduces switching losses compared to conventional three-phase rectifiers, in which all six switches typically switch at each switching period. By limiting the switching operation to only two switches per cycle, the present system lowers the thermal stress on the components, enhancing the overall system efficiency P7251 PC00

[0017] 3 and extending the lifespan of the switches. The modulation strategy applied allows for optimal control over the switches, ensuring that power conversion remains efficient even when fewer switches are involved in each period. The reduction in switching activity also simplifies cooling requirements, as less heat is generated, potentially allowing for more compact and cost-effective designs.

[0018] The rectifier can operate at varying predefined modulation frequencies, allowing for flexibility in different applications where specific switching frequencies may be required. The design is particularly suitable for high-efficiency power conversion systems, where minimizing switching losses without compromising performance is desirable.

[0019] Additionally, the rectifier’s ability to maintain unity power factor makes it advantageous in applications requiring precise control of power quality, such as renewable energy systems or industrial motor drives. The inventive approach, in which only two switches are switching in each switching period presents a highly efficient alternative to conventional rectifier designs, while maintaining reliable performance across a wide range of operating conditions.

[0020] In one embodiment of the present disclosure, the predefined modulation frequency is between 1 kHz and 1 MHz. A preferred range for the predefined modulation frequency is between 5 kHz and 500 kHz, and a most preferred range is between 5 kHz and 200 kHz. This range allows flexibility in different applications and offers a balance between efficiency and control, as higher frequencies can reduce the size of passive components while still maintaining stable operation, whereas lower frequencies can decrease switching losses.

[0021] In one embodiment of the present disclosure, each of the three AC phases is coupled to the rectifier through an input coil arranged in series between the AC source and the respective top and bottom switches. These input coils help to smooth out the current entering the rectifier, minimizing current ripple and improving power quality. The choice of inductance impacts both the dynamic response and the filtering capability of the system. The optimal values for such input impedances depend on the input voltage, the switching frequency, and the required current ripple. It can be calculated, for instance, by the formulaL = in which Vmis the peak value of an AC phase voltage, fswis the switching frequency, and Almax is the maximum value of the peakpeak current ripple. P7251 PC00

[0022] 4

[0023] In one embodiment of the present disclosure, the duty cycle of the two switches being modulated or at least being configured to be modulated is determined by the output of a controller. The controller is configured to maintain unity power factor by minimizing the difference between a reference current and the current of the AC phase with the middle voltage value. The reference current is proportional to the voltage of the AC phase with the middle voltage value. By controlling the switches in this manner, the system can ensure efficient energy conversion while maintaining high power quality, which is particularly important in applications that demand low harmonic distortion and efficient power usage.

[0024] In one embodiment of the present disclosure, the DC-link capacitance between the positive side and the negative side of the DC-link is configured to be below 100 pF. Preferably, this capacitance is below 20 pF, and most preferred it is below 10 pF. It is a requirement that the DC-link capacitance is small enough not to filter out the ripple in the DC-link current (see Fig. 7), which is required along with a constant power load for obtaining unity power factor with a three-phase input. Further discussion of this subject can be found in “Analysis, Modeling, Design, and Limitations of Current Injection based UPF Rectifier with Small DC-Link Capacitor” (Ramkrishan Maheshwari et al.), Mesago PCIM GmbH, 2024.

[0025] In one embodiment of the present disclosure, the rectifier further comprises a load emulator behaving or at least being configured to behave as a high-frequency load. This load emulator draws current proportional to the high-frequence component of the DC-link voltage and is applied between the positive and negative sides of the DC-link. The inclusion of a load emulator allows the rectifier to simulate various load conditions, enhancing the flexibility and applicability of the system for testing and adaptive control in dynamic environments. In particular, the use of a load emulator as described is one way of mitigating the negative impedance instability problem, which may apply to some rectifier configurations.

[0026] In one embodiment of the present disclosure, the rectifier further includes a diode inserted between the three top switches and the positive side of the DC-link, or alternatively, between the three bottom switches and the negative side of the DC-link. P7251 PC00

[0027] 5

[0028] This diode arrangement ensures that the capacitance between the positive side and the negative side of the DC-link is not short-circuited if both the top switch and the bottom switch of one of the AC phases are on at the same time.

[0029] In one embodiment of the present disclosure, the rectifier further comprises a diode arranged in series with a parallel RC circuit to form a DC clamp connection across the active switches. Additionally, a plurality of primary side switches is arranged and controlled or at least configured to be controlled to convert the DC voltage across the DC clamp connection to an AC voltage. The system also includes a transformer, with the primary side receiving the AC voltage from the primary side switches, and a plurality of secondary side switches configured to convert the output from the secondary side of the transformer to a DC voltage across a DC-link capacitor. This configuration allows for efficient isolation and transformation of the rectified voltage, enabling the system to adapt to different voltage levels and improve the efficiency of power transmission and conversion.

[0030] In one embodiment of the present disclosure, the primary side switches are arranged in a bridge configuration, which results in an input voltage for the transformer having a square waveform. A square waveform provides efficient energy transfer through the transformer, reducing switching losses and ensuring high power density in the system. This configuration is particularly useful in applications where efficiency and compact design are prioritized.

[0031] In one embodiment of the present disclosure, the rectifier further comprises a switch, such as a MOSFET transistor, connected in parallel with the diode. This switch is configured to be turned on when the diode is conducting, allowing for more efficient current conduction and reduced losses during operation. The ability to bypass the diode can significantly reduce conduction losses, which are typically high for a diode, thus improving overall system efficiency.

[0032] In one embodiment of the present disclosure, as part of the modulation strategy, both the top switch and the bottom switch for the AC phase with the middle voltage value may be turned on at the same time, short-circuiting all three AC phases. This feature provides an alternative to the zero vector known in space vector pulse width modulation, which is normally obtained by having all three top switches or all three P7251 PC00

[0033] 6 bottom switches on at the same time. These conventional zero vectors are not used in the modulation strategy of the present disclosure in which, for the two AC phases not being modulated, one top switch and one bottom switch, respectively, are always off.

[0034] In one embodiment of the present disclosure, the primary side switches are controlled or at least configured to be controlled in such a way that they only switch when both the top switch and the bottom switch for the AC phase with the middle voltage value are on simultaneously. This selective switching eliminates any switching losses in the primary side switches. Thus, this control strategy provides a significant advantage in applications requiring high efficiency and low thermal stress on power components.

[0035] In a second aspect of the present disclosure, it relates to a method for controlling active switches of a three-phase front-end rectifier, which is configured as a two-level converter, in which six active switches are arranged so that each of the three AC phases is connected to a positive side and a negative side of a DC-link through a top switch and a bottom switch, respectively. The method comprises, for each switching period, the steps of turning the top switch on and the bottom switch off for the AC phase, for which the voltage is the highest, turning the top switch off and the bottom switch on for the AC phase, for which the voltage is the lowest, and modulating the top switch and the bottom switch for the AC phase with the middle voltage value, i.e. the AC phase for which the voltage is neither the highest nor the lowest, at a predefined modulation frequency.

[0036] In one embodiment of the present disclosure, as a part of the modulation of the top switch and the bottom switch for the AC phase with the middle voltage value, the top switch and the bottom switch may be turned on at the same time.

[0037] In one embodiment of the present disclosure, the rectifier, the active switches of which are being controlled, is a rectifier as described above.

[0038] Brief description of the drawings

[0039] In the following, a few embodiments of the disclosure are described in more detail with reference to the drawings, of which P7251 PC00

[0040] 7

[0041] Fig. 1 is a diagram of a conventional two-level rectifier as known within the art,

[0042] Fig. 2 is a diagram of a two-level rectifier according to a first embodiment of the disclosure,

[0043] Fig. 3 is a diagram of a circuit, which is equivalent to the rectifier shown in Fig. 2 when modulated using a modulation strategy according to an embodiment of the disclosure,

[0044] Fig. 4 illustrates schematically a controller for determining the duty cycle of the switches being modulated,

[0045] Fig. 5 is a graph showing an example of the variation of the voltages and currents of the three AC phases being fed into the rectifier,

[0046] Fig. 6 is a graph showing an example of the variation of a reference current for the controller shown in Fig. 4,

[0047] Fig. 7 is a graph showing an example of the variation of the DC-link voltage and current, respectively, of the rectifier shown in Fig. 1,

[0048] Fig. 8 is a diagram of a two-level rectifier according to a second embodiment of the disclosure,

[0049] Fig. 9 is a diagram of a circuit, which is equivalent to the rectifier shown in Fig. 8 when modulated using a modulation strategy according to an embodiment of the disclosure,

[0050] Fig. 10 is a space vector diagram used for illustrating the principles of space vector pulse width modulation, and

[0051] Fig. 11 is a diagram of a two-level rectifier according to a third embodiment of the disclosure. P7251 PC00

[0052] 8

[0053] Detailed description

[0054] The diagram in Fig. 1 shows a conventional three-phase two-level front-end rectifier configured for converting three-phased AC voltage to DC voltage. The input for the rectifier is three AC phases Ph A, Ph B, Ph C, each of which is connected through an input coil LA, LB, LC to a pair of active switches Si , S2; S3, S4; S5, Se. Each or these pairs comprise a top switch Si , S3, S5, which is connected to the positive side of a Delink, and a bottom switch S2, S4, Se, which is connected to the negative side of the Delink.

[0055] The six active switches Si , S2, S3, S4, S5, Se are modulated, i.e. the individual switch Si , S2, S3, S4, S5, Se is switch on or off at specific times according to well-known modulation strategies, such as sinusoidal or space vector pulse width modulation (PWM), in order to convert the three-phased AC input to a DC voltage across the Delink. According to these modulation strategies, each of the six active switches are typically switched on and off once in each switching period. Typically, the switching frequency is in the kHz range, such as for instance 20 kHz corresponding to a switching period of 50 ps, and every switching transition causes power loss. Therefore, bringing down the number of switching transitions will reduce the power loss of the rectifier.

[0056] A DC-link capacitor CDC is arranged across the DC-link for stabilising the DC-link voltage of the rectifier, which is the difference between the voltage +VDC at the positive side of the DC-link and the voltage -VDC at the negative side of the DC-link. Fig. 1 also indicates how a load is arranged across the DC-link to receive the output from the rectifier.

[0057] The topology of the rectifier according to a first embodiment of the disclosure, the diagram of which is shown in Fig. 2, is very close to the conventional topology shown in Fig. 1. In fact, the only difference, which can be seen in the diagram is that, in the rectifier according to the present disclosure, the DC-link capacitance has been divided into DC-link capacitors CDCI , CDC2, the connection point between which has been grounded. This means that the DC-link voltage of the rectifier is centred about the ground level. It should be noted that such a centre ground configuration is neither necessary for nor restricted to the present disclosure and is also known from P7251 PC00

[0058] 9 conventional rectifiers. Also, the load connected to the rectifier shown in Fig. 2 differs from the load shown in Fig. 1 , as is discussed below.

[0059] The main difference between the two rectifiers of Figs. 1 and 2, respectively, which cannot be seen from the diagram is that in the present disclosure a novel modulation strategy is used for controlling the active switches Si , S2, S3, S4, S5, Se, and that, as a consequence thereof, the DC-link capacitance CDCI , CDC2 must be very small compared to that CDC of the conventional rectifier as described above. A positive side effect of using a very small DC-link capacitance CDCI , CDC2 is that the level of harmonic distortion is reduced. Harmonic currents are mostly generated when filter capacitors are being charged and the level of harmonic currents depends on filter capacitance. Therefore filters (or rectifiers) with low capacitance generate lower levels of harmonics.

[0060] According to this novel modulation strategy, only two SmT, SmB of the six active switches are switched on and off once during each switching period. This, and the fact that it is always the numerically smallest current (the one of the AC phase Vmid with the middle voltage value) being modulated, means that the switching loss of the two modulated active switches SmT, SmB of the rectifier according to the present disclosure corresponds to less than a third of the switching loss of the six active switches Si , S2, S3, S4, S5, Se of the conventional rectifier.

[0061] At any given time, the AC phase Vmax, for which the voltage is the highest, is connected to the positive side of the DC-link by setting the respective top switch on and the respective bottom switch off. Likewise, the AC phase Vmin, for which the voltage is the lowest, is connected to the negative side of the DC-link by setting the respective top switch off and the respective bottom switch on. Thus, only the top switch SmT and the bottom switch SmB for the AC phase Vmid with the middle voltage value, i.e. the AC phase for which the voltage is neither the highest nor the lowest, are modulated.

[0062] This means that the rectifier shown in Fig. 2 is equivalent to the rectifier circuit shown in Fig. 3 when this modulation strategy is applied. In this relation, it should be remembered that it changes six times for each period of the AC input signal, how the AC phase Vmax with the highest voltage, the AC phase Vmin with the lowest voltage, and the AC phase Vmid with the middle voltage value are represented by the three AC phases Ph A, Ph B, Ph C, respectively, cf. the graphs shown in Fig. 5. P7251 PC00

[0063] 10

[0064] The modulation of the two switches SmT, SmB so that unity power factor is achieved is controlled by a controller, which is depicted schematically in Fig. 4. This controller uses a transfer function Gc(z) for continuously adjusting the duty cycle d in such a way that the difference between the current i of the AC phase Vmid with the middle voltage value and a reference current lref. This reference current lref is proportional to the voltage of the AC phase Vmid with the middle voltage value, the proportionality factor being decided by the output power demand.

[0065] Fig. 5 shows schematically the variation of the voltages and currents of the three AC phases Ph A, Ph B, Ph C of a normal 50 Hz three phase AC signal, in which unity power factor is achieved, i.e. for each of the three AC phases Ph A, Ph B, Ph C the voltage and current are in phase with each other. The bold parts of the voltage graph represents the voltage of the AC phase Vmid with the middle voltage value at all times, to which the reference current lref for the controller shown in Fig. 4 is proportional.

[0066] This reference signal lref is shown in the graph in Fig. 6. As described above, the waveshape of the reference signal lref is decided by the middle voltage value as indicated in Fig. 5, whereas the magnitude of the reference signal lref is decided by and proportional to the output power demand.

[0067] A main limitation of the rectifier according to this first embodiment of the disclosure is that the load must be a constant power load CPL as indicated in Fig. 2. The DC-link voltage is decided by the voltage of the three-phase AC input signal, i.e. typically a utility grid voltage, which is defined by factors outside the rectifier circuit and cannot be controlled. An example of the variation of the DC-link voltage and the current of a rectifier circuit according to this embodiment is indicated in Fig. 7.

[0068] This rectifier circuit has the problem of negative impedance instability at high power, which may, for instance, be mitigated by emulating a load that behaves as a high- frequency load, which draws current proportional to the high-frequency component of the DC-link voltage. This solution is indicated in Fig. 2 by the high-frequency resistive load emulator LE applied between the positive side and the negative side of the DC- link of the rectifier. P7251 PC00

[0069] 11

[0070] Thus, the main advantages of rectifiers according to this first embodiment of the disclosure are low total harmonic distortion (THD), low power loss and high reliability, whereas the main disadvantages are the lack of output voltage control, the need for a constant power load and the negative impedance instability problem at high power.

[0071] These disadvantages may be overcome by using a rectifier according to a second embodiment of the present disclosure, a diagram of which is shown in Fig. 8. In this rectifier circuit, a diode DaUx is inserted in series with the DC-link. Optionally, also a switch Saux is arranged parallel to this diode DaUx as is the case in Fig. 8. Thus, if the diode Daux is shorted, this circuit corresponds to a conventional two-level rectifier.

[0072] The purpose of this switch SaUx, which is on when the diode DaUx is conducting and off when the diode DaUx is not conducting, is to reduce power losses, since diode conduction losses are typically relatively high.

[0073] A modulation strategy similar to the one described above for the rectifier according to the first embodiment of the disclosure being applied, the rectifier shown in Fig. 8 is equivalent to the rectifier circuit shown in Fig. 9. Thus, the relationship between the two diagrams shown in Fig. 8 and Fig. 9, respectively, is exactly the same as the relationship between the two diagrams of Fig. 2 and 3, respectively.

[0074] For the conventional two-level rectifier, sinusoidal or space vector pulse width modulation (PWM) can be used. In either case, each of the six active switches Si , S2, S3, S4, S5, Se is switched on and off once for every switching period. At any given point in time, the rectifier is said to apply a switching state depending on the actual status of each of the six active switches Si, S2, S3, S4, S5, Se.

[0075] The switching state describes which of the top switches Si , S3, S5 and the bottom switches S2, S4, Se relating to the three AC phases Ph A, Ph B, Ph C, respectively, are on. If a top switch Si , S3, S5 is on, it is denoted by +, and if a bottom switch S2, S4, Se is on, it is denoted by -. The top Si , S3, S5 and bottom S2, S4, Se switches relating to the same AC phase Ph A, Ph B, Ph C cannot be turned on at the same time. As an example, the switching state ++- denotes that the top switches Si , S3 for the first two AC phases Ph A, Ph B and the bottom switch Se for the third AC phase Ph C are on. P7251 PC00

[0076] 12

[0077] A pulse width modulation strategy is characterised by a switching sequence, which is a series of consecutive switching states within a switching period, such as for instance

[0078] — — > +— — > ++- — > +++ — > ++- — > +— — > —

[0079] In two of the switching states (— and +++), which are also known as zero vectors Vo, all three AC phases Ph A, Ph B, Ph C are connected to the negative side or the positive side of the DC-link, respectively, which means that they are shorted. The other six positive switching states Vi (+--), V2 (++-), V3 (-+-), V4 (-++), 5 (--+), Ve (+-+) are known as active vectors.

[0080] Fig. 10 shows a diagram with the space vectors Vo-Ve corresponding to eight possible switching states the that can be generated by a two-level rectifier, remembering that the zero vector VO corresponds to two switching states (— and +++). This diagram can be used for discussing the well-known concept of space vector PWM.

[0081] The reference vector Vref revolves in the counter-clockwise direction around the centre of the diagram with an angular velocity co so that a full round is completed within one period of the three-phase AC input signal. The purpose of the modulation strategy is continuously to generate a voltage vector corresponding to the revolving reference vector Vref. This is done by combining the zero vector Vo and the two active vectors between which the reference vector Vref is situated in the given switching period. Thus, for the reference vector Vref shown in Fig. 10, the desired voltage vector is generated by combining the space vectors Vo, Vi and V2.

[0082] It is noticed that, within any of the six areas l-VI of the diagram in Fig. 10, only one phase has to shift for switching between the two active vectors defining the area. Thus, for area I, in which the reference vector Vref is situated in Fig. 10, switching between the active vectors Vi and V2 only requires that the second AC phase Ph B shifts between + and -.

[0083] This means that, no matter in which area of the diagram in Fig. 10 the reference vector Vref is situated, the switching between the two relevant active vectors can be obtained by the modulation strategy of the present disclosure, in which only the two active switches SmT, SmB corresponding to one of the three AC phases Ph A, Ph B, Ph C switch within a given switching period. However, because there is always at least one + P7251 PC00

[0084] 13 and at least one - in each of the switching states, which can be obtained by the rectifier using the modulation strategy of the present disclosure, none of the conventional zero vectors vo (— or +++) can be obtained.

[0085] As mentioned above, this means for the rectifier according to the first embodiment described above that the DC-link voltage cannot be controlled which, in turn, leads to the disadvantages of this embodiment likewise mentioned above.

[0086] In the rectifier according to the second embodiment as illustrated in Fig. 8 and 9, however, an alternative zero vector can be obtained by letting both of the regulated switches SmT, SmB be on at the same time. In that case, four of the six active switches Si , S2, S3, S4, S5, Se are on at the same time, and all three AC phases Ph A, Ph B, Ph C are shorted. This is why the diode DaUx is needed in order to avoid a shortcircuiting of the DC-link capacitor CDC. Thus, when an active vector Vi-Ve is applied, the diode Daux and, if present, the switch SaUx parallel to it are turned on, and when the alternative zero vector is applied by turning both switches SmT, SmB relating to the AC phase VmidWith the middle voltage value on, the diode DaUx and, if present, the switch Saux parallel to it are turned off.

[0087] Thus, by applying an suitable PWM algorithm to the rectifier according to this second embodiment of the present disclosure, the same advantages can be obtained as with conventional sinusoidal or space vector modulation. However, the switching losses of the active switches Si, S2, S3, S4, S5, Se are reduced, because only two out of the six switches Si , S2, S3, S4, S5, Se switch within any given switching period.

[0088] Fig. 11 is a diagram a rectifier according to a third embodiment of the present disclosure. This embodiment is an isolated version of the rectifier shown in Figs. 8 and 9. In this rectifier, the DC-link with the DC-link capacitor CDC is galvanically isolated from the active switches Si-Se by a transformer Tr with coupled in series, on its primary side, with a leaking inductance . This embodiment is bidirectional, which means that it can also be used for producing a three-phase AC signal (Ph A, Ph B, Ph C) from a DC signal which may, for instance, provided by a battery connected in place of the load Ld shown in Fig. 11. P7251 PC00

[0089] 14

[0090] In this rectifier circuit, a diode DCiamPand a switch Sciamp are arranged in series with a parallel RC circuit RCiamP, CCiamPto form a DC clamp connection across the active switches Si-Se. At the transition from the zero vector Vo to an active vector i- e, current needs to shift to the leakage inductance Lik.

[0091] Any instantaneous change in the inductor current needs a large voltage. To avoid this, an active or passive clamped circuit like the one shown in Fig. 11 can be used to take care of the problems associated with the current change in the leakage inductor Lik.

[0092] Four primary side switches Sip, S2P, S3P, S4Pare arranged and controlled to convert the DC voltage across the DC clamp connection to an AC voltage to be fed to the primary side of the transformer Tr. The primary side switches Sip, S2P, S3P, S4Pare arranged in a bridge configuration and are controlled in such a way that Sipand S4Pare on half or the time, and S2Pand Ssp are on when Sipand S4Pare off. Thus, the output from this bridge configuration and, thereby, the input voltage for the transformer (Tr) has a square waveform.

[0093] Four secondary side switches Sis, S2s, Sss, S4s are arranged and controlled to convert the output from the secondary side of the transformer Tr to the DC-link voltage across the DC-link capacitor CDC.

[0094] Preferably, the primary side switches Sip, S2P, S3P, S4Pare controlled in such a way that they only switch when both the top switch SmT and the bottom switch SmB for the AC phase mid with the middle voltage value is on at the same time. In that case, there is no voltage across the primary side switches Sip, S2P, S3P, S4Pwhen they switch and, thus, the switching results in no switching loss for these four switches Sip, S2P, S3P, S4P.

[0095] P7251 PC00

[0096] 15

[0097] List of reference

[0098] Cdamp Clamp capacitor, isolated rectifier

[0099] CDC DC-link capacitor

[0100] CDCI DC-link capacitor, positive side

[0101] CDC2 DC-link capacitor, negative side

[0102] CPL Constant power load d Duty cycle

[0103] Daux Diode, non-isolated rectifier

[0104] Ddamp Diode, isolated rectifier

[0105] Gc(z) T ransfer function for controller k Current of the AC phase with middle voltage value

[0106] Iref Reference current for controller labc Current variation for three phases of AC input signal LA Input coil for first phase of AC input signal

[0107] LB Input coil for second phase of AC input signal

[0108] Lc Input coil for third phase of AC input signal

[0109] Lmax Input coil for AC phase with highest voltage

[0110] Lmid Input coil for AC phase with middle voltage value

[0111] Lmin Input coil for AC phase with lowest voltage

[0112] Ld Load

[0113] Lik Leaking inductance

[0114] LE High-frequency resistive load emulator

[0115] Ph A First phase of AC input signal

[0116] Ph B Second phase of AC input signal

[0117] Ph C Third phase of AC input signal

[0118] Rciamp Clamp resistor, isolated rectifier

[0119] 51 Top switch for first phase of AC input signal

[0120] SipFirst primary side switch

[0121] Sis First secondary side switch

[0122] 52 Bottom switch for first phase of AC input signal

[0123] S2PSecond primary side switch

[0124] S2s Second secondary side switch

[0125] 53 Top switch for second phase of AC input signal

[0126] Sap Third primary side switch P7251 PC00

[0127] 16

[0128] Sss Third secondary side switch

[0129] 54 Bottom switch for second phase of AC input signal

[0130] S4PFourth primary side switch

[0131] S4s Fourth secondary side switch

[0132] 55 T op switch for third phase of AC input signal

[0133] Se Bottom switch for third phase of AC input signal

[0134] Saux Switch parallel to diode, non-isolated rectifier

[0135] Sciamp Switch parallel to diode, isolated rectifier

[0136] SmT Top switch for AC phase with middle voltage value

[0137] SmB Bottom switch for AC phase with middle voltage value

[0138] Tr Transformer

[0139] Vo Zero vector, space vector pulse width modulation

[0140] Vi-Vo Active vectors, space vector pulse width modulation

[0141] + dc Voltage at positive side of DC-link

[0142] -Vdc Voltage at negative side of DC-link

[0143] Vmax AC phase with highest voltage

[0144] Vmid AC phase with middle voltage value

[0145] Vmin AC phase with lowest voltage

[0146] Vref Reference vector, space vector pulse width modulation

[0147] Vabc Voltage variation for three phases of AC input signal cot Angular position of revolving reference vector

Claims

P7251 PC0017Claims1 . A front-end rectifier configured for converting three-phased AC voltage to DC voltage while maintaining unity power factor, wherein the rectifier is configured as a two-level converter, in which six active switches (Si-Se) are arranged so that each of the three AC phases (Ph A, Ph B, Ph C) is connected to a positive side and a negative side of a DC-link through a top switch (Si , S3, S5) and a bottom switch (S2, S4, Se), respectively, and wherein the three top switches (Si, S3, S5) and the three bottom switches (S2, S4, Se) are controlled according to a modulation strategy so that, at any given time, for the AC phase (Vmax), for which the voltage is the highest, the top switch is on and the bottom switch is off; for the AC phase (Vmin), for which the voltage is the lowest, the top switch is off and the bottom switch is on; and for the AC phase (Vmid) with the middle voltage value, i.e. the AC phase for which the voltage is neither the highest nor the lowest, the top switch (Sm-r) and the bottom switch (Sms) are modulated at a predefined modulation frequency.

2. The front-end rectifier according to claim 1 , further comprising a dedicated controller, which is configured for controlling and modulating the relevant switches of the front-end rectifier according to a desired modulation strategy.

3. The front-end rectifier according to claim 1 or 2, wherein the predefined modulation frequency is between 1 kHz and 1MHz, preferably between 5 kHz and 500 kHz, most preferred between 5 kHz and 200 kHz.P7251 PC00184. The front-end rectifier according to any of the preceding claims, wherein each of the three AC phases (Ph A, Ph B, Ph C) is coupled to the rectifier through an input coil (LA, LB, LC) arranged in series between the AC source and the respective top (Si , S3, S5) and bottom (S2, S4, Se) switches.

5. The front-end rectifier according to any of the preceding claims, wherein the duty cycle of the two switches (SmT, Sms) being modulated is decided by the output of a controller, which is configured to maintain unity power factor (UPF) by minimising the difference between a reference current (lref) and the current (k) of the AC phase with the middle voltage value, the reference current being proportional to the voltage of the AC phase (Vmid) with the middle voltage value.

6. The front-end rectifier according to any of the preceding claims, wherein a Delink capacitance (CDC) between the positive side and the negative side of the DC-link is below 100 pF, preferably below 20 pF, most preferred below 10 pF.

7. The front-end rectifier according to claim 6, further comprising a load emulator (LE) behaving as a high-frequency load, which draws current proportional to the high-frequency component of the DC-link voltage and is applied between the positive side and the negative side of the DC-link.

8. The front-end rectifier according to any of claims 1-5, further comprising a diode (Daux) inserted between the three top switches (Si , S3, S5) on the one side and the positive side of the DC-link on the other side or, alternatively, between the three bottom (S2, S4, Se) switches on the one side and the negative side of the DC-link on the other side.

9. The front-end rectifier according to any of claims 1-5, further comprising a diode (DCiamP) arranged in series with a parallel RC circuit (Rciamp, Cciamp) to form a DC clamp connection across the active switches (Si-Se),P7251 PC0019 a plurality of primary side switches (Sip, S2P, SsP, S4P) arranged and controlled to convert the DC voltage across the DC clamp connection to an AC voltage, a transformer (Tr), the primary side of which receives the AC voltage from the primary side switches (Sip, S2P, S3P, S4P), and a plurality of secondary side switches (Sis, S2s, Sss, S4s) arranged and controlled to convert an output from the secondary side of the transformer (Tr) to a DC voltage across a DC-link capacitor (CDC).

10. The front-end rectifier according to claim 9, wherein the primary side switches (Sip, S2P, S3P, S4P) are arranged in a bridge configuration resulting in an input voltage for the transformer (Tr) having a square waveform.11 . The front-end rectifier according to any of claims 8-10, further comprising a switch (Saux; SCiamP), such as a MOSFET transistor, which is connected in parallel with the diode (DaUx; DCiamP) and configured to be turned on when the diode (Daux; DCiamP) is conducting.

12. The front-end rectifier according to any of claims 8-11 , wherein, as part of the modulation strategy, both the top switch (Sm-r) and the bottom switch (Sms) for the AC phase (Vmid) with the middle voltage value may be on at the same time, in which case all three AC phases (Ph A, Ph B, Ph C) are shorted.

13. The front-end rectifier according to claims 9 and 12, wherein the primary side switches (Sip, S2P, S3P, S4P) are controlled in such a way that they only switch when both the top switch (Sm-r) and the bottom switch (Sms) for the AC phase (Vmid) with the middle voltage value are on at the same time.

14. A method for controlling active switches (Si-Se) of a three-phase front-end rectifier, which is configured as a two-level converter, in which six active switches (Si-Se) are arranged so that each of the three AC phases (Ph A, Ph B, Ph C) is connected to a positive side and a negative side of a DC-linkP7251 PC0020 through a top switch (Si , S3, S5) and a bottom switch (S2, S4, Se), respectively, which method comprises, for each switching period, the steps of turning the top switch on and the bottom switch off for the AC phase (Vmax), for which the voltage is the highest, turning the top switch off and the bottom switch on for the AC phase (Vmin), for which the voltage is the lowest, and modulating the top switch (Sm-r) and the bottom switch (Sms) for the AC phase (Vmid) with the middle voltage value, i.e. the AC phase for which the voltage is neither the highest nor the lowest, at a predefined modulation frequency.

15. The method according to claim 14, wherein as a part of the modulation of the top switch (Sm-r) and the bottom switch (Sms) for the AC phase (Vmid) with the middle voltage value, the top switch (Sm-r) and the bottom switch (Sms) may be turned on at the same time.

16. The method according to claim 14 or 15, wherein the rectifier, the active switches (Si-Se) of which are being controlled, is a rectifier according to any of claims 1-13.

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