Semiconductor device and method for producing semiconductor device

Abstract

Provided is a highly reliable semiconductor device. The present invention has a semiconductor layer, a first conductive layer and a second conductive layer that are on the semiconductor layer and that are isolated from each other, an insulation layer that is located between the first conductive layer and the second conductive layer, and a third conductive layer that is on the insulation layer, wherein: the semiconductor layer has indium and oxygen; the semiconductor layer has a first region in contact with the first conductive layer, a second region in contact with the second conductive layer, and a third region located between the first region and the second region; the third region has boron; and the boron content in the third region is higher than each of the boron content in the first region and the boron content in the second region.

Description

Semiconductor device and method for manufacturing a semiconductor device.

[0001] One aspect of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them. A semiconductor device refers to any device that can function by utilizing semiconductor properties.

[0003] In recent years, the development of semiconductor devices has progressed, and these devices are mainly used in LSIs (Large Scale Integration), CPUs (Central Processing Units), and memory. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and capacitors) formed on chips by processing semiconductor wafers, and electrodes that serve as connection terminals are formed on them.

[0004] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memory are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0005] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0006] Transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that utilizes the characteristic of low leakage current of transistors using oxide semiconductors. Patent Document 2 also discloses a memory device that uses oxide semiconductors and can retain stored data for a long period of time.

[0007] Furthermore, Non-Patent Document 1 reports on a polycrystalline indium oxide film exhibiting high hole mobility and a transistor using it. Also, Non-Patent Document 2 reports on In ２ O ３ Its use in thin-film transistors has been reported.

[0008] Japanese Patent Publication No. 2012-257187 Japanese Patent Publication No. 2011-151383

[0009] Y. Magari et al. , “High-mobility hydrogenated polycrystalline In▲2▼O▲3▼(In▲2▼O▲3▼:H) thin-film transistors”, Nature Communications 13, 1078, (2022). Dhananjay and C. W. Chu “Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process”Appl. Phys. Lett. 91, 132111 (2007). Takashi Koida, "High-Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology (AIST), AIST Photovoltaic Power Generation Research Results Presentation 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] One aspect of the present invention aims to provide a transistor with good electrical characteristics. One aspect of the present invention aims to provide a transistor with a large on-current. One aspect of the present invention aims to provide a transistor with low parasitic capacitance. One aspect of the present invention aims to provide a highly reliable transistor, semiconductor device, or memory device. One aspect of the present invention aims to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated. One aspect of the present invention aims to provide a semiconductor device or memory device with low power consumption. One aspect of the present invention aims to provide a memory device with a fast operating speed.

[0011] One aspect of the present invention aims to provide a semiconductor device having a novel configuration. Another aspect of the present invention aims to mitigate at least one of the problems of the prior art.

[0012] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc.

[0013] One aspect of the present invention is a semiconductor device comprising a semiconductor layer, a first conductive layer and a second conductive layer located on the semiconductor layer and separated from each other, an insulating layer located between the first conductive layer and the second conductive layer, and a third conductive layer on the insulating layer, wherein the semiconductor layer comprises indium and oxygen, and the semiconductor layer comprises a first region in contact with the first conductive layer, a second region in contact with the second conductive layer, and a third region located between the first and second regions, the third region comprising boron, and the boron content in the third region being higher than the boron content in the first region and the boron content in the second region, respectively.

[0014] In the above-described semiconductor device, the thickness of the semiconductor layer is preferably 1 nm or more and 6 nm or less.

[0015] In the semiconductor device described above, the shortest distance between the first conductive layer and the second conductive layer is preferably 1 nm or more and 15 nm or less.

[0016] One aspect of the present invention is a method for manufacturing a semiconductor device, comprising: a first step of forming a semiconductor film; a second step of forming a conductive film on the semiconductor film; a third step of processing the semiconductor film and the conductive film into island shapes to form a semiconductor layer and a first conductive layer; a fourth step of processing the first conductive layer to expose the upper surface of a part of the semiconductor layer and to form a second conductive layer and a third conductive layer; a fifth step of supplying boron to a region of the semiconductor layer that does not overlap with the second conductive layer and the third conductive layer; a sixth step of forming an insulating layer on the semiconductor layer; and a seventh step of forming a fourth conductive layer on the insulating layer.

[0017] In the above-described method for manufacturing a semiconductor device, it is preferable to use plasma ion doping or ion implantation in the fifth step.

[0018] In the above-described method for manufacturing a semiconductor device, in the first step, it is preferable to use an atomic layer deposition method, and in the atomic layer deposition method, it is preferable to use a precursor containing indium and an oxidizing agent.

[0019] In the above-described method for manufacturing a semiconductor device, in the first step, it is preferable to use a sputtering method, and in the sputtering method, it is preferable to use a sputtering target containing indium and a gas containing hydrogen as the sputtering gas.

[0020] In the above-described method for manufacturing a semiconductor device, it is preferable to perform a heat treatment before carrying out the fifth step, and to perform the heat treatment at a temperature of 300°C to 700°C.

[0021] According to one aspect of the present invention, a transistor with good electrical characteristics can be provided. According to one aspect of the present invention, a transistor with a large on-current can be provided. According to one aspect of the present invention, a transistor with low parasitic capacitance can be provided. According to one aspect of the present invention, a highly reliable transistor, semiconductor device, or memory device can be provided. According to one aspect of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one aspect of the present invention, a semiconductor device or memory device with low power consumption can be provided. According to one aspect of the present invention, a memory device with a fast operating speed can be provided.

[0022] According to one aspect of the present invention, a semiconductor device having a novel configuration can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be mitigated.

[0023] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc.

[0024] Figures 1A and 1B show examples of semiconductor device configurations. Figures 1C, 1D, 1E, and 1F show band diagrams. Figure 2A shows an example of semiconductor device configuration. Figures 2B and 2C show band diagrams. Figures 3A, 3B, 3C, and 3D show examples of semiconductor device configurations. Figure 4 shows an example of semiconductor device configuration. Figures 5A and 5B are schematic diagrams of tunnel current. Figure 6 shows an example of semiconductor device configuration. Figures 7A and 7B show examples of semiconductor device configurations. Figure 8 shows an example of semiconductor device configuration. Figures 9A, 9B, and 9C show examples of semiconductor device configurations. Figures 10A, 10B, 10C, and 10D show examples of semiconductor device configurations. Figures 11A, 11B, 11C, and 11D show examples of semiconductor device configurations. Figures 12A and 12B show examples of semiconductor device configurations. Figures 13A and 13B show examples of semiconductor device configurations. Figures 14A and 14B show examples of semiconductor device configurations. Figures 15A, 15B, and 15C show examples of semiconductor device configurations. Figures 16A1, 16A2, 16B1, 16B2, 16C1, 16C2, 16D1, and 16D2 illustrate methods for manufacturing semiconductor devices. Figure 17 illustrates methods for manufacturing semiconductor devices. Figures 18A1, 18A2, 18B1, 18B2, 18C1, and 18C2 illustrate methods for manufacturing semiconductor devices. Figures 19A and 19B illustrate the carrier concentration dependence of Hall mobility. Figure 19C is a cross-sectional view illustrating an indium oxide film. Figure 20 shows an example of a memory device configuration. Figures 21A and 21B show examples of memory device configurations. Figures 22A, 22B, 22C, and 22D show examples of memory device configurations. Figure 23 shows an example of a memory device configuration. Figures 24A and 24B show an example of a display device configuration. Figure 25 shows an example of a display device configuration. Figures 26A, 26B, 26C, and 26D show an example of an electronic device configuration. Figures 27A, 27B, 27C, 27D, 27E, and 27F show an example of an electronic device configuration. Figures 28A, 28B, 28C, 28D, 28E, 28F, and 28G show an example of an electronic device configuration. Figures 29A and 29B show an example of an electronic component configuration. Figures 30A, 30B, and 30C show an example of a mainframe computer configuration.Figures 31A and 31B are perspective views of a semiconductor device. Figure 32 is a perspective view of a semiconductor device.

[0025] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0026] In the configuration of the invention described below, the same reference numerals are used in common across different drawings for parts that are the same or have similar functions, and repeated explanations are omitted. Also, when referring to similar functions, the hatching patterns are the same, and reference numerals may not be assigned.

[0027] In the figures described herein, the size of each component, the thickness of the layers, or the area may be exaggerated for clarity. Therefore, the scale is not necessarily limited to those figures.

[0028] Furthermore, ordinal numbers such as "the first," "the second," etc., used in this specification are added to avoid confusion of constituent elements and do not imply any numerical limitation.

[0029] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0030] Furthermore, the functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0031] Furthermore, in this specification, "electrically connected" includes cases where a connection is made via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0032] In this specification, cases where two nodes are connected via an insulator, such as the dielectric of a capacitive element, the gate insulating film of a transistor, or an interlayer insulating film, are not included in the definition of "electrical connection."

[0033] In this specification, "heights match" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as the substrate surface) are equal in a cross-sectional view. For example, if there are two layers with different heights (here referred to as layer A and layer B) with respect to the reference surface, the heights also match if the difference between the height of the top surface of layer A and the height of the top surface of layer B is 10 nm or less.

[0034] In this specification, "side edges coincide" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. For example, in the case of two stacked layers (here referred to as layer A and layer B), if the shortest distance from the side edge of layer A to the side edge of layer B in a plan view is 10 nm or less, then the side edges also coincide.

[0035] In general, it can be difficult to clearly distinguish between "exact match" and "approximate match." Therefore, in this specification, "match" may include both exact matches and approximate matches.

[0036] In this specification, the top surface shape of a component refers to the contour shape of that component in a plan view. A plan view refers to a view from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0037] In the following, expressions indicating direction, such as "up" and "down," will generally be used in accordance with the orientation shown in the drawings. However, for the purpose of simplifying explanations, the direction referred to as "up" or "down" in the specification may not always coincide with that of the drawings. For example, when explaining the stacking order (or formation order) of a laminate, even if the side on which the laminate is provided (the surface to be formed, the support surface, the adhesive surface, the flat surface, etc.) is located above the laminate in the drawing, the surface to be formed may be described as "down" and the laminate side as "up."

[0038] Furthermore, in this specification, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0039] Furthermore, unless otherwise specified in this specification, off-current refers to the drain current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage Vgs between the gate and source is lower than the threshold voltage Vth (in a p-channel transistor, it is higher than Vth).

[0040] In this specification, space groups are expressed using international notation (or Hermann-Mauguin notation) in short notation. Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by superscripting numbers, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a superscript. Individual orientations within a crystal are represented by [ ], collective orientations representing all equivalent orientations are represented by < >, individual crystal planes are represented by ( ), and collective planes with equivalent symmetry are represented by {}.

[0041] In this specification and the like, the content rate of a certain metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if the metal oxide contains metal element X, metal element Y, and metal element Z, and the number of atoms of metal element X, metal element Y, and metal element Z contained in the metal oxide are A Ｘ , A Ｙ , A Ｚ respectively, the content rate of metal element X can be expressed as A Ｘ / (A Ｘ + A Ｙ + A Ｚ ). Further, when the ratio of the number of atoms (atom ratio) of metal element X, metal element Y, and metal element Z in the metal oxide is B Ｘ : B Ｙ : B Ｚ , the content rate of metal element X can be expressed as B Ｘ / (B Ｘ + B Ｙ + B Ｚ ). In this specification and the like, boron, silicon, and arsenic contained in indium oxide are treated as semi-metal elements, and the "metal element" described in this specification and the like includes semi-metal elements.

[0042] (Embodiment 1) In this embodiment, a semiconductor device according to an aspect of the present invention and a method for manufacturing the same will be described. A semiconductor device according to an aspect of the present invention includes a transistor.

[0043] [Configuration example of semiconductor device] FIG. 1A is a schematic cross-sectional view of a transistor. FIG. 1B is a schematic cross-sectional view of a transistor different from FIG. 1A. As shown in FIGS. 1A and 1B, a transistor according to an aspect of the present invention has a semiconductor layer 30, an oxide layer 31, an insulating layer 50, and a conductive layer 60. The oxide layer 31 is located between the semiconductor layer 30 and the insulating layer 50, and the conductive layer 60 has a region overlapping the semiconductor layer 30 with the oxide layer 31 and the insulating layer 50 interposed therebetween.

[0044] Figure 1A shows a configuration in which the conductive layer 60 is provided above the semiconductor layer 30, and Figure 1B shows a configuration in which the conductive layer 60 is provided below the semiconductor layer 30. In Figures 1A and 1B, the semiconductor layer 30, oxide layer 31, insulating layer 50, and conductive layer 60 are stacked perpendicular to the substrate surface (not shown). However, the present invention is not limited to these configurations. For example, the semiconductor layer 30, oxide layer 31, insulating layer 50, and conductive layer 60 can also be stacked parallel to the substrate surface (not shown).

[0045] In a transistor according to one aspect of the present invention, the conductive layer 60 functions as a gate electrode, and the insulating layer 50 functions as a gate insulating layer. The semiconductor layer 30 also has a channel formation region. At least a portion of the region of the semiconductor layer 30 that overlaps with the conductive layer 60 via the insulating layer 50 functions as a channel formation region.

[0046] A transistor according to one aspect of the present invention has a semiconductor layer 30 including a channel-forming region, which contains a metal oxide (also called an oxide semiconductor) that functions as a semiconductor. In other words, this transistor can be called an OS transistor. In this specification, a semiconductor layer having an oxide semiconductor can be referred to as an oxide semiconductor layer.

[0047] For the semiconductor layer 30, it is preferable to use an indium-containing oxide, and particularly preferable to use indium oxide. The band gap of the indium-containing oxide is 2.0 eV or more, or 2.5 eV or more. By using a metal oxide with a larger band gap than silicon for the semiconductor layer 30, the off-current of the transistor can be reduced. Because the off-current of the OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. In addition, because the frequency characteristics of the OS transistor are high, the semiconductor device can be operated at high speed.

[0048] For information on indium oxide that can be used as the semiconductor layer 30, please refer to the description in Embodiment 3. A detailed explanation is omitted here.

[0049] When the semiconductor layer 30 and the insulating layer 50 are in contact, defects such as point defects and adsorbed atoms may form near the interface between the semiconductor layer 30 and the insulating layer 50. Since the area near the interface between the semiconductor layer 30 and the insulating layer 50 includes the surface of the semiconductor layer 30 on the insulating layer 50 side, these defects can also be called surface defects. Because carriers tend to flow near the surface of the semiconductor layer 30 on the insulating layer 50 side, there is a concern that carrier conduction may be suppressed due to scattering caused by surface defects (also called surface scattering).

[0050] In one aspect of the present invention, an oxide layer 31 is provided between a semiconductor layer 30 and an insulating layer 50. The oxide layer 31 is a mixed layer formed at the interface between the semiconductor layer 30 and the insulating layer 50. That is, the oxide layer 31 contains the elements that constitute the semiconductor layer 30 and the elements that constitute the insulating layer 50. For example, if the semiconductor layer 30 contains indium and oxygen, and the insulating layer 50 contains a metal element and oxygen, then the oxide layer 31 contains indium, the said metal element, and oxygen. The mixed layer can also be described as a region where the semiconductor layer 30 and the insulating layer 50 are alloyed. Hereafter, the metal element contained in the insulating layer 50 may be referred to as the first element.

[0051] The first element is preferably an element that can take the same valency as the metallic element present in the semiconductor layer 30. For example, if the semiconductor layer 30 contains indium, the first element is preferably an element that can become a trivalent cation. Examples of the first element include aluminum, gallium, yttrium, erbium, gadolinium, ytterbium, samarium, and neodymium. Because the oxide layer 31 contains the first element, carriers are not generated even if the first element is substituted for indium, thus suppressing the n-type transformation of the oxide layer 31 or the semiconductor layer 30 near the oxide layer 31.

[0052] Aluminum and gallium have electronegativity close to that of indium. Therefore, oxides containing indium and at least one of aluminum and gallium have a nearly uniform electron distribution in each oxygen atom, resulting in a homogeneous structure. This is preferable because it makes it less prone to defects. It is also preferable because it makes it less prone to defects even when structural disorder occurs in the oxide layer 31 containing the oxide (for example, when it has an amorphous structure). Furthermore, it is particularly preferable to use aluminum as the first element. When aluminum is used as the first element, oxygen can be captured in the film. For example, excess oxygen (also called exO) that may be present in the semiconductor layer 30 can be captured (gettered) by the aluminum in the insulating layer 50.

[0053] Yttrium, erbium, gadolinium, ytterbium, samarium, and neodymium are preferred because their oxides have the same cubic crystal structure as indium oxide, thus suppressing the formation of surface defects at the interface between the oxide layer 31 containing the oxide and the semiconductor layer 30 containing indium oxide. In particular, yttrium, erbium, gadolinium, and ytterbium are more preferred because the bond length between the metal atom and the oxygen atom is close to the bond length between the indium atom and the oxygen atom, resulting in a small degree of lattice mismatch.

[0054] Furthermore, rare earth elements such as yttrium, erbium, gadolinium, ytterbium, samarium, and neodymium readily form hydrides. Therefore, if the insulating layer 50 containing rare earth elements has a polycrystalline, microcrystalline, or amorphous structure, the rare earth elements with dangling bonds may combine with hydrogen, causing hydrogen in the semiconductor layer 30 to be captured or fixed to the insulating layer 50. Consequently, the hydrogen concentration in the semiconductor layer 30 can be reduced, thereby improving the reliability of the transistor.

[0055] Based on the above, it is preferable that the first element is at least one selected from aluminum, gallium, yttrium, erbium, gadolinium, and ytterbium. By forming an oxide layer 31 which is a mixed layer of semiconductor layer 30 and insulating layer 50, surface defects occurring at the interface between semiconductor layer 30 and oxide layer 31, and at the interface between oxide layer 31 and insulating layer 50 can be reduced. In addition, a carrier path is formed near the interface between semiconductor layer 30 and oxide layer 31. As a result, the effects of surface scattering can be reduced, and on-current can be increased or reliability can be improved. Therefore, a transistor with a large on-current can be provided. Furthermore, a highly reliable transistor or semiconductor device can be provided.

[0056] The oxide layer 31 preferably has a region with a film thickness of 0.1 nm or more and 2 nm or less, more preferably has a region with a film thickness of 0.1 nm or more and 1 nm or less, and even more preferably has a region with a film thickness of 0.2 nm or more and 1 nm or less. By setting the film thickness of the oxide layer 31 within the above range, miniaturization of the semiconductor device can be achieved.

[0057] The content of the first element in the oxide layer 31 is preferably 1 atomic% to 50 atomic%, more preferably 1 atomic% to 30 atomic%, and even more preferably 1 atomic% to 20 atomic%. By setting the content of the first element in the oxide layer 31 within the above range, the oxide layer 31 can function as a semiconductor layer. This allows the channel to be moved away from the interface of the gate insulating layer, thereby increasing the field-effect mobility.

[0058] Furthermore, the oxide layer 31 has a concentration gradient in which the concentration of the first element decreases from the lower surface of the insulating layer 50 toward the upper surface of the semiconductor layer 30. In other words, the oxide layer 31 has a concentration gradient in the film thickness direction in which the concentration of the first element decreases toward the semiconductor layer 30.

[0059] The oxide layer 31 can be confirmed, for example, by cross-sectional TEM images, cross-sectional scanning transmission electron microscope (STEM) images, etc. Furthermore, the oxide layer 31 may be confirmed at and around the interface between the semiconductor layer 30 and the insulating layer 50 by using secondary ion mass spectrometry (SIMS), or by performing line analysis of the composition using energy-dispersive X-ray spectroscopy (EDX).

[0060] Here, a band diagram of a transistor according to one aspect of the present invention is shown in Figures 1C and 1E. As a comparative example, a band diagram of a transistor without the oxide layer 31 is shown in Figures 1D and 1F. In Figures 1C to 1F, the vertical axis represents energy, and the horizontal axis represents the concepts of the semiconductor layer 30, oxide layer 31, and insulating layer 50 near the channel formation region. Figures 1C and 1D show the energy at the upper end of the valence band (denoted as Ev) and the energy at the lower end of the conduction band (denoted as Ec) of the semiconductor layer 30 and oxide layer 31, respectively, when no voltage is applied between the gate and source. Figures 1E and 1F show the Ev and Ec of the semiconductor layer 30 and oxide layer 31, respectively, when a positive voltage is applied between the gate and source. Note that the band diagrams shown in Figures 1C to 1F assume an n-channel type transistor. Furthermore, Ev and Ec vary depending on the constituent elements and their compositions of the semiconductor layer 30 and oxide layer 31, respectively. Therefore, we will mainly explain the relative levels of Ec.

[0061] When indium oxide is used as the semiconductor layer 30 and aluminum oxide is used as the insulating layer 50, the band gap of the insulating layer 50 is larger than the band gap of the semiconductor layer 30. Also, since the oxide layer 31 contains indium and aluminum, the band gap of the oxide layer 31 is larger than the band gap of the semiconductor layer 30 and smaller than the band gap of the insulating layer 50. For example, the lower end of the conduction band of the oxide layer 31 is located between the lower end of the conduction band of the semiconductor layer 30 and the lower end of the conduction band of the insulating layer 50. In other words, the electron affinity of the oxide layer 31 is smaller than the electron affinity of the semiconductor layer 30 and larger than the electron affinity of the insulating layer 50. Furthermore, if the oxide layer 31 has the concentration gradient described above, the lower end of the conduction band may change continuously, as shown in Figure 1C. Specifically, there may be a gradient in which the electron affinity of the oxide layer 31 increases from the lower surface of the insulating layer 50 toward the upper surface of the semiconductor layer 30.

[0062] When a positive voltage is applied between the gate and source, as shown in Figure 1F, the lower end of the conduction band near the insulating layer 50 of the semiconductor layer 30 decreases, and electrons, which are carriers, accumulate on the insulating layer 50 side of the semiconductor layer 30. In transistors without an oxide layer 31, there is a concern that carrier conduction will be suppressed due to the effects of surface scattering. On the other hand, in transistors with an oxide layer 31, electrons, which are carriers, accumulate near the interface between the semiconductor layer 30 and the oxide layer 31 (see Figure 1E). As a result, the path through which carriers flow is moved away from the interface of the insulating layer 50, and the effects of surface scattering can be reduced. As a result, it is possible to increase the on-current or improve reliability.

[0063] Aluminum oxide and gallium oxide have barrier properties against oxygen. By using aluminum oxide or gallium oxide in the insulating layer 50 provided between the channel-forming region of the semiconductor layer 30 and the conductive layer 60, it is possible to suppress the diffusion of oxygen contained in the channel-forming region into the conductive layer 60 and the formation of oxygen vacancies in the channel-forming region. Furthermore, it is possible to suppress the diffusion of oxygen contained in the semiconductor layer 30 into the conductive layer 60 and the oxidation of the conductive layer 60.

[0064] Figures 1A and 1B show an example where the insulating layer 50 has a single-layer structure. However, the insulating layer 50 can also have a laminated structure of two or more layers. When the insulating layer 50 has a laminated structure of two or more layers, it is preferable to use an insulating material (typically aluminum oxide) applicable to the insulating layer 50 as the layer in contact with the semiconductor layer 30 among the two or more layers included in the insulating layer 50.

[0065] The transistor shown in Figure 1A or Figure 1B may have a conductive layer that functions as a second gate (back gate). Figure 2A is a schematic cross-sectional view of the transistor. The transistor shown in Figure 2A differs from the transistor shown in Figure 1A mainly in that it has a conductive layer 61, an insulating layer 51, and an oxide layer 32. The transistor shown in Figure 2A can be called a dual-gate transistor, a double-gate transistor, or an S-channel (surrounded channel) transistor. In an S-channel transistor, the channel formation region can be electrically surrounded by the electric field of either or both of the first and second gates. Therefore, by adopting an S-channel structure, it is possible to create a transistor with high resistance to short-channel effects, or in other words, a transistor in which short-channel effects are less likely to occur. Furthermore, since the S-channel structure electrically surrounds the channel formation region, it can be said that it is essentially equivalent to the GAA (Gate All Around) structure. By adopting the GAA structure, it is possible to improve the current density flowing through the transistor, which can be expected to improve the transistor's on-current or increase its field-effect mobility.

[0066] An insulating layer 51 is provided on a conductive layer 61, and a semiconductor layer 30 is provided on the insulating layer 51. The oxide layer 32 is located between the insulating layer 51 and the semiconductor layer 30. The conductive layer 61 has a region that overlaps with the semiconductor layer 30, with the insulating layer 51 and the oxide layer 32 in between. The conductive layer 61 also has a region that overlaps with the conductive layer 60, with the semiconductor layer 30 in between.

[0067] In the transistor shown in Figure 2A, the conductive layer 60 functions as a first gate electrode, the insulating layer 50 functions as a first gate insulating layer, the conductive layer 61 functions as a second gate electrode, and the insulating layer 51 functions as a second gate insulating layer.

[0068] By using the conductive layer 61 as a second gate electrode, the on-current can be increased or the threshold voltage can be controlled. For example, by setting the conductive layer 60 and the conductive layer 61 to the same potential and driving them as a double-gate transistor, the on-current can be increased. Also, by applying a different potential to the conductive layer 61 than to the conductive layer 60, the threshold voltage can be controlled. Therefore, by controlling the threshold voltage, it is easy to realize a transistor with normally-off characteristics.

[0069] The conductive layer 61 can use a conductive material applicable to the conductive layer 60. The insulating layer 51 can use an insulating material applicable to the insulating layer 50. By using an insulating material applicable to the insulating layer 50 for the insulating layer 51, an oxide layer 32 can be provided between the semiconductor layer 30 and the insulating layer 51. The oxide layer 32 can be described by referring to the description of the oxide layer 31 above.

[0070] Here, the band diagram of the transistor shown in Figure 2A is shown in Figures 2B and 2C. In Figures 2B and 2C, the vertical axis represents energy, and the horizontal axis represents the concepts of the oxide layer 32, semiconductor layer 30, oxide layer 31, and insulating layer 50 near the channel formation region. Figure 2B shows the Ev and Ec of the oxide layer 32, semiconductor layer 30, and oxide layer 31 respectively when no voltage is applied between the first gate and source, and Figure 2C shows the Ev and Ec of the oxide layer 32, semiconductor layer 30, and oxide layer 31 respectively when a positive voltage is applied between the first gate and source. Note that in Figures 2B and 2C, no voltage is applied between the second gate and source.

[0071] The relationship between the Ec values ​​of the semiconductor layer 30 and the oxide layer 32 can be explained using Figures 1C and 1E, so a detailed explanation is omitted. For example, by substituting insulating layer 50 with insulating layer 51 and oxide layer 31 with oxide layer 32, the explanation using Figures 1C and 1E can be referenced. By adopting the configuration shown in Figure 2A, the carrier flow path is moved away from the interface of insulating layer 50 and insulating layer 51, reducing the effects of surface scattering. As a result, it is possible to increase the on-current or improve reliability. Furthermore, it is possible to realize an embedded channel type transistor in which the channel is moved away from the interface of the gate insulating layer, thereby increasing the field-effect mobility.

[0072] [Example of Fabrication Method] The following describes a method for fabricating semiconductor films using diagrams.

[0073] First, we will explain an example of a method for fabricating the semiconductor device shown in Figure 1A.

[0074] First, a semiconductor layer 30 is formed on a substrate (not shown).

[0075] A single-crystal substrate can be used as the substrate. For example, single-crystal substrates such as YSZ (yttria-stabilized zirconia), zirconium oxide, silicon, silicon carbide, gallium nitride, and gallium oxide can be used. As the substrate, a material with a small lattice mismatch with the semiconductor layer 30 to be formed later can be used.

[0076] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystal of the formed film (e.g., semiconductor layer 30) with respect to the crystal of the film to be formed (e.g., substrate) is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystal in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the formed film, or the lattice constant.

[0077] The lattice mismatch Δa between the substrate and the semiconductor layer 30 is preferably small in absolute value, and most preferably 0%. For example, Δa is preferably -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0078] For example, indium oxide with a cubic crystal structure (bixbite type) has a lattice constant of 1.0117 nm (see ICSD (Inorganic Crystal Structure Database) col.code.14387). On the other hand, YSZ (Zr) with a cubic crystal structure (fluorite type) ０．９ Y ０．１ O １．９５ The lattice constant of ) is 0.51481 nm (see ICSD col.code.248790). Therefore, the lattice mismatch of the indium oxide crystal with respect to the YSZ crystal is -1.74%. Here, the yttrium content in YSZ can be 2 atomic% or more and 15 atomic% or less, preferably 5 atomic% or more and 10 atomic% or less.

[0079] Furthermore, the crystal structure of the substrate and the crystal structure of the semiconductor layer 30 do not necessarily have to have the same crystal orientation. For example, a substrate having a hexagonal or trigonal crystal structure can be used beneath an indium oxide having a cubic crystal structure. For example, by setting the crystal orientation of the substrate surface to

[001] , the crystal orientation requirements necessary for epitaxial growth such that the crystal orientation of the lower surface of the semiconductor layer 30 becomes

[111] can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is In-Ga-Zn oxide (IGZO).

[0080] Furthermore, an insulating layer can be provided between the substrate and the semiconductor layer 30. In other words, an insulating layer (not shown) can be formed on the substrate, and the semiconductor layer 30 can be formed on the insulating layer. As the insulating layer, an oxide containing yttrium, erbium, gadolinium, ytterbium, samarium, or neodymium can be used. Since these oxides have the same cubic crystal structure as indium oxide, the crystallinity of the semiconductor layer 30 formed on the insulating layer can be improved.

[0081] By providing the semiconductor layer 30 on a substrate or the insulating layer in which the lattice mismatch Δa with the semiconductor layer 30 is not 0%, the semiconductor layer 30 may have lattice distortion. The presence of lattice distortion in the semiconductor layer 30 can, in some cases, increase the field-effect mobility of the transistor, similar to a strained silicon transistor. Alternatively, the stress of a conductive film in contact with the semiconductor layer 30 can be used to form lattice distortion within the semiconductor layer 30, thereby increasing the field-effect mobility of the transistor. For example, tensile stress can be applied to the channel formation region of the semiconductor layer 30 using a conductive film in contact with the semiconductor layer 30 (e.g., a conductive film functioning as a source electrode or drain electrode). This can reduce electron scattering in the semiconductor layer 30. Furthermore, the effective mass of electrons may decrease. As a result, electron mobility improves, making it possible to increase the field-effect mobility of the transistor.

[0082] The semiconductor layer 30 can be formed by methods such as atomic layer deposition (ALD), sputtering, chemical vapor deposition (CVD), pulsed laser deposition (PLD), molecular beam epitaxy (MBE), and wet methods. In particular, it is preferable to form it by the ALD method or the sputtering method.

[0083] The semiconductor layer 30 is preferably formed using the ALD method. By using the ALD method, which deposits atoms individually, rather than the sputtering method, which causes particles to collide with the surface to be formed, the formation of crystal nuclei in the film can be suppressed. This prevents unintended polycrystallization of the semiconductor layer 30.

[0084] For the deposition of the semiconductor layer 30, for example, an ALD method using a precursor and an oxidizing agent can be used. When forming a film containing indium as the semiconductor layer 30, an indium-containing precursor can be used. When using an indium-containing precursor, it is preferable to use a thermal ALD method. Alternatively, a plasma-enhanced ALD (PEALD) method can be used.

[0085] Indium-containing precursors that can be used include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolat)indium.

[0086] Furthermore, inorganic precursors that do not contain hydrocarbons may be used as indium precursors. Examples of indium-containing inorganic precursors include halogenated indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film deposition by the ALD method can be performed while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0087] In the method for forming the semiconductor layer 30, it is preferable to use a precursor with a low impurity concentration, i.e., a high purity precursor. For example, by using a precursor with a purity of 3N (99.9%) or higher, preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher, the impurities in the semiconductor layer 30 can be sufficiently reduced.

[0088] The gallium and aluminum content of the indium-containing precursor is preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, even more preferably 50 ppm or less, even more preferably 10 ppm or less, and even more preferably 1 ppm or less. Reducing the gallium concentration in the channel formation region of the semiconductor layer 30 can improve the reliability of the transistor. Furthermore, reducing the aluminum concentration in the channel formation region of the semiconductor layer 30 can improve the crystallinity of the semiconductor layer 30.

[0089] Examples of oxidizing agents include ozone (O ３ ), oxygen (O ２ ), water (H ２ O), Nitrogen dioxide (NO) ２ ), nitrous oxide (N ２ O), hydrogen peroxide (H ２ O ２ ) and others can be used, and two or more of these may be used.

[0090] When forming single crystals or polycrystalline materials with large grain sizes, it is preferable to use an oxidizing agent containing hydrogen to suppress the formation of crystal nuclei in the initial stages of film formation. For example, H ２ O, or H ２ O ２ It is preferable to use . After forming a film with few crystal nuclei, crystal growth can be achieved by heat applied during film formation or by heat treatment after film formation, thereby forming a single crystal film or a polycrystalline film with a large grain size. On the other hand, when reducing the hydrogen and nitrogen concentrations in the film, O is used as the oxidizing agent. ２ or O ３ It is preferable to use O ３It is preferable to use

[0091] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the duration of the source gas flow, and the order in which the source gases are flowed. By adjusting these factors, it is also possible to deposit films with continuously changing compositions. Furthermore, it becomes possible to deposit two or more films with different compositions in succession.

[0092] When introducing the precursor into the reaction chamber, the substrate heating temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, for example, the substrate heating temperature can be 100°C to 350°C, preferably 150°C to 300°C.

[0093] It is preferable to perform a heat treatment after the formation of the semiconductor layer 30. The heat treatment makes it possible to improve the crystallinity of the semiconductor layer 30, even if crystallization was insufficient during film formation.

[0094] The above heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm (0.001%) or more, 1% or more, or 10% or more of an oxidizing gas. For example, when heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to have about 20% oxygen gas. The heat treatment may also be carried out under reduced pressure. Alternatively, after heat treatment in an atmosphere of nitrogen gas or an inert gas, heat treatment can be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed.

[0095] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb (1 × 10⁻¹⁶). −３ Preferably less than ppm, and 0.1 ppb (1 × 10⁻¹⁰ −４ It is more preferable to have a ppm or less, and 0.05 ppb (5 × 10) −５ A concentration of ppm or less is even more preferable. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and other substances from being incorporated into the semiconductor layer 30 as much as possible.

[0096] There are no special limitations on the heating device used for the heat treatment; it may be a device that heats the object to be treated by heat conduction or thermal radiation from a heat source such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the object to be treated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas. Heat treatment can also be performed by irradiation with laser light. For example, an infrared laser, a visible light laser, or an ultraviolet laser can be used as the laser light.

[0097] Here, the heat treatment performed under reduced pressure is referred to as the first treatment, and the heat treatment performed in an atmosphere containing an oxidizing gas is referred to as the second treatment. The temperature of the first treatment is preferably 200°C to 500°C, more preferably 350°C to 450°C. Typically, it can be 400°C. The temperature of the second treatment is preferably 300°C to 700°C, more preferably 450°C to 650°C. Typically, it can be 450°C. As the second treatment, for example, the flow rate ratio of nitrogen gas to oxygen gas can be set to 4:1, and the treatment can be performed at a temperature of 450°C for 1 hour.

[0098] When forming the semiconductor layer 30 using the ALD method, it is preferable to perform the first and second heat treatments in this order. The first treatment can reduce impurities such as carbon, water, and hydrogen in the semiconductor layer 30, and the second treatment can replenish the oxygen removed in the first treatment. Furthermore, it can reduce impurities such as water and hydrogen in the semiconductor layer 30. This can improve the reliability of the transistor.

[0099] When depositing the semiconductor layer 30 using the sputtering method, it is preferable to perform the second treatment as the heat treatment described above. By using a sputtering target with a reduced carbon concentration, the first treatment can be omitted. Details of the method for depositing the semiconductor layer 30 using the sputtering method will be described later.

[0100] Here, a film with a smaller coefficient of thermal expansion than the semiconductor layer 30 can be placed between the substrate and the semiconductor layer 30. As a result, when the substrate temperature is lowered after the deposition of the semiconductor layer 30, tensile stress is generated in the semiconductor layer 30, causing it to become unstable. Consequently, the semiconductor layer 30 is more likely to become a stable crystal rather than an amorphous one, which can accelerate crystallization and make it easier to form large-area crystalline regions.

[0101] Unnecessary portions of the semiconductor layer 30 may be removed by etching. For example, by removing unnecessary portions, island-shaped semiconductor layers 30 can be formed.

[0102] Next, an insulating layer 50 is formed on the semiconductor layer 30. The insulating layer 50 can be formed by methods such as ALD, sputtering, CVD, PLD, MBE, or wet methods.

[0103] For example, the ALD method using a precursor and an oxidizing agent can be used to form the insulating layer 50. When forming an aluminum oxide film as the insulating layer 50, an aluminum-containing precursor can be used. Examples of aluminum-containing precursors include aluminum chloride and trimethylaluminum. As the oxidizing agent, an oxidizing agent that can be used for forming the semiconductor layer 30 can be applied.

[0104] It is preferable to perform a heat treatment after forming the insulating layer 50. In particular, it is preferable to perform the heat treatment when forming the insulating layer 50 using the ALD method. By performing the heat treatment, an oxide layer 31 can be formed between the semiconductor layer 30 and the insulating layer 50. Details of the heat treatment can be found in the above description.

[0105] The heat treatment performed after the formation of the insulating layer 50 is called the third treatment. The temperature of the third treatment is preferably 150°C to 350°C. Typically, it can be set to 250°C. The third treatment can reduce the amount of oxygen and hydrogen contained in the interface between the semiconductor layer 30 and the insulating layer 50. Furthermore, by setting the temperature of the third treatment lower than the temperatures of the first and second treatments, the deep diffusion of the first element into the semiconductor layer 30 can be suppressed.

[0106] Furthermore, when the insulating layer 50 is formed using the sputtering method, the sputtering damage can create an oxide layer 31 in which the components contained in the semiconductor layer 30 and the components contained in the insulating layer 50 are mixed. In this case, the above-mentioned heat treatment may be omitted.

[0107] Furthermore, when the semiconductor layer 30 and the insulating layer 50 are formed continuously using the ALD method, an oxide layer 31 of any composition can be formed by using multiple different types of precursors. Alternatively, when multiple different types of precursors are introduced, an oxide layer 31 of any composition can be formed by controlling the number of cycles of each precursor. For example, a semiconductor layer 30 can be formed using an indium-containing precursor and an oxidizing agent, an oxide layer 31 can be formed using an indium-containing precursor, an aluminum-containing precursor and an oxidizing agent, and an insulating layer 50 can be formed using an aluminum-containing precursor and an oxidizing agent.

[0108] Next, a conductive layer 60 is formed on the insulating layer 50.

[0109] Based on the above, the semiconductor device shown in Figure 1A can be fabricated.

[0110] Next, an example of a method for manufacturing the semiconductor device shown in Figure 1B will be described.

[0111] First, a conductive layer 60 is formed on a substrate (not shown). Next, an insulating layer 50 is formed so as to cover the conductive layer 60. The upper surface of the insulating layer 50 may be flattened. The material of the substrate and the method of forming the insulating layer 50 can be found in the previously described instructions.

[0112] Next, a semiconductor layer 30 is formed on the insulating layer 50.

[0113] The semiconductor layer 30 is preferably formed using a sputtering method. When forming a film containing indium as the semiconductor layer 30, a sputtering target containing indium can be used. For example, an indium oxide sputtering target can be used. By forming the semiconductor layer 30 using a sputtering method, an oxide layer 31 can be formed by mixing the components contained in the semiconductor layer 30 and the components contained in the insulating layer 50 due to damage caused by sputtering. In other words, an oxide layer 31 can be formed between the insulating layer 50 and the semiconductor layer 30.

[0114] Furthermore, when forming the semiconductor layer 30 using the sputtering method, the sputtering gas is hydrogen (H ２ It is preferable that the following are included. By introducing hydrogen when forming the semiconductor layer 30 by sputtering, a semiconductor layer 30 with low crystallinity can be formed. In addition, the generation of crystal nuclei can be suppressed or the disappearance of crystal nuclei can be promoted during the formation of the semiconductor layer 30. Note that a noble gas (typically argon) or a single gas of oxygen, or a mixed gas of a noble gas and oxygen can also be used as the sputtering gas.

[0115] Furthermore, when forming the semiconductor layer 30 using the sputtering method, the substrate temperature during film formation of the semiconductor layer 30 is preferably between room temperature (25°C) and 250°C, more preferably between room temperature and 200°C, and even more preferably between room temperature and 140°C. For example, setting the substrate temperature to between room temperature and 140°C is preferable because it increases productivity. It is also preferable because it suppresses the generation of crystal nuclei. In addition, the metal oxide layer can be formed at room temperature or without heating the substrate.

[0116] It is preferable to form a low-crystallinity semiconductor layer 30 using a sputtering method, and then perform a heat treatment. This heat treatment can be performed, for example, at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. By performing this heat treatment, crystal growth can be promoted, and the crystal grains in the semiconductor layer 30 can be enlarged. Thus, a crystalline semiconductor layer 30 can be formed. Furthermore, by performing the heat treatment, the amount of hydrogen contained in the semiconductor layer 30 can be reduced.

[0117] The method for forming the semiconductor layer 30 can also be found in the previously mentioned description. For example, when using an oxide with a small lattice mismatch with indium oxide (typically yttrium oxide) as the insulating layer 50, it is preferable to form the semiconductor layer 30 having indium oxide using the ALD method. This allows for epitaxial growth of indium oxide on the insulating layer 50, thereby increasing the crystallinity of the semiconductor layer 30. At this time, by performing a heat treatment after the formation of the semiconductor layer 30, an oxide layer 31 can be formed between the insulating layer 50 and the semiconductor layer 30. Details of the heat treatment can be found in the previously mentioned description.

[0118] Based on the above, the semiconductor device shown in Figure 1B can be fabricated.

[0119] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0120] (Embodiment 2) This embodiment describes an example of the configuration of a semiconductor device according to one aspect of the present invention, and an example of a method for manufacturing the same. Here, a transistor will be described as an example of a semiconductor device. The semiconductor layer of the transistor described below can be the same semiconductor layer as described in Embodiment 1.

[0121] [Example of semiconductor device configuration] Figures 3A to 3D are top views and cross-sectional views of the transistor 200. Figure 3A is a top view of the transistor 200, and Figures 3B, 3C, and 3D are cross-sectional views corresponding to the cutting lines A1-A2, A3-A4, and A5-A6 in Figure 3A, respectively. Figure 3B corresponds to the cross-section of the transistor 200 in the channel length direction, and Figures 3C and 3D correspond to the cross-section in the channel width direction, respectively. Figures 4 and 6 are enlarged views of Figure 3B. Note that some components are omitted in Figure 3A.

[0122] The transistor 200 includes an insulating layer 201 provided on a substrate 210, a semiconductor layer 230 provided on the insulating layer 201, conductive layers 242a and 242b on the semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. An oxide layer 231 is also provided between the semiconductor layer 230 and the insulating layer 250. An insulating layer 275 is provided covering the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b, and an insulating layer 280 is provided on the insulating layer 275. The insulating layer 280 and the insulating layer 275 are provided with openings (also called grooves) that reach the semiconductor layer 230, and the conductive layer 242a and the conductive layer 242b are separated by these openings. The insulating layer 250 is provided inside the opening, along the surfaces of the insulating layer 280, insulating layer 275, conductive layer 242a, conductive layer 242b, and semiconductor layer 230. The conductive layer 260 is provided on the insulating layer 250 so as to fill the opening. In addition, insulating layers 282 and 285 are provided in order, covering the insulating layer 280, insulating layer 250, and conductive layer 260.

[0123] The semiconductor layer 230 functions as the channel formation region of the transistor 200. The conductive layer 260 functions as the gate electrode of the transistor 200. The insulating layer 250 functions as the gate insulating layer of the transistor 200. The conductive layer 242a functions as either the source electrode or the drain electrode of the transistor 200, and the conductive layer 242b functions as the other.

[0124] The semiconductor layer 230, oxide layer 231, insulating layer 250, and conductive layer 260 can be made of the semiconductor layer 30, oxide layer 31, insulating layer 50, and conductive layer 60 as exemplified in Embodiment 1, respectively. The substrate 210 can be made of the substrate exemplified in Embodiment 1. The insulating layer 201 may be made of a film with a smaller coefficient of thermal expansion than the semiconductor layer 30 as exemplified in Embodiment 1.

[0125] The conductive layer 242a and conductive layer 242b are arranged on the semiconductor layer 230, spaced apart from each other. Preferably, the conductive layer 242a and conductive layer 242b each have a laminated structure. Preferably, a conductor that is resistant to oxidation, such as a metal nitride, is used on the side in contact with the semiconductor layer 230. This prevents the conductive layer 242a and conductive layer 242b from being excessively oxidized by the oxygen contained in the semiconductor layer 230. Preferably, a metal or alloy with higher conductivity than the layer in contact with the semiconductor layer 230 is used on the side not in contact with the semiconductor layer 230. This allows the conductive layer 242a and conductive layer 242b to function as highly conductive wiring or electrodes.

[0126] In conductive layers 242a and 242b, it is preferable to use a metal nitride on the side in contact with the semiconductor layer 230. For example, it is preferable to use a tantalum nitride, a titanium nitride, a molybdenum nitride, a tungsten nitride, a tantalum and aluminum nitride, or a titanium and aluminum nitride. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0127] In conductive layers 242a and 242b, the side in contact with the semiconductor layer 230 can be made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a conductive metal oxide (also called an oxide conductor), or a conductive material that has the function of suppressing oxygen diffusion. By using an oxygen-containing conductive material as conductive layers 242a and 242b, conductivity can be maintained even if conductive layers 242a and 242b absorb oxygen. For example, metal oxides such as indium tin oxide (In-Sn oxide, also called ITO), silicon-containing indium tin oxide (also called ITSO), indium zinc oxide (In-Zn oxide, also called IZO®), and indium titanium oxide (In-Ti oxide) can be used as conductive layers 242a and 242b, respectively.

[0128] Here, the region of the semiconductor layer 230 that overlaps with the conductive layer 242a is called the first region, and the region of the semiconductor layer 230 that overlaps with the conductive layer 242b is called the second region. The first region is in contact with the conductive layer 242a, and the second region is in contact with the conductive layer 242b. Furthermore, the region of the semiconductor layer 230 located between the first region and the second region is called the third region. The third region is also the region of the semiconductor layer 230 that does not overlap with the conductive layer 242a and the conductive layer 242b.

[0129] By using the above-mentioned metal oxide as conductive layer 242a and conductive layer 242b, metal elements other than indium (e.g., tin, titanium, etc.) are mixed into each of the first and second regions, thereby reducing the resistance of the first and second regions. In this case, one of the first and second regions can function as the source region of the transistor 200, and the other of the first and second regions can function as the drain region of the transistor 200. Hereafter, the metal elements other than indium present in conductive layer 242a and conductive layer 242b may be referred to as the third element. Examples of the third element include tin and titanium.

[0130] Furthermore, by using the above-mentioned metal oxide or metal nitride as conductive layer 242a and conductive layer 242b, a portion of the oxygen in the first region is absorbed by conductive layer 242a, and an oxygen vacancy is formed in the first region. Also, by using the above-mentioned metal oxide or metal nitride as conductive layer 242a and conductive layer 242b, hydrogen in conductive layer 242a diffuses into the first region, and the hydrogen concentration in the first region increases. Alternatively, V Ｏ H is formed. Therefore, the first region can be made to have low resistance and function as a source region or a drain region. The same applies to the second region.

[0131] Furthermore, the above-mentioned metal oxides are materials whose resistance can be controlled by at least one of the following: oxygen vacancies in the film and the concentration of impurities such as hydrogen and water in the film. Therefore, by increasing at least one of the oxygen vacancies and impurity concentrations in the film, they can be applied to conductive layers, and by decreasing at least one of the oxygen vacancies and impurity concentrations, they can be applied to semiconductor layers.

[0132] The conductive layers 242a and 242b can also be single-layer structures. In this case, the conductive layers 242a and 242b can be nitrides such as tantalum-containing nitrides or titanium-containing nitrides, metal oxides such as ITO or ITSO, etc.

[0133] The insulating layer 201 is a film in contact with the semiconductor layer 230, and it is preferable to use an oxide insulating film. For example, it is preferable to use silicon oxide or silicon oxynitride as the insulating layer 201. When indium oxide is used as the semiconductor layer 230, the silicon oxide film and the silicon oxynitride film are films with a smaller coefficient of thermal expansion than the semiconductor layer 230.

[0134] Furthermore, an insulating layer that functions as a barrier layer may be provided between the insulating layer 201 and the semiconductor layer 230, or between the insulating layer 201 and the substrate 210. Preferably, the insulating layer has barrier properties against hydrogen. Examples of hydrogen barrier layers include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. This makes it possible to keep the hydrogen concentration in the semiconductor layer 230 low, thereby improving the reliability of the transistor 200.

[0135] It is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the semiconductor layer 230.

[0136] The band gap of the metal oxide functioning as a semiconductor is preferably 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a larger band gap than silicon, the off-current of the transistor can be reduced. A transistor having a metal oxide in the channel formation region in this way is called an OS transistor. Because OS transistors have a small off-current, the power consumption of semiconductor devices can be significantly reduced. In addition, because OS transistors have high frequency characteristics, semiconductor devices can be operated at high speeds.

[0137] It is preferable to use indium oxide as the semiconductor layer 230. In particular, it is preferable to use a single-crystal indium oxide film. It is preferable to use a crystalline film for the semiconductor layer 230, and it is particularly preferable to use indium oxide with a single-crystal structure, but it is also possible to use indium oxide with a polycrystalline or microcrystalline structure. By using indium oxide with a single-crystal structure, carrier scattering at the grain boundaries can be suppressed, and a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized.

[0138] When using indium oxide having a polycrystalline structure, it is preferable that no grain boundaries are observed, at least in the channel-forming region (the region superimposed on the conductive layer 260). This allows indium oxide having a polycrystalline structure to achieve the same effects as when it has a single-crystal structure.

[0139] In this specification, indium oxide having at least a crystalline portion or crystalline region in a film may be referred to as crystalline indium oxide (Crystal IO) or crystalline indium oxide (Crystalline IO). Examples of Crystal IO or Crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0140] The thickness of the semiconductor layer 230 is more preferably 1 nm to 50 nm, more preferably 2.5 nm to 30 nm, more preferably 2.5 nm to 20 nm, more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. The semiconductor layer 230 only needs to have regions with the above-mentioned thickness in at least a portion of it. For example, the channel formation region of the semiconductor layer 230 only needs to have regions with the above-mentioned thickness. Increasing the thickness of the semiconductor layer 230 makes it possible to increase the on-current of the transistor. On the other hand, if the thickness of the semiconductor layer 230 is made too thick, the extension length of the grain boundaries increases, and the on-current of the transistor may decrease due to the influence of carrier scattering at the grain boundaries. Furthermore, by making the thickness of the semiconductor layer 230 thinner, it is possible to suppress the decrease in the threshold voltage and make it possible to create a normally-off transistor. On the other hand, if the thickness of the semiconductor layer 230 is made too thin, the crystallinity of the semiconductor layer 230 will vary within the substrate surface, which may cause variations in the electrical characteristics of the transistor. Therefore, by setting the thickness of the semiconductor layer 230 within the above range, the crystallinity of the semiconductor layer 230 can be increased. By increasing the crystallinity of the semiconductor layer 230, the semiconductor layer 230 can have crystals.

[0141] In transistors using silicon as the semiconductor layer (also called Si transistors), it is said that reducing the thickness of the semiconductor layer (for example, reducing the thickness to 5 nm or less) changes the wave function in the direction of the film thickness, and thus reduces the field-effect mobility. On the other hand, in metal oxides such as indium oxide, the s orbitals of heavy metals (for example, indium) mainly contribute to carrier conduction, and because the anisotropy of carrier conduction is small, it is less affected by surface scattering due to irregularities on the film surface. Therefore, in OS transistors, even when the thickness of the semiconductor layer is reduced, the field-effect mobility does not decrease significantly. Accordingly, in transistors with a thin semiconductor layer 230, metal oxides such as indium oxide can be suitably used as the semiconductor layer 230. In this case, the thickness of the semiconductor layer 230 can be 1 nm or more and 10 nm or less, preferably 1 nm or more and 6 nm or less, and more preferably 2 nm or more and 6 nm or less.

[0142] Furthermore, in Si transistors, shortening the channel length (for example, reducing it to 10 nm or less) increases the leakage current due to the tunneling current between the source and drain. The tunneling current between the source and drain depends on the height of the potential barrier between the source and drain, and the potential barrier depends on the band gap of the semiconductor material.

[0143] Here, schematic diagrams of tunnel current are shown in Figures 5A and 5B. Figure 5A is the band diagram of an off-state Si transistor, and Figure 5B is the band diagram of an off-state OS transistor. The double arrows in Figures 5A and 5B correspond to the potential barrier, the single arrows in Figures 5A and 5B correspond to the tunnel current, and the thickness of the single arrow corresponds to the amount of tunnel current. Because metal oxides such as indium oxide have a larger band gap compared to silicon, the OS transistor has a higher potential barrier than the Si transistor. Therefore, the source-drain tunnel current can be kept lower in the OS transistor than in the Si transistor. As a result, good electrical characteristics can be observed even when the channel length is shortened. In the OS transistor, the channel length can be 1 nm or more and 15 nm or less, preferably 3 nm or more and 15 nm or less, and more preferably 3 nm or more and 10 nm. The channel length of transistor 200 can be rephrased as the shortest distance between conductive layer 242a and conductive layer 242b.

[0144] Among highly crystalline oxide semiconductors, indium oxide films are films in which hydrogen and / or oxygen can move more easily compared to, for example, IGZO (In-Ga-Zn oxide) films. Therefore, indium oxide films can be said to be films in which hydrogen and / or oxygen can be supplied and expelled more easily compared to, for example, IGZO films. As a result, excess oxygen or excess hydrogen that can become carriers or fixed charges is less likely to accumulate in the semiconductor layer 230, making it possible to create transistors with good electrical characteristics and reliability.

[0145] As will be explained in detail in Embodiment 3, in indium oxide, the lower the carrier concentration, the greater the hole mobility, and the hole mobility is maximized when the Fermi level (Ef) and the intrinsic Fermi level (Ei) become the same. In other words, a transistor having indium oxide can achieve high field-effect mobility by setting Ef = Ei. A semiconductor layer with Ef = Ei can be said to be i-type.

[0146] It is preferable to supply a second element to the channel formation region of the i-type semiconductor layer. By supplying a second element to the channel formation region, the threshold voltage can be controlled, and a transistor with good electrical characteristics can be realized. One or more of the following can be used as the second element: boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, magnesium, and silicon. It is particularly preferable to use boron as the second element. In this case, the region located between the first and second regions of the semiconductor layer 230 (region 230c in Figure 6), that is, the third region of the semiconductor layer 230, contains boron. Furthermore, the content of the second element in the third region of the semiconductor layer 230 is higher than the content of the second element in the first region of the semiconductor layer 230, and the content of the second element in the second region of the semiconductor layer 230. Note that the oxide layer 231 is omitted in Figure 6.

[0147] When an element that readily bonds with oxygen is used as the second element, the second element removes oxygen from the metal oxide and exists in a state of being bonded with oxygen in the semiconductor layer 230. In addition, oxygen vacancies (V) exist in the metal oxide. Ｏ ) is generated. If an element that becomes stable when bonded with oxygen is used as the second element, the second element in the semiconductor layer 230 exists stably in an oxidized state, so it is less likely to be desorbed by heat applied during the semiconductor device manufacturing process, and the resistivity or carrier concentration of the channel formation region can be maintained. Therefore, a highly reliable semiconductor device can be provided. For this reason, it is preferable to use an element as the second element in which its oxide can exist as a solid at least at the temperature during the manufacturing process. Boron and phosphorus, or both, can be suitably used as the second element.

[0148] In addition, metal oxides that can be used in the semiconductor layer 230 include tin oxide, zinc oxide, ITO, In-Zn oxide, In-Ti oxide, indium gallium oxide, indium gallium aluminum oxide, indium gallium tin oxide, gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, indium gallium zinc oxide, indium gallium tin zinc oxide, and indium gallium aluminum zinc oxide. Alternatively, ITSO, gallium tin oxide, and aluminum tin oxide can also be used. When using these, it is preferable that the film has at least crystalline properties, and more preferably that it has a single-crystal structure.

[0149] The insulating layer 250 is located on the semiconductor layer 230, between the conductive layer 242a and the conductive layer 242b. Preferably, the insulating layer 250 has the function of capturing and fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the semiconductor layer 230. This makes the channel formation region i-type or substantially i-type.

[0150] Examples of insulators having the function of capturing and fixing hydrogen include metal oxides having an amorphous structure. It is preferable to use a metal oxide such as magnesium oxide, or an oxide containing one or both of aluminum and hafnium, as the insulating layer 250. In such amorphous metal oxides, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, amorphous metal oxides have a high ability to capture or fix hydrogen.

[0151] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulating layer 250. An example of a high-k material is an oxide containing either or both aluminum and hafnium. By using a high-k material for the insulating layer 250, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. Additionally, it becomes possible to thin the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulating layer.

[0152] It is preferable to use an oxide containing one or both of aluminum and hafnium as the insulating layer 250, more preferably an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and even more preferably aluminum oxide having an amorphous structure.

[0153] As described in Embodiment 1, the insulating layer 250 can be a laminated structure of two or more layers. For example, as shown in Figure 7A, it is preferable that the insulating layer 250 has a laminated structure of insulating layer 250_1 in contact with the semiconductor layer 230, insulating layer 250_2 on insulating layer 250_1, and insulating layer 250_3 on insulating layer 250_2. In this case, the insulating layer 50 exemplified in Embodiment 1 can be applied to insulating layer 250_1.

[0154] The insulating layer 250_2 preferably uses an insulator with a thermally stable structure, such as silicon oxide or silicon oxynitride. Furthermore, the insulating layer 250_2 preferably has a region containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen). By providing an insulating layer having a region containing excess oxygen near the semiconductor layer 230, oxygen is supplied to the channel formation region of the semiconductor layer 230, thereby eliminating oxygen deficiencies and V in the channel formation region. Ｏ H can be reduced. Silicon oxide or silicon oxynitride is suitable as an insulator because it easily forms regions containing excess oxygen.

[0155] It is preferable that the thickness of the insulating layer 250_1 be thin. By making the thickness of the insulating layer 250_1 thin, the oxygen contained in the insulating layer 250_2 is supplied to the channel formation region of the semiconductor layer 230, and oxygen deficiencies and V in the channel formation region are reduced.Ｏ H can be reduced. The insulating layer 250_1 preferably has a region with a film thickness of 0.1 nm or more and 10 nm or less, preferably has a region with a film thickness of 0.1 nm or more and 5 nm or less, and more preferably has a region with a film thickness of 0.1 nm or more and 3 nm or less.

[0156] Since aluminum oxide and gallium oxide have barrier properties against oxygen, it is preferable that the thickness of the insulating layer 250_1 having aluminum oxide or gallium oxide be thin. For example, the insulating layer 250_1 having aluminum oxide preferably has a region with a thickness of 0.5 nm or more and 2.5 nm or less, more preferably has a region with a thickness of 0.5 nm or more and 2 nm or less, and even more preferably has a region with a thickness of 0.5 nm or more and 1.5 nm or less. The insulating layer 250_1 having gallium oxide preferably has a region with a thickness of 0.5 nm or more and 10 nm or less, more preferably has a region with a thickness of 0.5 nm or more and 5 nm or less, and even more preferably has a region with a thickness of 0.5 nm or more and 3 nm or less.

[0157] Furthermore, oxygen vacancies and V in the channel formation region of the semiconductor layer 230 Ｏ If H is sufficiently reduced, it is preferable that the insulating layer 250_1 in contact with the channel-forming region has barrier properties against oxygen. This prevents oxygen contained in the channel-forming region from diffusing outward and suppresses the formation of oxygen vacancies in the channel-forming region. The insulating layer 250_1 preferably has a region with a film thickness of 1.5 nm or more and 15 nm or less, preferably a region with a film thickness of 2 nm or more and 15 nm or less, and more preferably a region with a film thickness of 3 nm or more and 15 nm or less.

[0158] For example, the insulating layer 250_1 having aluminum oxide preferably has a region with a film thickness of 1.5 nm or more and 10 nm or less, more preferably has a region with a film thickness of 2 nm or more and 10 nm or less, and even more preferably has a region with a film thickness of 3 nm or more and 10 nm or less. The insulating layer 250_1 having gallium oxide preferably has a region with a film thickness of 2 nm or more and 15 nm or less, more preferably has a region with a film thickness of 3 nm or more and 15 nm or less, and even more preferably has a region with a film thickness of 5 nm or more and 15 nm or less.

[0159] The insulating layer 250_3 preferably has barrier properties against oxygen. The insulating layer 250_3 is provided between the channel-forming region of the semiconductor layer 230 and the conductive layer 260, and between the insulating layer 280 and the conductive layer 260. With this configuration, oxygen contained in the channel-forming region of the semiconductor layer 230 can diffuse into the conductive layer 260, suppressing the formation of oxygen vacancies in the channel-forming region of the semiconductor layer 230. In addition, oxygen contained in the semiconductor layer 230 and oxygen contained in the insulating layer 280 can diffuse into the conductive layer 260, suppressing oxidation of the conductive layer 260. The insulating layer 250_3 preferably has lower oxygen permeability than at least the insulating layer 250_2. For example, it is preferable to use a silicon nitride film as the insulating layer 250_3. In this case, the insulating layer 250_3 contains at least nitrogen and silicon.

[0160] Furthermore, it is preferable that the insulating layer 250_3 has barrier properties against hydrogen. This prevents impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230.

[0161] Furthermore, as shown in Figure 7B, a structure in which an insulating layer 250_4 is provided on top of the insulating layer 250_2 may also be used. In this case, the insulating layer 250_4 can be an insulator having the function of capturing and fixing hydrogen. For example, an oxide containing one or both of aluminum and hafnium can be used as the insulating layer 250_4. By providing the insulating layer 250_4 between the insulating layer 250_3 and the insulating layer 250_2, hydrogen contained in the insulating layer 250_2 and the like can be captured and fixed more effectively.

[0162] Hafnium oxide has the function of capturing and fixing oxygen. Therefore, by using hafnium oxide in the insulating layer 250_4, excess oxygen contained in the semiconductor layer 230, the insulating layer 250_2, or near the interface between the semiconductor layer 230 and the insulating layer 250 can be captured and fixed. Consequently, a positive shift in the threshold voltage caused by excess oxygen can be suppressed, and a highly reliable semiconductor device can be provided. In addition, oxidation of the conductive layer 260 can be suppressed.

[0163] Aluminum oxide, gallium oxide, and silicon oxide have lower hydrogen barrier properties compared to silicon nitride. Therefore, by using aluminum oxide or gallium oxide for insulating layer 250_1 and silicon oxide for insulating layer 250_2, hydrogen from the semiconductor layer 230 can be captured and fixed to insulating layer 250_4 via insulating layers 250_1 and 250_2, thereby reducing the hydrogen concentration in the channel formation region of the semiconductor layer 230.

[0164] Furthermore, the above film configuration can also be viewed as a layered structure consisting of a film that can supply oxygen to the indium oxide film (e.g., a silicon oxide film), a film that can getter hydrogen (e.g., a hafnium oxide film), and a film that suppresses the intrusion of oxygen and hydrogen (e.g., a silicon nitride film). With this configuration, oxygen deficiencies in the indium oxide film are compensated for by oxygen in the silicon oxide film. Also, hydrogen in the indium oxide film is captured by the hafnium oxide film through heat treatment or other means. In addition, the silicon nitride film provides a film configuration that minimizes the intrusion of oxygen and hydrogen from the outside. In other words, by using the above film configuration, the indium oxide film can be made closer to type i. Therefore, transistors having the above-described indium oxide film have high field-effect mobility and high reliability.

[0165] When the insulating layer 250 has a four-layer structure, it is generally preferable that insulating layer 250_1, insulating layer 250_2, insulating layer 250_4, and insulating layer 250_3 be made of aluminum oxide or gallium oxide, silicon oxide, hafnium oxide, and silicon nitride, respectively. Also, generally, the film thicknesses of insulating layer 250_1, insulating layer 250_2, insulating layer 250_4, and insulating layer 250_3 are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a configuration, good electrical characteristics can be maintained even when the transistor is miniaturized or highly integrated.

[0166] The insulating layer 275 preferably has barrier properties against oxygen. The insulating layer 275 is provided between the insulating layer 280 and the conductive layer 242a, and between the insulating layer 280 and the conductive layer 242b. This configuration suppresses the diffusion of oxygen contained in the insulating layer 280 into the conductive layers 242a and 242b. Therefore, it is possible to suppress the oxidation of the conductive layers 242a and 242b by oxygen contained in the insulating layer 280, which increases their resistivity and reduces the on-current. The insulating layer 275 preferably has lower oxygen permeability than at least the insulating layer 280. For example, silicon nitride is preferably used as the insulating layer 275. In this case, the insulating layer 275 contains at least nitrogen and silicon.

[0167] Furthermore, in this embodiment, it is preferable to configure the semiconductor device to suppress the mixing of hydrogen into the transistor 200, etc., in addition to the above configuration. For example, it is preferable to provide an insulator having the function of suppressing hydrogen diffusion so as to cover the transistor 200. In the semiconductor device described in this embodiment, the insulator is, for example, an insulating layer 282 and an insulating layer 283. Note that the insulating layer 283 can be provided between the insulating layer 282 and the insulating layer 285, as shown in Figure 4. Alternatively, a similar film may be provided under the transistor 200.

[0168] It is preferable that one or more of the insulating layers 282 and 283 function as a barrier insulator that suppresses the diffusion of impurities such as water and hydrogen from above the transistor 200 to the transistor 200. Therefore, it is preferable that one or more of the insulating layers 282 and 283 function as a barrier insulator that suppresses the diffusion of impurities such as water and hydrogen to the transistor 200 from above. ２ O, NO, NO ２ It is preferable to have an insulating material that has the function of suppressing the diffusion of impurities such as copper atoms (i.e., the above-mentioned impurities do not easily permeate). Alternatively, it is preferable to have an insulating material that has the function of suppressing the diffusion of oxygen (i.e., at least one such as oxygen atoms and oxygen molecules) (i.e., the above-mentioned oxygen does not easily permeate).

[0169] The insulating layer 282 and insulating layer 283 preferably have an insulator that has the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has higher hydrogen barrier properties, as the insulating layer 283. Also, for example, it is preferable that the insulating layer 282 has aluminum oxide or magnesium oxide, which have high hydrogen capture and hydrogen fixation functions. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located outside the insulating layer 283 to the transistor 200, etc. Also, it is possible to suppress the diffusion of oxygen contained in the insulating layer 280, etc., upward from the transistor 200, etc. via the insulating layer 282, etc. Furthermore, by providing a film similar to one or both of the insulating layers 282 and 283 below the transistor 200, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200, etc.

[0170] As shown in Figure 4, an insulating layer 271a can be provided between the conductive layer 242a and the insulating layer 275, and an insulating layer 271b can be provided between the conductive layer 242b and the insulating layer 275. The insulating layers 271a and 271b are inorganic insulators that function as etching stoppers during processing of the conductive layers 242a and 242b and protect them. Furthermore, since the insulating layers 271a and 271b are in contact with the conductive layers 242a and 242b, it is preferable that they are inorganic insulators that do not easily oxidize the conductive layers 242a and 242b. For example, the insulating layers 271a and 271b can be arranged in a laminated structure, with silicon nitride used on the side in contact with the conductive layers 242a and 242b, and silicon oxide used on the other sides.

[0171] Insulating layers 285, 283, 282, 280, 275, and 271a have openings that reach the conductive layer 242a, and the conductive layer 240a and insulating layer 241a are provided within these openings. An insulating layer 241a is provided adjacent to the side wall of the opening, and the conductive layer 240a is provided inside the insulating layer 241a. In addition, insulating layers 285, 283, 282, 280, 275, and 271b have openings that reach the conductive layer 242b, and the conductive layer 240b and insulating layer 241b are provided within these openings. An insulating layer 241b is provided adjacent to the side wall of the opening, and the conductive layer 240b is provided inside the insulating layer 241b. The conductive layers 240a and 240b function as vias connecting wiring and the like provided on the transistor 200 to the source or drain of the transistor 200.

[0172] The conductive layers 240a and 240b are preferably made of conductive materials mainly composed of tungsten, copper, or aluminum. The conductive layers 240a and 240b may also be arranged in a laminated structure.

[0173] For example, as shown in Figure 4, the conductive layer 240a and conductive layer 240b may be arranged in a two-layer laminated structure. The conductive layer 240a has a conductive layer 240a1 formed along the opening and a conductive layer 240a2 formed inside the conductive layer 240a1. The conductive layer 240b has a conductive layer 240b1 formed along the opening and a conductive layer 240b2 formed inside the conductive layer 240b1.

[0174] It is preferable to use conductive materials such as tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide for conductive layers 240a1 and 240b1, which have the function of suppressing the permeation of impurities such as water and hydrogen. Furthermore, the conductive material having the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated form. By providing conductive layers 240a1 and 240b1, it is possible to suppress the mixing of impurities such as water and hydrogen into the semiconductor layer 230 through conductive layers 240a2 and 240b2. The conductive layers 240a2 and 240b2 may be conductive materials that can be used for conductive layers 240a and 240b described above.

[0175] Furthermore, as shown in Figure 3B, the upper surfaces of the conductive layers 240a and 240b can be formed so that their height matches that of the upper surface of the insulating layer 285. Also, as shown in Figure 4, the lower part of the conductive layer 240a may be formed to be embedded in the conductive layer 242a. Similarly, the lower part of the conductive layer 240b may be formed to be embedded in the conductive layer 242b.

[0176] As insulating layers 241a and 241b, barrier insulators that can be used for insulating layer 275 and the like can be used. For example, silicon nitride can be used as insulating layer 241a and insulating layer 241b. Insulating layer 241a is provided in contact with insulating layer 285, insulating layer 283, insulating layer 282, insulating layer 275, and insulating layer 271a, and insulating layer 241b is provided in contact with insulating layer 285, insulating layer 283, insulating layer 282, insulating layer 275, and insulating layer 271b. This makes it possible to suppress the mixing of impurities such as water and hydrogen contained in insulating layer 280, etc., into the semiconductor layer 230 through conductive layer 240a and conductive layer 240b. Silicon nitride is particularly suitable because it has high barrier properties against hydrogen. In addition, it is possible to prevent oxygen contained in insulating layer 280 from being absorbed by conductive layer 240a and conductive layer 240b.

[0177] The conductive layer 260 is preferably provided extending in the channel width direction, as shown in Figures 3A and 3C. With this configuration, when multiple transistors are provided, the conductive layer 260 functions as wiring.

[0178] The conductive layer 260 may have a laminated structure. Figure 4 shows an example in which the conductive layer 260 has a conductive layer 260a located on the side in contact with the insulating layer 250 and a conductive layer 260b above it. In this case, it is preferable to use a conductive material that is resistant to oxidation, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, or a conductive material that has the function of suppressing oxygen diffusion, for the conductive layer 260a. It is also preferable to use a low-resistance conductive material such as tungsten, copper, or aluminum for the conductive layer 260b.

[0179] The insulating layer 280 preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, the insulating layer 280 preferably has one or more of the following: silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with vacancies. Silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0180] [Variations] The following describes an example with some configuration differences from the above example. Note that the following explanation omits parts that overlap with the above.

[0181] [Modification 1] Figure 8 shows an example having a conductive layer 205 that functions as a back gate. The configuration shown in Figure 8 has a conductive layer 205 and an insulating layer 202.

[0182] The conductive layer 205 is provided so as to be embedded in the insulating layer 202. The insulating layer 201 is provided so as to cover the insulating layer 202 and the conductive layer 205.

[0183] The conductive layer 205 functions as the second gate (back gate) of the transistor 200. The conductive layer 205 is provided in a region that overlaps with the conductive layer 260 via the semiconductor layer 230.

[0184] The conductive layer 205 can be made of a material that can be used for the conductive layer 260. Furthermore, the conductive layer 205 may have a laminated structure.

[0185] Furthermore, the conductive layer 205 can also be made of an oxide conductor. Compared to materials composed of metal elements (also called metallic materials), this oxide conductor is more likely to maintain its conductivity even when absorbing oxygen. For example, even when an oxide insulating film is used for the insulating layer 202, the conductive layer 205 can maintain its conductivity, making it suitable. Examples of such oxide conductors include metal oxides such as ITO, ITSO, In-Zn oxide, and In-Ti oxide.

[0186] When the conductive layer 205 functions as the second gate of the transistor 200, the insulating layer 201 functions as the second gate insulating layer. In this case, it is preferable to have a laminated structure for the insulating layer 201 and to use a high dielectric constant material such as hafnium oxide, aluminum oxide, or hafnium aluminate in part thereof.

[0187] When the insulating layer 51 exemplified in Embodiment 1 is applied to the insulating layer 201, an oxide layer 232 is formed between the insulating layer 250 and the semiconductor layer 230, as shown in Figure 9A. The oxide layer 232 corresponds to the oxide layer 32 exemplified in Embodiment 1.

[0188] The insulating layer 201 can have a laminated structure. For example, as shown in Figure 9B, the insulating layer 201 can have a laminated structure consisting of an insulating layer 201_1 in contact with the semiconductor layer 230, an insulating layer 201_2 below insulating layer 201_1, an insulating layer 201_4 below insulating layer 201_2, and an insulating layer 201_3 below insulating layer 201_4. Alternatively, as shown in Figure 9C, the insulating layer 201 may be configured without insulating layer 201_2. Insulating layers 201_1 to 201_4 can be made from materials that can be used for insulating layers 250_1 to 250_4, respectively.

[0189] When the insulating layer 201 has a laminated structure, it is preferable that the insulating layer 201 and the insulating layer 250 have a symmetrical structure in the vertical direction (lamination direction) with respect to the semiconductor layer 230. For example, the insulating layer 250 can be constructed by laminating insulating layer 250_1, insulating layer 250_2, insulating layer 250_4, and insulating layer 250_3 in the order described above, and the insulating layer 201 can be constructed by laminating insulating layer 201_3, insulating layer 201_4, insulating layer 201_2, and insulating layer 201_1 in the order described above. In other words, the semiconductor layer 230 can be sandwiched between insulating layers 250_1 and 201_1, this three-layer structure can be sandwiched between insulating layers 250_2 and 201_2, this five-layer structure can be sandwiched between insulating layers 250_4 and 201_4, and this seven-layer structure can be sandwiched between insulating layers 250_3 and 201_3. This allows for appropriate hydrogen and oxygen concentration distributions in and around the semiconductor layer 230, resulting in good electrical characteristics and high reliability in the transistor. Note that if an appropriate amount of oxygen can be supplied to the semiconductor layer 230, at least one of insulating layers 250_2 or 201_2 may be omitted. For example, the insulating layer 250 can be constructed by stacking insulating layer 250_1, insulating layer 250_2, insulating layer 250_4, and insulating layer 250_3 in the order described above, and the insulating layer 201 can be constructed by stacking insulating layer 201_3, insulating layer 201_4, and insulating layer 201_1 in the order described above. When the insulating layer 201 has a three-layer structure, it is generally preferable that insulating layer 201_3, insulating layer 201_4, and insulating layer 201_1 be silicon nitride, hafnium oxide, and aluminum oxide or gallium oxide, respectively.

[0190] The insulating layer 202 can be made of a silicon oxide film. It is preferable to provide an insulating film, such as silicon nitride or aluminum oxide, which has oxygen barrier properties, between the insulating layer 202 and the conductive layer 205, as this suppresses oxidation of the conductive layer 205.

[0191] [Modification 2] Figures 10A to 10D show examples of transistor 200 configurations that differ in some aspects from the above. Figure 10A is a top view, and Figures 10B to 10D are cross-sectional views. The configurations shown in Figures 10A to 10D differ from the above configuration mainly in that they have an insulating layer 255. In addition, the insulating layer 250 is in contact with the side surface of the insulating layer 255.

[0192] Here, conductive layers 242a and 242b are shown as having a two-layer structure. Conductive layer 242a has a laminated structure consisting of conductive layer 242a1 and conductive layer 242a2 on conductive layer 242a1. Conductive layer 242b has a laminated structure consisting of conductive layer 242b1 and conductive layer 242b2 on conductive layer 242b1.

[0193] The insulating layer 255 is positioned inside an opening formed in the insulating layer 280, etc., and is in contact with the side surface of the insulating layer 280, the side surface of the conductive layer 242a2, the side surface of the conductive layer 242b2, the upper surface of the conductive layer 242a1, the upper surface of the conductive layer 242b1, and the upper surface of the insulating layer 201 within the opening. In other words, the insulating layer 255 can be said to be formed in a sidewall shape in contact with the side wall of the opening formed in the insulating layer 280, etc. Here, the side wall of the opening corresponds, for example, to the side surface of the insulating layer 280, etc. within the opening.

[0194] The insulating layer 255 preferably has barrier properties against oxygen. The insulating layer 255 having barrier properties against oxygen suppresses oxidation of the sides of the conductive layers 242a and 242b, preventing the formation of an oxide film on those sides. This suppresses a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility. As the insulating layer 255, a barrier insulator that can be used for the insulating layer 275, etc., can be used. For example, silicon nitride can be used as the insulating layer 255.

[0195] The openings provided in the insulating layer 280, etc., overlap with the region between the conductive layer 242a2 and the conductive layer 242b2. In a top view, the side surface of the insulating layer 280 inside the opening coincides with the side surface of the conductive layer 242a2 and the side surface of the conductive layer 242b2. Furthermore, parts of the conductive layer 242a1 and the conductive layer 242b1 are formed to protrude inward into the opening. In other words, in the conductive layer 242a1, the portion on which the insulating layer 255 is formed on the upper surface (hereinafter sometimes referred to as the protruding portion of the conductive layer 242a1) protrudes toward the conductive layer 260 from the conductive layer 242a2. Similarly, in the conductive layer 242b1, the portion on which the insulating layer 255 is formed on the upper surface (hereinafter sometimes referred to as the protruding portion of the conductive layer 242b1) protrudes toward the conductive layer 260 from the conductive layer 242b2.

[0196] Here, a portion of the upper surface of conductive layer 242a1 is in contact with conductive layer 242a2, and a portion of the upper surface of conductive layer 242b1 is in contact with conductive layer 242b2. Therefore, within the opening, the insulating layer 255 is in contact with the other portion of the upper surface of conductive layer 242a1, the other portion of the upper surface of conductive layer 242b1, the side surface of conductive layer 242a2, and the side surface of conductive layer 242b2. In addition, the insulating layer 250 is in contact with the upper surface of semiconductor layer 230, the side surface of conductive layer 242a1, the side surface of conductive layer 242b1, and the side surface of insulating layer 255.

[0197] The insulating layer 255 can be formed by depositing an insulating film that will become the insulating layer 255, and then anisotropically etching the insulating film.

[0198] [Modification 3] Figures 11A to 11D show examples of the configuration of the transistor 200 illustrated below. The configuration shown in Figures 11A to 11D differs from Modification 2 above mainly in that it does not have an insulating layer 255.

[0199] In the configuration without the insulating layer 255, a portion of the insulating layer 250 is positioned overlapping the protrusions of the conductive layer 242a1 and the conductive layer 242b1. In some cases, a portion of the conductive layer 260 is positioned overlapping the protrusions of the conductive layer 242a1 and the conductive layer 242b1. Here, the protrusions of the conductive layer 242a1 and the conductive layer 242b1 are in contact with the insulating layer 250. Also, the side surface of the insulating layer 250 is in contact with the side surface of the insulating layer 280, the side surface of the insulating layer 275, the side surface of the insulating layer 271a, the side surface of the insulating layer 271b, the side surface of the conductive layer 242a2, and the side surface of the conductive layer 242b2.

[0200] The portion of the insulating layer 250 that is positioned inside an opening provided in the insulating layer 280, etc., is formed to reflect the shape of the opening. Therefore, the insulating layer 250 is formed to reflect the shape of the conductive layer 242a1 and conductive layer 242b1 that protrude into the opening.

[0201] As shown in Figure 11B, in a cross-sectional view of the transistor 200 in the channel length direction, the distance between conductive layer 242a1 and conductive layer 242b1 is smaller than the distance between conductive layer 242a2 and conductive layer 242b2. This configuration allows for a shorter distance between the source and drain, and consequently, a shorter channel length. Therefore, the frequency characteristics of transistor 200 can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0202] [Modification 4] The above describes a configuration in which the gate electrode is embedded in an insulating layer, but the following describes a transistor with a different configuration.

[0203] Figure 12A shows a cross-sectional view of transistor 200a in the channel length direction. Transistor 200a has a semiconductor layer 230, an insulating layer 250, a conductive layer 260, a conductive layer 242a, and a conductive layer 242b. Although not shown in Figure 12A, there is also the aforementioned oxide layer 231 between the semiconductor layer 230 and the insulating layer 250.

[0204] An insulating layer 250 is provided covering the semiconductor layer 230, and a conductive layer 260 is provided on the insulating layer 250 at a position overlapping with the semiconductor layer 230. Furthermore, insulating layers 281 and 280 are laminated and provided covering the insulating layer 250 and the conductive layer 260. A pair of openings reaching the semiconductor layer 230 is provided in the insulating layer 281, insulating layer 280, and insulating layer 250, respectively. Conductive layers 242a and 242b are provided on the insulating layer 280 and are in contact with the semiconductor layer 230 at their respective openings.

[0205] As the insulating layer 281, an insulator having barrier properties against hydrogen and oxygen, similar to that of the insulating layer 275, can be used. This suppresses the diffusion of impurities contained in the insulating layer 280 into the semiconductor layer 230, and the diffusion of oxygen contained in the semiconductor layer 230 towards the insulating layer 280.

[0206] The region of the semiconductor layer 230 that overlaps with the conductive layer 260 functions as a channel-forming region. Furthermore, a pair of regions 230n flanking the channel-forming region function as a source region or a drain region. It is preferable that regions 230n have lower resistance than the channel-forming region.

[0207] For example, region 230n preferably contains an element that imparts conductivity to the semiconductor layer 230. Examples of such elements include titanium, tantalum, tungsten, tin, silicon, germanium, zirconium, hafnium, antimony, magnesium, hydrogen, boron, and phosphorus. These elements can be introduced into a portion of the semiconductor layer 230 by methods such as doping, ion implantation, or thermal diffusion. For example, using the conductive layer 260 as a mask, the above elements can be introduced into a region of the semiconductor layer 230 that does not overlap with the conductive layer 260 via the insulating layer 250 by doping or ion implantation.

[0208] Figure 12B shows an example where the insulating layer 250 is located only in the region overlapping with the conductive layer 260 and is not provided on the region 230n of the semiconductor layer 230. In this case, by using a film containing the above-mentioned elements for the insulating layer 281 in contact with region 230n, the above-mentioned elements can be introduced into region 230n during the formation of the insulating layer 281 or by subsequent heat treatment. For example, it is preferable to use silicon nitride containing hydrogen for the insulating layer 281. Alternatively, an oxide containing a metallic element from among the above-mentioned elements may be used.

[0209] [Modification 5] Figure 13A shows an example in which a conductive layer 205, which functions as a second gate electrode, is provided in the configuration shown in Figure 12A.

[0210] The conductive layer 205 is provided on the substrate 210, and the insulating layer 201 is provided so as to cover the conductive layer 205. The transistor 200a shown in Figure 13A has the aforementioned oxide layer 232 (not shown) between the semiconductor layer 230 and the insulating layer 201. The structure, materials, etc. of the conductive layer 205 and the insulating layer 201 can be found in the above description.

[0211] Figure 13B shows an example in which the insulating layer 250 is located only in the region overlapping with the conductive layer 260 and is not provided on the region 230n of the semiconductor layer 230.

[0212] [Modification 6] The following describes a transistor in which the conductive layer, which functions as a gate electrode, is located below the semiconductor layer.

[0213] Figure 14A shows a cross-sectional view of transistor 200b in the channel length direction. Transistor 200b has a semiconductor layer 230, an insulating layer 201, a conductive layer 205, a conductive layer 242a, and a conductive layer 242b. Although not shown in Figure 14A, there is also the aforementioned oxide layer 232 between the semiconductor layer 230 and the insulating layer 201. The conductive layer 205 functions as the gate electrode of transistor 200b. The insulating layer 201 functions as the gate insulating layer of transistor 200b.

[0214] The composition and materials of the substrate 210, conductive layer 205, insulating layer 201, and semiconductor layer 230 can be found in the information described above.

[0215] Each of the conductive layer 242a and conductive layer 242b has a region in contact with the upper surface of the semiconductor layer 230 and a region in contact with the side surface of the semiconductor layer 230. The insulating layer 280 is provided so as to cover the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b.

[0216] Figure 14B shows an example in which an insulating layer 284 is provided in the configuration shown in Figure 14A.

[0217] The insulating layer 284 is provided so as to cover the semiconductor layer 230 and has a first opening and a second opening that reach the semiconductor layer 230. Within the first opening, the conductive layer 242a is in contact with the semiconductor layer 230, and within the second opening, the conductive layer 242b is in contact with the semiconductor layer 230.

[0218] The insulating layer 284 functions as a channel protection film that protects the channel formation region when forming the conductive layers 242a and 242b. The insulating layer 284 is formed on the semiconductor layer 230, a first opening and a second opening are formed in the insulating layer 284, conductive films that will become the conductive layers 242a and 242b are deposited on the insulating layer 284, and the conductive layers 242a and 242b can be formed by processing the conductive films. Since the channel formation region is not exposed during the deposition and processing of the conductive films, damage to the channel formation region can be suppressed. Therefore, a transistor with good electrical characteristics can be made.

[0219] As the insulating layer 284, a material that can be used for the insulating layer 280 can be applied.

[0220] [Variation 7] Below, we will describe a vertical transistor in which the source electrode and drain electrode are located at different heights.

[0221] Figure 15A shows a schematic cross-sectional view of transistor 200c. Transistor 200c has a semiconductor layer 230, an insulating layer 250, a conductive layer 260, a conductive layer 245, and a conductive layer 246. Although not shown in Figure 15A, there is also the aforementioned oxide layer 231 between the semiconductor layer 230 and the insulating layer 250. The conductive layer 245 functions as either the source electrode or the drain electrode of transistor 200c, and the conductive layer 246 functions as the other.

[0222] A conductive layer 245 is provided on an insulating layer 201, and an insulating layer 211 is provided covering the conductive layer 245. A conductive layer 246 is provided on the insulating layer 211. The conductive layer 246 and the insulating layer 211 are provided with openings that reach the conductive layer 245. The semiconductor layer 230 is provided in contact with the upper surface of the conductive layer 246, the side surface of the conductive layer 246 at the opening, the side surface of the insulating layer 211, and the upper surface of the conductive layer 245. The insulating layer 250 is provided covering the semiconductor layer 230 at the opening, and the conductive layer 260 is provided covering the insulating layer 250.

[0223] In transistor 200c, the source electrode and drain electrode are located at different heights, and current flows in the height direction through the semiconductor layer. That is, the channel length direction has a component in the height direction (vertical direction), so transistor 200c can be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, or vertical channel type transistor. In transistor 200c, two or more of the source electrode, semiconductor, and drain electrode can be stacked, so the occupied area can be significantly reduced compared to a so-called planar type transistor (which can also be called a lateral transistor or LFET (Lateral FET)) in which the semiconductor is arranged on a plane.

[0224] Furthermore, the channel length of transistor 200c can be precisely controlled by the thickness of the insulating layer 211, which functions as a spacer, thus significantly reducing the variation in channel length compared to planar transistors. Moreover, by thinning the insulating layer 211, transistors with extremely short channel lengths can be fabricated. For example, transistors with channel lengths of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and with channel lengths of 5 nm or more, 7 nm or more, or 10 nm or more can be fabricated. Therefore, transistors with extremely short channel lengths, which were not possible with mass-production exposure equipment, can be realized. Additionally, transistors with channel lengths of less than 10 nm can be realized without using the extremely expensive exposure equipment used in state-of-the-art LSI technology.

[0225] In transistor 200c, the shape of the opening provided in the insulating layer 211 can be of various shapes.

[0226] Figure 15B shows a perspective view with the insulating layer 211 and the semiconductor layer 230 extracted. Here, an example is shown in which a cylindrical opening 290o is provided in the insulating layer 211. In this case, the semiconductor layer 230 has a cylindrical portion along the side wall of the opening 290o and flat portions parallel to the substrate surface at the bottom and top. In the configuration shown in Figure 15B, the channel width of the transistor is approximately equal to the circumference of the cylindrical portion. Therefore, in the configuration shown in Figure 15B, it is easy to make the channel length small and the channel width large, and a transistor capable of carrying extremely large currents can be realized.

[0227] On the other hand, Figure 15C shows an example in which a slit-shaped opening 290s is provided in the insulating layer 211. As shown in Figure 15C, multiple semiconductor layers 230 can be arranged in the opening 290s, making it suitable for high-density arrangement of transistors. Although not shown here, a conductive layer 260 that functions as a gate electrode can be embedded in the opening 290s and used as wiring extending in the direction of extension of the opening 290s.

[0228] The above is an explanation of the variations.

[0229] [Example of Manufacturing Method] Below, an example of a method for manufacturing a transistor according to one aspect of the present invention will be described. Here, the transistor 200 illustrated in Figures 3A to 3D will be used as an example.

[0230] Figures 16A1, 16B1, 16C1, 16D1, 18A1, 18B1, and 18C1 are schematic cross-sectional views of each stage of the example manufacturing method described below, while Figures 16A2, 16B2, 16C2, 16D2, 18A2, 18B2, and 18C2 are perspective views. Note that the perspective views are partially cut off. In addition, in the perspective views, only the outlines of some components (such as the insulating layer) are shown with dashed lines.

[0231] First, an insulating layer 201 is formed on the substrate 210, and a semiconductor film 230f is deposited on the insulating layer 201. The substrate 210 and the semiconductor film 230f can be prepared by referring to the method for manufacturing the substrate and semiconductor layer 30 in Embodiment 1, respectively.

[0232] It is preferable to perform a heat treatment on the semiconductor film 230f. Examples of such heat treatments include the first treatment and the second treatment described in Embodiment 1. By performing the heat treatment, the crystallinity of the semiconductor film 230f can be improved. Furthermore, by performing the heat treatment, oxygen can be supplied to the semiconductor film 230f, reducing oxygen vacancies in the semiconductor film 230f. This can improve the reliability of the transistor 200. In addition, hydrogen can be removed from the semiconductor film 230f by the heat treatment. Details of the heat treatment can be found in the above description.

[0233] Next, a conductive film 242f is deposited on the semiconductor film 230f (Figures 16A1 and 16A2). By depositing the conductive film 242f in contact with the semiconductor film 230f without an etching process after the deposition of the semiconductor film 230f, the upper surface of the semiconductor film 230f can be protected by the conductive film 242f. This suppresses the diffusion of impurities into the semiconductor layer 230 that constitutes the transistor, thereby improving the electrical characteristics and reliability of the semiconductor device.

[0234] The conductive film 242f can be deposited using sputtering, CVD, MBE, PLD, or ALD methods.

[0235] When a metal oxide is deposited as the conductive film 242f, the third element described above may be mixed into the semiconductor film 230f. When a metal oxide or metal nitride is deposited as the conductive film 242f, oxygen vacancies may be formed in the semiconductor film 230f.

[0236] In this embodiment, tantalum nitride is deposited as the conductive film 242f using a sputtering method. A heat treatment may be performed before depositing the conductive film 242f. This heat treatment may be carried out under reduced pressure, and the conductive film 242f may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the semiconductor film 230f can be removed, and the moisture and hydrogen concentrations in the semiconductor film 230f can be further reduced. The heat treatment temperature is preferably between 100°C and 400°C.

[0237] Next, the semiconductor film 230f and the conductive film 242f are processed into island-like structures using lithography to form the semiconductor layer 230 and the conductive layer 242 (Figures 16B1 and 16B2). Dry etching or wet etching can be used for this processing. Dry etching is suitable for microfabrication. Furthermore, the processing of the semiconductor film 230f and the conductive film 242f may be carried out under different conditions.

[0238] Alternatively, a layer that functions as a hard mask may be formed on the conductive film 242f. Using a hard mask is preferable because it improves processability and makes it easier to process into the desired shape.

[0239] In this case, it is preferable to process the semiconductor layer 230 and the conductive layer 242 together in an island shape. In this case, it is preferable that the side edge of the conductive layer 242 coincides with the side edge of the semiconductor layer 230. By adopting such a configuration, the number of processes for the semiconductor device according to one aspect of the present invention can be reduced. Therefore, a method for manufacturing a semiconductor device with good productivity can be provided.

[0240] As shown in Figure 16B1, the sides of the semiconductor layer 230 and the conductive layer 242 may be tapered. The taper angle of the sides of the semiconductor layer 230 and the conductive layer 242 can be, for example, 60° or more and less than 90°. By making the sides tapered in this way, the coverage of the insulating layer 275 and other components can be improved in subsequent processes, and defects such as porosity can be reduced.

[0241] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, by etching through this resist mask, conductors, semiconductors, or insulators can be processed into the desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology may be used, where a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, an electron beam or ion beam may be used instead of the aforementioned light. When using an electron beam or ion beam, a mask may not be necessary in some cases.

[0242] Furthermore, the resist mask that is no longer needed after processing can be removed by dry etching, such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), wet etching, wet etching after dry etching, or dry etching after wet etching.

[0243] Furthermore, a hard mask made of an insulator or conductor may be used beneath the resist mask. When a hard mask is used, an insulating film or conductive film that will serve as the hard mask material is formed on the conductive film 242f, a resist mask is formed on top of it, and a hard mask of the desired shape can be formed by etching the hard mask material. For example, tungsten may be used as the hard mask material. Etching of the conductive film 242f may be performed after removing the resist mask, or it may be performed while the resist mask is still in place. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching of the semiconductor film 230f. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask.

[0244] Alternatively, a configuration may be used in which an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film are deposited between the workpiece and the resist mask. By using the SOC film and SOG film as masks, the adhesion to the resist mask can be improved, and the durability of the mask pattern can be enhanced. For example, lithography can be performed by depositing the SOC film, SOG film, and resist mask in that order on the workpiece.

[0245] Next, an insulating layer 275 is formed to cover the semiconductor layer 230 and the conductive layer 242, and then an insulating layer 280 is formed on top of the insulating layer 275 (Figures 16C1 and 16C2).

[0246] Preferably, the insulating layer 280 is formed by creating an insulating film that will serve as the insulating layer 280, and then performing CMP treatment on the insulating film to form an insulating layer with a flat upper surface. Alternatively, silicon nitride may be deposited on the insulating layer 280, for example, by sputtering, and then CMP treatment may be performed on the silicon nitride until it reaches the insulating layer 280.

[0247] The insulating layer 275 and the insulating layer 280 can be formed using, for example, sputtering, CVD, MBE, PLD, or ALD.

[0248] It is preferable to use an insulator that has the function of suppressing oxygen permeation for the insulating layer 275. For example, it is preferable to deposit silicon nitride as the insulating layer 275 using the PEALD method. Alternatively, the insulating layer 275 may be configured by depositing aluminum oxide using the sputtering method and then depositing silicon nitride on top of it using the PEALD method. By making the insulating layer 275 such a structure, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0249] Furthermore, it is preferable to deposit silicon oxide as the insulating layer 280 using a sputtering method. By depositing the insulating film that will become the insulating layer 280 using a sputtering method in an oxygen-containing atmosphere, an insulating layer 280 containing excess oxygen can be formed. In addition, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. Before depositing the insulating film, a heat treatment may be performed. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulating layer 275 can be removed. The heat treatment conditions described above can be used for this heat treatment.

[0250] Next, the conductive layer 242, insulating layer 275, and insulating layer 280 are processed using lithography to form openings that reach the semiconductor layer 230 and the insulating layer 201 (Figures 16D1 and 16D2). At this point, a portion of the upper surface of the semiconductor layer 230 is exposed. The conductive layer 242 is also divided to form conductive layer 242a and conductive layer 242b. The openings formed in the insulating layer 280 and insulating layer 275 overlap with the semiconductor layer 230.

[0251] Furthermore, if the etching selectivity ratio between the semiconductor layer 230 and the conductive layer 242 is low, a recess may be formed in the semiconductor layer 230 at a position overlapping with the aforementioned opening. In other words, the film thickness of the region of the semiconductor layer 230 overlapping with the aforementioned opening may be thinner than the film thickness of the first region or the second region of the semiconductor layer 230. The region of the semiconductor layer 230 overlapping with the aforementioned opening corresponds to the third region described above.

[0252] When a metal oxide is formed as the conductive film 242f, the aforementioned third element may be mixed into the semiconductor film 230f. However, by forming the recess described above, the region containing the third element can be removed. In this case, the content of the third element in the first region of the semiconductor layer 230 and the content of the third element in the second region of the semiconductor layer 230 are each higher than the content of the third element in the third region of the semiconductor layer 230.

[0253] Next, an insulating film, which will become the insulating layer 250, is formed to cover the openings formed in the insulating layer 280, etc. Here, the insulating film is formed along the openings. The insulating film is in contact with the insulating layer 280, the conductive layer 242a, the conductive layer 242b, the insulating layer 201, and the semiconductor layer 230.

[0254] The above insulating film can be formed using sputtering, CVD, MBE, PLD, or ALD. Since the insulating layer 250 is preferably formed with a thin film thickness, it is preferable to form the insulating film using the ALD method, which has excellent coverage and allows for easy control of film thickness.

[0255] Furthermore, when the above insulating film is deposited by the ALD method, ozone (O) is used as the oxidizing agent. ３ ), oxygen (O ２ ), water (H ２ O) can be used. Hydrogen-free ozone (O) ３ ), oxygen (O ２ By using oxidizing agents such as ), the amount of hydrogen diffusing into the semiconductor layer 230 can be reduced.

[0256] Furthermore, it is preferable to perform microwave treatment before, after, or during the deposition of the insulating film.

[0257] More specifically, microwave processing is preferably performed in an oxygen-containing atmosphere. Here, microwave processing refers to processing using, for example, a device having a power supply that generates high-density plasma using microwaves. Furthermore, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0258] In microwave processing, it is preferable to use a microwave processing apparatus that has a power supply for generating high-density plasma using microwaves. The frequency of the microwave processing apparatus can typically be set to 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply for applying microwaves to the microwave processing apparatus is preferably 1000 W to 10000 W, and preferably 2000 W to 5000 W. The microwave processing apparatus may also have a power supply for applying RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the semiconductor layer 230.

[0259] Furthermore, the microwave treatment described above is preferably carried out under reduced pressure, with a pressure of 10 Pa to 1000 Pa, and more preferably 300 Pa to 700 Pa. The treatment temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be, for example, around 250°C. In addition, after the oxygen plasma treatment, a continuous heat treatment may be performed without exposure to the outside air. The heat treatment temperature is preferably, for example, 100°C to 750°C, and more preferably 300°C to 500°C.

[0260] By performing microwave processing in an oxygen-containing atmosphere, the oxygen gas can be plasma-generated using microwaves or high-frequency waves such as RF, and oxygen radicals can be applied to the third region of the semiconductor layer 230. Due to the action of oxygen radicals, microwaves, etc., the V of the third region Ｏ H can be separated into an oxygen deficiency and hydrogen, and hydrogen can be removed from the third region. In addition, by supplying oxygen radicals to the third region, the oxygen deficiency in the third region can be reduced. As a result, the oxygen deficiency and V in the third region can be reduced. Ｏ H can be reduced.

[0261] Before forming the insulating film that will become the insulating layer 250, at least one of the microwave treatment and the second treatment described in Embodiment 1 can be performed to create an i-type or substantially i-type third region of the semiconductor layer 230. When performing both the microwave treatment and the second treatment, the semiconductor layer 230 may be formed first, followed by the microwave treatment and then the second treatment, or the second treatment and then the microwave treatment.

[0262] It is preferable to supply a second element to a third region of the semiconductor layer 230 after it has been made i-type or substantially i-type. Plasma ion doping or ion implantation can be suitably used to supply the second element. These methods allow for highly precise control of the concentration profile in the depth direction by the ion acceleration voltage and dose amount. Productivity can be increased by using plasma ion doping. Furthermore, the purity of the supplied impurities can be increased by using ion implantation with mass separation.

[0263] In supplying the second element, it is preferable to adjust the supply conditions so that the concentration of the second element is highest on the surface of the semiconductor layer 230, or in the portion close to the surface.

[0264] For supplying the second element, for example, a gas containing the second element can be used as the raw material. When supplying boron, typically B ２ H ６ Gas, or BF ３ One or more gases can be used. Also, when supplying phosphorus, typically pH ３ Gases can be used. Alternatively, gases obtained by diluting these source gases with noble gases can also be used.

[0265] For example, CH is used as a raw material for supplying the second element. ４ , N ２ NH ３ SiH ４ Si ２ H ６ F ２ , HF, and (C ５ H ５ ) ２Mg can be used. Furthermore, the raw material is not limited to a gas; a solid or liquid can also be heated and vaporized for use.

[0266] The supply of the second element can be controlled by setting conditions such as acceleration voltage and dose amount, taking into consideration the composition, density, and thickness of the semiconductor layer 230. Furthermore, by supplying the second element to the semiconductor layer 230 after the conductive layers 242a and 242b have been formed, the second element can be selectively supplied to the third region of the semiconductor layer 230 (region 230c in Figure 17), i.e., the channel formation region. Figure 17 schematically shows, with arrows, how the second element is supplied to the semiconductor layer 230.

[0267] The method of supplying impurities is not limited to this; for example, plasma treatment or treatment utilizing thermal diffusion by heating can also be used. In the case of plasma treatment, impurities can be supplied by generating plasma in a gas atmosphere containing the impurities to be supplied and performing plasma treatment. As the apparatus for generating the plasma, dry etching apparatus, ashing apparatus, plasma CVD apparatus, high-density plasma CVD apparatus, etc., can be used.

[0268] Next, a conductive film to form the conductive layer 260 is deposited. This conductive film can be deposited using sputtering, CVD, MBE, PLD, plating, or ALD. For example, a titanium nitride film and a tungsten film can be deposited by laminating them using the CVD method.

[0269] Next, the insulating film that will become the insulating layer 250 and the conductive film that will become the conductive layer 260 are polished by CMP treatment until the insulating layer 280 is exposed. In other words, the portions of the insulating layer and the conductive film exposed from the opening are removed. This forms the insulating layer 250 and the conductive layer 260 within the opening that reaches the semiconductor layer 230 (Figures 18A1 and 18A2).

[0270] As a result, the insulating layer 250 is provided within the opening in contact with the conductive layer 242a, the conductive layer 242b, the semiconductor layer 230, and the insulating layer 201. The conductive layer 260 is also arranged to fill the opening via the insulating layer 250. In this way, the transistor 200 is formed.

[0271] Next, an insulating layer 282 is formed on the insulating layer 250, the conductive layer 260, and the insulating layer 280. The insulating layer 282 can be formed using, for example, sputtering, CVD, MBE, PLD, or ALD. It is preferable to form the insulating layer 282 using the sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 282 can be reduced.

[0272] Here, by using the sputtering method to deposit the insulating layer 282 in an oxygen-containing atmosphere, oxygen can be added to the insulating layer 280 during film formation. This allows the insulating layer 280 to contain excess oxygen.

[0273] Next, an insulating layer 285 is formed on the insulating layer 282 (Figures 18B1 and 18B2). The insulating layer 285 can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to deposit the insulating layer 285 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 285 can be reduced.

[0274] Next, openings reaching the conductive layers 242a and 242b are formed in the insulating layer 275, insulating layer 280, insulating layer 282, and insulating layer 285, respectively. These openings can be formed using lithography. It is preferable to process the workpiece using a dry etching method when forming these openings. The shape of the openings in a top view can be a circle, an ellipse or other approximate circle, a quadrilateral or other polygon, or a quadrilateral or other polygon with rounded corners.

[0275] Next, after the opening is formed, a heat treatment can be performed. The temperature of the heat treatment can be 100°C to 600°C, preferably 250°C to 550°C, and more preferably 350°C to 450°C. The heat treatment is preferably performed in an atmosphere of nitrogen gas or an inert gas. Furthermore, since the heat treatment is performed with the conductive layer 242a and conductive layer 242b exposed, it is preferable to perform it in an atmosphere that does not contain oxidizing gases or oxygen gas. For example, it is preferable to perform the heat treatment in a nitrogen gas atmosphere at a temperature of 400°C for 1 hour. The heat treatment may also be performed under reduced pressure. The heat treatment allows oxygen contained in the insulating layer 280 to be supplied to the semiconductor layer 230 via the insulating layer 250. Furthermore, by performing the heat treatment at the stage when the opening is provided in the insulating layer 280, some of the oxygen contained in the insulating layer 280 can be released, and the amount of oxygen contained in the insulating layer 280 can be adjusted. This prevents the reliability from being compromised due to excessive oxygen.

[0276] Next, insulating films, which will become insulating layers 241a and 241b, are formed along the shape of the opening. The insulating films can be formed using sputtering, CVD, MBE, PLD, or ALD. Since the insulating films are formed in an opening with a large aspect ratio, it is preferable to form them using the ALD method. Furthermore, it is preferable to use an insulating film that has the function of suppressing oxygen permeation. For example, it is preferable to form silicon nitride using the PEALD method. Silicon nitride is preferred because it has high barrier properties against hydrogen.

[0277] Next, the insulating film is anisotropically etched to form insulating layers 241a and 241b. Here, insulating layer 241a is formed to cover the sidewall of the opening on the conductive layer 242a, and insulating layer 241b is formed to cover the sidewall of the opening on the conductive layer 242b. For the anisotropic etching of the insulating film that will become insulating layers 241a and 241b, a dry etching method or the like may be used. For example, reactive ion etching is preferred. By providing insulating layers 241a and 241b on the sidewalls of the openings, the permeation of oxygen from the outside is suppressed, and oxidation of the conductive layers 240a and 240b to be formed next can be prevented. In addition, impurities such as water and hydrogen contained in the insulating layer 280 can be prevented from diffusing into the conductive layers 240a and 240b. Note that, as a result of this anisotropic etching, recesses may be formed on a part of the upper surface of conductive layers 242a and 242b.

[0278] Next, conductive films that will become conductive layer 240a and conductive layer 240b are formed. It is desirable that the conductive films have a laminated structure that includes a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. The conductive films can be formed using sputtering, CVD, MBE, PLD, or ALD methods.

[0279] Next, a CMP treatment is performed to remove a portion of the conductive film, exposing the upper surface of the insulating layer 285 (Figures 18C1 and 18C2). As a result, the conductive film remains only in the openings, allowing for the formation of conductive layers 240a and 240b with flat upper surfaces. Note that this CMP treatment may remove a portion of the upper surface of the insulating layer 285.

[0280] Furthermore, a heat treatment may be performed after the conductive layer 240a and conductive layer 240b have been formed. The same conditions as those used for the above heat treatment can be used for this heat treatment. By performing this heat treatment, the amount of oxygen supplied to the semiconductor layer 230 can be adjusted. This can improve the electrical characteristics and reliability of the transistor 200.

[0281] Based on the above, the transistor 200 shown in Figures 3A to 3D can be manufactured.

[0282] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0283] (Embodiment 3) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor according to one aspect of the present invention.

[0284] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0285] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 19A shows silicon (Si) and indium oxide (InO Ｘ Figure 19B is a schematic diagram of the carrier concentration dependence of hole mobility with respect to IGZO.

[0286] First, as indicated by the arrows in Figure 19B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 19A, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 3). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 19A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 19A.

[0287] In Figure 19A, the range R1 with low carrier concentration exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm−３ in a range including, for example, 1×10 １４ cm −３ or more and 1×10 １８ cm −３ or less. By sufficiently reducing the carrier concentration, it can be expected that the value of the hole mobility can be increased to about 270 cm ２ / (V·s).

[0288] Incidentally, in indium oxide, the region where the carrier concentration is in the range R1 can contain an element that lowers the carrier concentration. Examples of the element that lowers the carrier concentration include magnesium, calcium, zinc, cadmium, copper, etc. By these elements substituting indium, the carrier concentration can be lowered. Also, examples of the element that lowers the carrier concentration include nitrogen, phosphorus, arsenic, antimony, etc. For example, by nitrogen, phosphorus, arsenic, or antimony substituting oxygen, the carrier concentration can be lowered.

[0289] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and it can be said that it is a suitable carrier concentration range for, for example, the source region and drain region of a transistor, or a resistor, or a transparent conductive film. The range R2 is a range including a carrier concentration value of 1×10 ２０ cm −３ or more and 1×10 １９ cm −３ or less. By sufficiently increasing the carrier concentration, it can be expected that the resistivity can be reduced to 1×10 ２２ cm −３ Ω·cm or less. −４

[0290] ​In the case of indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements whose oxides are conductive or semiconducting. As for the supply method of elements that increase the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. In this specification, unless otherwise specified, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions by mass separation is called ion implantation, and a method of supplying ions without mass separation is called ion doping.

[0291] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In contrast, with IGZO, strain can form in the source and drain regions due to stress on the electrodes in contact with IGZO, and n-type regions may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require strain to form in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 19A within the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0292] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0293] In addition, the i-type nature of a semiconductor means that the Fermi level (Ef) and the intrinsic Fermi level (Ei) are the same (Ef = Ei). As shown in Figure 19B, in IGZO, the lower the carrier concentration, the lower the hole mobility. Therefore, when Ef = Ei is reached, there are no carriers left (in other words, the material has properties similar to an insulator), and it may cease to function as a transistor. On the other hand, in indium oxide, as shown in Figure 19A, the lower the carrier concentration, the higher the hole mobility, and when Ef = Ei is reached, the hole mobility is maximized. That is, transistors containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Furthermore, because transistors containing indium oxide have a low carrier concentration, they tend to be normally off. Therefore, transistors containing indium oxide can be normally off and achieve high field-effect mobility.

[0294] Normally off refers to the state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0V. Normally off can be evaluated using the transistor's threshold voltage (Vth) or shift value (Vsh). Unless otherwise specified, Vth will be calculated using the constant current method. More specifically, Vth is the value of drain current (Id) × channel length (L) ÷ channel width (W) in the transistor's Id-Vg characteristic, where Vth is 1nA (1 × 10⁻¹⁰). −９ Let Vg be the gate voltage (Vg) when A) is true. Also, Vsh is defined as the tangent to the maximum slope when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically, and Id = 1pA (1 × 10⁻¹⁰). −１２ Vg is the gate voltage (Vg) at the intersection with line A), or the Vg at the intersection of the line extrapolated from the two points where the slope of Id is maximized when Id is expressed logarithmically in the transistor's Id-Vg characteristic, and the line where Id = 1 pA. For example, if either or both of Vth and Vsh are zero or positive values, it can be considered a normally-off transistor.

[0295] Furthermore, in transistors containing indium oxide, the film configuration in contact with the indium oxide film is crucial for making the semiconductor i-type, that is, for achieving Ef = Ei. For example, in transistors containing indium oxide, a film configuration can be obtained in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in contact with the indium oxide film. By using this film configuration, it is possible to create a semiconductor device that satisfies Ef = Ei and is highly reliable.

[0296] Furthermore, in the above film configuration, oxygen-containing films such as silicon oxide-nitride films, silicon oxide nitride films, aluminum oxide films, and gallium oxide films can be used instead of the silicon oxide film. Also, in the above film configuration, silicon oxide nitride films, silicon oxide nitride films, etc. can be used instead of the silicon nitride film. In addition, the hafnium oxide film located on the indium oxide side of the silicon nitride film functions as a hydrogen gettering site.

[0297] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using single-crystal films, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0298] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0299] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0300] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0301] The channel formation region refers to the area within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0302] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, impurities can also inhibit crystal growth in the indium oxide film. The indium oxide film preferably has an impurity concentration of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0303] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0304] Also, the indium oxide film in this specification and the like has a high film density. Here, the film density of the indium oxide film (here, In ２ O ３ ) applicable to one aspect of the present invention is shown in Table 1.

[0305]

[0306] As shown in Table 1, the film density of the indium oxide film is evaluated at six levels of Sample 1 to Sample 6. In Table 1, Condition 1 is the condition of the base of the indium oxide film. Samples 1 to 3 are glass, Sample 4 is a SiO₂ film formed by the sputtering method, and Samples 5 and 6 are yttria-stabilized zirconia (YSZ). Also, Condition 2 is the film formation condition of the indium oxide film. Samples 1 to 3 are film formation by the sputtering (SP) method, and Samples 4 to 6 are film formation by the ALD method. Also, Condition 3 is the heat treatment condition after the indium oxide film formation. Samples 1, Sample 4, and Sample 5 are without heat treatment (as-depo), Sample 2 is baked at 350 °C in a CDA atmosphere, Sample 3 is baked at 650 °C in a CDA atmosphere, and Sample 6 is baked at 250 °C in a vacuum atmosphere.

[0307] In Table 1, CDA means dry air (CDA: Clean Dry Air). The content of hydrogen, water, etc. in the atmosphere of the heat treatment (corresponding to Condition 3) after the indium oxide film formation is preferably as small as possible. As the atmosphere, it is preferable to use a high purity gas with a dew point of -60 °C or lower, preferably -100 °C or lower.

[0308] As shown in Table 1, the indium oxide film tends to have a higher film density when heat-treated compared to when it is not heat-treated (Sample 1, Sample 4, or Sample 5). This is because the heat treatment causes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) to be removed from the film, resulting in a higher purity in the indium oxide film. Furthermore, as shown in Sample 5 and Sample 6, the indium oxide film on YSZ has a film density of 7.00 g / cm³. ３ It exceeds [value]. The theoretical value of the film density of the indium oxide film is 7.18 g / cm³. ３ In this specification, the range of film density for indium oxide films is 6.70 g / cm³. ３ 7.18g / cm or more ３ The following, preferably 6.90 g / cm³ ３ 7.18g / cm or more ３ The following, and more preferably 7.00 g / cm³ ３ 7.18g / cm or more ３ The following applies:

[0309] Furthermore, film density can be evaluated using methods such as Rutherford backscattering (RBS) or X-ray reflectivity (XRR). Differences in film density can sometimes be evaluated using transmission electron microscopy (TEM) images of the cross-section. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a fainter (brighter) transmission electron (TE) image.

[0310] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0311] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 19C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. Ｏ If oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0312] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0313] Furthermore, as shown in Figure 19C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２ It is released as ) or by reacting with oxygen contained in the film, and released as water molecules. The above-mentioned oxygen and hydrogen diffuse through the indium oxide film by heat treatment. The temperature of the heat treatment is 200°C to 700°C, preferably 350°C to 650°C, and more preferably 400°C to 500°C.

[0314] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0315] Table 2 shows single crystal indium oxide (here, In ２ O ３The effective masses of indium oxide and single-crystal silicon (Si) are shown below. As shown in Table 2, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Furthermore, as shown in Table 2, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0316]

[0317] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0318] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0319] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0320] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0321] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７An example of a crystal with a crystalline structure is IGZO. Indium oxide single crystal films can be formed not only on YSZ substrates but also on insulating films. On the other hand, it is difficult to form silicon single crystal films on insulating films. Silicon crystals have a diamond structure. Thus, in terms of single crystals, indium oxide and silicon have similar properties. However, when comparing indium oxide and silicon from the perspective of whether single crystals can be formed on insulating films, they have different properties.

[0322] Here, we compare transistors with crystalline indium oxide films, transistors with IGZO (In, Ga, Zn compound oxide) films, and transistors with silicon (Si) films. This comparison is shown in Table 3.

[0323]

[0324] In Table 3, transistors with a crystalline indium oxide film are explicitly labeled as "Crystal IO (LSI)" for LSI applications. Hereafter, they may simply be referred to as "Crystal IO". Transistors with a Si film are explicitly labeled as "Si (LSI)" for LSI applications. Hereafter, they may simply be referred to as "Si". Transistors with an IGZO film are explicitly labeled as "IGZO (Display)" for Display applications. Hereafter, they may simply be referred to as "IGZO". In Table 3, ◎ represents +2 points, ○ represents +1 point, △ represents 0 points, and × represents -1 point. Total is the sum of the points for ◎, ○, △, and × shown in Table 3. A higher point value indicates better performance than a lower point value.

[0325] In Table 3, the first comparison item is minimal off-current, in which crystalline IO and IGZO are superior to Si. The second comparison item is on-current (Ion) characteristics, in which Si, crystalline IO, and IGZO have the highest characteristics. The third comparison item is reliability, in which crystalline IO and Si are superior to IGZO. The fourth comparison item is channel length miniaturization, in which crystalline IO and IGZO are superior to Si. In the channel length miniaturization item, VFET represents a vertical transistor, UFET represents a U-shaped transistor, and 3D structure represents a three-dimensional structure. The fifth comparison item is cutoff frequency, in which crystalline IO and Si are superior to IGZO. The sixth comparison item is improved integration density, in which Si is superior to crystalline IO and IGZO. Furthermore, the seventh comparison item is threshold voltage controllability (Vth controllability), in which Si is superior to crystalline IO and IGZO. The eighth comparison item is radiation resistance, in which crystalline IO and IGZO are superior to Si. The ninth comparison item is 3D (multi-stage) integrated structure, in which crystalline IO and IGZO are superior to Si. The tenth comparison item is the potential for self-heating, in which crystalline IO and IGZO are superior to Si.

[0326] As shown in Table 3, the total score is 8 points for crystalline IO (LSI), and 4 points each for Si (LSI) and IGZO (Display). Thus, a semiconductor device according to one aspect of the present invention, particularly a semiconductor device having a crystalline indium oxide film, has the potential to replace semiconductor devices using Si.

[0327] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0328] (Embodiment 4) In this embodiment, a memory device according to one aspect of the present invention will be described with reference to Figures 20 to 23. In this embodiment, an example of the configuration of a memory device in which a layer having memory cells is stacked on a layer on which a drive circuit including a sense amplifier is provided will be described.

[0329] The transistors in the memory cells exemplified below can be the same type of transistor (referred to as an OS transistor) exemplified in Embodiment 2, in which a channel is formed in a single-crystal oxide semiconductor.

[0330] <Example of Storage Device Configuration> Figure 20 shows a block diagram illustrating an example of the configuration of a storage device 480 according to one aspect of the present invention. The storage device 480 shown in Figure 20 has a layer 420 and a stacked layer 470.

[0331] Layer 420 is a layer having Si transistors. In layer 470, element layers 430[1] to 430[m] (where m is an integer of 2 or more) are stacked. Element layers 430[1] to 430[m] are layers having OS transistors. Layer 470, in which layers having OS transistors are stacked, can be stacked on top of layer 420.

[0332] The elements in the element layers 430[1] to 430[m], such as OS transistors and capacitive elements, constitute memory cells. Figure 20 shows an example in which the element layers 430[1] to 430[m] have a plurality of memory cells 432 arranged in a matrix of m rows and n columns (where n is an integer of 2 or more).

[0333] In Figure 20, the memory cell 432 in the first row and first column is shown as memory cell 432[1,1], and the memory cell 432 in the mth row and nth column is shown as memory cell 432[m,n]. In this embodiment, an arbitrary row may be referred to as row i, and an arbitrary column may be referred to as column j. Therefore, i is an integer between 1 and m, and j is an integer between 1 and n. In this embodiment, the memory cell 432 in the ith row and jth column is shown as memory cell 432[i,j]. In this embodiment, when "i + α" (where α is a positive or negative integer) is used, "i + α" is not less than 1 and not greater than m. Similarly, when "j + α" is used, "j + α" is not less than 1 and not greater than n.

[0334] Figure 20 also illustrates, as an example, m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment, the first wiring WL (first row) is denoted as wiring WL[1], and the mth wiring WL (mth row) is denoted as wiring WL[m]. Similarly, the first wiring PL (first row) is denoted as wiring PL[1], and the mth wiring PL (mth row) is denoted as wiring PL[m]. Similarly, the first wiring BL (first column) is denoted as wiring BL[1], and the nth wiring BL (nth column) is denoted as wiring BL[n]. Note that the number of layers of element layers 430[1] to 430[m] and the number of wirings WL (and wirings PL) do not have to be the same.

[0335] Multiple memory cells 432 located in row i are electrically connected to the wiring WL (wiring WL[i]) and wiring PL (wiring PL[i]) in row i. Multiple memory cells 432 located in column j are electrically connected to the wiring BL (wiring BL[j]) in column j.

[0336] Wiring BL functions as a bit line for writing and reading data. Wiring WL functions as a word line for controlling the on or off state (conductive or non-conductive) of the access transistor, which functions as a switch. Wiring PL functions as a constant potential line connected to the capacitor. A separate wire can be provided to transmit the back gate potential.

[0337] The memory cells 432 in each of the element layers 430[1] to 430[m] are connected to the sense amplifier 446 via wiring BL. The wiring BL can be arranged in the parallel and perpendicular directions to the substrate surface on which layer 420 is provided. By configuring the wiring BL extending from the memory cells 432 in the element layers 430[1] to 430[m] with wiring arranged vertically in addition to wiring arranged horizontally on the substrate surface, the length of the wiring between the element layer 430 and the sense amplifier 446 can be shortened. The signal propagation distance between the memory cell and the sense amplifier can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thus reducing power consumption and signal delay. As a result, the power consumption and signal delay of the memory device 480 can be reduced. Furthermore, it becomes possible to operate even if the capacitance of the capacitor in the memory cell 432 is reduced. As a result, the memory device 480 can be miniaturized.

[0338] Layer 420 includes a PSW 471 (power switch), a PSW 472, and peripheral circuits 422. Peripheral circuits 422 include a drive circuit 440, a control circuit 473, and a voltage generation circuit 474. Each circuit in layer 420 is a circuit containing a Si transistor.

[0339] In the storage device 480, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0340] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 473.

[0341] The control circuit 473 is a logic circuit that has the function of controlling the overall operation of the storage device 480. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode of the storage device 480 (e.g., write operation, read operation). Alternatively, the control circuit 473 generates a control signal for the drive circuit 440 so that this operating mode is executed.

[0342] The voltage generation circuit 474 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 474. For example, when a high-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 474, and the voltage generation circuit 474 generates a negative voltage.

[0343] The drive circuit 440 is a circuit for writing and reading data to and from the memory cell 432. The drive circuit 440 includes a row decoder 442, a column decoder 444, a row driver 443, a column driver 445, an input circuit 447, an output circuit 448, and the aforementioned sense amplifier 446.

[0344] The row decoder 442 and column decoder 444 have the function of decoding the ADDR signal. The row decoder 442 is a circuit for specifying the row to access, and the column decoder 444 is a circuit for specifying the column to access. The row driver 443 has the function of selecting the wiring WL specified by the row decoder 442. The column driver 445 has the function of writing data to the memory cell 432, reading data from the memory cell 432, and holding the read data.

[0345] The input circuit 447 has the function of holding the signal WDA. The data held by the input circuit 447 is output to the column driver 445. The output data of the input circuit 447 is the data (Din) to be written to the memory cell 432. The data (Dout) read by the column driver 445 from the memory cell 432 is output to the output circuit 448. The output circuit 448 has the function of holding Dout. The output circuit 448 also has the function of outputting Dout to the outside of the storage device 480. The data output from the output circuit 448 is the signal RDA.

[0346] PSW 471 has the function of controlling the supply of VDD to the peripheral circuit 422. PSW 472 has the function of controlling the supply of VHM to the row driver 443. Here, the high power supply potential of the storage device 480 is VDD, and the low power supply potential is GND (ground potential). VHM is a high power supply potential used to raise the word line to a high level, and is higher than VDD. The on / off state of PSW 471 is controlled by signal PON1, and the on / off state of PSW 472 is controlled by signal PON2. In Figure 20, the number of power supply domains to which VDD is supplied in the peripheral circuit 422 is set to 1, but it can be multiple. In this case, a power switch can be provided for each power supply domain.

[0347] The element layers 430[1] to 430[m] can be layered on top of layer 420. Figure 21A shows a perspective view of a memory device 480 in which five layers (m=5) of element layers 430[1] to 430[5] are layered on top of layer 420.

[0348] In Figure 21A, the element layer 430 provided as the first layer is shown as element layer 430[1], the element layer 430 provided as the second layer is shown as element layer 430[2], and the element layer 430 provided as the fifth layer is shown as element layer 430[5]. Also in Figure 21A, wiring WL and wiring PL extending in the X direction, and wiring BL and wiring BLB extending in the Y direction and Z direction (directions perpendicular to the substrate surface on which the drive circuit is provided) are shown. Wiring BLB is an inverting bit line. Note that, in order to make the drawing easier to read, some of the wiring WL and wiring PL of each element layer 430 have been omitted from the description.

[0349] Figure 21B shows a schematic diagram illustrating an example configuration of the wiring BL and sense amplifier 446 connected to the wiring BLB shown in Figure 21A, and the memory cells 432 having element layers 430[1] to 430[5] connected to the wiring BL and wiring BLB. A configuration in which multiple memory cells (memory cells 432) are electrically connected to one wiring BL and wiring BLB is also called a "memory string".

[0350] Figure 21B illustrates an example of the circuit configuration of a memory cell 432 connected to wiring BLB. The memory cell 432 has a transistor 437 and a capacitive element 438. The transistor 437, the capacitive element 438, and each wiring (BL, WL, etc.) may also be referred to as wiring BL[1] and wiring WL[1], for example, wiring BL and wiring WL.

[0351] In the memory cell 432, either the source or drain of transistor 437 is connected to wiring BL. The other source or drain of transistor 437 is connected to one electrode of capacitive element 438. The other electrode of capacitive element 438 is connected to wiring PL. The gate of transistor 437 is connected to wiring WL.

[0352] The wiring PL provides a constant potential to maintain the potential of the capacitive element 438. By connecting multiple wiring PLs together and using them as a single wire, the number of wires can be reduced.

[0353] In one aspect of the present invention, OS transistors are stacked, and wiring that functions as bit lines is arranged perpendicular to the substrate surface on which layer 420 is provided. In addition, the transistors 437 and capacitive elements 438 of the memory cell 432 are arranged in a parallel direction perpendicular to the substrate surface on which layer 420 is provided. By providing each element and each wiring perpendicular to the substrate surface, the length of the wiring between element layers can be shortened, and the density of elements provided per unit area can be increased. Therefore, a memory device with excellent memory capacity and reduced power consumption can be obtained.

[0354] [Example Configuration of Memory Cell 432 and Sense Amplifier 446] Figures 22A and 22B show the circuit diagram corresponding to the memory cell 432 described above, and the circuit block diagram corresponding to the said circuit diagram. As shown in Figures 22A and 22B, the memory cell 432 may be represented as a block in drawings, etc. Note that the wiring BL shown in Figures 22A and 22B can be similarly represented when replaced with wiring BLB.

[0355] Furthermore, Figures 22C and 22D show the circuit diagram corresponding to the sense amplifier 446 described above, and the circuit block diagram corresponding to said circuit diagram. The sense amplifier 446 includes a switch circuit 482, a precharge circuit 483, a precharge circuit 484, and an amplification circuit 485. In addition to wiring BL and wiring BLB, wiring SA_OUT and wiring SA_OUTB, which output the readout signal, are also shown.

[0356] As shown in Figure 22C, the switch circuit 482 includes, for example, N-type transistors 482_1 and 482_2. The N-type transistors 482_1 and 482_2 switch the conduction state of the wiring pair SA_OUT and SA_OUTB, and the wiring pair BL and BLB, according to the signal CSEL.

[0357] As shown in Figure 22C, the pre-charge circuit 483 is composed of N-type transistors 483_1 to 483_3. The pre-charge circuit 483 is a circuit for pre-charging wiring BL and wiring BLB to an intermediate potential VPRE corresponding to the potential VDD / 2, in accordance with the signal EQ.

[0358] As shown in Figure 22C, the pre-charge circuit 484 is composed of P-type transistors 484_1 to 484_3. The pre-charge circuit 484 is a circuit for pre-charging wiring BL and wiring BLB to an intermediate potential VPRE corresponding to the potential VDD / 2, in accordance with the signal EQB.

[0359] As shown in Figure 22C, the amplification circuit 485 consists of P-type transistors 485_1 and 485_2 and N-type transistors 485_3 and 485_4 connected to wiring SAP or wiring SAN. Wiring SAP or wiring SAN is wiring that has the function of providing VDD or VSS. The P-type transistors 485_1 and 485_2 and N-type transistors 485_3 and 485_4 are transistors that constitute an inverter loop.

[0360] Furthermore, Figure 22D shows a circuit block diagram corresponding to the sense amplifier 446 described in Figure 22C, etc. As shown in Figure 22D, the sense amplifier 446 may be represented as a block in drawings, etc.

[0361] Figure 23 is a circuit diagram of the storage device 480 shown in Figure 20. Figure 23 illustrates the circuit blocks described in Figures 22A to 22D.

[0362] As shown in Figure 23, the layer 470, which includes the element layer 430 [m], has memory cells 432. The memory cells 432 shown in Figure 23 are connected, for example, to a pair of wiring BL[1] and wiring BLB[1], or wiring BL[2] and wiring BLB[2]. The memory cells 432 connected to wiring BL are memory cells on which data is written or read.

[0363] Wiring BL[1] and wiring BLB[1] are connected to sense amplifier 446[1], and wiring BL[2] and wiring BLB[2] are connected to sense amplifier 446[2]. Sense amplifiers 446[1] and 446[2] can read data according to the various signals described in Figure 22C.

[0364] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0365] (Embodiment 5) This embodiment describes an example of the configuration of a display device to which a transistor according to one aspect of the present invention can be applied.

[0366] Since the transistor according to one aspect of the present invention can be made extremely small, a display device to which the transistor according to one aspect of the present invention is applied can be an extremely high-resolution display device. For example, the display device according to one aspect of the present invention can be used in the display section of information terminals (wearable devices) such as wristwatches and bracelets, and in the display section of head-mounted displays (HMDs) such as VR devices such as head-mounted displays and AR devices such as glasses.

[0367] In one embodiment of the present invention, a display device can be provided with a drive circuit and a pixel circuit stacked on top of each other. In this case, the transistors constituting the pixels can be transistors in which channels are formed in a single-crystal oxide semiconductor, as exemplified in Embodiment 2.

[0368] [Display Module] Figure 24A shows a perspective view of the display module 580. The display module 580 includes a display device 500A and an FPC 590.

[0369] The display module 580 has substrates 591 and 592. The display module 580 has a display unit 581. The display unit 581 is an area for displaying an image.

[0370] Figure 24B shows a schematic perspective view illustrating the configuration of the substrate 591. A circuit section 582, a pixel circuit section 583 on the circuit section 582, and a pixel section 584 on the pixel circuit section 583 are stacked on the substrate 591. A terminal section 585 for connecting to the FPC 590 is provided in a portion of the substrate 591 that does not overlap with the pixel section 584. The terminal section 585 and the circuit section 582 are electrically connected by a wiring section 586, which is composed of multiple wires.

[0371] The pixel section 584 has a plurality of pixels 584a arranged periodically. An enlarged view of one pixel 584a is shown on the right side of Figure 24B. The pixel 584a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0372] The pixel circuit section 583 has a plurality of periodically arranged pixel circuits 583a. Each pixel circuit 583a is a circuit that controls the light emission of three light-emitting devices that one pixel 584a has. A single pixel circuit 583a may be configured to have three circuits that control the light emission of one light-emitting device. For example, each pixel circuit 583a may have at least one selection transistor, one current control transistor (drive transistor), and a capacitive element. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix type display panel.

[0373] The circuit section 582 has circuits for driving each pixel circuit 583a of the pixel circuit section 583. For example, it is preferable to have one or both of a gate line drive circuit and a source line drive circuit. In addition, it may have at least one of the following: an arithmetic circuit, a memory circuit, and a power supply circuit. Furthermore, transistors provided in the circuit section 582 may constitute a part of the pixel circuit 583a. That is, the pixel circuit 583a may be composed of transistors in the pixel circuit section 583 and transistors in the circuit section 582.

[0374] The FPC 590 functions as wiring for supplying video signals and power potential, etc., to the circuit section 582 from an external source. An IC may also be mounted on the FPC 590.

[0375] The display module 580 can be configured such that one or both of the pixel circuit section 583 and the circuit section 582 are superimposed on the lower side of the pixel section 584, thereby making the aperture ratio (effective display area ratio) of the display section 581 extremely high. For example, the aperture ratio of the display section 581 can be 40% or more and less than 100%, preferably 50% or more and 95%, and more preferably 60% or more and 95%. Furthermore, it is possible to arrange the pixels 584a at an extremely high density, making the resolution of the display section 581 extremely high. For example, it is preferable that the pixels 584a in the display section 581 are arranged at a density of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, with a resolution of 20000 ppi or less, or 30000 ppi or less.

[0376] Because such a display module 580 is extremely high-resolution, it is suitable for VR devices such as head-mounted displays, or AR devices such as glasses. For example, even in a configuration where the display part of the display module 580 is viewed through lenses, the display module 580 has an extremely high-resolution display part 581, so even when the display part is magnified with lenses, pixels are not visible, and a highly immersive display can be provided. Furthermore, the display module 580 is not limited to this, and is suitable for electronic devices with relatively small display parts. For example, it is suitable for the display part of wearable electronic devices such as wristwatches.

[0377] [Display device 500A] The display device 500A shown in Figure 25 has a substrate 301, a light-emitting element 110R, a light-emitting element 110G, a light-emitting element 110B, a capacitor 540, a transistor 310, and a transistor 320.

[0378] Transistor 310 is a transistor in which a channel is formed in a single-crystal substrate. Transistor 320 can be a transistor in which a channel is formed in a single-crystal oxide semiconductor, as exemplified in Embodiment 2.

[0379] Transistor 310 is a transistor having a channel formation region on a substrate 301. As the substrate 301, for example, a semiconductor substrate such as a single crystal silicon substrate can be used. Transistor 310 has a part of the substrate 301, a conductive layer 311, a low resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low resistance region 312 is a region in which the substrate 301 is doped with impurities and functions as one of the source or the drain. The insulating layer 314 is provided to cover the side surface of the conductive layer 311.

[0380] Also, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301.

[0381] Transistor 320 has a semiconductor layer 351, an insulating layer 353, a conductive layer 354, a pair of conductive layers 355, an insulating layer 356, and a conductive layer 357.

[0382] An insulating layer 352 is provided on the layer where the transitor 310 is provided via a wiring layer 316 and an interlayer insulating layer. The insulating layer 352 functions as a barrier layer that prevents impurities from diffusing into the transitor 320 from the substrate 301 side and prevents oxygen from desorbing from the semiconductor layer 351 to the insulating layer 352 side. As the insulating layer 352, for example, a film in which hydrogen or oxygen diffuses less easily than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

[0383] A conductive layer 357 is provided on the insulating layer 352, and an insulating layer 356 is provided to cover the conductive layer 357. The conductive layer 357 functions as the second gate electrode of the transitor 320, and a part of the insulating layer 356 functions as the second gate insulating layer. It is preferable to use an oxide insulating film such as a silicon oxide film in at least the region of the insulating layer 356 that contacts the semiconductor layer 351. The upper surface of the insulating layer 356 is preferably flattened.

[0384] The semiconductor layer 351 is provided on the insulating layer 356. Preferably, the semiconductor layer 351 has a metal oxide (also called an oxide semiconductor) film that exhibits semiconductor properties. A pair of conductive layers 355 are provided in contact with the semiconductor layer 351 and function as a source electrode and a drain electrode.

[0385] An insulating layer 358 and an insulating layer 350 are provided to cover the top and side surfaces of the pair of conductive layers 355, as well as the side surfaces of the semiconductor layer 351. The insulating layer 358 functions as a barrier layer to prevent impurities such as water or hydrogen from diffusing into the semiconductor layer 351 and to prevent oxygen from detaching from the semiconductor layer 351. An insulating film similar to that used for the insulating layer 352 can be used for the insulating layer 358.

[0386] The insulating layer 358 and the insulating layer 350 are provided with openings that reach the semiconductor layer 351. An insulating layer 353 in contact with the upper surface of the semiconductor layer 351 and a conductive layer 354 are embedded inside these openings. The conductive layer 354 functions as a first gate electrode, and the insulating layer 353 functions as a first gate insulating layer.

[0387] The upper surfaces of the conductive layer 354, the insulating layer 353, and the insulating layer 350 are flattened so that their heights are the same, and an insulating layer 359 is provided covering them. The insulating layer 359 functions as a barrier layer to prevent impurities such as water or hydrogen from diffusing into the transistor 320. An insulating film similar to that used for the insulating layer 352 can be used for the insulating layer 359.

[0388] The transistor 320 employs a configuration in which a semiconductor layer on which a channel is formed is sandwiched between two gates. The transistor may be driven by connecting the two gates and supplying them with the same signal. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential to control the threshold voltage to one of the two gates and a potential to drive the other gate.

[0389] An insulating layer 564 is provided on the insulating layer 359. The insulating layer 564 functions as an interlayer insulating layer.

[0390] The plug 574, which is electrically connected to one side of the conductive layer 355, is provided so as to be embedded in the insulating layer 564, insulating layer 359, insulating layer 350, and insulating layer 358. Here, it is preferable that the plug 574 has a conductive layer 574a that covers the side surface of the opening in the insulating layer 564, etc., and a part of the upper surface of the conductive layer 355, and a conductive layer 574b that is in contact with the upper surface of the conductive layer 574a. In this case, it is preferable to use a conductive material that does not easily allow oxygen to diffuse as the conductive layer 574a.

[0391] Furthermore, a capacitor 540 is provided on the insulating layer 564. The capacitor 540 has a conductive layer 541, a conductive layer 545, and an insulating layer 543 located between them. The conductive layer 541 functions as one electrode of the capacitor 540, the conductive layer 545 functions as the other electrode of the capacitor 540, and the insulating layer 543 functions as the dielectric of the capacitor 540.

[0392] The conductive layer 541 is embedded in an insulating layer 554 provided on an insulating layer 564. The conductive layer 541 is electrically connected to the conductive layer 355 of the transistor 320 by a plug 574. The insulating layer 543 is provided covering the conductive layer 541. The conductive layer 545 is provided in the region that overlaps with the conductive layer 541 via the insulating layer 543.

[0393] An insulating layer 555a is provided covering the capacitance 540, an insulating layer 555b is provided on top of the insulating layer 555a, and an insulating layer 555c is provided on top of the insulating layer 555b.

[0394] Insulating layers 555a, 555b, and 555c can each preferably be made of inorganic insulating films. For example, it is preferable to use silicon oxide films for insulating layers 555a and 555c, and silicon nitride films for insulating layer 555b. This allows insulating layer 555b to function as an etching protective film. In this embodiment, an example is shown in which a part of insulating layer 555c is etched and a recess is formed, but the insulating layer 555c does not necessarily have to have a recess.

[0395] A light-emitting element 110R, a light-emitting element 110G, and a light-emitting element 110B are provided on the insulating layer 555c.

[0396] The light-emitting element 110R has a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting elements 110R, 110G, and 110B. Note that the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B are sometimes collectively referred to as the pixel electrode 111.

[0397] The organic layer 112R of the light-emitting element 110R contains at least a luminescent organic compound that emits red light. The organic layer 112G of the light-emitting element 110G contains at least a luminescent organic compound that emits green light. The organic layer 112B of the light-emitting element 110B contains at least a luminescent organic compound that emits blue light. The organic layers 112R, 112G, and 112B can each also be called EL layers and each contains at least a luminescent organic compound (luminescent layer).

[0398] The display device 500A has different light-emitting devices for each light-emitting color, resulting in minimal change in chromaticity between low-brightness and high-brightness illumination. Furthermore, because the organic layers 112R, 112G, and 112B are separated, crosstalk between adjacent sub-pixels can be suppressed even in high-resolution display panels. Therefore, a display panel with high resolution and high display quality can be realized.

[0399] An insulating layer 125, a resin layer 126, and a layer 128 are provided in the region between adjacent light-emitting elements.

[0400] The pixel electrodes 111R, 111G, and 111B of the light-emitting element are electrically connected to the conductive layer 355 of the transistor 320 by plugs 556 embedded in insulating layers 555a, 555b, and 555c, a conductive layer 541 embedded in insulating layer 554, and plugs 574. The height of the upper surface of insulating layer 555c and the height of the upper surface of plug 556 are the same. Various conductive materials can be used for the plugs.

[0401] Furthermore, a protective layer 121 is provided on the light-emitting elements 110R, 110G, and 110B. The substrate 170 is bonded to the protective layer 121 by an adhesive layer 171.

[0402] There is no insulating layer covering the upper edge of the pixel electrode 111 between two adjacent pixel electrodes 111. Therefore, the spacing between adjacent light-emitting elements can be made extremely narrow. Consequently, a high-definition or high-resolution display device can be made.

[0403] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0404] (Embodiment 6) In this embodiment, an electronic device according to one aspect of the present invention will be described with reference to Figures 26A to 28G.

[0405] The electronic device of this embodiment has a display panel (display device) to which a transistor according to one aspect of the present invention is applied in the display unit. The display device according to one aspect of the present invention can be easily made high-definition and high-resolution, and can achieve high display quality. Therefore, it can be used in the display unit of various electronic devices.

[0406] Examples of electronic devices include television sets, desktop or laptop computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as other electronic devices with relatively large screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0407] In particular, a display panel according to one embodiment of the present invention is suitable for electronic devices having a relatively small display area because it can increase resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR devices such as glasses, and MR devices.

[0408] A display panel according to one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (resolution) of the display panel according to one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more. By using a display panel having either high resolution or high detail, or both, it becomes possible to further enhance the sense of presence and depth. Furthermore, there are no particular limitations on the aspect ratio of the display panel in one embodiment of the present invention. For example, the display panel can support various aspect ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0409] The electronic device of this embodiment may have sensors (including those with the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0410] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0411] An example of a wearable device that can be worn on the head will be described using FIGS. 26A to 26D. These wearable devices have one or both of the functions of displaying AR content and displaying VR content. Note that these wearable devices may have a function of displaying SR or MR content in addition to AR and VR. By having a function of displaying at least one content such as AR, VR, SR, and MR, it is possible to enhance the user's sense of immersion.

[0412] The electronic device 700A shown in FIG. 26A and the electronic device 700B shown in FIG. 26B each include a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting parts 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0413] The display panel 751 can be applied with the display panel of one aspect of the present invention. Therefore, an electronic device capable of extremely high-precision display can be obtained.

[0414] The electronic device 700A and the electronic device 700B can each project the image displayed on the display panel 751 onto the display area 756 of the optical member 753. Since the optical member 753 has translucency, the user can view the image displayed in the display area superimposed on the transmitted image viewed through the optical member 753. Therefore, the electronic device 700A and the electronic device 700B are each an electronic device capable of AR display.

[0415] The electronic device 700A and the electronic device 700B may each be provided with a camera capable of imaging the front as an imaging unit. In addition, the electronic device 700A and the electronic device 700B can each detect the orientation of the user's head by including an acceleration sensor such as a gyro sensor, and display an image corresponding to the orientation in the display area 756.

[0416] The communications unit has a wireless communication device, which can supply video signals and the like. Alternatively, instead of the wireless communication device, or in addition to the wireless communication device, it may be equipped with a connector to which a cable supplying video signals and power potential can be connected.

[0417] Furthermore, electronic devices 700A and 700B are equipped with batteries (not shown) that can be charged wirelessly, wired, or both.

[0418] The housing 721 may be equipped with a touch sensor module. The touch sensor module has the function of detecting when the outer surface of the housing 721 is touched. The touch sensor module can detect the user's tap or slide operations and perform various processes. For example, a tap operation can be used to pause or resume the video, and a slide operation can be used to fast forward or rewind. Furthermore, by providing a touch sensor module in each of the two housings 721, the range of operations can be expanded.

[0419] Various types of touch sensors can be applied to the touch sensor module. For example, various methods such as capacitive, resistive, infrared, electromagnetic induction, surface acoustic wave, and optical sensors can be used. In particular, it is preferable to apply a capacitive or optical sensor to the touch sensor module.

[0420] When using an optical touch sensor, a photoelectric conversion device (also called a photoelectric element) can be used as the light-receiving device (also called a photoelectric element). The active layer of the photoelectric conversion device can be made of either an inorganic semiconductor or an organic semiconductor, or both.

[0421] The electronic device 800A shown in Figure 26C and the electronic device 800B shown in Figure 26D each include a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0422] A display panel according to one embodiment of the present invention can be applied to the display unit 820. Therefore, an electronic device capable of displaying extremely high resolution can be created. This allows the user to experience a high level of immersion.

[0423] The display unit 820 is located inside the housing 821 in a position visible through the lens 832. Furthermore, by displaying different images on a pair of display units 820, a three-dimensional display using parallax can be achieved.

[0424] Electronic devices 800A and 800B can each be described as electronic devices for VR. A user wearing electronic device 800A or electronic device 800B can view the image displayed on the display unit 820 through the lens 832.

[0425] It is preferable that electronic devices 800A and 800B each have a mechanism that allows adjustment of the left and right positions of the lens 832 and the display unit 820 so that they are in the optimal position according to the user's eye position. It is also preferable that they have a mechanism that adjusts the focus by changing the distance between the lens 832 and the display unit 820.

[0426] The attachment portion 823 allows the user to attach the electronic device 800A or 800B to their head. While the attachment portion 823 is exemplified in Figure 26C and other figures as resembling the temples (or arms) of eyeglasses, it is not limited to this. The attachment portion 823 only needs to be wearable by the user; for example, it may be helmet-shaped or band-shaped.

[0427] The imaging unit 825 has the function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, multiple cameras may be provided to accommodate multiple angles of view, such as telephoto and wide-angle.

[0428] Although an example with an imaging unit 825 is shown here, any distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object can be provided. In other words, the imaging unit 825 is one form of the detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as LiDAR (Light Detection and Ranging) can be used. By using the image obtained by the camera and the image obtained by the distance image sensor, more information can be acquired, enabling more accurate gesture control.

[0429] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, housing 821, and mounting unit 823. This allows users to enjoy video and audio simply by wearing the electronic device 800A, without needing separate audio equipment such as headphones, earphones, or speakers.

[0430] Electronic devices 800A and 800B may each have input terminals. Cables can be connected to the input terminals to supply video signals from video output devices, etc., and power for charging batteries provided in the electronic devices.

[0431] An electronic device according to one aspect of the present invention may have a function for wireless communication with an earphone 750. The earphone 750 has a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., voice data) from the electronic device through its wireless communication function. For example, the electronic device 700A shown in Figure 26A has a function for transmitting information to the earphone 750 through its wireless communication function. Also, for example, the electronic device 800A shown in Figure 26C has a function for transmitting information to the earphone 750 through its wireless communication function.

[0432] Furthermore, the electronic device may have an earphone section. The electronic device 700B shown in Figure 26B has an earphone section 727. For example, the earphone section 727 and the control unit can be connected to each other by wire. Part of the wiring connecting the earphone section 727 and the control unit may be located inside the housing 721 or the mounting section 723.

[0433] Similarly, the electronic device 800B shown in Figure 26D has an earphone unit 827. For example, the earphone unit 827 and the control unit 824 can be connected to each other by wire. Part of the wiring connecting the earphone unit 827 and the control unit 824 may be located inside the housing 821 or the mounting unit 823. Also, the earphone unit 827 and the mounting unit 823 may have magnets. This allows the earphone unit 827 to be fixed to the mounting unit 823 by magnetic force, which is preferable as it facilitates storage.

[0434] Furthermore, the electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have an audio input terminal and / or an audio input mechanism. For example, a sound-collecting device such as a microphone can be used as the audio input mechanism. By having an audio input mechanism, the electronic device may be given the function of a so-called headset.

[0435] Thus, as one embodiment of the present invention, both eyeglass-type (electronic devices 700A and 700B, etc.) and goggle-type (electronic devices 800A and 800B, etc.) are preferred as electronic devices.

[0436] The electronic device 6500 shown in Figure 27A is a portable information terminal that can be used as a smartphone.

[0437] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The display unit 6502 has a touch panel function. The control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be applied to the display unit 6502, the control device 6509, etc. Using a semiconductor device according to one aspect of the present invention as the control device 6509 is preferable because it can reduce power consumption.

[0438] A display panel according to one embodiment of the present invention can be applied to the display unit 6502.

[0439] Figure 27B is a schematic cross-sectional view of the housing 6501 including the end on the microphone 6506 side.

[0440] A light-transmitting protective member 6510 is provided on the display side of the housing 6501, and the display panel 6511, optical member 6512, touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged in the space enclosed by the housing 6501 and the protective member 6510.

[0441] The protective member 6510 is fixed to the display panel 6511, the optical member 6512, and the touch sensor panel 6513 by an adhesive layer (not shown).

[0442] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back, and the FPC 6515 is connected to this folded portion. IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to terminals provided on the printed circuit board 6517.

[0443] A display device according to one embodiment of the present invention can be applied to the display panel 6511. As a result, an extremely lightweight electronic device can be realized. Furthermore, because the display panel 6511 is extremely thin, a large-capacity battery 6518 can be installed while keeping the thickness of the electronic device low. In addition, by folding back a part of the display panel 6511 and placing the connection part with the FPC 6515 on the back of the pixel section, an electronic device with a narrow bezel can be realized.

[0444] Figure 27C shows an example of a television system. The television system 7100 has a display unit 7000 incorporated into a housing 7101. Here, the housing 7101 is shown to be supported by a stand 7103.

[0445] The television device 7100 shown in Figure 27C can be operated using the operation switches on the housing 7101 and a separate remote control unit 7111. Alternatively, the display unit 7000 may be equipped with a touch sensor, and the television device 7100 can be operated by touching the display unit 7000 with a finger or the like. The remote control unit 7111 may have a display unit that displays information output from the remote control unit 7111. Channels and volume can be controlled and the image displayed on the display unit 7000 can be controlled using the operation keys or touch panel on the remote control unit 7111.

[0446] The television system 7100 is configured to include a receiver and a modem. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0447] Figure 27D shows an example of a notebook computer. The notebook computer 7200 includes a casing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, etc. A display unit 7000 is incorporated into the casing 7211. The control device 7216 has one or more components selected from, for example, a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be applied to the display unit 7000, the control device 7216, etc. Using a semiconductor device according to one aspect of the present invention as the control device 7216 is preferable because it can reduce power consumption.

[0448] Figures 27E and 27F show examples of digital signage.

[0449] The digital signage 7300 shown in Figure 27E includes a housing 7301, a display unit 7000, and a speaker 7303, etc. Furthermore, it may include LED lamps, operation keys (including a power switch or operation switch), connection terminals, various sensors, a microphone, etc.

[0450] Figure 27F shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 has a display unit 7000 that is provided along the curved surface of the column 7401.

[0451] The larger the display area 7000, the more information can be provided at once. Furthermore, a larger display area 7000 is more eye-catching, which can, for example, enhance the effectiveness of advertising.

[0452] Applying a touch panel to the display unit 7000 is preferable because it not only allows images or videos to be displayed on the display unit 7000, but also enables intuitive operation by the user. Furthermore, when used for purposes such as providing route information or traffic information, intuitive operation can enhance usability.

[0453] Furthermore, as shown in Figures 27E and 27F, it is preferable that the digital signage 7300 or digital signage 7400 can be linked wirelessly with an information terminal 7311 or information terminal 7411 such as a smartphone owned by the user. For example, the advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or information terminal 7411. Also, the display on the display unit 7000 can be switched by operating the information terminal 7311 or information terminal 7411.

[0454] Furthermore, the digital signage 7300 or digital signage 7400 can be used to run games using the screen of the information terminal 7311 or information terminal 7411 as the control device (controller). This allows an unspecified number of users to participate in and enjoy the game simultaneously.

[0455] In Figures 27C to 27F, a display panel according to one embodiment of the present invention can be applied to the display unit 7000.

[0456] The electronic device shown in Figures 28A to 28G includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), connection terminals 9006, a sensor 9007 (including a function to detect, identify, or measure force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation), a microphone 9008, and the like.

[0457] The electronic devices shown in Figures 28A to 28G have various functions. For example, they may have functions to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to control processing by various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. However, the functions of electronic devices are not limited to these and can have various functions. Electronic devices may have multiple display units. Furthermore, electronic devices may be equipped with a camera, etc., and have functions to capture still images or videos and save them to a recording medium (external or built into the camera), a function to display the captured images on a display unit, etc.

[0458] Details of the electronic equipment shown in Figures 28A to 28G will be explained below.

[0459] Figure 28A is a perspective view showing a personal digital information terminal (PDI) 9101. The PDI 9101 can be used, for example, as a smartphone. The PDI 9101 may also be equipped with a speaker 9003, connection terminals 9006, sensors 9007, etc. Furthermore, the PDI 9101 can display text and image information on multiple surfaces. Figure 28A shows an example where three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of incoming emails, SNS messages, and phone calls, the subject of an email or SNS message, the sender's name, date and time, battery level, and signal strength. Alternatively, icons 9050 or the like may be displayed in the location where the information 9051 is displayed.

[0460] Figure 28B is a perspective view showing a personal digital assistant (PDA) 9102. The PDA 9102 has the function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user can check information 9053, which is displayed in a position that can be observed from above the PDA 9102, while the PDA 9102 is stored in the breast pocket of their clothing. The user can check the display without taking the PDA 9102 out of their pocket and decide, for example, whether or not to answer a call.

[0461] Figure 28C is a perspective view showing the tablet terminal 9103. The tablet terminal 9103 can run various applications, such as mobile phone calls, email, document viewing and creation, music playback, internet communication, and computer games. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the housing 9000. The left side of the housing 9000 has operation keys 9005 as buttons for operation, and the bottom has connection terminals 9006.

[0462] Figure 28D is a perspective view showing a wristwatch-type personal information terminal 9200. The personal information terminal 9200 can be used, for example, as a smartwatch (registered trademark). The display unit 9001 has a curved display surface, allowing it to display information along the curved surface. The personal information terminal 9200 can also make hands-free calls by communicating with, for example, a wireless communication headset. Furthermore, the personal information terminal 9200 can transmit data to other information terminals and be charged via a connection terminal 9006. The charging operation may be performed by wireless power supply.

[0463] Figures 28E to 28G are perspective views showing a foldable portable information terminal 9201. Figure 28E shows the portable information terminal 9201 in an unfolded state, Figure 28G shows it in a folded state, and Figure 28F shows a perspective view of the state in between, transitioning from one of Figures 28E or 28G to the other. The portable information terminal 9201 offers excellent portability in its folded state and excellent readability of the display due to its seamless, wide display area in its unfolded state. The display unit 9001 of the portable information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a radius of curvature of 0.1 mm to 150 mm.

[0464] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0465] (Embodiment 7) This embodiment describes an application example of a semiconductor device according to one aspect of the present invention. A semiconductor device according to one aspect of the present invention can be used, for example, in electronic components, electronic devices, large computers, space equipment, and data centers (also referred to as Data Centers: DCs). Electronic components, electronic devices, large computers, space equipment, and data centers using a semiconductor device according to one aspect of the present invention are effective in achieving high performance, such as low power consumption.

[0466] Electronic components and the like to which a semiconductor device according to one embodiment of the present invention is applied can be applied to the electronic equipment exemplified in Embodiment 6.

[0467] [Electronic Components] Figure 29A shows a perspective view of a substrate (mounted substrate 704) on which electronic components 700 are mounted. The electronic component 700 shown in Figure 29A has a semiconductor device 710 inside a mold 711. Some details are omitted in Figure 29A to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 via a wire 714. The electronic component 700 is mounted on a printed circuit board 702, for example. Multiple such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounted substrate 704.

[0468] Furthermore, the semiconductor device 710 includes a drive circuit layer 715 and a storage layer 716. The storage layer 716 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 715 and the storage layer 716 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 715 and the storage layer 716, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0469] Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies using through-hole electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0470] Furthermore, it is preferable to form the multiple memory cell arrays in the memory layer 716 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or the memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 716, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0471] Furthermore, the semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0472] Next, a perspective view of the electronic component 730 is shown in Figure 29B. The electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0473] Electronic component 730 shows an example of using semiconductor device 710 as a high-bandwidth memory (HBM). Furthermore, semiconductor device 735 can be used in integrated circuits such as CPUs, GPUs (Graphics Processing Units), or FPGAs (Field Programmable Gate Arrays).

[0474] The package substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be, for example, a silicon interposer or a resin interposer.

[0475] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "redistribution board" or "intermediate board". In addition, through electrodes may be provided on the interposer 731, and these through electrodes may be used to electrically connect the integrated circuits and the package substrate 732. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0476] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires the formation of fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0477] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0478] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0479] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the semiconductor device 710 and the semiconductor device 735.

[0480] To mount the electronic component 730 onto another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. Figure 29B shows an example in which the electrodes 733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0481] The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0482] [Large-scale computer] Figure 30A shows a perspective view of the large-scale computer 5600. The large-scale computer 5600 houses multiple rack-mount type computers 5620 in rack 5610. The large-scale computer 5600 may also be referred to as a supercomputer.

[0483] Figure 30B shows a perspective view of an example of the computer 5620. The computer 5620 has a motherboard 5630. The motherboard 5630 is provided with multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into a slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0484] Figure 30C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, GPU, and memory device. The PC card 5621 has a board 5622 and connection terminals 5623, 5624, 5625, electronic component 5626, electronic component 5627, electronic component 5628, and connection terminal 5629 mounted on the board 5622. Note that Figure 30C shows components other than electronic component 5626, electronic component 5627, and electronic component 5628.

[0485] The connector 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0486] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0487] The electronic component 5626 has terminals (not shown) for inputting and outputting signals, and by inserting these terminals into a socket (not shown) on the board 5622, the electronic component 5626 and the board 5622 can be electrically connected.

[0488] Electronic components 5627 and 5628 have multiple terminals, and these terminals can be mounted to the wiring provided on board 5622 by, for example, reflow soldering. Examples of electronic component 5627 include FPGAs, GPUs, and CPUs. For example, electronic component 730 can be used as electronic component 5627. Examples of electronic component 5628 include memory devices. For example, electronic component 700 can be used as electronic component 5628.

[0489] The 5600 mainframe computer can also function as a parallel computer. By using the 5600 mainframe computer as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0490] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0491] (Embodiment 8) A semiconductor device according to one aspect of the present invention will be described. Figure 31A is a schematic perspective view of a semiconductor device 10 according to one aspect of the present invention. Figure 31B is a schematic perspective view of a part of the semiconductor device 10. Figure 32 is a schematic perspective view illustrating the configuration of the semiconductor device 10.

[0492] In Figures 31A, 31B, and 32, the semiconductor device 10 has an element layer 70 below an element layer 20 which includes a substrate 22 that is a semiconductor substrate, and a support substrate 40 above the element layer 20 via an insulating layer 41. The element layer 20 has a plurality of transistors 21 which constitute a functional circuit 11. The element layer 70 has a plurality of transistors 71 which constitute a switch circuit 15. The transistors 71 function as switches to control the conduction and non-conductivity between an external power supply line and a conductive layer 72 which functions as a power line.

[0493] The transistor exemplified in Embodiment 1 can be used for transistor 71.

[0494] The transistors 21 in the element layer 20 are formed on the front surface (also called the "first surface") of the substrate 22. The element layer 70 is formed on the back surface (the surface opposite to the front surface, also called the "second surface") of the substrate 22. Therefore, the transistors 71 in the element layer 70 are formed on the second surface of the substrate 22.

[0495] Figure 32 illustrates a functional circuit 11 consisting of a CPU 12, a GPU 13, and a memory 14.

[0496] Furthermore, the functional circuit 11 is not limited to the CPU 12, GPU 13, and memory 14, and one or more of these can be used. It is also possible to include circuits with other functions.

[0497] To improve the operating speed, mounting density, and power consumption of the semiconductor device 10, the functional circuit 11 requires miniaturization and thinning of transistors, wiring, etc., and reduction of the power supply potential. The switch circuit 15 can control the supply of voltage supplied from an external source to each circuit of the functional circuit 11, and to stop the supply. This makes it possible to stop the supply of power potential to circuits in standby mode, thereby reducing power consumption.

[0498] Furthermore, the transistors constituting the switch circuit 15 require high dielectric strength. One effective way to increase the dielectric strength of the transistors is to thicken the gate insulating film. Thus, transistors 21 and 71 require different performance characteristics. Therefore, different measures are needed to improve the characteristics of transistors 21 and 71.

[0499] Furthermore, miniaturization and thinning are required for the functional circuit 11. Therefore, if the switch circuit 15 is constructed using the same process node as the functional circuit 11, not only the routing wiring but also the wiring for supplying power (power lines) will become thinner, making it impossible to supply sufficient power to the functional circuit 11. In addition, if the wiring resistance increases due to miniaturization, voltage drop is likely to cause unevenness in the power supply potential within the functional circuit 11. To stably supply power to the functional circuit 11, it is preferable that the wiring constituting the switch circuit 15 has a lower wiring resistance than the wiring constituting the functional circuit 11. In particular, it is preferable that the wiring that functions as a power line has a lower wiring resistance than the wiring constituting the functional circuit 11. One means of reducing wiring resistance is to increase the cross-sectional area of ​​the conductive layer that functions as wiring. However, in order to increase the cross-sectional area of ​​the conductive layer, it is necessary to increase one or both of the width and height of the conductive layer. Thus, it is preferable to use different process nodes for the functional circuit 11 and the switch circuit 15.

[0500] In a semiconductor device 10 according to one aspect of the present invention, by providing the functional circuit 11 and the switch circuit 15 on different element layers, different improvement measures can be implemented in the functional circuit 11 and the switch circuit 15. Furthermore, the functional circuit 11 and the switch circuit 15 can be formed at different process nodes.

[0501] In one aspect of the present invention, a plurality of conductive layers 72 that function as power lines and a switch circuit 15 can be arranged below the functional circuit 11, thereby reducing the occupied area of ​​the semiconductor device 10. Furthermore, it is preferable that the element layer 70, which is superimposed on the element layer 20, is formed using thin-film formation techniques such as CVD or sputtering. Therefore, the transistor 71 included in the element layer 70 is preferably a thin-film transistor.

[0502] At least a portion of the multiple conductive layers 72 of the element layer 70 can function as power lines. Furthermore, if the element layer 70 has a clock signal generation circuit, at least a portion of the multiple conductive layers 72 can function as clock signal lines. It is also possible to supply either or both of the power supply and / or clock signal supplied from an external source to the functional circuit 11 of the element layer 20 via at least a portion of the multiple conductive layers 72.

[0503] For example, it is possible to manufacture a die (semiconductor chip) containing the functional circuit 11 and a die containing the switch circuit 15 separately, and then mechanically bond them together using 3D integration technology. However, with 3D integration technology, improving the alignment accuracy is difficult because the two are bonded together mechanically, and miniaturizing the bumps used to connect them is also difficult, making it difficult to narrow the pitch of the connection points. As a result, there was a challenge in shortening the wiring distance required to supply power to the necessary parts of the functional circuit 11.

[0504] According to one aspect of the present invention, an element layer 70 including a switch circuit 15 is formed on the back side of the substrate 22 using thin-film formation technology, photolithography technology, or the like. Therefore, the semiconductor device 10 according to one aspect of the present invention is a monolithically stacked semiconductor device.

[0505] By forming the element layer 70 using thin-film formation technology, high-precision alignment at the photolithography level can be achieved. Furthermore, conductive layers that function as power lines can be connected to the necessary locations of the functional circuit 11 over extremely short distances. Therefore, the necessary voltage of power can be supplied to the necessary locations of the functional circuit 11. In addition, in the semiconductor device 10 according to one aspect of the present invention, since the connection distance between the switch circuit 15 and the functional circuit 11 is short, power loss related to power transmission is reduced, and power consumption can be reduced.

[0506] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0507] 10: Semiconductor device, 11: Functional circuit, 12: CPU, 13: GPU, 14: Memory, 15: Switch circuit, 20: Element layer, 21: Transistor, 22: Substrate, 30: Semiconductor layer, 31: Oxide layer, 32: Oxide layer, 40: Support substrate, 41: Insulating layer, 50: Insulating layer, 51: Insulating layer, 60: Conductive layer, 61: Conductive layer, 70: Element layer, 71: Transistor, 72: Conductive layer, 110B: Light-emitting element, 110G: Light-emitting element, 110R: Light-emitting element, 111: Pixel electrode, 111B: Pixel electrode, 111G: Pixel electrode, 111R: Pixel electrode, 112B: Organic layer, 112G: Organic layer , 112R: Organic layer, 113: Common electrode, 114: Common layer, 121: Protective layer, 125: Insulating layer, 126: Resin layer, 128: Layer, 170: Substrate, 171: Adhesive layer, 200: Transistor, 200a: Transistor, 200b: Transistor, 200c: Transistor, 201: Insulating layer, 201_1: Insulating layer, 201_2: Insulating layer, 201_3: Insulating layer, 201_4: Insulating layer, 202: Insulating layer, 205: Conductive layer, 210: Substrate, 211: Insulating layer, 230: Semiconductor layer, 230c: Region, 230f: Semiconductor film, 230n: Region, 231: Oxide layer, 232: Oxide Physical layer, 240a: conductive layer, 240b: conductive layer, 241a: insulating layer, 241b: insulating layer, 242: conductive layer, 242a: conductive layer, 242b: conductive layer, 242f: conductive film, 245: conductive layer, 246: conductive layer, 250: insulating layer, 250_1: insulating layer, 250_2: insulating layer, 250_3: insulating layer, 250_4: insulating layer, 255: insulating layer, 260: conductive layer, 260a: conductive layer, 260b: conductive layer, 271a: insulating layer, 271b: insulating layer, 275: insulating layer, 280: insulating layer, 281: insulating layer, 282: insulating layer, 283: insulating layer, 284: insulating layer, 285: insulating layer, 29 0o: Aperture, 290s: Aperture, 301: Substrate, 310: Transistor, 311: Conductive layer, 312: Low resistance region, 313: Insulating layer, 314: Insulating layer, 315: Element isolation layer, 316: Wiring layer, 320: Transistor, 350: Insulating layer, 351: Semiconductor layer, 352: Insulating layer, 353: Insulating layer, 354: Conductive layer, 355: Conductive layer, 356: Insulating layer, 357: Conductive layer, 358: Insulating layer, 359: Insulating layer, 420: Layer, 422: Peripheral circuit, 430[1]: Element layer, 430[2]: Element layer, 430[5]: Element layer, 430[m]: Element layer, 430[m]m: Element layer,430: Element layer, 432[1,1]: Memory cell, 432[i,j]: Memory cell, 432[m,n]: Memory cell, 432: Memory cell, 437: Transistor, 438: Capacitive element, 440: Drive circuit, 442: Row decoder, 443: Row driver, 444: Column decoder, 445: Column driver, 446[1]: Sense amplifier, 446[2]: Sense amplifier, 446: Sense amplifier, 447: Input circuit, 448: Output circuit, 470: Layer, 471: PSW, 472: PSW, 473: Control circuit, 474: Voltage generation circuit, 480: Memory device, 482: S Switch circuit, 482_1: N-type transistor, 482_2: N-type transistor, 483: Pre-charge circuit, 483_1: N-type transistor, 483_3: N-type transistor, 484: Pre-charge circuit, 484_1: P-type transistor, 484_3: P-type transistor, 485: Amplifier circuit, 485_1: P-type transistor, 485_2: P-type transistor, 485_3: N-type transistor, 485_4: N-type transistor, 500A: Display device, 540: Capacitance, 541: Conductive layer, 543: Insulating layer, 545: Conductive layer, 554: Insulating layer, 555a: Insulating layer, 5 55b: insulating layer, 555c: insulating layer, 556: plug, 564: insulating layer, 574: plug, 574a: conductive layer, 574b: conductive layer, 580: display module, 581: display unit, 582: circuit unit, 583: pixel circuit unit, 583a: pixel circuit, 584: pixel unit, 584a: pixel, 585: terminal unit, 586: wiring unit, 590: FPC, 591: substrate, 592: substrate, 700: electronic component, 700A: electronic equipment, 700B: electronic equipment, 702: printed circuit board, 704: mounted board, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 71 4: Wire, 715: Drive circuit layer, 716: Memory layer, 721: Housing, 723: Mounting part, 727: Earphone part, 730: Electronic component, 731: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 750: Earphone, 751: Display panel, 753: Optical component, 756: Display area, 757: Frame, 758: Nose pad, 800A: Electronic device, 800B: Electronic device, 820: Display unit, 821: Housing, 822: Communication unit, 823: Mounting part, 824: Control unit, 825: Imaging unit, 827: Earphone part, 832: Lens, 5600: Large computer,5610: Rack, 5620: Calculator, 5621: PC Card, 5622: Board, 5623: Connector, 5624: Connector, 5625: Connector, 5626: Electronic component, 5627: Electronic component, 5628: Electronic component, 5629: Connector, 5630: Motherboard, 5631: Slot, 6500: Electronic device, 6501: Enclosure, 6502: Display unit, 6503: Power button, 6504: Button 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6509: Control device, 6510: Protective component, 6511: Display panel, 6512: Optical component, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 7000: Display unit, 7100: Television device, 7101: Housing, 7103: Stand, 711 1: Remote control unit, 7200: Notebook computer, 7211: Enclosure, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7216: Control unit, 7300: Digital signage, 7301: Enclosure, 7303: Speaker, 7311: Information terminal, 7400: Digital signage, 7401: Pillar, 7411: Information terminal, 9000: Enclosure, 9001: Front Display unit, 9002: Camera, 9003: Speaker, 9005: Operation key, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9101: Personal digital assistant, 9102: Personal digital assistant, 9103: Tablet terminal, 9200: Personal digital assistant, 9201: Personal digital assistant,

Claims

Semiconductor layer, On the semiconductor layer, there are a first conductive layer and a second conductive layer spaced apart from each other, and an insulating layer located between the first conductive layer and the second conductive layer. The insulating layer comprises a third conductive layer, The semiconductor layer comprises indium and oxygen. The semiconductor layer has a first region in contact with the first conductive layer, a second region in contact with the second conductive layer, and a third region located between the first region and the second region. The third region contains boron, A semiconductor device wherein the boron content in the third region is higher than the boron content in the first region and the boron content in the second region, respectively. 　 In claim 1, A semiconductor device having a semiconductor layer thickness of 1 nm or more and 6 nm or less. 　 In claim 1, A semiconductor device in which the shortest distance between the first conductive layer and the second conductive layer is 1 nm or more and 15 nm or less. 　 A first step of forming a semiconductor film, A second step involves forming a conductive film on the semiconductor film, A third step involves processing the semiconductor film and the conductive film into island shapes to form a semiconductor layer and a first conductive layer, A fourth step involves processing the first conductive layer to expose the upper surface of a portion of the semiconductor layer and to form a second conductive layer and a third conductive layer. A fifth step of supplying boron to a region of the semiconductor layer that does not overlap with the second conductive layer and the third conductive layer, A sixth step of forming an insulating layer on the semiconductor layer, A seventh step of forming a fourth conductive layer on the insulating layer, A method for manufacturing a semiconductor device having [a certain characteristic]. 　 In claim 4, The fifth step is a method for fabricating a semiconductor device using plasma ion doping or ion implantation. 　 In claim 4, In the first step described above, atomic layer deposition is used, The atomic layer deposition method described above is a method for fabricating a semiconductor device using an indium-containing precursor and an oxidizing agent. 　 In claim 4, In the first step described above, the sputtering method is used. The sputtering method described above uses a sputtering target containing indium and a gas containing hydrogen as the sputtering gas to manufacture a semiconductor device. 　 In claim 4, Before performing the fifth step described above, heat treatment is performed. The aforementioned heat treatment is performed at a temperature of 300°C to 700°C, in a method for manufacturing a semiconductor device.

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