Display device, electronic device, and method for producing display device

Abstract

Provided is a display device having high display quality and low power consumption. The display device comprises an organic EL element on a microlens array that is formed on an insulation layer. The organic EL element includes an EL layer that is separated for each sub-pixel using a lithography step. A negative electrode is connected to a negative electrode line via a conductive layer in a relief part that is capable of being formed using a shared step with the microlens array. For the conductive layer, a layer that is capable of being formed by a shared step with a positive electrode is used. Therefore, it is possible to simplify a step for connecting the negative electrode to the negative electrode line.

Description

Display device, electronic device, and method for manufacturing a display device.

[0001] One aspect of the present invention relates to a display device, an electronic device, and a method for manufacturing a display device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, imaging devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them. A semiconductor device refers to any device that can function by utilizing semiconductor properties.

[0003] As large-scale display devices, non-emissive displays using liquid crystals and self-emissive displays using organic EL elements or LEDs are known. Non-emissive displays can be formed with a relatively simple configuration using liquid crystal elements that control the light emitted from a light source such as a backlight.

[0004] On the other hand, self-emissive displays do not require a light source because the elements used emit light themselves, enabling the realization of thin, lightweight, high-contrast, and low-power display devices. For example, an example of a display device using organic EL elements is described in Patent Document 1.

[0005] Furthermore, in self-emissive displays, a structure is employed in which light emitted from light-emitting elements is extracted through microlenses in order to improve the efficiency of light extraction. Patent Document 2 discloses a method for forming microlenses using a radiation-sensitive resin composition.

[0006] Japanese Patent Publication No. 2018-107444 Japanese Patent Publication No. 2020-101659

[0007] Takashi Koida, "High-Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology (AIST), AIST Photovoltaic Power Generation Research Results Presentation 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0008] As mentioned above, self-emissive displays have many advantages, but they also have the problem of being difficult to manufacture. For example, organic EL elements can be made to emit light-emitting elements that emit red (R), green (G), and blue (B) light separately. Therefore, in full-color display devices, assigning light-emitting elements with different emission colors to each of the multiple subpixels of a pixel is ideal for display quality and low power consumption. These technologies have been realized in small and medium-sized display devices.

[0009] However, in large-area display devices, the process of manufacturing different types of light-emitting elements becomes particularly difficult, so configurations combining white light-emitting elements with color filters are often used. Since two-thirds of the light emitted by the light-emitting elements is lost through the color filter, the efficiency of light utilization decreases. Furthermore, there is a need for methods to efficiently extract the light emitted by the light-emitting elements to the outside.

[0010] Therefore, one aspect of the present invention aims to provide a display device with high display quality; another aspect aims to provide a display device with low power consumption; another aspect aims to provide a display device that can efficiently extract light emitted by a light-emitting element to the outside; another aspect aims to provide a display device with a high aperture ratio; another aspect aims to provide a novel semiconductor device, display device, etc.; or another aspect aims to provide a method for manufacturing the above-mentioned display device.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc.

[0012] One aspect of the present invention relates to a display device with high display quality and low power consumption.

[0013] One aspect of the present invention has a pixel having a transistor and a first wiring, has a first insulating layer on the transistor and the first wiring, and has a first concavo-convex portion and a second concavo-convex portion on the upper surface side of the first insulating layer. On the first concavo-convex portion, there is a first laminate that functions as an organic EL element. The first laminate has a configuration in which a first conductive layer, an organic EL layer, and a second conductive layer are provided in this order from the first concavo-convex portion side. On the second concavo-convex portion, there is a second laminate having a first region and a second region. The first region has a configuration in which a third conductive layer, an organic EL layer, and a second conductive layer are provided in this order from the second concavo-convex portion side. The second region has a connection portion between the third conductive layer and the second conductive layer. The first conductive layer has a region that connects to one of the source or drain of the transistor. The third conductive layer has a region that connects to the first wiring. This is a display device.

[0014] The first concavo-convex portion can have the function of a microlens array.

[0015] Preferably, the height H2 from the lowermost part to the uppermost part of the second concavo-convex portion is greater than the height H1 from the lowermost part to the uppermost part of the first concavo-convex portion.

[0016] Preferably, the pitch P2 of the concave portions in the second concavo-convex portion is greater than the pitch P1 of the concave portions in the first concavo-convex portion.

[0017] Preferably, the maximum value θ2 of the taper angle of the concave portions in the second concavo-convex portion is greater than the maximum value θ1 of the taper angle of the concave portions in the first concavo-convex portion.

[0018] Preferably, the first conductive layer has a region that is transparent to visible light, and the second conductive layer has a region that is reflective to visible light.

[0019] The second conductive layer has the function of the cathode of the organic EL element, and the first wiring can have the function of supplying a low power supply potential.

[0020] Preferably, each of the first conductive layer and the third conductive layer is a conductive layer formed separately from one conductive film.

[0021] The transistor preferably has an oxide semiconductor in the channel formation region. Furthermore, the oxide semiconductor is preferably indium oxide.

[0022] An electronic device having the above-mentioned display device and a speaker is also one embodiment of the present invention.

[0023] Another aspect of the present invention involves forming a first wiring and a transistor on a substrate, forming a first insulating layer on the first wiring and the transistor, forming a first uneven portion having a first taper angle and a second uneven portion having a second taper angle larger than the first taper angle in the first insulating layer, forming a first opening in the first insulating layer that reaches the first wiring and a second opening that reaches the source or drain of the transistor, forming a first conductive film that covers the first uneven portion, the second uneven portion, the first opening and the second opening, and processing the first conductive film to form a first covering the first uneven portion and the second opening. This is a method for manufacturing a display device, comprising: forming a conductive layer and a second conductive layer covering a second uneven portion and a first opening; forming a second insulating layer covering the first conductive layer near the end of the first uneven portion; forming a first EL layer on the first insulating layer, the second insulating layer, and the first conductive layer, and in a first region on the second conductive layer; forming a second conductive film on the first EL layer and in a second region on the second conductive layer; forming a third insulating layer on the second conductive film; providing a mask on the third insulating layer to process the first EL layer and the second conductive layer, thereby forming a second EL layer and a third conductive layer covering the first and second uneven portions.

[0024] According to one aspect of the present invention, a display device with high display quality can be provided. Alternatively, a display device with low power consumption can be provided. Alternatively, a display device that can efficiently extract light emitted by a light-emitting element to the outside can be provided. Alternatively, a display device with a high aperture ratio can be provided. Alternatively, a novel semiconductor device, display device, etc. can be provided. Alternatively, a method for manufacturing the above-mentioned display device can be provided.

[0025] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc.

[0026] Figure 1 is a top view illustrating the pixels of a display device. Figure 2A is a diagram illustrating the pixel circuit. Figures 2B and 2D are top views illustrating the display device. Figures 2C and 2E are block diagrams illustrating the pixels and wiring. Figures 3A, 3B, and 3C are cross-sectional views illustrating a microlens array. Figure 4 is a cross-sectional view illustrating the connection between the cathode and the cathode ray. Figures 5A and 5B are diagrams illustrating a method for manufacturing the microlens array and connection. Figure 6A is a diagram illustrating a method for manufacturing the microlens array and connection. Figure 6B is a perspective view of the microlens array and connection. Figures 7A and 7B are diagrams illustrating a method for manufacturing the microlens array and connection. Figure 8A is a diagram illustrating a method for manufacturing the microlens array and connection. Figure 8B is a perspective view of the microlens array and connection. Figures 9A, 9B, 9C, and 9D are cross-sectional views illustrating a method for manufacturing a display device. Figures 10A, 10B, and 10C are cross-sectional views illustrating a method for manufacturing a display device. Figures 11A and 11B are circuit diagrams illustrating a pixel circuit. Figures 11C, 11D, and 11E are cross-sectional views illustrating a transistor. Figures 12A and 12B illustrate the carrier concentration dependence of Hall mobility. Figure 12C is a cross-sectional view illustrating an indium oxide film. Figures 13A, 13B, 13C, and 13D are cross-sectional views illustrating an example of an electronic device.

[0027] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not to be interpreted as being limited to the descriptions of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated descriptions may be omitted. In addition, hatching of the same elements constituting the figures may be omitted or changed as appropriate between different drawings.

[0028] Furthermore, even if an element is shown as a single component in a circuit diagram, it can be composed of multiple components if there are no functional disadvantages. For example, multiple transistors that act as switches can be connected in series or parallel. Similarly, capacitors can be divided and placed in multiple locations.

[0029] Furthermore, a single conductor may have multiple functions, such as wiring, electrodes, and terminals, and in this specification, multiple designations may be used for the same element. Also, even if elements are shown as directly connected in a circuit diagram, they may actually be connected via one or more conductors, and in this specification, such configurations are included in the category of direct connection.

[0030] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to describe the connection relationships of circuit elements as physical objects. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; however, wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements.

[0031] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0032] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0033] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0034] (Embodiment 1) In this embodiment, a display device according to one aspect of the present invention will be described with reference to the drawings.

[0035] One aspect of the present invention is a display device with high display quality and low power consumption. The display device has an organic EL element on a microlens array formed on an insulating layer. Furthermore, the organic EL element has an EL layer separated for each subpixel using a lithography process. Therefore, due to the effect of the microlens array, the light extraction efficiency is high and the light emission of adjacent subpixels caused by crosstalk can be suppressed, resulting in a display device with high color purity and good display quality.

[0036] Furthermore, since the separation of the EL layer is performed along with the cathode, a connection between the cathode and the cathode ray is required. In one aspect of the present invention, in order to simplify the process, a conductive layer that connects to the cathode ray and the cathode are connected in a recessed portion that can be formed using a process common to that of the microlens array. The conductive layer can be a layer that can be formed using a process common to that of the anode.

[0037] The uneven portion has a larger taper angle and greater height difference than the uneven portion that acts as a microlens array. As a result, a region is formed on the conductive layer that is not covered by the EL layer, allowing connection to a cathode placed on that region. Therefore, the connection process between the cathode and the cathode ray can be simplified.

[0038] Although one embodiment of the present invention includes many circular elements, even if the design or intended shape is circular, the actual product is often approximately circular. Approximately circular refers to a shape that approximates a circle with multiple curvatures, and includes, for example, an ellipse. Therefore, the descriptions of circles such as diameter and radius in this specification can be applied to the circumscribed circle, inscribed circle, or approximating circle of an approximately circular element.

[0039] Figure 1 is a diagram illustrating a part of the pixels of a display device according to one embodiment of the present invention, and shows an example of a top view of two adjacent subpixels. Note that some elements are omitted in Figure 1 for clarity.

[0040] Sub-pixels SP1 and SP2 each have organic EL elements (OELs) with different emission colors. Furthermore, sub-pixels SP1 and SP2 can each have the circuit configuration shown in Figure 2A. Here, a 2Tr1C configuration (transistors Tr1, Tr2, and capacitive element C1) is shown as an example of a pixel circuit.

[0041] Transistor Tr1 controls the writing of data, and transistor Tr2 controls the current flowing through the organic EL element OEL. Capacitor element C1 functions as a data retention capacitor.

[0042] Either the source or drain of transistor Tr1 is connected to the gate of transistor Tr2. The gate of transistor Tr1 is connected to the gate line GL, which controls the pixels on which data is written. The other end of the source or drain of transistor Tr1 is connected to the source line SL, which supplies the data. Either the source or drain of transistor Tr2 is connected to the power line AL, which supplies the high power supply potential.

[0043] Furthermore, the pixel circuit configuration is not limited to 2Tr1C; it can also include a transistor to reset the source potential of transistor Tr2, and multiple transistors to correct the threshold voltage or mobility of transistor Tr2.

[0044] In Figure 1, the organic EL element (OEL) is composed of a laminate having, from the bottom, an anode AE1, an EL layer (not shown, with an upper surface shape equivalent to that of the cathode CE), and a cathode CE. The anode AE1 is also called the pixel electrode or bottom electrode and is connected to the source or drain of the transistor Tr2. The cathode CE is also called the top electrode and is connected to the cathode ray CL.

[0045] In Figure 1, a portion of the cathode CE of sub-pixel SP2 is cut out to clarify the components of the sub-pixel and the connection configuration between elements. Also, Figure 1 shows an example in which the cathode rays CL (cathode rays CL_H) are arranged parallel to the gate line GL, as shown in the top view of the display device in Figure 2B and the block diagram of the pixels in Figure 2C. In this case, by connecting the cathode ray CL_V, which is arranged parallel to the source line SL outside the display unit 10, to multiple cathode rays CL_H, it is possible to easily supply potential to the cathode rays CL_H.

[0046] Alternatively, cathode rays CL_V can also be arranged within the display unit 10, as shown in the top view of the display device in Figure 2D and the pixel block diagram in Figure 2E. Cathode rays CL_V can be arranged, for example, as shown in Figure 2E, with multiple sub-pixels sandwiched between them. By providing multiple cathode rays CL_V within the display unit 10, the cathode rays CL form a mesh-like structure, and the voltage drop of the cathode rays CL can be suppressed by reducing its resistance.

[0047] In addition, the block diagrams shown in Figures 2C and 2E illustrate an example in which pixel PIX has sub-pixels R that emit red light (R), sub-pixels G that emit green light (G), and sub-pixels B that emit blue light (B).

[0048] In one embodiment of the present invention, the organic EL element (OEL) has a configuration in which the EL layer and cathode (CE) are separated between adjacent subpixels. Furthermore, the EL layer is configured to emit light of one of the following colors: red, green, or blue.

[0049] Generally, in display devices that achieve full-color display by combining white-emitting organic EL elements and color filters, the EL layer and cathode CE are formed as a continuous layer between subpixels. While this configuration simplifies the manufacturing process, it is prone to unwanted light emission due to crosstalk, resulting in reduced display quality. Furthermore, when using white-emitting organic EL elements, the attenuation of light by the color filter is significant, leading to poor light utilization efficiency and thus high power consumption.

[0050] In one embodiment of the present invention, the EL layer and cathode CE are separated between adjacent sub-pixels, thus reducing the likelihood of unnecessary light emission due to crosstalk and improving display quality. Furthermore, since the EL layer emits light of one of the following colors (R, G, or B) rather than white light, a color filter is unnecessary, increasing the efficiency of light utilization. Additionally, since the separation of the EL layer and cathode CE between sub-pixels is achieved using a lithography process, high resolution and large area displays are possible.

[0051] However, in order to separate the cathode CE between subpixels, the cathode CE becomes island-like and requires connection to a power line (cathode ray CL) that supplies a low power potential. Simply put, the two can be connected by providing connecting wiring between the cathode CE and the cathode ray CL, but this would require adding multiple steps in the film deposition, lithography, and etching processes, significantly increasing the number of steps. In addition, providing connecting wiring would reduce the aperture ratio.

[0052] Therefore, in one aspect of the present invention, a configuration is used in which a conductive layer AE2, which can be formed in the same process as the anode AE1 and is connected to the cathode ray CL, and the cathode CE are connected within a sub-pixel. This connection is made by forming an uneven portion in the connection portion CA provided within the sub-pixel in which the EL layer cannot be partially covered, thereby connecting the conductive layer AE2 and the cathode CE.

[0053] The uneven surface provided in the connection section CA can be formed using the same process as the microlens array MLA which is arranged in parallel with the organic EL element OEL. Therefore, the cathode CE and cathode ray CL can be connected without increasing the number of processes. In addition, since connection wiring is unnecessary, the aperture ratio can be increased.

[0054] Now, let's explain the microlens array (MLA). As shown in Figure 1, the microlens array (MLA) is formed to overlap with the anode (AE1).

[0055] Figure 3A is a cross-sectional view corresponding to the area between A1 and A2 in Figure 1. The transistor Tr2 is provided on the substrate 100, and on the transistor Tr2, an insulating layer 110 and an insulating layer 120, which are transparent to visible light, are provided. The insulating layer 110 functions as a protective film for the transistor, and the insulating layer 120 functions as a planarization film. The upper surface of the insulating layer 120 is provided with a protruding portion consisting of multiple connected concave curved surfaces. This protruding portion acts as a microlens array (MLA).

[0056] Because microlens arrays (MLAs) have the effect of changing the direction of light propagation, they can extract light emitted from organic light-emitting diodes (OELs) in a specific direction that could not be extracted due to absorption or total internal reflection within the display device. In other words, they can improve the efficiency of light extraction.

[0057] On the microlens array MLA, an organic EL element OEL (a laminate of anode AE1, EL layer 130, and cathode CE) and a protective layer 140 are arranged in order from the microlens array MLA side. Here, the anode AE1, EL layer 130, and cathode CE each have a shape that reflects the irregularities of the microlens array MLA, and these also have the effect of promoting changes in the direction of light propagation.

[0058] In Figure 3A, an example of forming a microlens array (MLA) by forming multiple recesses on the upper surface of the insulating layer 120 is shown. However, as shown in Figure 3B, a microlens array (MLA) can also be formed by forming multiple protrusions on the upper surface of the insulating layer 120. Even with this configuration, the direction of light propagation emitted by the organic EL element (OEL) can be changed.

[0059] Here, the anode AE1 is transparent to light L (visible light) emitted by the organic EL element OEL, and the cathode CE is reflective to light L. In other words, one embodiment of the present invention is a bottom emission type display device.

[0060] The anode AE1 is connected to the other side of the source or drain of the transistor Tr2 at an opening CH1 provided in the insulating layer 120 and the insulating layer 110. Here, it is preferable to cover the recess caused by the opening CH1 and the end of the microlens array MLA with the insulating layer 150 to reduce the steep wall angle (taper angle) and improve the coverage of the EL layer 130.

[0061] The separation of the cathode CE and EL layer 130 between subpixels is performed by lithography and etching processes after a protective layer 140 is applied to the cathode CE. Therefore, the protective layer 140, cathode CE, and EL layer 130 have substantially the same or similar shape when viewed from above. The protective layer 140 can be formed from a material that can be used for the insulating layer 110. In addition, outside the cathode CE and EL layer 130, the thickness of the insulating layer 150 may become thinner during the separation process.

[0062] After the cathode CE and EL layer 130 are separated between the subpixels, a protective layer 141 is provided to cover the EL layer 130. The substrate 101 is bonded to the protective layer 141 via an adhesive layer 151.

[0063] Furthermore, since the anode AE1 is formed from a translucent metal oxide or the like, it has higher resistance compared to metal. Therefore, as shown in Figure 3C, the opening CH1 and the vicinity of the end of the microlens array MLA can be covered with a metal conductive layer 180, and the anode AE1 can be provided in contact with and covering the metal conductive layer 180. This configuration makes it easier to suppress fluctuations in the data potential supplied to the anode AE1.

[0064] The metal conductive layer 180 can be formed using one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy comprising one or more of the aforementioned metals.

[0065] Next, the connection part CA will be described. Figure 4 is a cross-sectional view corresponding to the section between B1 and B2 shown in Figure 1, and an enlarged view of the connection part CA. In the connection part CA, the upper surface of the insulating layer 120 is provided with an uneven section 160 having a steep wall surface, with a height from the bottom to the upper surface of the insulating layer 120 being greater than the uneven section that functions as a microlens array MLA.

[0066] As shown in Figure 4, the radius of curvature of the recess in the uneven portion acting as a microlens array (MLA) is r １ The radius of curvature of the recess in the uneven portion 160 is r ２ When this is the case, r ２ >r １ Each is formed in such a manner. As a result, if each recess is processed to be a semicircle of a circle of curvature in a cross-section including the center of the recess, the height H2 from the bottom of the uneven portion 160 to the top surface of the insulating layer 120 can be made larger than the height H1 from the bottom of the microlens array MLA to the top surface of the insulating layer 120.

[0067] Furthermore, in a microlens array (MLA), the cross-section is formed so that adjacent recesses are connected, resulting in the height H3 of the protrusion at the boundary (height from the bottom of the recess to the tip of the protrusion) being smaller than the height H1. This results in a taper angle θ of the protrusion. １This can be made smaller. On the other hand, in the uneven portion 160, in cross-section, the recesses are processed in a semicircular shape of a circle of curvature from the upper surface of the insulating layer 120, so the wall surface near the upper surface of the insulating layer 120 becomes steep. Therefore, the taper angle θ of the wall surface ２ θ １ They can be made larger. The methods for creating these will be described later.

[0068] A laminate having a conductive layer AE2, an EL layer, and a cathode CE is provided on the uneven portion 160. The laminate has a first region and a second region. The first region has a configuration in which the conductive layer AE2, the EL layer, and the cathode CE are provided in order from the uneven portion 160 side, and the second region has a connection portion between the conductive layer AE2 and the cathode CE. The conductive layer AE2 and the anode AE1 are layers separated from the same conductive film, and the conductive layer AE2 is connected to the cathode ray CL at the opening CH2.

[0069] In such uneven portions 160, the conductive layer AE2 and cathode CE, which are formed with a relatively thick film, have a taper angle θ ２ It can cover even steep wall surfaces like the one shown. The conductive layer AE2 and cathode CE are preferably formed using a film deposition method such as sputtering, which provides relatively good coverage. On the other hand, the EL layer 130 is formed using a vapor deposition method, which provides poor coverage, resulting in an extremely thin film thickness, making it difficult to cover steep wall surfaces.

[0070] It should be noted that a steep wall surface refers to a wall surface with a large taper angle that is nearly perpendicular to the top surface, but its effect on the film deposition process is not always the same. For example, on an excessively steep wall surface, film deposition may not be possible even by the sputtering method. Conversely, even on a steep wall surface, film deposition may be possible by the vapor deposition method depending on the conditions. Therefore, the shape of the uneven wall surface, the film deposition method, and the film deposition conditions should be appropriately set so that the feasibility of film deposition on steep walls can be adjusted as described above.

[0071] As shown in the enlarged view of the connection part CA, the upper surface of the insulating layer 120, the bottom of the uneven portion 160, and its vicinity do not have steep walls, so coating is possible even with a vapor deposition method which has poor coating properties. In other words, the region of the laminate formed above these areas corresponds to the first region.

[0072] On the other hand, in the region of the insulating layer 120 near the upper surface in the concavo-convex portion 160, the wall surface becomes steep. This steepness (taper angle) does not change significantly even when the conductive layer AE2 is coated. Therefore, the conductive layer AE2 also has a steep wall surface. Even when the step of forming the EL layer 130 on the conductive layer AE2 is performed, as indicated by the arrows in the figure, regions a, b, c, and d where the EL layer 130 is not formed are formed. By forming the cathode CE on these regions a, b, c, and d where the EL layer 130 is not formed, the conductive layer AE2 and the cathode CE can be connected. These regions a, b, c, and d correspond to the second region.

[0073] Also, the region e indicated by the arrow in the figure is the end of the conductive layer AE2. By exposing this region e without covering it with the insulating layer 150, the connection area between the conductive layer AE2 and the cathode CE can be increased.

[0074] As described above, the taper angle θ in the microlens array MLA １ can be made smaller than the taper angle θ of the concavo-convex portion 160 ２ Therefore, the EL layer 130 can cover the anode AE1.

[0075] Next, an example of a method for manufacturing the concavo-convex portion that becomes the microlens array MLA and the concavo-convex portion 160 in the connection portion CA will be described using FIGS. 5A to FIG. 6A. In each figure, the top view is shown on the upper side, and the cross-sectional view of C1 - C2 in the top view is shown on the lower side. Also, FIG. 6B shows a perspective view of the microlens array MLA and the connection portion CA.

[0076] Note that this is an example of the manufacturing method described here and can be applied when the insulating layer 120 is formed of a resin material that can be processed in an ashing process in the same manner as a resist mask.

[0077] First, a resist mask 170 is formed on the insulating layer 120. In the region where the microlens array MLA is formed, a plurality of recesses 171 are formed in the resist mask 170 that do not penetrate the resist mask 170. The plurality of recesses 171 are arranged in a staggered (zigzag) pattern, spaced apart from each other, when viewed from above. In addition, a plurality of openings 172 are formed in the uneven portion 160 that penetrate the resist mask 170. The plurality of openings 172 are arranged in a spaced-apart pattern, when viewed from above (see Figure 5A). The recesses 171 can be, for example, hemispherical. Alternatively, the recesses 171 can have an aspherical shape.

[0078] In this example, the top surface shape of the opening 172 is shown as circular, but it can also be a polygon or a roughly polygon with curvature at its corners. In the initial state, the diameter of the recess 171 in the top view is Y1, and the diameter of the opening 172 is X1.

[0079] Furthermore, as described above, in order to form the recesses 171 that do not penetrate the resist mask 170 and the openings 172 that penetrate the resist mask 170 in a common process, for example, a photolithography process using a multi-tone mask such as a grayscale mask can be used.

[0080] Next, the ashing process causes the resist mask 170 to recede while simultaneously processing the insulating layer 120. By performing the ashing isotropically, the resist mask 170 recedes, and the diameter of the recess 171 in the top view expands to Y2 (Y1 < Y2), and the diameter of the opening 172 expands to X2 (X1 < X2). In addition, the insulating layer 120 exposed at the opening 172 is processed in the depth direction (see Figure 5B).

[0081] Furthermore, as the ashing process continues until the resist mask 170 disappears, the recesses 171 are formed in the insulating layer 120, and their diameter virtually expands to Y3 (Y2 < Y3). However, because adjacent recesses 171 become connected, the shape of each recess 171, excluding the ends of the microlens array MLA, becomes hexagonal in a top view. Also, the height H3 of the protrusions formed at the boundaries of adjacent recesses 171 becomes smaller than the height H1, thus reducing the taper angle θ of the protrusions.１ This can be made smaller. The height of the protrusion formed at the boundary between adjacent recesses 171 can be rephrased as the height from the bottom to the top of the microlens array (MLA).

[0082] On the other hand, the diameter of the opening 172 is enlarged to X3 (X2 < X3), and the insulating layer 120 is processed in a semi-circular shape in the depth direction, for example, when viewed in cross-section (see Figure 6A). Therefore, the height H2 from the bottom of the uneven portion 160 to the top surface of the insulating layer 120 can be made larger than the heights H1 and H3 from the bottom to the top surface of the insulating layer 120 in the microlens array MLA. Note that the height from the bottom of the uneven portion 160 to the top surface of the insulating layer 120 can be rephrased as the height from the lowest part b to the highest part of the uneven portion 160.

[0083] As a result, the taper angle θ of the wall surface near the upper surface of the insulating layer 120 in the recessed portion 160 ２ This can be made larger. Furthermore, the taper angle of the wall surface near the top can be rephrased as the maximum value of the taper angle in the recess.

[0084] As described above, the uneven portion that functions as a microlens array (MLA) and the uneven portion 160 in the connecting portion CA can be manufactured using a common process.

[0085] Furthermore, using Figures 7A to 8A, an example of a method for manufacturing the uneven portion 160 in the connection part CA, different from the above, will be described. Figure 8B shows a perspective view of the microlens array MLA and the connection part CA.

[0086] First, a resist mask 170 is formed on the insulating layer 120. In the region where the microlens array MLA is formed, a plurality of recesses 171 are formed in the resist mask 170 that do not penetrate the resist mask 170. The plurality of recesses 171 are arranged in a staggered (zigzag) pattern, spaced apart from each other, when viewed from above.

[0087] Furthermore, in the uneven portion 160, multiple recesses 173 are formed that have the same shape as the recesses 171 but do not penetrate the resist mask 170. Here, when the pitch of the recesses 171 (distance between the centers of adjacent recesses) is P1 and the pitch of the recesses 173 is P2, P2 > P1 (see Figure 7A). The recesses 171 and 173 can be, for example, hemispherical. Alternatively, the recesses 171 and 173 can have an aspherical shape. In the initial state, the diameter of the recess 171 in a top view is Y1 and the diameter of the recess 173 is X1. Here, X1 = Y1.

[0088] Next, the resist mask 170 is pushed back by the ashing process. By performing the ashing isotropically, the resist mask 170 is pushed back, and the diameter of the recess 171 in the top view expands to Y2 (Y1 < Y2), and the diameter of the recess 173 expands to X2 (X1 < X2 = Y2) (see Figure 7B).

[0089] Furthermore, as the ashing process continues until the resist mask 170 disappears, recesses 171 and 173 are formed in the insulating layer 120, and the diameter of recess 171 virtually expands to Y3 (Y2 < Y3). However, because adjacent recesses 171 become connected, the shape of each recess 171, excluding the ends of the microlens array MLA, becomes hexagonal in a top view. Also, the height H3 of the protrusion formed at the boundary between adjacent recesses 171 becomes smaller than the height H1, thus reducing the taper angle θ of the protrusion. １ It can be made smaller.

[0090] On the other hand, the diameter of the recess 173 expands to X3 (X2 < X3 = Y3), and the insulating layer 120 is processed in a semicircular shape in the depth direction, for example, when viewed in cross-section (see Figure 8A). This can be achieved by setting P2 such that P2 > P1, and adjacent recesses 173 do not connect even when the diameter of the recess 173 expands to X3.

[0091] Therefore, the taper angle θ of the wall surface near the upper surface of the insulating layer 120 in the recessed portion 160 ２ It can be made larger.

[0092] As described above, the uneven portion that functions as a microlens array (MLA) and the uneven portion 160 in the connecting portion CA can be manufactured using a common process.

[0093] Next, a method for producing pixels according to one embodiment of the present invention will be explained with reference to Figures 9A to 10C.

[0094] First, cathode rays CL and transistors are formed on the substrate 100, and insulating layers 110 and 120 are formed on the cathode rays CL and transistors (see Figure 9A). Here, the transistor shown is the transistor Tr2 of the sub-pixel.

[0095] As the insulating layer 110, it is preferable to use an inorganic insulating film that is transparent to visible light. Examples of inorganic insulating films that can be used include silicon nitride film, silicon oxynitride film, silicon oxide film, silicon nitride oxide film, aluminum oxide film, aluminum nitride film, etc. Also, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film can be used. Furthermore, two or more of the above insulating films can be laminated and used. In this specification, oxynitride refers to a material in which the oxygen content is greater than the nitrogen content, and nitride oxide refers to a material in which the nitrogen content is greater than the oxygen content.

[0096] Furthermore, it is preferable to use an organic insulating layer that is transparent to visible light as the insulating layer 120. Examples of materials that can be used for the organic insulating layer include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. The insulating layer 120 can also be a laminated structure of an organic insulating layer and an inorganic insulating layer.

[0097] Next, using the method described above, a recessed portion that functions as a microlens array MLA and a recessed portion 160 of the connection portion CA are formed on the upper surface of the insulating layer 120. In addition, an opening CH1 that reaches either the source or drain of the transistor Tr2 and an opening CH2 that reaches the cathode ray CL are formed in the insulating layer 120 and the insulating layer 110 (see Figure 9B).

[0098] Next, a conductive film AE0 is formed to cover the uneven portion that functions as a microlens array MLA, the uneven portion 160 of the connecting portion CA, the opening CH1, and the opening CH2 (see Figure 9C).

[0099] Next, the conductive film AE0 is processed to remove unwanted areas, forming the anode AE1 and the conductive layer AE2 (see Figure 9D).

[0100] As materials for forming the anode AE1 and cathode CE, which are the pair of electrodes of an organic electroluminescent element (OEL), metals, alloys, electrically conductive compounds, and mixtures thereof can be used as appropriate. Specifically, examples include indium tin oxide (In-Sn oxide, also called ITO), In-Si-Sn oxide (also called ITSO), indium zinc oxide (In-Zn oxide), In-W-Zn oxide, aluminum-containing alloys such as aluminum, nickel, and lanthanum alloys (Al-Ni-La), and silver-palladium-copper alloys (Ag-Pd-Cu, also written as APC). In addition, metals such as aluminum (Al), titanium (Ti), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), gallium (Ga), zinc (Zn), indium (In), tin (Sn), molybdenum (Mo), tantalum (Ta), tungsten (W), palladium (Pd), gold (Au), platinum (Pt), silver (Ag), yttrium (Y), and neodymium (Nd), as well as alloys containing these in appropriate combinations, can also be used. Furthermore, elements belonging to Group 1 or Group 2 of the periodic table not exemplified above (for example, lithium (Li), cesium (Cs), calcium (Ca), strontium (Sr)), rare earth metals such as europium (Eu) and ytterbium (Yb), and alloys containing these in appropriate combinations, graphene, etc., can also be used.

[0101] Furthermore, it is preferable that the organic EL element (OEL) has a microcavity structure. Therefore, one of the pair of electrodes in the organic EL element (OEL) may have an electrode that is transparent and reflective to visible light (a semi-transmissive / semi-reflective electrode), and the other electrode may have an electrode that is reflective to visible light (a reflective electrode). By having a microcavity structure in the organic EL element (OEL), the light emitted from the light-emitting layer can be made to resonate between the two electrodes, thereby strengthening the light emitted from the light-emitting device.

[0102] Next, an insulating layer 150 is formed to cover the steep walls of the microlens array MLA, and an EL layer 130f, which will become the EL layer 130, is formed on the insulating layer 150 (see Figure 10A). At this time, in the uneven portion 160, a region is formed where the conductive layer AE2 is exposed and is not covered by the EL layer 130f.

[0103] The insulating layer 150 can be formed from a material that can be used for the insulating layer 120. The EL layer 130f (EL layer 130) has at least one layer containing a light-emitting substance (light-emitting layer). For example, the EL layer 130f (EL layer 130) can have a laminated structure consisting of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer from the anode AE1 side.

[0104] Next, a conductive layer CE0, which will serve as the cathode, is formed on the EL layer 130f, and a protective film 140f is formed on the conductive layer CE0 (see Figure 10B). In the region where the conductive layer AE2 is exposed in the uneven portion 160, the conductive layer CE0 and the conductive layer AE2 are connected.

[0105] Next, a mask is placed on the protective film 140f, and the protective film 140f, the conductive layer CE0, and the EL layer 130f are etched to form the EL layer 130, the cathode CE, and the protective layer 140. This allows the EL layer and cathode between subpixels to be separated.

[0106] Furthermore, in order to seal the exposed edges of the EL layer 130, the EL layer 130, cathode CE, and protective layer 140 are laminated together, and a protective layer 141 is formed on the insulating layer 150. Then, the substrate 101 is bonded to the protective layer 141 via an adhesive layer 151 (see Figure 10C). Note that the protective layer 140 and protective layer 141 can be formed from materials that can be used for the insulating layer 110.

[0107] Through the above manufacturing process, island-shaped cathodes separated between subpixels can be connected to cathode rays without adding any further steps.

[0108] Figures 11A and 11B are modified versions of the pixel circuit shown in Figure 2A. Figure 11A differs from the pixel circuit shown in Figure 2A in that it has a transistor Tr3. One of the sources or drains of transistor Tr3 is connected to the other source or drain of transistor Tr2, and the other source or drain is connected to a reset line RL. The reset line RL can supply a potential to reset the source potential of transistor Tr2. For example, a low power supply potential or GND potential can be used as the reset potential.

[0109] The source of transistor Tr2 is connected to the anode of OEL, and the source potential is not necessarily constant. Therefore, by making transistor Tr3 conduct when writing data to the gate of transistor Tr2, the source potential of transistor Tr2 can be reset, allowing for stable data writing.

[0110] Furthermore, Figure 11B differs from Figure 11A in that the transistor has a back gate. As shown in Figure 11B, by providing a back gate (second gate) to the transistor and connecting it to the front gate (first gate), the on-current can be increased. It is also possible to supply an appropriate fixed potential to the back gate. By supplying a fixed potential to the back gate, the threshold voltage can be controlled.

[0111] Figure 11C shows a cross-sectional view of an example of a transistor Tr having a back gate. A conductive layer 221 is provided on a substrate 100, and a semiconductor layer 225 is provided on the conductive layer 221 via an insulating layer 211b. An insulating layer 211a is provided on the semiconductor layer 225, and a conductive layer 223 is provided on the insulating layer 211b. An insulating layer 215 is provided on the insulating layer 211b, semiconductor layer 225, insulating layer 211a, and conductive layer 223, and the insulating layer 215 has two openings that reach the semiconductor layer 225. A conductive layer 222a is provided on the insulating layer 215, connecting to the semiconductor layer 225 through one of the openings. A conductive layer 222b is also provided on the insulating layer 215, connecting to the semiconductor layer 225 through the other opening. An insulating layer 218 is provided on the insulating layer 215, conductive layer 222a, and conductive layer 222b.

[0112] Here, one of the conductive layer 221 and conductive layer 223 acts as a first gate, and the other acts as a second gate. One of the insulating layer 211a and insulating layer 211b acts as a first gate insulating layer, and the other acts as a second gate insulating layer. One of the conductive layer 222a and conductive layer 222b acts as a source electrode, and the other acts as a drain electrode. The insulating layer 215 acts as an interlayer insulating film, and the insulating layer 218 acts as a protective film.

[0113] The conductive layer 221 can also act as a light-shielding layer. Since the display device according to one embodiment of the present invention is bottom-emission, the conductive layer 221 can shield the semiconductor layer 225 from light irradiated from the outside. Therefore, it is possible to suppress changes in transistor characteristics caused by light irradiation of the semiconductor layer 225 and to improve reliability.

[0114] Although Figure 11C illustrates a self-aligned transistor, a non-self-aligned transistor can also be used, as shown in Figure 11D.

[0115] Furthermore, in one aspect of the present invention, as shown in Figure 11E, a vertical transistor having a channel-forming region along the wall surface of the insulating layer can also be used. The transistor Tr shown in Figure 11E is provided with a semiconductor layer 225 covering an opening formed in the insulating layer 219, an insulating layer 211 functioning as a gate insulating layer, a conductive layer 223 functioning as a gate electrode, and an insulating layer 218 functioning as a protective film. A conductive layer 222b is provided between the insulating layer 219 and the substrate 100 and is connected to the semiconductor layer 225 at the bottom of the opening. In addition, a conductive layer 222a is provided on the insulating layer 219, and one of the conductive layers 222a and 222b connected to the semiconductor layer 225 functions as either a source electrode or a drain electrode, while the other functions as either a source electrode or a drain electrode.

[0116] Such vertical transistors can have a channel-forming region along the wall surface of the insulating layer, and can have a configuration in which the source electrode and drain electrode overlap, thus reducing the occupied area compared to planar transistors. Therefore, they are advantageous for improving the aperture ratio or achieving high resolution.

[0117] It is preferable to use an oxide semiconductor for the semiconductor layer 225. In this specification, a transistor having an oxide semiconductor in the channel formation region is called an OS transistor.

[0118] It is particularly preferable to use indium oxide for the semiconductor layer 225. By using single-crystal or polycrystalline indium oxide, a high-performance transistor can be realized that combines high field-effect mobility, high on-current, extremely low off-current, and high reliability.

[0119] Alternatively, it is preferable that the semiconductor layer 225 contains indium, M (where M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc.

[0120] Transistors using oxide semiconductors, which have a wider bandgap and lower carrier concentration than silicon, can achieve extremely low off-currents. Therefore, this low off-current allows the charge stored in a capacitor connected in series with the transistor to be retained for extended periods.

[0121] Therefore, it is preferable to use transistors made of oxide semiconductors for transistors Tr1 and Tr3, which are connected in series with the capacitive element C1. By using transistors having oxide semiconductors as transistors Tr1 and Tr3, it is possible to prevent the charge held in the capacitive element C1 from leaking through transistor Tr1 or Tr3. Furthermore, since the charge held in the capacitive element C1 can be held for a long period of time, it becomes possible to display still images for a long period of time without rewriting the pixel data.

[0122] In Figures 2A, 11A, and 11B, transistors are shown as n-channel type transistors, but p-channel type transistors can also be used. Furthermore, transistors (hereinafter referred to as Si transistors) having silicon (single-crystal silicon, polycrystalline silicon (LTPS), microcrystalline silicon, or amorphous silicon) in the channel formation region can be used for one or more of transistors Tr1 to Tr3. For example, since a transistor with high mobility and high current driving capability is suitable for transistor Tr2, a Si transistor can also be used for transistor Tr2.

[0123] Furthermore, the driver circuit that drives the pixels can be configured so that one or more of the multiple transistors are Si transistors, and the other transistors are OS transistors. Alternatively, the driver circuit can be configured so that one or more of the transistors are Si transistors, and the others are OS transistors.

[0124] This embodiment can be implemented in appropriate combination with other embodiments and examples described herein, at least in part.

[0125] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a display device according to one aspect of the present invention.

[0126] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0127] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0128] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 12A shows silicon (Si) and indium oxide (InO Ｘ Figure 12B is a schematic diagram of the carrier concentration dependence of hole mobility with respect to IGZO.

[0129] First, as indicated by the arrows in Figure 12B, IGZO tends to show higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 12A, indium oxide tends to show higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 1). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 12A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 12A.

[0130] In Figure 12A, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0131] Furthermore, in indium oxide, the region where the carrier concentration is in the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0132] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or for resistors or transparent conductive films. The range R2 is when the carrier concentration value is 1 × 10⁻⁶. ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0133] Furthermore, in the indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0134] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be considered an oxide in which valence electron control is possible. Note that in IGZO, strain may be formed in the source and drain regions due to stress on the electrodes in contact with IGZO, and an n-type region may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require strain to be formed in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 12A within the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0135] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0136] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using single-crystal films, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0137] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0138] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0139] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0140] The channel formation region refers to the area within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0141] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0142] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0143] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0144] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 12C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. Ｏ If oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0145] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0146] Furthermore, as shown in Figure 12C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２ It is released as ) or, by reacting with oxygen contained in the membrane, it is released as water molecules.

[0147] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0148] Table 1 shows single crystal indium oxide (here, In ２ O ３ The effective masses of indium oxide and single-crystal silicon (Si) are shown below. As shown in Table 1, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Also, as shown in Table 1, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0149]

[0150] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0151] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0152] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0153] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0154] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0155] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0156] (Embodiment 3) This embodiment describes an electronic device according to one aspect of the present invention.

[0157] The electronic device of this embodiment has a display device according to one aspect of the present invention in its display section. The display device according to one aspect of the present invention has high display quality and low power consumption. Therefore, it is possible to provide a product with high image visibility and low power consumption.

[0158] Examples of electronic devices include television sets, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as other electronic devices with relatively large screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0159] Figure 13A shows an example of a television device. The television device 7100 has a display unit 7000 incorporated into a housing 7101. Here, a configuration is shown in which the housing 7101 is supported by a stand 7103. A display device using a semiconductor device according to one embodiment of the present invention can be applied to the display unit 7000.

[0160] The television device 7100 can be operated using the operation switches on the housing 7101 and a separate remote controller 7111. Alternatively, the display unit 7000 can be equipped with a touch sensor, allowing the television device 7100 to be operated by touching the display unit 7000 with a finger or the like. The remote controller 7111 may also have a display unit that displays information output from the remote controller 7111. Channel and volume can be controlled and the image displayed on the display unit 7000 can be manipulated using the operation keys or touch panel on the remote controller 7111.

[0161] The television system 7100 is configured to include a receiver and a modem. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0162] Figure 13B shows an example of a notebook personal computer. The notebook personal computer 7200 has a casing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. A display unit 7000 is incorporated into the casing 7211. A display device using a semiconductor device according to one embodiment of the present invention can be applied to the display unit 7000.

[0163] Figures 13C and 13D show an example of digital signage. The digital signage 7300 shown in Figure 13C includes a housing 7301, a display unit 7000, and a speaker 7303, etc. Furthermore, it may include LED lamps, operation keys (including a power switch or operation switch), connection terminals, various sensors, a microphone, etc.

[0164] Figure 13D shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the column 7401. In Figures 13C and 13D, a display device using a semiconductor device according to one embodiment of the present invention can be applied to the display unit 7000.

[0165] The larger the display area 7000, the more information can be provided at once. Furthermore, a larger display area 7000 is more eye-catching, which can, for example, enhance the effectiveness of advertising.

[0166] Applying a touch panel to the display unit 7000 is preferable because it not only allows images or videos to be displayed on the display unit 7000, but also enables intuitive operation by the user. Furthermore, when used for purposes such as providing route information or traffic information, intuitive operation can enhance usability.

[0167] Furthermore, it is preferable that the digital signage 7300 or digital signage 7400 can be linked wirelessly with an information terminal 7311 or information terminal 7411 such as a smartphone owned by the user. For example, the advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or information terminal 7411. Also, the display on the display unit 7000 can be switched by operating the information terminal 7311 or information terminal 7411.

[0168] Furthermore, the digital signage 7300 or digital signage 7400 can be used to run games using the screen of the information terminal 7311 or information terminal 7411 as the control device (controller). This allows an unspecified number of users to participate in and enjoy the game simultaneously.

[0169] This embodiment can be implemented in appropriate combination with other embodiments and examples described herein, at least in part. [Explanation of Symbols] AL: Power line, CA: Connection part, CE: Cathode, CE0: Conductive layer, CL: Cathode ray, CL_H: Cathode ray, CL_V: Cathode ray, GL: Gate line, MLA: Microlens array, PIX: Pixel, RL: Reset line, SL: Source line, Tr: Transistor, AE0: Conductive film, AE1: Anode, AE2: Conductive layer, 10: Display part, 100: Substrate, 101: Substrate, 110: Insulating layer, 120: Insulating layer, 130: EL layer, 130f: EL layer, 140: Protective layer, 141: Protective layer, 150: Insulating layer, 151: Adhesive layer, 160: Rough part, 170: Resist mask, 171: Recess, 172: Opening, 173: Recess, 180: Metal conductive layer, 211: Insulating layer, 211a: Insulating layer, 211b: Insulating layer, 215: Insulating layer, 218: Insulating layer, 219: Insulating layer, 221: Conductive layer, 222a: Conductive layer, 222b: Conductive layer, 223: Conductive layer, 225: Semiconductor layer, 7000: Display unit, 7100: Television equipment, 7101: Enclosure, 7103: Stand, 7111: Remote controller, 7200: Notebook personal computer, 7211: Enclosure, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7300: Digital signage, 7301: Enclosure, 7303: Speaker, 7311: Information terminal, 7400: Digital signage, 7401: Pillar, 7411: Information terminal

Claims

It has a pixel having a transistor and a first wiring, A first insulating layer is provided on the transistor and the first wiring, The upper surface of the first insulating layer has a first uneven portion and a second uneven portion, The first uneven portion has a first laminate that functions as an organic EL element, The first laminate has a configuration in which a first conductive layer, an organic EL layer, and a second conductive layer are provided in order from the side of the first uneven portion. The second laminate has a first region and a second region on the second uneven portion, The first region has a configuration in which a third conductive layer, the organic EL layer, and the second conductive layer are provided in order from the second uneven portion side. The second region has a connection portion between the third conductive layer and the second conductive layer. The first conductive layer has a region that connects to either the source or the drain of the transistor. The third conductive layer is a display device having a region that connects to the first wiring. 　 In claim 1, The first uneven portion is a display device having the function of a microlens array. 　 In claim 1, A display device in which the height H2 from the bottom to the top of the second uneven portion is greater than the height H1 from the bottom to the top of the first uneven portion. 　 In claim 1, A display device in which the pitch P2 of the recesses in the second uneven portion is greater than the pitch P1 of the recesses in the first uneven portion. 　 In claim 1, A display device in which the maximum value θ2 of the taper angle of the recess in the second uneven portion is greater than the maximum value θ1 of the taper angle of the recess in the first uneven portion. 　 In claim 1, A display device comprising a first conductive layer having a region that is transparent to visible light, and a second conductive layer having a region that is reflective to visible light. 　 In claim 1, The second conductive layer has the function of the cathode of the organic EL element. The first wiring is a display device that has the function of supplying a low power potential. 　 In claim 1, A display device in which the first conductive layer and the third conductive layer are each conductive layers formed by separating them from a single conductive film. 　 In claim 1, The transistor is a display device having an oxide semiconductor in the channel formation region. 　 In claim 9, The aforementioned oxide semiconductor is indium oxide in the display device. 　 An electronic device comprising a display device according to any one of claims 1 to 10, and a speaker. 　 First wiring and transistors are formed on the substrate. A first insulating layer is formed on the first wiring and the transistor. The first insulating layer is formed with a first uneven portion having a first taper angle and a second uneven portion having a second taper angle that is larger than the first taper angle. A first opening reaching the first wiring and a second opening reaching the source or drain of the transistor are formed in the first insulating layer. A first conductive film is formed to cover the first uneven portion, the second uneven portion, the first opening, and the second opening. The first conductive film is processed to form a first conductive layer that covers the first uneven portion and the second opening, and a second conductive layer that covers the second uneven portion and the first opening. A second insulating layer is formed to cover the first conductive layer near the end of the first uneven portion. A first EL layer is formed on the first insulating layer, on the second insulating layer, on the first conductive layer, and in a first region on the second conductive layer. A second conductive film is formed on the first EL layer and in a second region on the second conductive layer. A third insulating layer is formed on the second conductive film. A method for manufacturing a display device, comprising: providing a mask on the third insulating layer and processing the first EL layer and the second conductive layer to form a second EL layer and a third conductive layer that cover the first and second uneven portions.

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