Light detecting device

Abstract

The present disclosure relates to a light detecting device that makes it possible to suppress a sudden drop in potential. The light detecting device comprises: a pixel array unit in which pixels are arranged, each pixel having an optical pulse response unit including at least a photoelectric conversion unit that multiplies charges generated from photons and a recharge unit that recharges the photoelectric conversion unit; and a capacitance provided between a first potential and a second potential for causing a current to flow through the optical pulse response unit in response to the incidence of photons, in units of one or a plurality of pixels. The present disclosure is applicable to image sensors that employ SPADs, for example.

Description

Optical detection device

[0001] The present disclosure relates to an optical detection device, and more particularly to an optical detection device capable of suppressing a rapid potential drop.

[0002] As a device that outputs a pulse in response to the incidence of photons, a SPAD (Single Photon Avalanche Diode) is known (see, for example, Patent Document 1). A SPAD is a device capable of pulse response in response to the incidence of photons by applying, for example, a negative voltage of 20 V (reverse bias voltage) between its cathode and anode. In a SPAD, since the cathode is charged and discharged in response to the incidence of photons to generate a pulse, a high S / N ratio can be realized particularly in a low illuminance environment.

[0003] International Publication No. 2021 / 172216

[0004] When pixels using a SPAD are adopted in a general image sensor of several tens of megapixels and high-intensity light such as sunlight is incident on the entire light-receiving surface, the cathodes of all pixels are charged and discharged in substantially the same period. In this case, a rapid potential drop on the order of several volts occurs in the entire pixel array section, which may make the operation of the pixel circuit difficult.

[0005] The present disclosure has been made in view of such a situation, and is intended to suppress a rapid potential drop.

[0006] The optical detection device of the present disclosure includes a pixel array section in which pixels having an optical pulse response section including at least a photoelectric conversion section that multiplies charges generated from photons and a recharge section that recharges the photoelectric conversion section are arranged, and a capacitor provided between a first potential and a second potential that allows a current to flow through the optical pulse response section in response to the incidence of photons in units of one or more of the pixels.

[0007] In this disclosure, the photodetector includes a pixel array in which pixels are arranged, each having an optical pulse response unit that includes at least a photoelectric conversion unit for multiplying the charge generated from a photon and a recharge unit for recharging the photoelectric conversion unit, and a capacitor provided between a first potential and a second potential that causes a current to flow in the optical pulse response unit in response to the incidence of a photon in one or more of the pixels.

[0008] This is a block diagram illustrating an example of the configuration of an imaging device. This is a block diagram illustrating an example of the configuration of a solid-state imaging device. This is a block diagram illustrating an example of the configuration of a pixel. This is a block diagram illustrating a first example of an optical pulse response unit. This is a block diagram illustrating a second example of an optical pulse response unit. This is a block diagram illustrating a third example of an optical pulse response unit. This is a block diagram illustrating a fourth example of an optical pulse response unit. This is a block diagram illustrating another example of the configuration of a pixel. This is a block diagram illustrating another example of the configuration of a solid-state imaging device. This is a block diagram illustrating another example of the configuration of an optical pulse response unit. This is a block diagram illustrating a problem of the prior art. This is a block diagram illustrating an overview of the technology related to this disclosure. This is a diagram illustrating a first example of an optical pulse response unit to which the technology related to this disclosure is applied. This is a diagram illustrating a second example of an optical pulse response unit to which the technology related to this disclosure is applied. This is a diagram illustrating a third example of an optical pulse response unit to which the technology related to this disclosure is applied. This is a diagram illustrating an example of the arrangement of capacitors in the pixel array. This is a diagram illustrating the size of the power supply parallel area. This is a circuit diagram showing an example of the configuration of a pixel with a two-substrate structure. This is a cross-sectional view showing another example of the configuration of a pixel with a two-substrate structure. This is a cross-sectional view showing yet another example of the configuration of a pixel with a two-substrate structure. This is a circuit diagram showing an example of the configuration of a pixel with a three-substrate structure. This is a cross-sectional view showing an example of the configuration of a pixel with a three-substrate structure. This is a circuit diagram showing another example of a pixel configuration with a three-substrate structure. This is a cross-sectional view showing yet another example of a pixel configuration with a three-substrate structure. This is a circuit diagram showing yet another example of a pixel configuration with a three-substrate structure. This is a cross-sectional view showing yet another example of a pixel configuration with a three-substrate structure. This is a diagram showing an example of CMOS capacitance. This is a cross-sectional view showing an example of a pixel configuration with capacitance in the pixel isolation section. This is a cross-sectional view showing an example of a pixel configuration with a multilayer stacked structure.

[0009] The following describes the forms for implementing this disclosure (hereinafter referred to as embodiments). The explanation will be given in the following order.

[0010] 1. Examples of imaging devices, solid-state imaging devices, and pixel configurations 2. Outline of prior art, its problems, and the technology described herein 3. Optical pulse response unit to which the technology described herein is applied 4. Examples of capacitor arrangement 5. Pixel with a two-substrate structure 6. Pixel with a three-substrate structure 7. Types of capacitors 8. Pixels with other structures

[0011] <1. Examples of Imaging Device, Solid-State Imaging Device, and Pixel Configurations> This section describes examples of imaging devices, solid-state imaging devices, and pixel configurations that may employ an optical detection device to which the technology described herein is applied.

[0012] Figure 1 is a block diagram showing an example of the configuration of an imaging device.

[0013] In the figure, the imaging device 100 comprises an optical system 101, a solid-state imager 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, image processing unit 104, storage unit 105, display unit 106, and operation unit 107 are connected to each other via a bus 108. The imaging device 100 may be used as a standalone unit, incorporated into a mobile terminal such as a smartphone, or incorporated into an authentication device or a monitoring device.

[0014] The optical system 101 directs light from the subject into the solid-state imager 102, forming an image of the subject on the light-receiving surface of the solid-state imager 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0015] The solid-state imaging device 102 converts light from the subject into an electrical signal for each pixel, and outputs the electrical signal digitized. The solid-state imaging device 102 may be, for example, an event-based vision sensor. The light received by the solid-state imaging device 102 may be visible light, near-infrared light (NIR), short-wavelength infrared light (SWIR), ultraviolet light, or X-rays, etc.

[0016] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure conditions and imaging timing of the solid-state imaging device 102.

[0017] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing unit 104 may also include an application processor that performs processing based on software.

[0018] The storage unit 105 stores images captured by the solid-state imaging device 102, as well as imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store programs that operate the imaging device 100 based on software. The storage unit 105 may include ROM (Read Only Memory), RAM (Random Access Memory), and a memory card.

[0019] The display unit 106 displays captured images and various information to support the imaging operation. The display unit 106 may be a liquid crystal display or an organic EL (Electro-Luminescence) display.

[0020] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0021] Figure 2 is a block diagram showing an example of the configuration of a solid-state imaging device.

[0022] In the figure, the solid-state imaging device 102 includes a pixel array section 111, a row scanning circuit 112, a column processing circuit 113, a control signal generation circuit 114, and a frame memory 115. These circuits may be arranged on a single semiconductor substrate or on a multilayer substrate.

[0023] In the pixel array section 111, pixels 121 are arranged in a matrix in the row and column directions. Each pixel 121 is connected to a signal line SVL for each column and to a horizontal control line CHL for each row via a switch 122. In addition, each pixel 121 is connected to a vertical control line CVL for each column. Each pixel 121 outputs the count value of the pulse generated in response to the incidence of a photon as pixel data. The light receiving section into which the photons are incident may be equipped with a SPAD (Single Photon Avalanche Diode) or an avalanche photodiode (APD).

[0024] The row scanning circuit 112 sequentially selects rows in synchronization with the vertical synchronization signal. At this time, the row scanning circuit 112 can select a pixel 121 via the horizontal control line CHL. The row scanning circuit 112 supplies a selection signal SEL<1>-<n> to the switch 122 for each row in order to select a pixel 121 row by row. The row scanning circuit 112 also supplies a count reset signal RST<1>-<n> to each pixel 121 row in order to reset the count value of each pixel 121 row by row. RST<1>-<n> may be reset by row scanning or by resetting all rows at once. Resetting all rows at once can shorten the time until readout begins. The row scanning circuit 112 may include a vertical arbiter that mediates the selection of the row containing the pixel 121 in which a photon has been detected.

[0025] The column processing circuit 113 performs various signal processing operations on the pixel data transmitted via the signal line SVL. The column processing circuit 113 may include a line scanner that scans the columns. The column processing circuit 113 may also include a horizontal arbiter that arbitrates the selection of the column containing the pixel 121 in which a photon was detected.

[0026] The control signal generation circuit 114 controls the exposure and recharging of the photoelectric conversion section of each pixel 121 via the vertical control line CVL. The control signal generation circuit 114 supplies the recharge control signal RCG, the through-current control signal QEN, the initialization signal INT, and the clipping signal CRP to each pixel 121 column by column. The frame memory 115 stores the pixel data for one frame.

[0027] Figure 3 is a block diagram showing an example of pixel configuration.

[0028] In the figure, the pixel 121 includes an optical pulse response unit 131, a readout circuit 132, and a counter 133.

[0029] The optical pulse response unit 131 outputs a pulse in response to the incidence of a photon. At this time, the optical pulse response unit 131 can multiply the charge generated from the photon in order to detect the photon.

[0030] The readout circuit 132 reads out pulses output from the optical pulse response unit 131 in response to the incidence of photons. The readout circuit 132 is connected downstream of the optical pulse response unit 131.

[0031] The counter 133 performs counting operations based on pulses read by the readout circuit 132. The counter 133 is connected downstream of the readout circuit 132. The counter 133 is connected to the signal line SVL via switch 122. Switch 122 is turned on / off based on the selection signal SEL. The counter 133 is also supplied with a count reset signal RST via the horizontal control line CHL.

[0032] Figure 4 is a block diagram showing a first example of the optical pulse response section.

[0033] In the figure, the optical pulse response unit 131 includes a photoelectric conversion unit 141, a resistance unit 142, a recharge unit 143, a detection unit 144, and an discharge unit 145.

[0034] The photoelectric conversion unit 141 has its first electrode connected to the VRLD (Voltage Range Dead). At this time, the photoelectric conversion unit 141 multiplies the charge generated from the photons and discharges that charge to the VRLD. The photoelectric conversion unit 141 includes a SPAD (Single Power Adapter) 151. The anode of the SPAD 151 is connected to the VRLD, and the cathode of the SPAD 151 is connected to the resistor 142. Here, the VRLD can be set to apply a reverse bias voltage of several tens of volts, which enables the SPAD 151 to operate in the Geiger region. At this time, the amplification factor of the avalanche amplification of the SPAD 151 is theoretically infinite. Therefore, the SPAD 151 can generate a saturated output current without depending on the amount of incident photons per unit time, and can detect photons one by one.

[0035] The resistor 142 is connected in series with the photoelectric conversion unit 141 at the second electrode opposite to the first electrode of the photoelectric conversion unit 141. At this time, a parasitic resistor C1 is added at the connection point between the photoelectric conversion unit 141 and the resistor 142. The resistor 142 includes a resistor 152. In this case, the resistance value of resistor 152 can be greater than the resistance of SPAD 151. The resistance of the resistor 142 may be the on-resistance of the transistor or the resistance of the current source.

[0036] The recharge unit 143 recharges the photoelectric conversion unit 141 via the resistor unit 142. The recharge unit 143 may also be directly connected to the resistor unit 142. In this case, a parasitic resistor C2 is added to the connection point between the resistor unit 142 and the recharge unit 143. The recharge unit 143 is supplied with a power supply voltage VDD. The recharge unit 143 is also input with a recharge control signal RCG. In this case, the recharge unit 143 disconnects the resistor unit 142 from the power supply voltage VDD during the exposure valid period in which photon detection is effective. The recharge unit 143 also connects the power supply voltage VDD to the resistor unit 142 when recharging so that the SPAD 151 can operate in the Geiger region.

[0037] The detection unit 144 detects the potential VK2 of the resistor 142 and outputs the detection signal AQ to the output unit 145. At this time, the potential VK2 of the resistor 142 is input to the detection unit 144.

[0038] The discharge unit 145 is connected to a potential VRL, where the potential difference from the potential opposite to the side of the recharge unit 143 to which the resistor 142 is connected is smaller than the potential VRLD. At this time, based on the detection signal AQ of the potential VK2 of the resistor 142, the discharge unit 145 discharges at least a portion of the charge that can flow out to the photoelectric conversion unit 141 to a potential VRL, where the potential difference from the power supply potential VDD of the recharge unit 143 is smaller than the potential VRLD. At least a portion of the charge that can flow out to the photoelectric conversion unit 141 includes the charge remaining in each parasitic resistor C1, C2 after the quenching of the SPAD 151. Quenching of the SPAD 151 is a phenomenon in which the avalanche amplification of the SPAD 151 stops.

[0039] The discharge unit 145 includes a switch 155. The switch 155 may be a field-effect transistor. In this case, the switch 155 is turned on based on the detection signal AQ of the potential VK2 of the resistor unit 142, so that the charge remaining in each parasitic resistor C1 and C2 after the SPAD 151 quench can be discharged to the potential VRL. By discharging the charge remaining in the parasitic resistor C2 to the potential VRLD via the discharge unit 145, power consumption can be reduced compared to discharging to the potential VRLD via the SPAD 151.

[0040] Figure 5 is a block diagram showing a second example of the optical pulse response section.

[0041] In the same figure, the optical pulse response unit 131 differs from the optical pulse response unit 131 in Figure 4 in that the polarity of the SPAD 151 is reversed. Except for the reversed polarity of the SPAD 151, the configuration is the same as that of the optical pulse response unit 131 in Figure 4. That is, the optical pulse response unit 131 in Figure 4 is configured to output a pulse corresponding to the potential on the cathode side of the SPAD 151 (the second electrode of the photoelectric conversion unit 141) by applying a negative voltage (power supply potential VDD) to the cathode side of the SPAD 151 (the second electrode of the photoelectric conversion unit 141). On the other hand, the optical pulse response unit 131 in Figure 5 is configured to output a pulse corresponding to the potential on the anode side of the SPAD 151 (the first electrode of the photoelectric conversion unit 141) by applying a positive voltage (power supply potential VDD) to the cathode side of the SPAD 151 (the second electrode of the photoelectric conversion unit 141).

[0042] In a pixel that can employ a photodetection device to which the technology according to the present disclosure is applied, as the polarity of the SPAD, it is also possible to set the polarity to be the same as that of the SPAD 151 (photoelectric conversion unit 141) of the optical pulse response unit 131 in FIG. 4, or to set the polarity to be the same as that of the SPAD 151 (photoelectric conversion unit 141) of the optical pulse response unit 131 in FIG. 5. The same shall apply to each configuration described hereinafter.

[0043] FIG. 6 is a block diagram showing a third example of the optical pulse response unit.

[0044] In this figure, the optical pulse response unit 161 includes a photoelectric conversion unit 171 instead of the photoelectric conversion unit 141 in FIG. 4. The other configuration of the optical pulse response unit 161 is the same as the configuration of the optical pulse response unit 131 in FIG. 4. The photoelectric conversion unit 171 includes a plurality of SPADs 151. These SPADs 151 are connected in parallel. The anodes of these plurality of SPADs 151 are connected to the potential VRDL, and the cathodes of these plurality of SPADs 151 are connected to the resistance unit 142. The photons detected by these plurality of SPADs 151 are added and output from the photoelectric conversion unit 171.

[0045] Here, by providing a plurality of SPADs 151 in the photoelectric conversion unit 171, the number of photons detected per pixel can be increased, and the signal-to-noise ratio can be improved.

[0046] FIG. 7 is a block diagram showing a fourth example of the optical pulse response unit.

[0047] In this figure, the optical pulse response unit 181 includes a photoelectric conversion unit 191 and a resistance unit 192 instead of the photoelectric conversion unit 171 and the resistance unit 142 in FIG. 6. The other configuration of the optical pulse response unit 181 is the same as that of the optical pulse response unit 161 in FIG. 6. The photoelectric conversion unit 191 includes a plurality of SPADs 151. The resistance unit 192 includes a plurality of resistors 152. Each SPAD 151 is connected in series to a resistor 152, and the series circuits of the SPAD 151 and the resistor 152 are connected in parallel. The anodes of these plurality of SPADs 151 are connected to the potential VRDL, and the connection points between the resistors 152 are connected to the recharge unit 143. The photons detected by these plurality of SPADs 151 are added and output from the photoelectric conversion unit 191.

[0048] Here, by providing a plurality of SPADs 151 in the photoelectric conversion unit 191, the number of photons detected per pixel can be increased, and the signal-to-noise ratio can be improved. <##

[0049] Thus, in the configuration of FIG. 7, based on the detection result of the potential VK2 of the resistance unit 192 connected in series to the photoelectric conversion unit 191, a charge is discharged from the power supply potential VDD to a potential VRL that is lower than the potential VRDL. Thereby, compared with the case where the charge remaining after quenching of the SPAD 151 is discharged to the potential VRDL via the SPAD 151, the power consumption can be reduced.

[0050] In the above example, the optical pulse response unit 131 and the readout circuit 132 are provided in the pixel 121. In the following example, a plurality of optical pulse response units 131 and a plurality of readout circuits 132 are provided in the pixel.

[0051] FIG. 8 is a block diagram showing another configuration example of the pixel.

[0052] In this figure, the pixel 221 includes a plurality of optical pulse response units 131, a plurality of readout circuits 132, an OR circuit 233, and a counter 133.

[0053] Each optical pulse response unit 131 is connected in series with a readout circuit 132. The series circuit of the optical pulse response unit 131 and the readout circuit 132 is connected to an OR circuit 233, and a counter 133 is connected downstream of the OR circuit 233. The detection results of the photons read out by each readout circuit 132 are added together in the OR circuit 233 and counted by the counter 133.

[0054] As shown above, in the configuration of Figure 8, multiple optical pulse response units 131 and multiple readout circuits 132 are provided on the pixel 221. This makes it possible to increase the number of photons detected per pixel and improve the signal-to-noise ratio.

[0055] In the above example, based on the detection signal AQ of the detection unit 144, charge was discharged to a potential VRL where the potential difference from the power supply potential VDD was lower than the potential VRLD. In the following example, based on the detection signal AQ of the detection unit 144, charge was discharged to a potential VRL where the potential difference from the power supply potential VDD was lower than the potential VRLD, and the recharge unit 143 was controlled.

[0056] Figure 9 is a block diagram showing another example of a solid-state imaging device configuration.

[0057] In the same figure, the solid-state imaging device includes a pixel array unit 116 instead of the pixel array unit 111 described with reference to Figure 2. Also, the solid-state imaging device in Figure 9 has the control signal generation circuit 114 removed from the solid-state imaging device 102 in Figure 2. The other configurations of the solid-state imaging device in Figure 9 are the same as those of the solid-state imaging device 102 in Figure 2.

[0058] In the pixel array section 116, pixels 123 are arranged in a matrix in the row and column directions. Each pixel 123 is connected to a signal line SVL for each column and to a horizontal control line CHL for each row via a switch 122. Each pixel 123 outputs the count value of the pulse generated in response to the incidence of a photon as pixel data.

[0059] Figure 10 is a block diagram showing another example of the configuration of the optical pulse response unit.

[0060] In the same figure, the optical pulse response unit 331 is the same as the optical pulse response unit 131 described with reference to Figure 4, with the addition of a pulse generation unit 341. Also, the input of the readout circuit 132 is connected to the connection point between the resistor unit 142 and the recharge unit 143. The other configurations of the optical pulse response unit 331 in Figure 10 are the same as those of the optical pulse response unit 131 in Figure 4.

[0061] The pulse generation unit 341 controls the discharge unit 145 based on the detection signal AQ from the detection unit 144 and generates a recharge control signal RCG for the recharge unit 143. At this time, the pulse generation unit 341 can output the detection signal AQ from the detection unit 144 to the discharge unit 145 in order to control the discharge unit 145. In addition, the pulse generation unit 341 can set the falling edge timing of the recharge control signal RCG based on the falling edge timing of the detection signal AQ.

[0062] As described above, in the configuration shown in Figure 10, based on the detection signal AQ of the detection unit 144, charge is discharged to a potential VRL where the potential difference from the power supply potential VDD is lower than that of potential VRLD, and a recharge control signal RCG for the recharge unit 143 is generated. This allows the recharge unit 143 to be controlled based on the output timing of the detection signal AQ of the detection unit 144. Therefore, the time lag between discharging the remaining charge after the quench of the SPAD 151 to potential VRL and returning the SPAD 151 to the Geiger region can be reduced.

[0063] <2. Conventional Technology, its Problems, and an Overview of the Technology in This Disclosure> When a typical image sensor with several tens of megapixels employs pixels using SPADs, and high-intensity light such as sunlight is incident on the entire light-receiving surface, the cathodes of all pixels will be charged and discharged at approximately the same time. In this case, a rapid potential drop of several volts occurs throughout the entire pixel array, which may make it difficult for the pixel circuit to operate.

[0064] Specifically, as shown in Figure 11A, when current flows through the optical pulse response unit 131 due to the potential difference between the power supply potential VDD and the potentials VRLD and VRL, the potentials VRLD and VRL fluctuate rapidly in response to the incidence of photons, as shown in Figure 11B. If such fluctuations in potentials VRLD and VRL occur simultaneously in all pixels 121 of the pixel array unit 111, the power supply potential VDD drops sharply.

[0065] In contrast, in the technology relating to this disclosure, as shown in Figure 12A, capacitors CA and CB are provided between the power supply potential VDD and potential VRLD, and between the power supply potential VDD and potential VRL, respectively. As a result, as shown in Figure 12B, fluctuations in potential VRLD are suppressed by supplying charge from, for example, capacitor CA. Consequently, it becomes possible to suppress a rapid drop in the power supply potential VDD.

[0066] The embodiments of this disclosure will be described below.

[0067] <3. Optical pulse response unit to which the technology described herein is applied> Here, an example of an optical pulse response unit to which the technology described herein is applied will be described.

[0068] (First Example) Figure 13 shows a first example of an optical pulse response unit to which the technology of this disclosure is applied.

[0069] In the optical pulse response unit 131 shown in Figure 13, a constant current source 411 is connected to the cathode of the SPAD 151, which is part of the photoelectric conversion unit 141 that multiplies the charge generated from photons. The constant current source 411 recharges the photoelectric conversion unit 141, similar to the recharge unit 143 described above.

[0070] In the optical pulse response unit 131 shown in Figure 13, current flows through the SPAD 151 due to the charge multiplication caused by the incidence of photons. When the cathode potential VK1 of the SPAD 151 decreases, a quench occurs as the SPAD 151 falls below the breakdown voltage. When a quench occurs, the current flowing through the SPAD 151 stops, and the cathode potential VK1 returns to its original potential with the supply of current from the constant current source 411. That is, current I_11 flows from the power supply potential VDD of the recharge unit (constant current source 411) to the anode side potential VRLD of the photoelectric conversion unit 141.

[0071] Therefore, in the optical pulse response unit 131 shown in Figure 13, a capacitance CP is provided between the power supply potential VDD and the potential VRLD, which supply current to the optical pulse response unit 131 in response to the incidence of photons. This makes it possible to suppress a rapid drop in the power supply potential VDD even when high-intensity light is incident on the entire light-receiving surface of the image sensor.

[0072] (Second Example) Figure 14 shows a second example of an optical pulse response unit to which the technology of this disclosure is applied.

[0073] In the optical pulse response unit 131 shown in Figure 14, an NMOS diode 421 is connected between the potential VK2 of the resistor 142 and a potential VRL, which is different from the anode potential VRLD of the photoelectric conversion unit 141. Here, the potential VRL is the substrate potential on which the NMOS diode 421 is formed. A clip transistor is also provided between the potential VK2 of the resistor 142 and the input of the readout circuit 132.

[0074] In the optical pulse response unit 131 shown in Figure 14, a current I_21 flows from the power supply potential VDD to the potential VRLD during photon incidence and recharge operation. On the other hand, when the cathode potential VK1 decreases due to leakage or the like, the NMOS diode 421 is turned ON to suppress the potential drop of the cathode potential VK1. This prevents the MOS from exceeding its breakdown voltage due to the potential drop. In other words, during charge multiplication and recharge operation, a current I_21 flows from the power supply potential VDD to the potential VRLD, and when the cathode potential VK1 decreases due to leakage or the like, a current I_22 flows from the potential VRL to the potential VRLD via the NMOS diode 421.

[0075] Therefore, in the optical pulse response unit 131 shown in Figure 14, capacitors CP1 and CP2 are provided between the power supply potential VDD and potential VRLD, which supply current to the optical pulse response unit 131 in response to the incidence of photons. Specifically, capacitor CP1 is provided between the power supply potential VDD and potential VRL, and capacitor CP2 is provided between potential VRL and potential VRLD, which supply current to the optical pulse response unit 131 when the cathode potential VK1 decreases. This makes it possible to suppress a rapid drop in the power supply potential VDD even when high-intensity light is incident on the entire light-receiving surface of the image sensor. Note that in the configuration of Figure 14, only one of capacitors CP1 or CP2 may be provided.

[0076] In a configuration with multiple current paths, such as the optical pulse response unit 131 shown in Figure 14, larger capacitance values ​​may be provided for current paths (potential differences) where larger currents flow. This makes it possible to suppress instantaneous drop in response to larger potential differences while simultaneously reducing the capacitance area.

[0077] (Third Example) Figure 15 shows a third example of an optical pulse response section in a pixel 121 to which the technology of this disclosure is applied.

[0078] In the optical pulse response unit 131 shown in Figure 15, the detection unit 144 and the discharge unit 145, as explained with reference to Figure 4, are connected to the potential VK2 of the resistor unit 142. As described above, the discharge unit 145 discharges the charge to the discharge destination potential VRL after the photoelectric conversion unit 141 has quenched.

[0079] In the optical pulse response unit 131 shown in Figure 15, during charge multiplication and recharge operations, current I_31 flows from the power supply potential VDD to potential VRLD, and after quenching, current I_32 flows from the power supply potential VDD to potential VRL.

[0080] Therefore, in the optical pulse response unit 131 shown in Figure 15, a capacitance CP1 is provided between the power supply potential VDD and potential VRLD, which supply current to the optical pulse response unit 131 in response to the incidence of photons, and a capacitance CP2 is provided between the power supply potential VDD and potential VRL, which supply current to the optical pulse response unit 131 after quenching. This makes it possible to suppress a rapid drop in the power supply potential VDD even when high-intensity light is incident on the entire light-receiving surface of the image sensor. Note that even in the configuration of Figure 15, only one of capacitances CP1 or CP2 may be provided.

[0081] In a configuration with multiple current paths, such as the optical pulse response unit 131 shown in Figure 15, larger capacitance values ​​may be provided for current paths (potential differences) where larger currents flow. This makes it possible to suppress instantaneous drop in response to larger potential differences while simultaneously reducing the area of ​​the capacitance.

[0082] <4. Example of Capacity Arrangement> In the embodiments of this disclosure, the above-mentioned capacity is provided in units of one or more pixels.

[0083] Here, with reference to Figure 16, an example of the arrangement of capacitances in a plan view of the pixel array 111 will be described. Figures A to C of Figure 16 show pixels 121 arranged in a matrix in the pixel array 111. Although not shown in the figure, each pixel 121 shown in Figures A to C is assumed to have an optical pulse response unit that includes at least the photoelectric conversion unit and a recharge unit for recharging the photoelectric conversion unit.

[0084] In each pixel 121 shown in Figure 16A, as explained with reference to Figures 14 and 15, there are two current paths in the optical pulse response section, and each pixel 121 is provided with capacitances CP1 and CP2 corresponding to the current paths. In this way, each of the pixels arranged in the pixel array section may be provided with capacitances corresponding to each of the current paths in the optical pulse response section.

[0085] In each pixel 121 shown in Figure 16B, as explained with reference to Figures 14 and 15, there are two current paths in the optical pulse response section, and capacitances CP1 and CP2 corresponding to the current paths are provided for each of the multiple pixels 121 (for every four pixels 121 in the example of Figure B). In this way, capacitances corresponding to the current paths of the optical pulse response section may be provided for each of the multiple pixels arranged in the pixel array section.

[0086] In each pixel 121 shown in Figure 16, as explained with reference to Figure 13, there is one current path in the optical pulse response section, and each pixel 121 is provided with either a capacitance CP1 or CP2 corresponding to the current path. In this way, each of the pixels arranged in the pixel array section may be provided with a capacitance corresponding to the current path of the optical pulse response section.

[0087] In particular, in the example shown in Figure 16, in the optical pulse response section of each pixel 121, a larger capacitance value is provided for current paths (between the first potential and the second potential) where a larger current flows.

[0088] Specifically, the more current a current flows through a current path (between the first potential and the second potential), the more capacitive elements should be provided as capacitance. For example, in the example in Figure 16, if the current flowing through the current path corresponding to capacitance CP1 is greater than the current flowing through the current path corresponding to capacitance CP2, then it is sufficient to have more capacitive elements constituting capacitance CP1 than capacitive elements constituting capacitance CP2.

[0089] Furthermore, the current path through which a larger current flows (between the first potential and the second potential) may be provided with a larger capacity in the parallel area of ​​the power supply. For example, as shown in Figure 17, the current I_A flowing from power supply potential VDD to potential VSS_A is greater than the current I_B flowing from power supply potential VDD to potential VSS_B. In this case, the area of ​​the wiring layout for potential VSS_A relative to power supply potential VDD is made larger than the area of ​​the wiring layout for potential VSS_B relative to power supply potential VDD.

[0090] In other words, as shown in Figure 18A, the coverage area of ​​the vertical wiring layout is made such that the wiring layout with a potential VSS_A relative to the power supply potential VDD is larger than the wiring layout with a potential VSS_B relative to the power supply potential VDD.

[0091] Furthermore, as shown in Figure B, the coverage area of ​​the wiring layout in the planar direction may be such that the wiring layout with a potential VSS_A relative to the power supply potential VDD is larger than the wiring layout with a potential VSS_B relative to the power supply potential VDD.

[0092] In this way, by providing a larger capacitance value for current paths carrying larger currents, it becomes possible to suppress the instantaneous drop in power supply potential within a limited area.

[0093] <5. Pixel with Two-Substrate Structure> The pixel 121 to which the technology of this disclosure is applied can adopt a two-substrate structure formed of two substrates. In this case, the first potential and the second potential that constitute the current path for supplying current to the optical pulse response unit 131 may be supplied to the same substrate or to different substrates. The counter 133 that performs counting based on the pulses output from the optical pulse response unit 131 may be provided on the same substrate as the substrate to which at least one of the first potential and the second potential is supplied, or it may be provided on different substrates.

[0094] (Example 1 of a two-substrate structure) Figure 19 is a circuit diagram showing an example of the configuration of a pixel 121 in a two-substrate structure.

[0095] The pixel 121 shown in Figure 19 has a circuit configuration equivalent to the pixel 121 having an optical pulse response unit 131 described with reference to Figure 13, except that it has a clipping transistor between the potential VK2 of the resistor 142 and the input of the readout circuit 132.

[0096] The pixel 121 shown in Figure 19 is formed from a first substrate B1 on which a photoelectric conversion unit 141 is provided, and a second substrate B2 laminated on the first substrate B1. The dashed line in Figure 19 indicates the bonding surface between the first substrate B1 and the second substrate B2.

[0097] In the example shown in Figure 19, the second substrate B2 is provided with a counter 133 that counts based on pulses output from the optical pulse response unit 131 in response to the incidence of photons, as well as the clip transistors mentioned above.

[0098] In the pixel 121 shown in Figure 19, the power supply potential VDD is supplied to the second substrate B2, and the potential VRLD is supplied to the first substrate B1. A capacitance CP is formed on the second substrate B2, between the power supply potential VDD and the potential VRLD. The capacitance CP formed on the second substrate B2 and the potential VRLD on the first substrate B1 are connected via a Cu-Cu junction JCT, which is formed by joining metal wirings formed on each substrate.

[0099] In this way, the power supply potential VDD and the potential VRLD are applied to different substrates, and the capacitance CP provided between them can be formed on the same substrate as the power supply potential VDD. Furthermore, the capacitance CP and the potential VRLD, which is applied to a substrate different from the substrate on which the capacitance CP is formed, can be connected via a Cu-Cu junction JCT.

[0100] (Example 2 of a two-substrate structure) Figure 20 is a cross-sectional view showing another example of a two-substrate structure for a pixel 121.

[0101] The pixel 121 shown in Figure 20 is constructed by bonding together a pixel substrate 521, which is the first substrate B1, and a logic substrate 551, which is the second substrate B2.

[0102] The pixel substrate 521 has a semiconductor substrate 522 made of silicon or the like, a wiring layer 523, and an on-chip lens 524. Hereinafter, the wiring layer 523 of the pixel substrate 521 will be referred to as the sensor-side wiring layer 523 to distinguish it from the wiring layer 553 of the logic substrate 551, which will be described later, and the wiring layer 553 of the logic substrate 551 will be referred to as the logic-side wiring layer 553. The sensor-side wiring layer 523 of the pixel substrate 521 and the logic-side wiring layer 553 of the logic substrate 551 are joined facing each other. With respect to the semiconductor substrate 522, the surface on which the sensor-side wiring layer 523 is formed is the front surface of the semiconductor substrate 522, and the surface on which the on-chip lens 524 is formed, which is on the upper side in the figure, is the back surface of the semiconductor substrate 522 and is also the light-receiving surface to which light is incident.

[0103] On the semiconductor substrate 522, an N-well 531, a P-type diffusion layer 532, an N-type diffusion layer 533, and a hole accumulation layer 534 are formed inside the pixel separation portion 535. The pixel separation portion 535 is located at the pixel boundary, which is the boundary between adjacent pixels in a plan view.

[0104] The N-well 531 is formed by controlling the semiconductor substrate 522 to an N-type with a low impurity concentration, and forms an electric field that transfers electrons generated by photoelectric conversion in the pixel 121 to the avalanche multiplication region. Alternatively, a P-well, which is a P-type with a low impurity concentration, can be used instead of the N-well 531.

[0105] The P-type diffusion layer 532 is a dense P-type diffusion layer formed in a rectangular planar region within the N-well 531. The N-type diffusion layer 533 is a dense N-type diffusion layer formed in a rectangular planar region slightly larger than the planar region of the P-type diffusion layer 532. A portion of the N-type diffusion layer 533 near the substrate surface is formed with even higher density and serves as a contact layer 533A connected to a cathode electrode to supply a negative voltage for forming an avalanche multiplication region. The depletion layer formed in the PN junction region where the P-type diffusion layer 532 and the N-type diffusion layer 533 join forms the avalanche multiplication region. In this way, the P-type diffusion layer 532 and the N-type diffusion layer 533 constitute the photoelectric conversion unit (SPAD).

[0106] The hole accumulation layer 534 is a P-type diffusion layer formed to surround the side and bottom surfaces (the surfaces facing the on-chip lens 524) of the N-well 531, and accumulates holes. Furthermore, a portion of the hole accumulation layer 534 near the front surface is formed with an even higher density and serves as a contact layer 534A that is electrically connected to the anode electrode.

[0107] The pixel isolation section 535 is formed at the boundary with an adjacent pixel and electrically isolates it from other adjacent pixels. The pixel isolation section 535 may consist of, for example, only an insulating layer, or it may be a double structure in which the outside (N-well 531 side) of a metal layer such as tungsten (W), aluminum (Al), titanium (Ti), or titanium nitride (TiN) is covered with an insulating layer such as SiO2.

[0108] The sensor-side wiring layer 523 has contact electrodes and metal wiring formed on it, which serve as cathode electrodes. The contact electrodes, which serve as cathode electrodes, and the logic-side wiring layer 553 are connected via a Cu-Cu junction JCT, which is formed by joining metal wiring formed on the pixel substrate 521 and the logic substrate 551, with the aforementioned clip transistor in between.

[0109] Furthermore, in the sensor-side wiring layer 523, a contact electrode (not shown) that serves as an anode electrode electrically connected to the contact layer 534A is electrically connected to the metal wiring of the logic board 551. The anode-side potential VRLD supplied from the logic board 551 is supplied to the contact layer 534A via the metal wiring and the contact electrode. In other words, the potential VRLD is also supplied to the hole accumulation layer 534 via the contact layer 534A.

[0110] On the other hand, the logic board 551 has a semiconductor substrate 552 made of silicon or the like, and a wiring layer 553 (logic-side wiring layer 553).

[0111] In the diagram, multiple MOS transistors, including MOS transistors that serve as a constant current source and MOS transistors that constitute an inverter, are formed on the front surface of the upper semiconductor substrate 552.

[0112] Metal wiring and contact electrodes are formed on the logic-side wiring layer 553. The contact electrodes of the logic-side wiring layer 553 and the sensor-side wiring layer 523 are connected via a Cu-Cu junction JCT, which is formed by joining metal wiring formed on the pixel substrate 521 and the logic substrate 551, with the aforementioned clip transistor in between.

[0113] In the pixel 121 shown in Figure 20, the power supply potential VDD is applied to the sensor-side wiring layer 523 of the pixel substrate 521 (first substrate B1), and the potential VRLD is applied to the hole accumulation layer 534 (contact layer 534A) of the pixel substrate 521 (first substrate B1). The capacitance CP provided between the power supply potential VDD and the potential VRLD is formed in the sensor-side wiring layer 523 of the pixel substrate 521 (first substrate B1).

[0114] In this way, the power supply potential VDD and the potential VRLD are applied to the same substrate, and the capacitance CP provided between them can also be formed on the same substrate as the power supply potential VDD and the potential VRLD.

[0115] (Example 3 of a two-substrate structure) Figure 21 is a cross-sectional view showing yet another example of the configuration of a pixel 121 in a two-substrate structure.

[0116] The pixel 121 shown in Figure 21 is basically configured in the same way as the pixel 121 described with reference to Figure 20.

[0117] However, in the pixel 121 shown in Figure 21, the power supply potential VDD is applied to the logic-side wiring layer 553 of the logic board 551 (second board B2), and the potential VRLD is applied to the hole accumulation layer 534 (contact layer 534A) of the pixel board 521 (first board B1). A capacitance CP provided between the power supply potential VDD and the potential VRLD is formed in the sensor-side wiring layer 523 of the pixel board 521 (first board B1). The capacitance CP formed on the pixel board 521 and the power supply potential VDD of the logic board 551 are connected via a Cu-Cu junction JCT formed by joining metal wiring formed on the pixel board 521 and the logic board 551, respectively.

[0118] In this way, the power supply potential VDD and the potential VRLD are supplied to different substrates, and the capacitance CP provided between them can be formed on the same substrate as the potential VRLD. Furthermore, the capacitance CP and the power supply potential VDD supplied to a substrate different from the substrate on which the capacitance CP is formed can be connected via a Cu-Cu junction JCT.

[0119] <6. Pixel with a three-substrate structure> The pixel 121 to which the technology of this disclosure is applied can also adopt a three-substrate structure formed of three substrates. In this case, the first potential (power supply potential VDD), the second potential (potential VRLD), and the third potential (potential VRL) that constitute the current path for supplying current to the optical pulse response section 131 may be supplied to the same substrate, or at least one of them may be supplied to different substrates.

[0120] (Example of a three-substrate structure configuration 1) Figure 22 is a circuit diagram showing an example of a three-substrate structure for a pixel 121.

[0121] The pixel 121 shown in Figure 22 has a circuit configuration equivalent to the pixel 121 having an optical pulse response unit 131 described with reference to Figure 15. That is, the MOS transistor group E11 of the pixel 121 shown in Figure 22 corresponds to the detection unit 144 and the emission unit 145 in Figure 15.

[0122] The pixel 121 shown in Figure 22 is formed from a first substrate B1 on which a photoelectric conversion unit 141 is provided, a second substrate B2 laminated on the first substrate B1, and a third substrate B3 laminated on the second substrate B2. The dashed lines in Figure 22 indicate the bonding surfaces between the first substrate B1 and the second substrate B2, and between the second substrate B2 and the third substrate B3.

[0123] In the example shown in Figure 22, the third substrate B3 is provided with a counter 133 that counts based on pulses output from the optical pulse response unit 131 in response to the incidence of photons.

[0124] Figure 23 is a cross-sectional view showing an example of the configuration of a pixel 121 in the three-substrate structure shown in Figure 22.

[0125] The pixel 121 shown in Figure 23 is basically configured the same as the pixel 121 described with reference to Figure 20. However, the pixel 121 shown in Figure 23 differs from the pixel 121 described with reference to Figure 20 in that the semiconductor substrate 522, the sensor-side wiring layer 523, and the logic substrate 551 are bonded together as the first substrate B1, the second substrate B2, and the third substrate B3, respectively.

[0126] In the pixel 121 shown in Figures 22 and 23, the power supply potential VDD is supplied to the logic-side wiring layer 553 of the logic board 551 (third board B3), the potential VRL is supplied to the sensor-side wiring layer 523 (second board B2), and the potential VRLD is supplied to the hole accumulation layer 534 of the pixel board 521 (first board B1). Capacitors CP1 and CP2, provided between the power supply potential VDD and the potential VRLD, are formed on the sensor-side wiring layer 523 (second board B2). Capacitors CP1 and CP2 formed on the sensor-side wiring layer 523 and the power supply potential VDD of the logic board 551 are connected via a Cu-Cu junction JCT formed by joining metal wirings formed on the sensor-side wiring layer 523 and the logic board 551, respectively. Furthermore, the capacitance CP1 formed on the sensor-side wiring layer 523 and the potential VRLD of the pixel substrate 521 are connected via the contact layer 534A.

[0127] Thus, the power supply potentials VDD, VRLD, and VRL are applied to different substrates, and the capacitance CP1, located between the power supply potential VDD and VRLD, and the capacitance CP2, located between the power supply potential VDD and VRL, can be formed on the same substrate. Furthermore, the capacitances CP1 and CP2, and the power supply potential VDD, which is applied to a substrate different from the substrate on which the capacitances CP1 and CP2 are formed, can be connected via a Cu-Cu junction JCT. In addition, area reduction can be achieved by forming the capacitances on a substrate separate from the substrate on which the counter requiring high stacking is installed.

[0128] (Example 2 of a three-substrate structure) Figure 24 is a circuit diagram showing another example of the configuration of the pixel 121 in a three-substrate structure, and Figure 25 is a cross-sectional view showing the example of the pixel 121 configuration shown in Figure 24.

[0129] The pixels 121 shown in Figures 24 and 25 are basically configured in the same way as the pixels 121 described with reference to Figures 22 and 23. However, the pixels 121 shown in Figures 24 and 25 differ from the pixels 121 described with reference to Figures 22 and 23 in that the capacitance CP2 provided between the power supply potential VDD and the potential VRL is formed in the logic side wiring layer 553 of the logic board 551 (third board B3).

[0130] In this case, the capacitance CP2 formed on the logic board 551 (third board B3) and the potential VRL of the sensor-side wiring layer 523 (second board B2) are connected via a Cu-Cu junction JCT formed by joining metal wirings formed on the sensor-side wiring layer 523 and the logic board 551, respectively.

[0131] Thus, the power supply potentials VDD, VRLD, and VRL are each applied to different substrates, and the capacitance CP1 provided between the power supply potential VDD and VRLD, and the capacitance CP2 provided between the power supply potential VDD and VRL, can each be formed on different substrates. Furthermore, capacitance CP1 and the power supply potential VDD, which is applied to a substrate different from the substrate on which capacitance CP1 is formed, can be connected via a Cu-Cu junction JCT. In addition, capacitance CP2 and the potential VRL, which is applied to a substrate different from the substrate on which capacitance CP2 is formed, can be connected via a Cu-Cu junction JCT.

[0132] (Example 3 of a three-substrate structure) Figure 26 is a circuit diagram showing yet another example of the configuration of the pixel 121 in a three-substrate structure, and Figure 27 is a cross-sectional view showing the example of the pixel 121 configuration shown in Figure 26.

[0133] The pixel 121 shown in Figure 26 adopts a circuit configuration equivalent to the pixel 121 having the optical pulse response unit 131 described with reference to Figure 14. That is, the MOS transistor group E11 of the pixel 121 shown in Figure 26 corresponds to the NMOS diode 421 in Figure 14.

[0134] In the pixel 121 shown in Figures 26 and 27, the power supply potential VDD is supplied to the logic-side wiring layer 553 of the logic board 551 (third board B3), the potential VRL is supplied to the sensor-side wiring layer 523 (second board B2), and the potential VRLD is supplied to the hole accumulation layer 534 (contact layer 534A) of the pixel board 521 (first board B1). Capacitors CP1 provided between the power supply potential VDD and the potential VRL, and capacitors CP2 provided between the potential VRL and the potential VRLD are formed on the sensor-side wiring layer 523 (second board B2). Capacitors CP1 formed on the sensor-side wiring layer 523 and the power supply potential VDD of the logic board 551 are connected via a Cu-Cu junction JCT formed by joining metal wirings formed on the sensor-side wiring layer 523 and the logic board 551, respectively. Furthermore, the capacitance CP2 formed on the sensor-side wiring layer 523 and the potential VRLD of the pixel substrate 521 are connected via the contact layer 534A.

[0135] In this way, the power supply potentials VDD, VRLD, and VRL are applied to different substrates, and the capacitance CP1 provided between the power supply potential VDD and VRL, and the capacitance CP2 provided between VRL and VRLD, can be formed on the same substrate. Furthermore, capacitance CP1 and the power supply potential VDD, which is applied to a substrate different from the substrate on which capacitance CP1 is formed, can be connected via a Cu-Cu junction JCT.

[0136] (Example 4 of a three-substrate structure) Figure 28 is a cross-sectional view showing yet another example of the configuration of a pixel 121 in a three-substrate structure.

[0137] Although the circuit diagram of pixel 121 is omitted here, the MOS transistor group E11 of pixel 121 shown in Figure 28 corresponds to the NMOS diode 421 in Figure 14, similar to the pixel 121 shown in Figures 26 and 27.

[0138] The pixel 121 shown in Figure 28 is basically configured the same as the pixel 121 described with reference to Figure 27. However, the pixel 121 shown in Figure 28 differs from the pixel 121 described with reference to Figure 27 in that the capacitance CP1 provided between the power supply potential VDD and the potential VRL is formed in the logic side wiring layer 553 of the logic board 551 (third board B3).

[0139] In this case, the capacitance CP1 formed on the logic board 551 (third board B3) and the potential VRL of the sensor-side wiring layer 523 (second board B2) are connected via a Cu-Cu junction JCT formed by joining metal wirings formed on the sensor-side wiring layer 523 and the logic board 551, respectively.

[0140] Thus, the power supply potentials VDD, VRLD, and VRL are each applied to different substrates, and the capacitance CP1 provided between the power supply potential VDD and VRL, and the capacitance CP2 provided between VRL and VRLD, can each be formed on different substrates. Furthermore, capacitance CP1 and the potential VRL, which is applied to a substrate different from the one on which capacitance CP1 is formed, can be connected via a Cu-Cu junction JCT.

[0141] <7. Types of Capacitance> Various capacities can be adopted as the capacities CP (CP1, CP2) provided in the pixel 121 to which the technology relating to this disclosure is applied.

[0142] For example, the capacitance CP may be composed of MIM (Metal-Insulator-Metal) capacitance. In this case, since the area of ​​the underlying substrate is not consumed and the wiring area can be suppressed, it is possible to achieve a smaller pixel area.

[0143] Furthermore, the capacitance CP may be composed of MOM (Metal-Oxide-Metal) capacitance. In this case, since it does not consume the area of ​​the underlying substrate, it is possible to achieve smaller pixel areas. In addition, since it does not require a dedicated process, costs can be reduced.

[0144] Furthermore, the capacitance CP may be composed of a MOS (Metal Oxide Semiconductor) capacitance as shown in Figure 29.

[0145] For example, as shown in Figure 29A, the capacitance CP may be a MOS capacitance consisting of a P-type MOS transistor, where one end, the gate, is connected to a high potential (e.g., the power supply potential VDD), and the other end, which connects the source and drain, is connected to a low potential (e.g., the potential VRL).

[0146] Furthermore, as shown in Figure B, the capacitance CP may be a MOS capacitance consisting of a P-type MOS transistor, where one end, the gate, is connected to a low potential (e.g., potential VRL), and the other end, which connects the source and drain, is connected to a high potential (e.g., power supply potential VDD).

[0147] Furthermore, as shown in Figure C, the capacitance CP may be a MOS capacitance consisting of an N-type MOS transistor, where one end, the gate, is connected to a high potential (e.g., the power supply potential VDD), and the other end, which connects the source and drain, is connected to a low potential (e.g., the potential VRL).

[0148] Furthermore, as shown in Figure D, the capacitance CP may be a MOS capacitance consisting of an N-type MOS transistor, where one end, the gate, is connected to a low potential (e.g., potential VRL), and the other end, which connects the source and drain, is connected to a high potential (e.g., power supply potential VDD).

[0149] For example, as in the pixel 121 of the three-substrate structure described with reference to Figures 22 and 23, if the capacitance CP2 between the power supply potential VDD and the charge discharge potential VRL is placed on the second substrate B2 where the high-voltage transistor is located, it does not consume the area of ​​the third substrate B3, which has a high integration density of logic circuits, thus enabling a smaller pixel area.

[0150] <8. Pixels with other structures> (Pixels with capacitance in the pixel separation portion) In a pixel 121 to which the technology of this disclosure is applied, the pixel separation portion may also be provided with capacitance.

[0151] Figure 30 is a cross-sectional view showing an example of a pixel configuration with capacitance in the pixel separation section.

[0152] The pixel 121 shown in Figure 30 is basically configured the same as the pixel 121 described with reference to Figure 23. However, the pixel 121 shown in Figure 30 differs from the pixel 121 described with reference to Figure 23 in that the capacitance CP1 provided between the power supply potential VDD and the potential VRLD is formed between the hole accumulation layer 534 and the pixel separation portion 535, along the pixel separation portion 535.

[0153] Furthermore, in the pixel 121 shown in Figure 30, the pixel separation portion 535, which is the boundary with the adjacent pixel, has a fixed power supply potential VDD applied to it via a Cu-Cu junction JCT. As described above, the hole accumulation layer 534 is given a potential VRLD by a contact layer 534A that is electrically connected to the anode electrode. This makes it possible to provide a capacitance CP1 between the power supply potential VDD and the potential VRLD in the pixel 121 shown in Figure 30.

[0154] In addition, in the pixel 121 shown in Figure 30, the potential VRLD becomes approximately -20V, so a high electric field is generated around the pixel separation section 535. However, since capacitance CP1 can be formed on the first substrate B1, the design constraints on the second substrate B2 and the third substrate B3 can be reduced.

[0155] (Multilayered Pixel Structure) A pixel 121 to which the technology of this disclosure is applied can adopt a multilayered structure different from the structure described above.

[0156] Figure 31 is a cross-sectional view showing an example of the configuration of a multilayer stacked pixel 121.

[0157] The pixel 121 shown in Figure 31 is formed by a substrate 611 on which a photoelectric conversion unit is provided, a substrate 612 stacked on the substrate 611, and a substrate 613 stacked on the substrate 612.

[0158] The pixel 121 shown in Figure 31 may employ a structure such as those disclosed in International Publication No. 2022 / 149467 or International Publication No. 2022 / 091607. Specifically, the pixel 121 shown in Figure 31 can adopt a two-stage pixel structure in which a pixel substrate on which at least a photoelectric conversion unit is formed and a two-layer circuit substrate on which a part of the pixel circuit excluding the photoelectric conversion unit is formed are stacked.

[0159] Furthermore, the pixel 121 shown in Figure 31 may employ a structure such as that disclosed in International Publication No. 2022 / 265059. Specifically, the pixel 121 shown in Figure 31 can adopt a three-layer stacked structure in which three or more semiconductor layers, including a semiconductor layer on which a photoelectric conversion unit is formed, are stacked.

[0160] The effects described herein are merely illustrative and not limited to those described herein; other effects may also occur.

[0161] Furthermore, embodiments applying the technology described herein are not limited to those described above, and various modifications are possible without departing from the gist of the technology described herein.

[0162] Furthermore, the present disclosure can take the following configurations: (1) A photodetector comprising: a pixel array section on which pixels are arranged, each having an optical pulse response section that includes at least a photoelectric conversion section for multiplying the charge generated from a photon and a recharge section for recharging the photoelectric conversion section; and a capacitor provided between a first potential and a second potential that causes a current to flow in the optical pulse response section in response to the incidence of a photon, in one or more of the pixel units. (2) The photodetector according to (1), wherein the pixels further have a counter that counts based on pulses output from the optical pulse response section in response to the incidence of a photon, and are formed from two or more substrates, and the first potential and the second potential are either applied to the same substrate or to different substrates. (3) The photodetector according to (2), wherein the capacitor is provided with a larger capacitance value as the distance between the first potential and the second potential increases the current flowing. (4) The photodetector according to (3), wherein the capacitance is provided with a larger power supply parallel area as the distance between the first potential and the second potential through which a larger current flows. (5) The photodetector according to (3), wherein more capacitive elements are provided as the capacitance as the distance between the first potential and the second potential through which a larger current flows. (6) The photodetector according to any one of (2) to (5), wherein the first potential is the power supply potential of the recharge unit, and the second potential is the potential on one electrode side of the photoelectric conversion unit. (7) The photodetector according to any one of (2) to (5), wherein the first potential is the power supply potential of the recharge unit, the second potential is the potential on one electrode side of the photoelectric conversion unit, and further has a third potential that is different from the potential on one electrode side of the photoelectric conversion unit. (8) The optical pulse response unit further comprises a discharge unit that discharges charge after the photoelectric conversion unit has been quenched, and the third potential is the destination of the charge discharged by the discharge unit, as described in (7). (9) The optical pulse response unit further comprises a MOS diode that suppresses the potential drop on the other electrode side of the photoelectric conversion unit, and the third potential is the substrate potential on which the MOS diode is formed, as described in (7).(10) The photodetector according to any one of (2) to (9), comprising: a first substrate on which the photoelectric conversion unit is provided; a second substrate laminated on the first substrate and having at least the capacitance provided; and a third substrate laminated on the second substrate and having at least the counter provided. (11) The photodetector according to any one of (2) to (10), wherein the capacitance is composed of a MIM (Metal-Insulator-Metal) capacitance. (12) The photodetector according to any one of (2) to (10), wherein the capacitance is composed of a MOM (Metal-Oxide-Metal) capacitance. (13) The photodetector according to any one of (2) to (10), wherein the capacitance is composed of a MOS (Metal Oxide Semiconductor) capacitance. (14) The photodetector according to any one of (2) to (13), wherein the first potential is a fixed potential of the pixel separation portion which is the boundary with an adjacent pixel, the second potential is the potential on the anode side of the photoelectric conversion portion, and the capacitance is formed along the pixel separation portion. (15) The photodetector according to any one of (2) to (13), wherein the capacitance and at least one of the first potential and the second potential applied to a substrate different from the substrate on which the capacitance is formed are connected via a Cu-Cu junction. (16) The photodetector according to any one of (1) to (15), which adopts a two-stage pixel structure in which at least a pixel substrate on which the photoelectric conversion portion is formed and a two-layer circuit board on which a part of the pixel circuit excluding the photoelectric conversion portion is formed are stacked. (17) The photodetector according to any one of (1) to (15), which adopts a three-layer stacked structure in which three or more semiconductor layers, including a semiconductor layer on which the photoelectric conversion portion is formed, are stacked.

[0163] 100 Imaging device, 101 Optical system, 102 Solid-state imaging device, 103 Imaging control unit, 104 Image processing unit, 105 Storage unit, 106 Display unit, 107 Operation unit, 108 Bus, 111 Pixel array unit, 112 Row scanning circuit, 113 Column processing circuit, 114 Control signal generation circuit, 115 Frame memory, 121 Pixel, 122, 155 Switches, 131 Optical pulse response unit, 132 Readout circuit, 133 Counter, 141 Photoelectric conversion unit, 142 Resistor unit, 143 Recharge unit, 144 Detection unit, 145 Ejection unit, 151 SPAD, 152 Resistor, CP, CP1, CP2 Capacitors

Claims

1. A photodetector comprising: a pixel array section in which pixels are arranged, each having an optical pulse response section that includes at least a photoelectric conversion section for multiplying the charge generated from a photon and a recharge section for recharging the photoelectric conversion section; and a capacitor provided between a first potential and a second potential for supplying current to the optical pulse response section in response to the incidence of a photon in one or more of the pixel units.

2. The photodetector according to claim 1, wherein the pixel further comprises a counter that performs counting based on pulses output from the optical pulse response unit in response to the incidence of photons, and is formed of two or more substrates, and the first potential and the second potential are either applied to the same substrate or to different substrates.

3. The photodetector according to claim 2, wherein the capacitance is provided such that the capacitance value is larger as the distance between the first potential and the second potential increases, resulting in a larger current.

4. The photodetector according to claim 3, wherein the capacitance is provided such that the power supply parallel area is larger as the distance between the first potential and the second potential through which a larger current flows increases.

5. The photodetector according to claim 3, wherein more capacitive elements are provided as capacitances as the distance between the first potential and the second potential through which a larger current flows.

6. The photodetector according to claim 2, wherein the first potential is the power supply potential of the recharge unit, and the second potential is the potential on one electrode side of the photoelectric conversion unit.

7. The photodetector according to claim 2, wherein the first potential is the power supply potential of the recharge unit, the second potential is the potential on one electrode side of the photoelectric conversion unit, and the photodetector further has a third potential different from the potential on one electrode side of the photoelectric conversion unit.

8. The photodetector according to claim 7, wherein the optical pulse response unit further comprises a discharge unit that discharges charge after the photoelectric conversion unit quenches, and the third potential is the destination of the charge discharged by the discharge unit.

9. The photodetector according to claim 7, wherein the optical pulse response unit further comprises a MOS diode that suppresses the potential drop on the other electrode side of the photoelectric conversion unit, and the third potential is the substrate potential on which the MOS diode is formed.

10. The photodetector according to claim 2, comprising: a first substrate on which the photoelectric conversion unit is provided; a second substrate laminated on the first substrate and having at least the capacitance; and a third substrate laminated on the second substrate and having at least the counter.

11. The photodetector according to claim 2, wherein the capacitance is a MIM (Metal-Insulator-Metal) capacitance.

12. The photodetector according to claim 2, wherein the capacitance is composed of MOM (Metal-Oxide-Metal) capacitance.

13. The photodetector according to claim 2, wherein the capacitance is a MOS (Metal Oxide Semiconductor) capacitance.

14. The photodetector according to claim 2, wherein the first potential is a fixed potential of the pixel separation portion which is the boundary with an adjacent pixel, the second potential is the potential on the anode side of the photoelectric conversion portion, and the capacitance is formed along the pixel separation portion.

15. The photodetector according to claim 2, wherein the capacitance and at least one of the first potential and the second potential applied to a substrate different from the substrate on which the capacitance is formed are connected via a Cu-Cu junction.

16. The photodetector according to claim 1, which employs a two-stage pixel structure comprising a pixel substrate on which at least the photoelectric conversion unit is formed, and two layers of circuit substrates on which a part of the pixel circuit excluding the photoelectric conversion unit is formed.

17. The photodetector according to claim 1, which adopts a three-layer stacked structure in which three or more semiconductor layers, including the semiconductor layer on which the photoelectric conversion unit is formed, are stacked.

Images