Semiconductor structure and manufacturing method for semiconductor structure

Abstract

A semiconductor structure and a manufacturing method for a semiconductor structure. The semiconductor structure comprises: a substrate (10); a capacitor structure (107) located on the substrate (10), the capacitor structure (107) comprising a first electrode layer (1071), a capacitor dielectric layer (1072), and a second electrode layer (1073) which are sequentially stacked; a conductive plate (108) located on the surface of the second electrode layer (1073), the conductive plate (108) at least comprising a base layer and a first transition layer (1082) located on the surface of the base layer; and a contact member (109) inserted into the conductive plate (108), the contact member (109) being electrically connected to the second electrode layer (1073) by means of the conductive plate (108). The base layer comprises a first silicon germanium layer (1081), and the first transition layer (1082) comprises a first boron-doped polycrystalline silicon layer (1082b) and a second silicon germanium layer (1082a) arranged in a stack. The semiconductor structure has high reliability and stability.

Description

Semiconductor structure and methods for fabricating semiconductor structures

[0001] This application claims priority to Chinese Patent Application No. 202411399653.1, filed on October 8, 2024, entitled "Semiconductor Structure and Method of Manufacturing a Semiconductor Structure", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for fabricating the semiconductor structure. Background Technology

[0003] Dynamic Random Access Memory (DRAM) is a type of volatile memory. A DRAM device typically includes a memory array region consisting of memory cells and a peripheral region consisting of logic control circuitry. A typical memory cell includes a switching structure (such as a transistor) and a storage structure (such as a capacitor). The logic control circuitry in the peripheral region addresses each memory cell in the memory array region via multiple word lines and bit lines passing through it, and activates the switching structure to electrically connect to the storage structure, thereby performing data reads, writes, or accesses.

[0004] However, in the process of manufacturing storage devices, since the storage array area and the peripheral area need to be fabricated with different structures, and the storage array area and the peripheral area have significant differences in morphology and film layers, there are still many technical challenges that need to be solved in the manufacturing process. Summary of the Invention

[0005] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising: a substrate; a capacitor structure located on the substrate, the capacitor structure comprising a first electrode layer, a capacitor dielectric layer, and a second electrode layer stacked sequentially; a conductive electrode plate located on the surface of the second electrode layer, the conductive electrode plate comprising at least a base layer and a first transition layer located on the surface of the base layer; and a contact inserted into the conductive electrode plate, the contact being electrically connected to the second electrode layer through the conductive electrode plate; wherein the base layer comprises a first silicon germanide layer, and the first transition layer comprises a stack of a first boron-doped polysilicon layer and a second silicon germanide layer.

[0006] In some embodiments, the first transition layer includes a stack of two first boron-doped polysilicon layers and a single second silicon germanide layer, wherein the single second silicon germanide layer is located between the two first boron-doped polysilicon layers.

[0007] In some embodiments, the conductive electrode plate further includes a contact layer and a second transition layer located on the surface of the contact layer, the contact layer being located on the surface of the first transition layer.

[0008] In some embodiments, the contact layer further includes a metal material layer and a metal barrier layer, the second transition layer includes a stack of a second boron-doped polysilicon layer and a third silicon germanide layer, and the bottom of the contact is located in the metal material layer.

[0009] In some embodiments, the second transition layer comprises a stack of two second boron-doped polysilicon layers and a single third silicon germanide layer, wherein the single third silicon germanide layer is located between the two second boron-doped polysilicon layers.

[0010] In some embodiments, the thickness of the first transition layer and / or the second transition layer ranges from 5 to 10 nm, and the thickness of the base layer ranges from 50 to 100 nm.

[0011] In some embodiments, the germanium content ratio in the first silicon germanide layer is greater than or equal to the germanium content ratio in the second silicon germanide layer, and the germanium content ratio in the second silicon germanide layer is substantially the same as the germanium content ratio in the third silicon germanide layer.

[0012] In some embodiments, the conductive electrode plate further includes a seed layer located between the second electrode layer and the base layer, and in direct contact with the second electrode layer and the base layer, the seed layer comprising a polycrystalline germanium layer.

[0013] In some embodiments, the semiconductor structure further includes: a transistor structure located on the substrate surface, wherein the capacitor structure is electrically connected to the second source and drain of the transistor structure through the first electrode layer; a bit line structure located on the substrate surface, wherein the bit line structure is electrically connected to the first source and drain of the transistor structure; and a word line structure located on the substrate surface, wherein the word line structure is electrically connected to the gate of the transistor structure.

[0014] According to a second aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising: providing a substrate; forming a capacitor structure on the substrate, the capacitor structure comprising a first electrode layer, a capacitor dielectric layer, and a second electrode layer stacked sequentially; forming a conductive electrode plate on the surface of the second electrode layer, the conductive electrode plate comprising at least a base layer and a first transition layer located on the surface of the base layer; forming a contact element inserted into the conductive electrode plate, the contact element being electrically connected to the second electrode layer through the conductive electrode plate; wherein the base layer comprises a first silicon germanide layer, and the first transition layer comprises a stack of a first boron-doped polysilicon layer and a second silicon germanide layer.

[0015] In some embodiments, forming a conductive electrode plate on the surface of the second electrode layer includes: forming a first silicon germanide layer on the surface of the second electrode layer; forming a first transition layer on the surface of the first silicon germanide layer, including a stack of a single-layer first boron-doped polysilicon layer, a single-layer second silicon germanide layer and another single-layer first boron-doped polysilicon layer formed sequentially.

[0016] In some embodiments, the conductive electrode plate further includes a contact layer and a second transition layer located on the surface of the contact layer, the contact layer being located on the surface of the first transition layer; forming the conductive electrode plate on the surface of the second electrode layer further includes: forming the contact layer on the surface of the first transition layer, including sequentially forming a metal material layer and a metal barrier layer; forming the second transition layer on the surface of the contact layer, including sequentially forming a stack of a single-layer second boron-doped polysilicon layer, a single-layer third silicon germanide layer and another single-layer second boron-doped polysilicon layer.

[0017] In some embodiments, forming a contact inserted into the conductive electrode plate includes: forming a blind hole in the conductive electrode plate, the bottom of the blind hole ending in the metal material layer; and filling the blind hole with a contact material to form the contact.

[0018] In some embodiments, the conductive electrode plate further includes a seed layer, the seed layer including a polycrystalline germanium layer; forming the conductive electrode plate on the surface of the second electrode layer further includes: forming the polycrystalline germanium layer on the surface of the second electrode layer before forming the base layer; and forming the first silicon germanide layer on the surface of the seed layer.

[0019] In some embodiments, prior to forming the capacitor structure, the method further includes: forming a transistor structure, a bit line structure, and a word line structure on the substrate surface, wherein the first source and drain of the transistor structure are electrically connected to the bit line structure, the second source and drain of the transistor structure are electrically connected to the subsequently formed first electrode layer, and the gate of the transistor structure is electrically connected to the word line structure. Attached Figure Description

[0020] Figure 1 is a schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0021] Figure 2 is a schematic diagram showing a partially enlarged structure of region D in Figure 1 according to an exemplary embodiment;

[0022] Figure 3 is a schematic diagram of a partially enlarged structure of region D in Figure 1 according to an exemplary embodiment 2;

[0023] Figure 4 is a schematic diagram of a partially enlarged structure of region D in Figure 1 according to an exemplary embodiment;

[0024] Figure 5 is a schematic diagram of a partially enlarged structure of region D in Figure 1 according to an exemplary embodiment 4;

[0025] Figure 6 is a schematic diagram illustrating the formation of a substrate according to an exemplary embodiment;

[0026] Figure 7 is a schematic diagram illustrating the formation of an active region and a shallow trench isolation structure according to an exemplary embodiment;

[0027] Figure 8 is a schematic diagram illustrating the formation of a word line structure according to an exemplary embodiment;

[0028] Figure 9 is a schematic diagram illustrating the formation of a bitline structure according to an exemplary embodiment;

[0029] Figure 10 is a schematic diagram illustrating the formation of a landing pad according to an exemplary embodiment;

[0030] Figure 11 is a schematic diagram illustrating the formation of a capacitor structure according to an exemplary embodiment;

[0031] Figure 12 is a schematic diagram illustrating the formation of a conductive electrode plate and contacts according to an exemplary embodiment. Detailed Implementation

[0032] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0033] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0034] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0035] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0036] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0037] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0038] In related technologies, the fabrication process of Dynamic Random Access Memory (DRAM) structures typically requires the formation of memory cell-related structures, such as memory transistors, memory capacitors, bit lines, and word lines, in the memory array region, while peripheral transistors and metal interconnects are formed in the peripheral region. The inventors of this application have discovered that after fabricating the capacitor structure in the memory array region, a photoresist protective layer needs to be formed on the top surface of the capacitor structure. Then, contact holes and other structures are formed on the top and peripheral regions of the capacitor structure to form interconnects between the top and peripheral devices. However, the top surface of the capacitor is typically made of silicon germanium, which has poor roughness and hydrophobicity. The photoresist formed on this top surface has poor adhesion, and subsequent wet etching or cleaning can easily damage the film surface, leading to breakage and other problems, severely affecting device yield.

[0039] To address the aforementioned technical problems, this disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure. The following will describe, in conjunction with Figures 1 to 12, an exemplary semiconductor structure and a method for fabricating the semiconductor structure provided by this disclosure. Figures 1 to 5 are schematic diagrams illustrating semiconductor structures according to several exemplary embodiments of this disclosure, and Figures 6 to 12 are schematic diagrams illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of this disclosure.

[0040] In an exemplary embodiment of this disclosure, a semiconductor structure is provided, as shown in Figures 1 and 2, wherein Figure 2 is a partially enlarged schematic diagram of the portion within the dashed box D in Figure 1. The semiconductor structure includes: a substrate 10; a capacitor structure 107 located on the substrate 10, the capacitor structure 107 including a first electrode layer 1071, a capacitor dielectric layer 1072, and a second electrode layer 1073 stacked sequentially; a conductive electrode plate 108 located on the surface of the second electrode layer 1073, the conductive electrode plate 108 including at least a base layer and a first transition layer 1082 located on the surface of the base layer; and a contact 109 inserted into the conductive electrode plate 108, the contact 109 being electrically connected to the second electrode layer 1073 through the conductive electrode plate 108. The base layer includes a first silicon germanide layer 1081, and the first transition layer 1082 includes a stack of a first boron-doped polysilicon layer 1082b and a second silicon germanide layer 1082a.

[0041] The substrate 10 may be made of at least one of the following semiconductor materials or group III-V materials: silicon, germanium, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). In an exemplary embodiment of this disclosure, the substrate 10 is made of single-crystal silicon.

[0042] Referring again to Figure 1, the semiconductor structure includes a memory cell array region and a peripheral device region. Using the dashed line C-C' in Figure 1 as an example, the area to the left of the dashed line C-C' is the memory cell array region, and the area to the right of the dashed line C-C' is the peripheral device region. In the memory cell array region, a first shallow trench isolation (STI) structure 102 is formed on the surface of the substrate 10 to divide the surface of the substrate 10 on the memory cell array region into multiple arrayed first active areas 101 (AA). The first active areas 101 may be doped with N-type or P-type ions. In an exemplary embodiment of this disclosure, the material of the first shallow trench isolation structure 102 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of this disclosure, the material of the first shallow trench isolation structure 102 is silicon oxide.

[0043] The surface of the substrate 10 also has a word line structure 103. In some embodiments, the word line structure 103 can be a buried word line structure, formed in a region of the shallow surface of the substrate 10, interspersed between a plurality of first active regions 101 and a first shallow trench isolation structure 102. In an exemplary embodiment of this disclosure, a portion of the word line structure 103 in the first active region 101 itself serves as the gate of a transistor structure. In some embodiments, the word line structure 103 includes a gate dielectric layer, a word line conductive layer, and a word line insulating layer stacked sequentially. The gate dielectric layer can be made of any one or more of silicon oxide, hafnium oxide, zirconium oxide, and aluminum oxide. The word line conductive layer can be made of any one or more of doped polycrystalline silicon, tungsten, and titanium nitride. The word line insulating layer can be made of at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride. In one exemplary embodiment of this disclosure, the gate dielectric layer is made of silicon oxide, the word line conductive layer is made of titanium nitride, and the word line insulating layer is made of silicon nitride (not shown in detail in the figures). In some embodiments, the portion of the word line structure 103 in the first active region 101 has a smaller depth and width than the portion in the first shallow trench isolation structure 102 (not shown in detail in the figures). In some embodiments, the word line structure 103 is connected to the gate of a transistor structure formed in the first active region 101 to provide a gate signal to control the turning on or off of the storage transistor structure. In some embodiments, multiple character line structures 103 extend along the X direction and are arranged parallel to each other at intervals. It should be noted that the term "surface" as used above should be understood as the area near the surface, including not only the area above the surface but also the shallow surface area below the surface.

[0044] The surface of the substrate 10 also has a bit line structure 104. In some embodiments, the bit line structure 104 is located on the surface of the substrate 10, spanning multiple first active regions 101 and a portion of the first shallow trench isolation structure 102. In some embodiments, the bit line structure 104 includes a first bit line conductive layer 1041, a second bit line conductive layer 1042, and a bit line insulating layer 1043. The bit line insulating layer 1043 is located not only on top of the second bit line conductive layer 1042 but also on the sidewalls of the first bit line conductive layer 1041 and the second bit line conductive layer 1042. In some embodiments, the material of the first bit line conductive layer 1041 may be doped polycrystalline silicon, the material of the second bit line conductive layer 1042 may be tungsten or titanium nitride, and the material of the bit line insulating layer 1043 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of this disclosure, the bit line insulating layer 1043 is made of a silicon nitride-silicon oxide-silicon nitride (NON) composite stack, which can provide good leakage current resistance. In some embodiments, the bottom of the first bit line conductive layer 1041 has a bit line contact layer, which is inserted into the surface of the first active region 101 and electrically connected to a source-drain electrode of a transistor structure formed in the first active region 101, for providing or sensing stored charge. In some embodiments, multiple bit line structures 104 extend along the Y direction and are arranged parallel to each other at intervals.

[0045] The substrate 10 also has a storage node contact structure 105. In an exemplary embodiment of this disclosure, the storage node contact structure 105 includes a storage node contact plug 1051 and a landing pad 1052. In some embodiments, the landing pad 1052 includes an upper landing pad 1052b and a lower landing pad 1052a that are connected to each other and staggered. The upper landing pad 1052b is electrically in contact with the first electrode layer 1071 of the capacitor structure 107 and is also partially located on the bit line insulating layer 1053. The lower landing pad 1052a is electrically in contact with the storage node contact plug 1051. The storage node contact plug 1051 is inserted into the surface of the first active region 101 and electrically connected to another source-drain electrode of the transistor structure formed in the first active region 101, for electrically connecting the capacitor structure and the transistor structure. In some embodiments, the material of the storage node contact plug 1051 may be doped polycrystalline silicon, and the material of the landing pad 1052 may be a combination of tungsten and / or titanium nitride. In some embodiments, the plurality of lower landing pads 1052a are arranged in a tetragonal pattern along a plane parallel to the surface of the substrate 10, while the plurality of upper landing pads 1052b are arranged in a hexagonal pattern. In some embodiments, adjacent landing pads 1052 are separated by a first support layer 1061, and the material of the first support layer 1061 may be silicon nitride.

[0046] In some embodiments, the capacitor structure 107 is located on the storage node contact structure 105, and the first electrode layer 1071 of the capacitor structure 107 is in direct contact with the upper landing pad 1052b of the storage node contact structure 105. In an exemplary embodiment of this disclosure, the capacitor structure 107 is arranged in a plurality of hexagonal close-packed cylindrical shapes, that is, the first electrode layer 1071 is a hollow cylinder. In another exemplary embodiment, the capacitor structure 107 is arranged in a plurality of hexagonal close-packed cylindrical shapes, that is, the first electrode layer 1071 is a solid column. A support layer is provided between adjacent cylindrical capacitors as a stabilizing structure. The support layer includes a first support layer 1061, a second support layer 1062, and a third support layer 1063 spaced apart along the Z direction. The top surface of the first electrode layer 1071 is flush with the top surface of the third support layer located at the top layer. In other embodiments, the support layer may include two or more layers. The first support layer 1061, the second support layer 1062, and the third support layer 1063 are all parallel to the plane direction of the substrate surface. In some embodiments, the materials of the first support layer 1061, the second support layer 1062, and the third support layer 1063 may be silicon nitride.

[0047] In some embodiments, the capacitor junction 107 is a double-sided capacitor, that is, the capacitor dielectric layer 1072 covers the inner and outer sides of the cylindrical first electrode layer 1071, and the second electrode layer 1073 covers the surface of the capacitor dielectric layer 1072. Thus, capacitors are formed on both the inner and outer sides of the cylindrical first electrode layer 1071, which increases the area of ​​the capacitor plates to a certain extent, thereby improving the capacity to store charge. In some embodiments, the materials of the first electrode layer 1071 and the second electrode layer 1073 of the capacitor junction 107 may be a combination of one or more of titanium nitride, tantalum nitride, and silicon-doped titanium nitride; the material of the capacitor dielectric layer 1072 of the capacitor structure 107 may be a combination of at least one or more of zirconium oxide (ZrO2) and aluminum oxide (Al2O3). In other embodiments, the capacitor dielectric material may also be a combination of at least one or more of silicon oxide (SiO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), and lead titanate (PZT).

[0048] In some embodiments, the conductive electrode plate 108 covers the surface of the second electrode layer 1073, and the base layer of the conductive electrode plate 108 is partially inserted into the cylindrical capacitor structure 107. The conductive electrode plate 108 is electrically connected to the second electrode layer 1073. In some embodiments, the memory cell array region further includes a memory region interlayer dielectric layer 110, which covers the surface of the conductive electrode plate 108. The material of the memory region interlayer dielectric layer 110 may be silicon oxide.

[0049] In an exemplary embodiment of this disclosure, referring to FIG2, the conductive electrode plate 108 includes a first silicon germanide layer 1081, a second silicon germanide layer 1082a, and a first boron-doped polysilicon layer 1082b stacked sequentially. The single first silicon germanide layer 1081 constitutes a base layer; the stack of the single second silicon germanide layer 1082a and the single first boron-doped polysilicon layer 1082b constitutes a first transition layer 1082. In some embodiments, the germanium content in the first silicon germanide layer 1081 is greater than or equal to the germanium content in the second silicon germanide layer 1082a. In some embodiments, the thickness of the first transition layer 1082 ranges from 5 to 10 nm, and the thickness of the base layer ranges from 50 to 100 nm.

[0050] In some embodiments, the contact 109 is inserted into the conductive electrode plate 108, and the contact 109 is electrically connected to the second electrode layer 1073 through the conductive electrode plate 108. Specifically, referring to FIG2, the contact 109 penetrates the first transition layer 1082 (i.e., a stack of a single-layer second silicon germanide layer 1082a and a single-layer first boron-doped polysilicon layer 1082b), and the bottom of the contact 109 stops in the base layer, i.e., the first silicon germanide layer 1081. The contact 109 is electrically connected to the second electrode layer 1073 through the first silicon germanide layer 1081. In some embodiments, the material of the contact 109 can be tungsten, copper, or other metal materials with good conductivity.

[0051] In an exemplary embodiment two of this disclosure, referring to FIG3, the conductive electrode plate 108 includes a first silicon germanide layer 1081, a first boron-doped polysilicon layer 1082b, a second silicon germanide layer 1082a, and a first boron-doped polysilicon layer 1082b stacked sequentially. The first silicon germanide layer 1081 constitutes a base layer. A stack of a single second silicon germanide layer 1082a and two single first boron-doped polysilicon layers 1082b constitutes a first transition layer 1082, wherein the single second silicon germanide layer 1082a is located between the two single first boron-doped polysilicon layers 1082b. In some embodiments, the germanium content ratio in the first silicon germanide layer 1081 is greater than or equal to the germanium content ratio in the second silicon germanide layer 1082a. In some embodiments, the thickness of the first transition layer 1082 ranges from 5 to 10 nm, and the thickness of the base layer ranges from 50 to 100 nm. The sandwich structure of the first transition layer 1082 (i.e., a single second silicon germanium layer 1082a located between two single first boron-doped polysilicon layers 1082b) can effectively reduce resistivity and improve the electrical performance of the memory device.

[0052] In some embodiments, the contact 109 is inserted into the conductive electrode plate 108, and the contact 109 is electrically connected to the second electrode layer 1073 through the conductive electrode plate 108. Specifically, referring to FIG3, the contact 109 penetrates the first transition layer 1082 (i.e., a stack of a single-layer second silicon germanide layer 1082a and two single-layer first boron-doped polysilicon layers 1082b), and the bottom of the contact 109 stops in the base layer, i.e., the first silicon germanide layer 1081. The contact 109 is electrically connected to the second electrode layer 1073 through the first silicon germanide layer 1081. In some embodiments, the material of the contact 109 can be tungsten, copper, or other metal materials with good conductivity.

[0053] In an exemplary embodiment three of this disclosure, as shown in FIG4, the conductive electrode plate 108 includes a base layer and a first transition layer 1082, as well as a contact layer 1083 and a second transition layer 1084, that is, the conductive electrode plate 108 includes a first silicon germanide layer 1081, a first transition layer 1082, a contact layer 1083 and a second transition layer 1084 stacked sequentially. In some embodiments, a first silicon germanide layer 1081 constitutes a base layer; a stack of a single second silicon germanide layer 1082a and two single first boron-doped polysilicon layers 1082b constitutes a first transition layer 1082, wherein the single second silicon germanide layer 1082a is located between the two single first boron-doped polysilicon layers 1082b; a stack of a single third silicon germanide layer 1084a and two single second boron-doped polysilicon layers 1084b constitutes a second transition layer 1084, wherein the single third silicon germanide layer 1084a is located between the two single second boron-doped polysilicon layers 1084b. In some embodiments, the germanium content ratio in the first silicon germanide layer 1081 is greater than or equal to the germanium content ratio in the second silicon germanide layer 1082a, and the germanium content ratio in the second silicon germanide layer 1082a is substantially the same as the germanium content ratio in the third silicon germanide layer 1084a. In some embodiments, the thickness of the first transition layer 1082 and / or the second transition layer 1084 ranges from 5 to 10 nm, and the thickness of the base layer ranges from 50 to 100 nm.

[0054] In some embodiments, the contact 109 is inserted into the conductive electrode plate 108, and the contact 109 is electrically connected to the second electrode layer 1073 through the conductive electrode plate 108. Specifically, referring to FIG4, the contact 109 penetrates the second transition layer 1084 (i.e., a stack of a single-layer third silicon germanide layer 1084a and two single-layer second boron-doped polysilicon layers 1084b), and the bottom of the contact 109 stops in the contact layer 1083. The contact 109 is electrically connected to the second electrode layer 1073 through the contact layer 1083. In some embodiments, the material of the contact 109 can be tungsten, copper, or other metal materials with good conductivity, and the material of the contact layer 1083 can be one or more combinations of tungsten and titanium nitride. The combination of the metal material of the contact layer 1083 and the base layer (first silicon germanide layer 1081) has a lower resistivity, which greatly improves the read and write efficiency of the memory device.

[0055] In an exemplary embodiment four of this disclosure, referring to FIG5, the conductive electrode plate 108 includes a base layer, a first transition layer 1082, a contact layer 1083, and a second transition layer 1084, as well as a seed layer. That is, the conductive electrode plate 108 includes a seed layer, a first silicon germanide layer 1081, a first transition layer 1082, a contact layer 1083, and a second transition layer 1084 stacked sequentially. In some embodiments, a polycrystalline germanium layer 1080 constitutes a seed layer; a first silicon germanide layer 1081 constitutes a base layer; a stack of a single second silicon germanide layer 1082a and two single first boron-doped polycrystalline silicon layers 1082b constitutes a first transition layer 1082, wherein the single second silicon germanide layer 1082a is located between the two single first boron-doped polycrystalline silicon layers 1082b; a stack of a metal material layer 1083a and a metal barrier layer 1083b constitutes a contact layer 1083, wherein the metal barrier layer 1083b covers the top surface of the metal material layer 1083a; a stack of a single third silicon germanide layer 1084a and two single second boron-doped polycrystalline silicon layers 1084b constitutes a second transition layer 1084, wherein the single third silicon germanide layer 1084a is located between the two single second boron-doped polycrystalline silicon layers 1084b. In some embodiments, the germanium content in the first silicon germanide layer 1081 is greater than or equal to the germanium content in the second silicon germanide layer 1082a, and the germanium content in the second silicon germanide layer 1082a is substantially the same as the germanium content in the third silicon germanide layer 1084a. In some embodiments, the thickness of the first transition layer 1082 and / or the second transition layer 1084 ranges from 5 to 10 nm, and the thickness of the base layer ranges from 50 to 100 nm. The polycrystalline germanium layer 1080, which serves as a seed layer with a higher germanium content, can better prevent boron ions in the first boron-doped polycrystalline silicon layer 1082b or the second boron-doped polycrystalline silicon layer 1084b from diffusing into the capacitor dielectric layer 1072 in the capacitor structure 107, thereby improving the leakage current problem of the capacitor structure.

[0056] In some embodiments, the contact 109 is inserted into the conductive electrode plate 108, and the contact 109 is electrically connected to the second electrode layer 1073 through the conductive electrode plate 108. Specifically, referring to FIG5, the contact 109 penetrates the second transition layer 1084 (i.e., a stack of a single-layer third silicon germanide layer 1084a and two single-layer second boron-doped polysilicon layers 1084b), and the bottom of the contact 109 stops in the contact layer 1083. More specifically, the bottom of the contact 109 stops in the metal material layer 1083a, and the contact 109 is electrically connected to the second electrode layer 1073 through the metal material layer 1083a. In some embodiments, the material of the contact 109 can be tungsten, copper, or other metal materials with good conductivity, the material of the metal material layer 1083a can be tungsten, and the material of the metal barrier layer 1083b can be one or more combinations of tungsten nitride and titanium nitride. The metal barrier layer 1083b can prevent the diffusion of the metal material.

[0057] In an exemplary embodiment of this disclosure, referring to FIG1, a second shallow trench isolation (STI) structure 202 is formed on the surface of the substrate 10 in the peripheral device region to divide the surface of the substrate 10 in the peripheral device region into a plurality of second active areas 201 (AA), wherein the second active areas 201 may be doped with N-type or P-type ions. In an exemplary embodiment of this disclosure, the material of the second shallow trench isolation structure 202 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of this disclosure, the material of the second shallow trench isolation structure 202 adopts a silicon oxide-silicon nitride-silicon oxide stack combination. In some embodiments, the size of the second shallow trench isolation structure 202 is larger than the size of the first shallow trench isolation structure 102, and the size of the second active area 201 is also larger than the size of the first active area 101.

[0058] In some embodiments, the semiconductor structure in the peripheral device region further includes peripheral devices 203, which may be field-effect transistors (MOSFETs), diodes, polarized junction transistors (BJTs), etc.; and peripheral interconnect structures, including a first peripheral contact structure 2041, a first peripheral metal wiring layer 2042, and a second peripheral contact structure 2043; and peripheral dielectric layers, including a first peripheral interlayer dielectric layer 2051, a second peripheral interlayer dielectric layer 2052, and a peripheral isolation dielectric layer 206. The first peripheral contact structure 2041 is located in the first peripheral interlayer dielectric layer 2051, the first peripheral metal wiring layer 2042 is located in the peripheral isolation dielectric layer 206, and the second peripheral contact structure 2043 is located in the second peripheral interlayer dielectric layer 2052. In some embodiments, the first peripheral metal wiring layer 2042 and the upper landing pad 1052b are substantially located in the same horizontal layer, and the peripheral isolation dielectric layer 206 and the first support layer 1061 are substantially located in the same horizontal layer. In some embodiments, the second peripheral interlayer dielectric layer and the memory region interlayer dielectric layer 110 are integrally connected. In some embodiments, the second peripheral contact structure 2052 is flush with the top surface of the contact 109. In some embodiments, the peripheral interconnect structure further includes a plurality of peripheral metal wiring layers interspersed between the first peripheral contact structure 2041 and the second peripheral contact structure 2042 to reduce wiring density and the depth of the second peripheral contact structure 2042, thereby reducing process complexity and improving reliability in terms of process and device performance.

[0059] In some embodiments, the materials of the first peripheral contact structure 2041 and the second peripheral contact structure 2043 may be tungsten; the material of the first peripheral metal wiring layer may be aluminum or copper. In some embodiments, the materials of the first peripheral interlayer dielectric layer 2051, the second peripheral interlayer dielectric layer 2052, and the peripheral isolation dielectric layer 206 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of this disclosure, the materials of the first peripheral interlayer dielectric layer 2051 and the second peripheral interlayer dielectric layer 2052 are silicon oxide, and the material of the peripheral isolation dielectric layer 206 is silicon nitride.

[0060] The semiconductor structure disclosed herein includes a transition layer comprising a stack of silicon germanide and boron-doped polysilicon in the conductive electrode plate formed on the upper electrode of the capacitor structure. The boron-doped polysilicon layer is located on the surface of the silicon germanide layer. On the one hand, it protects the silicon germanide layer from corrosion damage during etching and cleaning processes; on the other hand, its low surface roughness and low surface energy result in better hydrophobicity, enhancing photoresist adhesion in subsequent processes and avoiding the risk of photoresist detachment and breakage. Furthermore, the stacked structure of boron-doped polysilicon and silicon germanide, particularly the sandwich structure (i.e., one silicon germanide layer located between two boron-doped polysilicon layers), effectively reduces resistivity and improves the operating performance of the memory device.

[0061] Based on the above semiconductor structure, this disclosure also provides a method for fabricating a semiconductor structure, including: providing a substrate 10, as shown in FIG6, wherein FIG6(a) is a top view of the substrate in the opposite direction along the Z direction, and FIG6(b) is a cross-sectional schematic diagram along the dashed line A-A' in FIG6(a), and the cross-section along the dashed line A-A' is perpendicular to the top surface of the substrate 10.

[0062] The substrate 10 may be made of at least one of the following semiconductor materials or group III-V materials: silicon, germanium, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). In an exemplary embodiment of this disclosure, the substrate 10 is made of single-crystal silicon.

[0063] Next, referring to Figure 7, where Figure 7(a) is a top view facing the substrate in the opposite direction along the Z direction, and Figure 7(b) is a cross-sectional view along the dashed line A-A' in Figure 7(a), the cross-section along the dashed line A-A' is perpendicular to the top surface of the substrate 10, and a first shallow trench isolation structure 102 (STI) is formed on the surface of the substrate 10 to divide the surface of the substrate 10 into multiple arrayed first active areas 101 (AA). Specifically, the substrate 10 can be etched to form shallow trenches, which divide the surface of the substrate 10 into multiple arrayed first active areas 101, and then the shallow trenches are filled with isolation material to form the first shallow trench isolation structure 102. Before or after forming the first shallow trench isolation structure 102, the first active areas 101 can be doped with N-type or P-type ions. In an exemplary embodiment of this disclosure, as can be seen from FIG7(a), the top view of the first active region 101 is a long strip with rounded ends, and adjacent first active regions 101 are staggered. In other embodiments, the top view of the first active region 101 may also be a long strip of parallelogram, and adjacent first active regions 101 may be arranged without staggering.

[0064] In some embodiments, a photolithography process can be used to etch the surface of the substrate 10 to form shallow trenches. Specifically, a photoresist mask layer can be formed on the surface of the substrate 10. By exposure and development, the pattern of the first active region 101 is formed in the photoresist mask layer, and then dry etching is performed to etch the substrate 10 along the pattern to form shallow trenches. In some embodiments, before coating the photoresist mask layer, an anti-reflection layer and a hard mask layer (not shown) are also formed on the surface of the substrate 10, and both are removed after the shallow trenches are formed.

[0065] In some embodiments, the material of the first shallow trench isolation structure 102 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In some embodiments, the deposition method of the isolation material in the first shallow trench isolation structure 102 may employ at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin-coated dielectric layer (SOD), and thermal oxidation growth.

[0066] Then, referring to Figure 8, where Figure 8(a) is a top view facing the substrate in the opposite direction along the Z direction, and Figure 8(b) is a cross-sectional view along the dashed line A-A' in Figure 8(a), the cross-section along the dashed line A-A' is perpendicular to the top surface of the substrate 10, and a word line structure 103 extending in the X direction is formed on the surface of the substrate 10. The word line structure 103 is an embedded word line structure, that is, the word line structure 103 is located in a part of the area below the top surface of the substrate 10. Specifically, multiple word line trenches extending in the X direction are first etched on the surface of the substrate 10. The word line trenches span multiple first active regions 101 and first shallow trench isolation structures 102. Then, a gate dielectric layer 1031, a word line conductive layer 1032, and a word line insulating layer 1033 are sequentially formed in the word line trenches to jointly constitute the word line structure 103, as shown in the partially enlarged schematic diagram of the structure within the dashed box E in Figure 8(b). In some embodiments, as shown in FIG8(a), a plurality of word line structures 103 extend along the X direction and are arranged parallel to each other at intervals in the Y direction. In some embodiments, the depth of the word line structures 103 is less than the depth of the first shallow trench isolation structure 103. In some embodiments, the portion of the word line structure 103 located in the first shallow trench isolation structure 103 is larger in size than the portion located in the first active region 101, including depth and / or width dimensions.

[0067] In some embodiments, photolithography can be used to etch the surface of the substrate 10 to form word line trenches. Specifically, a photoresist mask layer can be formed on the surface of the substrate 10. By exposure and development, the pattern of the word line structure is formed in the photoresist mask layer. Then, dry etching is performed to etch the substrate 10 (including the first active region 101 and the first shallow trench isolation structure 102) along the pattern to form word line trenches. In some embodiments, before coating the photoresist mask layer, an anti-reflection layer and a hard mask layer (not shown) are also formed on the surface of the substrate 10, and both are removed after the word line trenches are formed.

[0068] In some embodiments, the gate dielectric layer 1031 may be a combination of at least one or more of silicon oxide (SiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), and lead titanate (PZT). In an exemplary embodiment of this disclosure, the gate dielectric layer 1031 is made of silicon oxide. In some embodiments, the word line conductive layer 1032 may be a combination of at least one or more of doped polycrystalline silicon, titanium nitride (TiN), silicon-doped titanium nitride (TiSiN), titanium (Ti), tungsten (W), tungsten nitride (WN), and silicon-doped tungsten nitride (WSiN). In other embodiments, the word line conductive layer 1032 may also be a combination of at least one or more of molybdenum (Mo), ruthenium (Ru), tantalum (Ta), platinum (Pt), copper (Cu), and their nitrides. In an exemplary embodiment of this disclosure, the word line conductive layer 1032 is made of titanium nitride. In some embodiments, the material of the word line insulating layer 1033 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of this disclosure, the material of the word line insulating layer 1033 is silicon nitride.

[0069] In some embodiments, the gate dielectric layer 1031, word line conductive layer 1032, and word line insulating layer 1033 can be formed using at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin-coated dielectric layer (SOD), in-situ water vapor growth (ISSG), and thermal oxidation growth. It should be noted that the gate dielectric layer 1031 in the word line structure 103 can also be selectively formed only in the first active region 101.

[0070] In some embodiments, before forming the word line structure 103, the first active region 101 is further doped with N-type or P-type. After forming the word line structure 103, the doped portions of the first active region 101 located on both sides of the word line structure 103 serve as two source and drain electrodes, the doped portion of the first active region 101 located below the word line structure 103 serves as a channel region, and together with the word line conductive layer 1032 in the word line structure 103 itself serving as a gate conductive layer, they constitute a transistor structure. The word line conductive layer 1032, as a gate conductive layer, can be considered as a gate connection between the word line structure 103 and the transistor structure, used to provide a gate signal to control the turning on or off of the storage transistor structure. In an exemplary embodiment of this disclosure, a single first active region 101 is spanned by two adjacent word line structures 103 to form two transistor structures.

[0071] Next, as shown in Figure 9, where Figure 9(a) is a top view facing the substrate in the opposite direction along the Z direction, and Figure 9(b) is a cross-sectional view along the dashed line A-A' in Figure 9(a), the cross-section along the dashed line A-A' is perpendicular to the top surface of the substrate 10, and a bit line structure 104 is formed on the surface of the substrate 10. Unlike the word line structure 103, the bit line structure 104 is basically located in a portion of the area above the top surface of the substrate 10. Specifically, a bit line contact hole is first formed at the middle position of the top surface of each first active region 101, and then a bit line material stack is formed on the surface of the substrate 10. The bit line material stack is etched along the Y direction to form an initial bit line structure (not shown), and an isolation layer is formed on the surface of the initial bit line structure to form the bit line structure 104, including a first bit line conductive layer 1041, a second bit line conductive layer 1042, and a bit line insulating layer 1043. In some embodiments, as shown in Figure 9(a), multiple bit line structures 104 extend along the Y direction and are arranged parallel to each other in the X direction. In some embodiments, a portion of the first bit-line conductive layer 1041 of the bit-line structure 104 is located within the bit-line contact hole, that is, a portion of the first bit-line conductive layer 1041 is inserted below the top surface of the substrate 10 and directly contacts the middle position of the top surface of the first active region 101. In some embodiments, a second bit-line conductive layer 1042 is located on the top surface of the first bit-line conductive layer 1041, and a bit-line insulating layer 1043 is located not only on the top surface of the second bit-line conductive layer 1042, but also on the sidewalls of the first bit-line conductive layer 1041 and the second bit-line conductive layer 1042.

[0072] In some embodiments, the bit line material stack includes at least a first bit line conductive layer 1041, a second bit line conductive layer 1042, and a portion of a bit line insulating layer 1043. In an exemplary embodiment of this disclosure, the first bit line conductive layer 1041 is made of doped polycrystalline silicon, the second bit line conductive layer 1042 is made of a combination of at least one or more of titanium nitride, titanium, tungsten nitride, and tungsten, and the bit line insulating layer 1043 is made of a combination of silicon oxide and silicon nitride, specifically a silicon nitride-silicon oxide-silicon nitride (NON) stack, which can provide better leakage current resistance. In some embodiments, the method for forming the bitline material stack can employ at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), in-situ water vapor growth (ISSG), and thermal oxidation growth.

[0073] In some embodiments, photolithography can be used to etch the bit line material stack to form an initial bit line structure (not shown). Specifically, a photoresist mask layer can be formed on the surface of the bit line material stack. By exposure and development, the pattern of the bit line structure is formed in the photoresist mask layer. Then, dry etching is performed to etch the bit line material stack along the pattern to form the initial bit line structure. In some embodiments, before coating the photoresist mask layer, an anti-reflection layer and a hard mask layer (not shown) are formed on the surface of the bit line material stack, and both are removed after the initial bit line structure is formed.

[0074] In some embodiments, after forming the initial bit line structure, a supplementary insulating material is formed on the surface of the initial bit line structure. The supplementary insulating material and the top insulating layer in the initial bit line structure together constitute the bit line insulating layer 1043, wherein the supplementary insulating material is a silicon nitride-silicon oxide-silicon nitride (NON) composite stack. The method for forming the supplementary insulating material is the same as the method for forming the bit line material stack in the foregoing embodiments, and will not be repeated here.

[0075] In some embodiments, the first conductive layer 1041 of the bit line structure 104 is electrically connected to a source and drain of a transistor structure in a plurality of first active regions 101 for providing or sensing stored charge. In an exemplary embodiment of this disclosure, two transistor structures are formed in a single first active region 101, the two transistor structures share a first source and drain, and are electrically connected to the first conductive layer 1041 of the bit line structure 104.

[0076] Next, referring to Figure 10, where Figure 10(a) is a top view facing the substrate in the opposite direction along the Z direction, and Figure 10(b) is a cross-sectional view along the dashed line B-B' in Figure 10(a). It should be noted that the cross-section along the dashed line B-B' is perpendicular to the top surface of the substrate 10, and the dashed line B-B' is parallel to the X direction but not within the word line structure 103. Therefore, the word line structure 103 in Figure 10(b) is indicated by a dashed line to show its approximate location. After forming the bit line structure 104, a memory node contact structure 105 is formed between adjacent bit line structures 104, including a memory node contact plug 1051 and a landing pad 1052. Specifically, a fence isolation layer 106 is first formed between adjacent bit line structures 104. Multiple fence isolation layers 106 extend along the X direction and are arranged parallel to each other in the Y direction, as shown in Figure 10(a). Next, a square array of multiple storage node contact holes is formed. Then, storage node contact plugs 1051 are filled into the multiple storage node contact holes. A landing pad material layer is then formed to cover the storage node contact plugs 1051, the top surfaces of the bit line structures 104 and the fence isolation layers 106. Finally, [the process is completed]. The landing pad material layer is etched to form a plurality of landing pads 105 that are disconnected from each other. Each landing pad 105 includes an upper landing pad 1052b and a lower landing pad 1052a that are connected to each other and staggered. The upper landing pad 1052b is electrically in contact with the first electrode layer 1071 of the capacitor structure 107 and is also partially located on the bit line insulating layer 1053. The lower landing pad 1052a is located in the storage node contact hole and is electrically in contact with the storage node contact plug 1051. In some embodiments, the plurality of lower landing pads 1052a are arranged in a tetragonal distribution along a plane parallel to the surface of the substrate 10, while the plurality of upper landing pads 1052b are arranged in a hexagonal distribution.

[0077] In some embodiments, the material of the fence isolation layer 106 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of this disclosure, the fence isolation layer 106 is made of silicon nitride, the storage node contact plug 1051 is made of doped polycrystalline silicon, and the landing pad 1052 is made of a combination of tungsten and titanium nitride. In some embodiments, the fence isolation layer 106, the storage node contact plug 1051, and the landing pad 1052 may be formed by at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and spin coating dielectric layer (SOD).

[0078] In some embodiments, a photolithography process can be used to etch the landing pad material layer to form an upper landing pad 1052b and a lower landing pad 1052a. Specifically, a photoresist mask layer can be formed on the surface of the landing pad material layer. By exposure and development, the pattern of the upper landing pad 1052b is formed in the photoresist mask layer. Then, dry etching is performed to etch the landing pad material layer along the pattern to form landing pads 1052 that are disconnected from each other. In some embodiments, before coating the photoresist mask layer, an anti-reflective layer and a hard mask layer (not shown) are also formed on the surface of the landing pad material layer, and both are removed after the landing pad 1052 is formed.

[0079] In some embodiments, a storage node contact plug 1051 is inserted into the surface of the first active region 101 and electrically connected to another source-drain electrode of a transistor structure formed within the first active region 101, for electrically connecting the transistor structure to a subsequently formed capacitor structure. In an exemplary embodiment of this disclosure, two transistor structures sharing a first source-drain electrode are formed within a single first active region 101, and the second source-drain electrodes of a transistor structure formed at each end of the first active region 101 are respectively contacted and electrically connected to a corresponding storage node contact plug 1051.

[0080] Next, referring to Figure 11, where Figure 11(a) is a cross-sectional view along the dashed line D-D' direction of Figure 11(b), and Figure 11(b) are all cross-sectional views along the dashed line B-B' direction of Figure 11(a). Figures 11(c) and 11(d) are schematic diagrams of different embodiments of the subsequent steps of Figure 11(b). It should be noted that the cross-section along the dashed line D-D' direction is parallel to the top surface of the substrate 10, and the cross-section along the dashed line B-B' direction is perpendicular to the top surface of the substrate 10. The dashed line B-B' direction is parallel to the X direction, but is not within the word line structure 103. Therefore, the word line structure 103 in Figures 11(b), 11(c), and 11(d) is indicated by dashed lines to show its approximate location. A capacitor structure 107 and a conductive electrode plate 108 are formed on the substrate 10. Specifically, after forming the storage node contact structure 105, firstly, a support material stack is formed on the storage node contact structure 105, including a first support layer 1061, a first sacrificial layer (not shown), a second support layer 1062, a second sacrificial layer (not shown), and a third support layer 1063 formed sequentially; then, the support material stack is etched to form a plurality of capacitor holes, which are arranged in a hexagonal array, exposing the top surface of each upper landing pad 1052b; next, a first electrode layer 1071 in a cylindrical shape is formed in the capacitor holes; then, the third support layer 1063 is etched to form a first opening. 1060a exposes the surface of the second sacrificial layer. The second sacrificial layer is removed through the first opening 1060a. Then, the second support layer 1062 is etched to form a second opening 1060b to expose the surface of the first sacrificial layer. The first sacrificial layer is removed through the second opening 1060b, as shown in Figures 11(a) and 11(b). Next, a capacitor dielectric layer 1072 is sequentially formed to cover the surfaces of the first electrode layer 1071, the first support layer 1061, the second support layer 1062, and the third support layer 1063. The second electrode layer 1073 covers the surface of the capacitor dielectric layer 1072, and the conductive electrode plate 108 covers the surface of the second electrode layer 1073. In some embodiments, the second electrode layer 1073 fills the gap between adjacent capacitor structures, as shown in Figure 11(c). The subsequently formed conductive electrode plate 108 is only located on the topmost surface of the capacitor structure 107, i.e., the area above the third support layer 1063. In other embodiments, the second electrode layer 1073 does not fill the gap between adjacent capacitor structures. The subsequently formed conductive electrode plate 108 is located not only on the top surface of the capacitor structure 107, but also between adjacent capacitor structures 107, as shown in FIG11(d).

[0081] In some embodiments, the materials of the first support layer 1061, the second support layer 1062, and the third support layer 1063 of the support material stack can be silicon nitride, and the materials of the first sacrificial layer (not shown) and the second sacrificial layer (not shown) of the support material stack can be silicon oxide. In some embodiments, the materials of the first electrode layer 1071 and the second electrode layer 1073 of the capacitor junction trench 107 can be a combination of one or more of titanium nitride, tantalum nitride, and silicon-doped titanium nitride; the material of the capacitor dielectric layer 1072 of the capacitor structure 107 can be a combination of at least one or more of zirconium oxide (ZrO2) and aluminum oxide (Al2O3). In other embodiments, the capacitor dielectric material can also be a combination of at least one or more of silicon oxide (SiO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), and lead titanate (PZT). In some embodiments, the method for forming the support material stack and the capacitor structure 107 may employ at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), physical vapor deposition (PVD), and sputtering.

[0082] In some embodiments, photolithography can be used to etch the support material stack to form multiple capacitor holes. Specifically, a photoresist mask layer can be formed on the surface of the support material stack. Through exposure and development, the pattern of the capacitor holes is formed in the photoresist mask layer. Then, dry etching is performed to etch the support material stack along the pattern to form multiple capacitor holes exposing the top surface of the landing pad 1052b. In some embodiments, before coating the photoresist mask layer, an anti-reflection layer and a hard mask layer (not shown) are formed on the top surface of the support material stack, and both are removed after the capacitor holes are formed. In some instances, forming the first opening 1060a in the third support layer 1063 and the second opening 1060b in the second support layer 1062 can employ a similar photolithography process to that described in the above embodiments, and will not be repeated here. In some embodiments, the method of removing the second sacrificial layer through the first opening 1060a and the first sacrificial layer through the second opening 1060b can employ a highly selective wet chemical etching process.

[0083] In an exemplary embodiment of this disclosure, referring to FIG2, a conductive electrode plate 108 is formed on the surface of the capacitor structure 107. Specifically, a first silicon germanide layer 1081, a second silicon germanide layer 1082a, and a first boron-doped polysilicon layer 1082b are sequentially formed on the surface of the second electrode layer 1073, wherein a single first silicon germanide layer 1081 constitutes a base layer; the stack of a single second silicon germanide layer 1082a and a single first boron-doped polysilicon layer 1082b constitutes a first transition layer 1082. In some embodiments, the germanium content ratio in the first silicon germanide layer 1081 is greater than or equal to the germanium content ratio in the second silicon germanide layer 1082a. In some embodiments, the thickness of the first transition layer 1082 ranges from 5 to 10 nm, and the thickness of the base layer ranges from 50 to 100 nm. Next, a contact 109 is formed and inserted into the conductive electrode plate 108, and the contact 109 is electrically connected to the second electrode layer 1073 through the conductive electrode plate 108. Specifically, an etching process forms a contact hole that penetrates the first transition layer 1082 (i.e., a stack of a single-layer second silicon germanium layer 1082a and a single-layer first boron-doped polysilicon layer 1082b). The bottom of the contact hole stops in the base layer, i.e., the first silicon germanium layer 1081. A contact 109 is formed within the contact hole, and the contact 109 is electrically connected to the second electrode layer 1073 through the first silicon germanium layer 1081. In some embodiments, the material of the contact 109 can be tungsten, copper, or other metals with good conductivity.

[0084] In an exemplary embodiment two of this disclosure, referring to FIG3, a conductive electrode plate 108 is formed on the surface of the capacitor structure 107. Specifically, a first silicon germanide layer 1081, a first boron-doped polysilicon layer 1082b, a second silicon germanide layer 1082a, and a first boron-doped polysilicon layer 1082b are sequentially formed on the surface of the second electrode layer 1073, wherein the first silicon germanide layer 1081 constitutes a base layer; the stack of a single second silicon germanide layer 1082a and two single first boron-doped polysilicon layers 1082b constitutes a first transition layer 1082, wherein the single second silicon germanide layer 1082a is located between the two single first boron-doped polysilicon layers 1082b. In some embodiments, the germanium content ratio in the first silicon germanide layer 1081 is greater than or equal to the germanium content ratio in the second silicon germanide layer 1082a. In some embodiments, the thickness of the first transition layer 1082 ranges from 5 to 10 nm, and the thickness of the base layer ranges from 50 to 100 nm. The sandwich structure of the first transition layer 1082 (i.e., a single second silicon germanium layer 1082a located between two single first boron-doped polysilicon layers 1082b) effectively reduces resistivity and improves the electrical performance of the memory device. Next, a contact 109 is formed and inserted into the conductive electrode plate 108, and the contact 109 is electrically connected to the second electrode layer 1073 through the conductive electrode plate 108. Specifically, a contact hole is etched to form penetrating the first transition layer 1082 (i.e., a stack of a single second silicon germanium layer 1082a and two single first boron-doped polysilicon layers 1082b), with the bottom of the contact hole stopping in the base layer, i.e., the first silicon germanium layer 1081. The contact 109 is formed within the contact hole, and the contact 109 is electrically connected to the second electrode layer 1073 through the first silicon germanium layer 1081. In some embodiments, the material of the contact 109 can be tungsten, copper, or other metals with good conductivity.

[0085] In an exemplary embodiment three of this disclosure, referring to FIG4, a conductive electrode plate 108 is formed on the surface of the capacitor structure 107. In addition to a base layer and a first transition layer 1082, the conductive electrode plate 108 also includes a contact layer 1083 and a second transition layer 1084. Specifically, a first silicon germanide layer 1081, a first transition layer 1082, a contact layer 1083, and a second transition layer 1084 are sequentially formed on the surface of the second electrode layer 1073. In some embodiments, a first silicon germanide layer 1081 constitutes a base layer; a stack of a single second silicon germanide layer 1082a and two single first boron-doped polysilicon layers 1082b constitutes a first transition layer 1082, wherein the single second silicon germanide layer 1082a is located between the two single first boron-doped polysilicon layers 1082b; a stack of a single third silicon germanide layer 1084a and two single second boron-doped polysilicon layers 1084b constitutes a second transition layer 1084, wherein the single third silicon germanide layer 1084a is located between the two single second boron-doped polysilicon layers 1084b. In some embodiments, the germanium content ratio in the first silicon germanide layer 1081 is greater than or equal to the germanium content ratio in the second silicon germanide layer 1082a, and the germanium content ratio in the second silicon germanide layer 1082a is substantially the same as the germanium content ratio in the third silicon germanide layer 1084a. In some embodiments, the thickness of the first transition layer 1082 and / or the second transition layer 1084 ranges from 5 to 10 nm, and the thickness of the base layer ranges from 50 to 100 nm. Next, a contact 109 is formed and inserted into the conductive electrode plate 108, and the contact 109 is electrically connected to the second electrode layer 1073 through the conductive electrode plate 108. Specifically, a contact hole is etched to form penetrating the second transition layer 1084 (i.e., a stack of a single-layer third silicon germanide layer 1084a and two single-layer second boron-doped polysilicon layers 1084b), with the bottom of the contact hole ending in the contact layer 1083. A contact 109 is formed within the contact hole, and the contact 109 is electrically connected to the second electrode layer 1073 through the contact layer 1083. In some embodiments, the material of the contact 109 can be tungsten, copper, or other metals with good conductivity, and the material of the contact layer 1083 can be one or a combination of tungsten and titanium nitride. The combination of the metal material of the contact layer 1083 and the base layer (first silicon germanium layer 1081) results in a lower resistivity, which greatly improves the read and write efficiency of the memory device.

[0086] In an exemplary embodiment four of this disclosure, referring to FIG5, a conductive electrode plate 108 is formed on the surface of the capacitor structure 107. In addition to a base layer, a first transition layer 1082, a contact layer 1083, and a second transition layer 1084, the conductive electrode plate 108 also includes a seed layer. Specifically, a seed layer, a first silicon germanide layer 1081, a first transition layer 1082, a contact layer 1083, and a second transition layer 1084 are sequentially formed on the surface of the second electrode layer 1073. In some embodiments, a polycrystalline germanium layer 1080 constitutes a seed layer; a first silicon germanide layer 1081 constitutes a base layer; a stack of a single second silicon germanide layer 1082a and two single first boron-doped polycrystalline silicon layers 1082b constitutes a first transition layer 1082, wherein the single second silicon germanide layer 1082a is located between the two single first boron-doped polycrystalline silicon layers 1082b; a stack of a metal material layer 1083a and a metal barrier layer 1083b constitutes a contact layer 1083, wherein the metal barrier layer 1083b covers the top surface of the metal material layer 1083a; a stack of a single third silicon germanide layer 1084a and two single second boron-doped polycrystalline silicon layers 1084b constitutes a second transition layer 1084, wherein the single third silicon germanide layer 1084a is located between the two single second boron-doped polycrystalline silicon layers 1084b. In some embodiments, the germanium content ratio in the first silicon germanide layer 1081 is greater than or equal to the germanium content ratio in the second silicon germanide layer 1082a, and the germanium content ratio in the second silicon germanide layer 1082a is substantially the same as the germanium content ratio in the third silicon germanide layer 1084a. In some embodiments, the thickness of the first transition layer 1082 and / or the second transition layer 1084 ranges from 5 to 10 nm, and the thickness of the base layer ranges from 50 to 100 nm. The polycrystalline germanium layer 1080, which serves as a seed layer with a higher germanium content ratio, can better prevent boron ions in the first boron-doped polycrystalline silicon layer 1082b or the second boron-doped polycrystalline silicon layer 1084b from diffusing into the capacitor dielectric layer 1072 in the capacitor structure 107, thereby improving the leakage current problem of the capacitor structure. Next, a contact 109 is formed and inserted into the conductive electrode plate 108, and the contact 109 is electrically connected to the second electrode layer 1073 through the conductive electrode plate 108. Specifically, an etching process forms a contact hole that penetrates the second transition layer 1084 (i.e., a stack of a single-layer third silicon germanide layer 1084a and two single-layer second boron-doped polysilicon layers 1084b). The bottom of the contact hole stops in the contact layer 1083, and more specifically, the bottom of the contact hole stops in the metal material layer 1083a. A contact element 109 is formed within the contact hole, and the contact element 109 is electrically connected to the second electrode layer 1073 through the metal material layer 1083a. In some embodiments, the material of the contact element 109 can be tungsten, copper, or other metal materials with good conductivity. The material of the metal material layer 1083a can be tungsten, and the material of the metal barrier layer 1083b can be one or more combinations of tungsten nitride and titanium nitride. The metal barrier layer 1083b can prevent the diffusion of the metal material.

[0087] In the exemplary embodiments one to four of this disclosure, the method for forming the conductive electrode plate 108 and the contact element 109 can employ at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), physical vapor deposition (PVD), and sputtering. In the exemplary embodiments one to four of this disclosure, the method for etching to form the contact hole can employ a photolithography process similar to that in the foregoing embodiments, and will not be described again here.

[0088] In some embodiments, while a contact 109 is formed in the memory cell array region and inserted into the conductive electrode plate 108, a second peripheral contact structure 2043 is simultaneously formed in the peripheral device region, as shown in FIG12. Specifically, contact holes are formed simultaneously in the memory cell array region and the peripheral device region using a photolithography process. The bottom of the contact hole in the memory cell array region ends within the conductive electrode plate 108, and the contact hole in the peripheral device region ends at the surface of the first peripheral metal wiring layer 2042. Then, a conductive metal material is filled into the contact hole to form a contact 109 in the memory cell array region and a second peripheral contact structure 2043 in the peripheral device region. In some embodiments, the material of the contact 109 and the second peripheral contact structure 2043 may be tungsten.

[0089] The semiconductor structure formed by the semiconductor structure formation method disclosed herein includes a transition layer of stacked silicon germanide and boron-doped polysilicon in the conductive electrode plate formed on the upper electrode of the capacitor structure. The boron-doped polysilicon layer is located on the surface of the silicon germanide layer. On the one hand, it can protect the silicon germanide layer from corrosion damage during the etching and cleaning process; on the other hand, its surface roughness is low, and it has low surface energy, which can achieve better hydrophobicity, enhance the adhesion of photoresist in subsequent processes, and avoid the risk of photoresist detachment and breakage. In addition, the stacked structure of boron-doped polysilicon and silicon germanide, especially the sandwich structure (i.e., one layer of silicon germanide is located between two layers of boron-doped polysilicon), can effectively reduce resistivity and improve the operating performance of the memory device.

[0090] It should be noted that the semiconductor structure in the embodiments of this disclosure can be used to fabricate DRAM devices, or other devices that require the formation of capacitor structures or conductive electrode plates in different areas, without further limitations.

[0091] The various semiconductor structures illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).

[0092] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate (10); A capacitor structure (107) is located on the substrate (10). The capacitor structure (107) includes a first electrode layer (1071), a capacitor dielectric layer (1072), and a second electrode layer (1073) stacked sequentially. A conductive electrode plate (108) is located on the surface of the second electrode layer (1073). The conductive electrode plate (108) includes at least a base layer and a first transition layer (1082) located on the surface of the base layer (1081). A contact (109) is inserted into the conductive electrode plate (108), and the contact (109) is electrically connected to the second electrode layer (1073) through the conductive electrode plate (108); The base layer includes a first silicon germanium layer (1081), and the first transition layer (1082) includes a stack of a first boron-doped polysilicon layer (1082b) and a second silicon germanium layer (1082a).

2. The semiconductor structure according to claim 1, characterized in that, The first transition layer (1082) comprises a stack of two first boron-doped polysilicon layers (1082b) and a single second silicon germanide layer (1082a), wherein the single second silicon germanide layer (1082a) is located between the two first boron-doped polysilicon layers (1082b).

3. The semiconductor structure according to claim 1, characterized in that, The conductive electrode plate (108) further includes a contact layer (1083) and a second transition layer (1084) located on the surface of the contact layer (1083), wherein the contact layer (1083) is located on the surface of the first transition layer (1082).

4. The semiconductor structure according to claim 3, characterized in that, The contact layer (1083) further includes a metal material layer (1083a) and a metal barrier layer (1083b). The second transition layer (1084) includes a stack of a second boron-doped polysilicon layer (1084b) and a third silicon germanide layer (1084a). The bottom of the contact (109) is located in the metal material layer (1083a).

5. The semiconductor structure according to claim 4, characterized in that, The second transition layer (1084) comprises a stack of two second boron-doped polysilicon layers (1084b) and a single third silicon germanide layer (1084a), wherein the single third silicon germanide layer (1084a) is located between the two second boron-doped polysilicon layers (1084b).

6. The semiconductor structure according to claim 5, characterized in that, The thickness of the first transition layer (1082) and / or the second transition layer (1084) ranges from 5 to 10 nm, and the thickness of the base layer ranges from 50 to 100 nm.

7. The semiconductor structure according to claim 5, characterized in that, The germanium content ratio in the first silicon germanium layer (1081) is greater than or equal to the germanium content ratio in the second silicon germanium layer (1082a), and the germanium content ratio in the second silicon germanium layer (1082a) is basically the same as the germanium content ratio in the third silicon germanium layer (1084a).

8. The semiconductor structure according to claim 1, characterized in that, The conductive electrode plate (108) further includes a seed layer, which is located between the second electrode layer (1073) and the base layer and is in direct contact with the second electrode layer (1073) and the base layer. The seed layer includes a polycrystalline germanium layer (1080).

9. The semiconductor structure according to any one of claims 1-8, characterized in that, Also includes: A transistor structure is located on the surface of the substrate (10), and the first electrode layer (1071) of the capacitor structure (107) is electrically connected to the second source and drain of the transistor structure; Bit line structure (104) is located on the surface of the substrate (10), and the bit line structure (104) is electrically connected to the first source and drain of the transistor structure; A word line structure (103) is located on the surface of the substrate (10), and the word line structure (103) is electrically connected to the gate of the transistor structure.

10. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate (10); A capacitor structure (107) is formed on the substrate (10), the capacitor structure (107) including a first electrode layer (1071), a capacitor dielectric layer (1072) and a second electrode layer (1073) stacked sequentially; A conductive electrode plate (108) is formed on the surface of the second electrode layer (1073), the conductive electrode plate (108) including at least a base layer and a first transition layer (1082) located on the surface of the base layer; A contact (109) is formed and inserted into the conductive electrode plate (108), and the contact (109) is electrically connected to the second electrode layer (1073) through the conductive electrode plate (108); The base layer includes a first silicon germanium layer (1081), and the first transition layer (1082) includes a stack of a first boron-doped polysilicon layer (1082b) and a second silicon germanium layer (1082a).

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, A conductive electrode plate (108) is formed on the surface of the second electrode layer (1073), comprising: The first silicon germanide layer (1081) is formed on the surface of the second electrode layer (1073); The first transition layer (1082) is formed on the surface of the first silicon germanide layer (1081), including a stack of a single layer of the first boron-doped polysilicon layer (1082b), a single layer of the second silicon germanide layer (1082a), and another single layer of the first boron-doped polysilicon layer (1082b) formed sequentially.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The conductive electrode plate (108) further includes a contact layer (1083) and a second transition layer (1084) located on the surface of the contact layer (1083), wherein the contact layer (1083) is located on the surface of the first transition layer (1082); A conductive electrode plate (108) is formed on the surface of the second electrode layer (1073), and the method further includes: The contact layer (1083) is formed on the surface of the first transition layer (1082), including the sequential formation of a metal material layer (1083a) and a metal barrier layer (1083b); The second transition layer (1084) is formed on the surface of the contact layer (1083), including a stack of a single layer of a second boron-doped polysilicon layer (1084b), a single layer of a third silicon germanium layer (1084a), and another single layer of the second boron-doped polysilicon layer (1084b) formed in sequence.

13. The method for fabricating a semiconductor structure according to claim 12, characterized in that, Forming a contact element (109) inserted into the conductive electrode plate (108), including: A blind hole is formed in the conductive electrode plate (108), and the bottom of the blind hole terminates in the metal material layer (1083a); The blind hole is filled with contact material to form the contact element (109).

14. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The conductive electrode plate (108) further includes a seed layer, which includes a polycrystalline germanium layer (1080); A conductive electrode plate (108) is formed on the surface of the second electrode layer (1073), and the method further includes: Before forming the base layer, the polycrystalline germanium layer (1080) is formed on the surface of the second electrode layer (1073); The first silicon germanium layer (1081) is formed on the surface of the seed layer.

15. The method for fabricating a semiconductor structure according to any one of claims 10-14, characterized in that, Before forming the capacitor structure (107), the following is also included: A transistor structure, a bit line structure (104), and a word line structure (103) are formed on the surface of the substrate. The first source and drain of the transistor structure are electrically connected to the bit line structure (104), the second source and drain of the transistor structure are electrically connected to the first electrode layer (1071) formed subsequently, and the gate of the transistor structure is electrically connected to the word line structure (103).

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