Semiconductor integrated circuit

Abstract

This semiconductor integrated circuit includes: a first insulated gate field effect transistor having a first floating gate electrode in an electrically floating state, and having a first channel conductivity type; a second insulated gate field effect transistor having a second floating gate electrode formed integrally with the first floating gate electrode and being in an electrically floating state, and having a second channel conductivity type opposite to the first channel conductivity type; and a first capacitive element electrically coupled in series to the first floating gate electrode and the second floating gate electrode, and including a ferroelectric insulator.

Description

Semiconductor integrated circuits

[0001] This disclosure relates to semiconductor integrated circuits.

[0002] Non-patent document 1 discloses a negative capacitance field-effect transistor (NCFET) having a metal / ferroelectric / metal / insulator / semiconductor (MFMIS) structure. Research and development of NCFETs are progressing as devices effective for reducing power consumption. This will be explained in detail.

[0003] An NCFET has a source electrode and a drain electrode, and a semiconductor channel region is formed between these two electrodes. The semiconductor consists of an insulator made of an oxide layer, a metal intermediate gate, a ferroelectric material, and a metal control gate, all of which are sequentially stacked. In other words, the capacitance formed by the intermediate gate, ferroelectric material, and control gate (hereinafter simply referred to as "MFM capacitance") is electrically coupled to the intermediate gate.

[0004] Non-patent document 1 further discloses an inverter. This inverter is a circuit combining a pMOS (Metal Oxide Semiconductor) and an nMOS. Each of the pMOS and nMOS is formed by an NCFET having an MFMIS structure. That is, in a p-channel conductive NCFET, an MFM capacitance is electrically coupled to its internal gate. On the other hand, in an n-channel conductive NCFET, another MFM capacitance is electrically coupled to its internal gate.

[0005] S. Semwal et al., “Unconventional VTC of subthreshold inverter with MFMIS negative capacitance transistor: An analytical modeling framework with implications for ultralow power logic design”, Semiconductor Sci. Technol (2022).

[0006] When forming memory cells using NCFETs having the aforementioned MFMIS structure and constructing a non-volatile memory, the following points are not taken into consideration.

[0007] First, the memory cell is composed of an inverter. In an NCFET with an MFMIS structure, the information writing characteristics and information erasing characteristics are determined by the voltage distribution between the capacitance formed by the internal gate, insulator, and channel region and the MFM capacitance. P-channel conductive NCFETs and n-channel conductive NCFETs are both formed individually. That is, the internal gate and MFM capacitance of a p-channel conductive NCFET are formed independently of the internal gate and MFM capacitance of an n-channel conductive NCFET. For this reason, the capacitance formed by the internal gate, insulator, and channel region of a p-channel conductive NCFET and the capacitance formed by the internal gate, insulator, and channel region of an n-channel conductive NCFET are both small. Consequently, it is difficult to sufficiently improve the information writing characteristics and information erasing characteristics.

[0008] Furthermore, the MFM capacitance coupled to the internal gate of a p-channel conductive NCFET is formed independently of the MFM capacitance coupled to the internal gate of an n-channel conductive NCFET. Therefore, variations in the processing of the MFM capacitance cause variations in the threshold voltages of both the p-channel and n-channel conductive NCFETs. Consequently, it is difficult to sufficiently improve the inverter characteristics.

[0009] As mentioned above, it is desirable to significantly improve the inverter characteristics of semiconductor integrated circuits. Furthermore, in non-volatile memory and semiconductor integrated circuits equipped with such non-volatile memory, it is desirable to significantly improve the information writing characteristics, information erasure characteristics, and inverter characteristics.

[0010] The semiconductor integrated circuit according to the first embodiment of this disclosure comprises a first insulated gate field-effect transistor having a first floating gate electrode that is electrically floating and having a first channel conductivity type; a second insulated gate field-effect transistor having a second floating gate electrode that is integrally formed with the first floating gate electrode and is electrically floating, and having a second channel conductivity type opposite to that of the first channel conductivity type; and a first capacitive element containing a ferroelectric insulator, electrically coupled in series to the first floating gate electrode and the second floating gate electrode. In the semiconductor integrated circuit according to the first embodiment, the first insulated gate field-effect transistor has a pair of first main electrodes, one of which is electrically connected to a first power supply and the other which is an output. The second insulated gate field-effect transistor has a pair of second main electrodes, one of which is electrically connected to a second power supply different from the first power supply and the other which is an output. The first insulated gate field-effect transistor and the second insulated gate field-effect transistor constitute an inverter. Furthermore, in the semiconductor integrated circuit according to the first embodiment, an interlayer insulating film is provided on the first floating gate electrode and the second floating gate electrode, and a first through-hole is provided in the interlayer insulating film that penetrates in the thickness direction. The first floating gate electrode and the second floating gate electrode are electrically coupled to the first capacitive element through the first through-hole.

[0011] In the semiconductor integrated circuit according to the second embodiment of this disclosure, a second capacitance element is further provided in series with the output, in addition to the semiconductor integrated circuit according to the first embodiment. In the semiconductor integrated circuit according to the second embodiment, an interlayer insulating film is disposed on the output, and a second through-hole is provided in the interlayer insulating film that penetrates in the thickness direction. The output is electrically coupled to the second capacitance element through the second through-hole.

[0012] In the semiconductor integrated circuit according to the third embodiment of this disclosure, in the semiconductor integrated circuit according to the second embodiment, the first insulated-gate field-effect transistor, the second insulated-gate field-effect transistor, the first capacitor element, and the second capacitor element constitute a memory cell. The semiconductor integrated circuit according to the third embodiment includes a non-volatile memory constructed by arranging a plurality of memory cells.

[0013] Figure 1 is a system block diagram of a non-volatile memory according to a first embodiment of the present disclosure, or a non-volatile memory mounted on a semiconductor integrated circuit. Figure 2 is a circuit diagram of a memory cell of the non-volatile memory shown in Figure 1. Figure 3 is a plan view of the memory cell shown in Figure 2. Figure 4 is a cross-sectional view of the memory cell shown in Figure 3 (a cross-sectional view cut along the A-A cutting line shown in Figure 3). Figure 5 is a circuit diagram of the information writing operation of the memory cell shown in Figure 2. Figure 6 is an equivalent circuit diagram of the information writing operation of the memory cell shown in Figure 2. Figure 7 is a graph showing the relationship between the information writing voltage and the memory window with respect to the ratio of the transistor size to the capacitive element size of the memory cell shown in Figure 5. Figure 8A is a graph showing the relationship between the operating voltage and output current of the memory cell shown in Figure 2. Figure 8B is a graph corresponding to Figure 8A showing the relationship between the operating voltage and output current of a memory cell according to a comparative example. Figure 9 is a graph showing the relationship between the input voltage and output voltage of the memory cell shown in Figure 2. Figure 10 is a circuit diagram of the memory cell array in the information writing operation of the memory cell shown in Figure 2. Figure 11 is a circuit diagram of a memory cell array corresponding to Figure 10 in the memory cell information read operation. Figure 12 is a circuit diagram of a memory cell array corresponding to Figure 10 in the memory cell information erase operation. Figure 13 is a plan view of a non-volatile memory according to a second embodiment of this disclosure, or a non-volatile memory mounted on a semiconductor integrated circuit, corresponding to Figure 3. Figure 14 is a cross-sectional view of the memory cell shown in Figure 13 (a cross-sectional view cut along the B-B cutting line shown in Figure 13). Figure 15 is a circuit diagram of a memory cell array corresponding to Figure 10 of a non-volatile memory according to a third embodiment of this disclosure, or a non-volatile memory mounted on a semiconductor integrated circuit. Figure 16 is a plan view of a memory cell corresponding to Figure 3 of the non-volatile memory shown in Figure 15. Figure 17 is a perspective view of the memory cell shown in Figure 16. Figure 18 is a plan view of a memory cell corresponding to Figure 3 of a non-volatile memory according to a fourth embodiment of this disclosure, or a non-volatile memory mounted on a semiconductor integrated circuit. Figure 19 is a plan view of a memory cell corresponding to Figure 3 of a non-volatile memory according to the fifth embodiment of the present disclosure, or a non-volatile memory mounted on a semiconductor integrated circuit.Figure 20 is a cross-sectional view of the memory cell shown in Figure 19 (a cross-sectional view taken along the C-C cutting line shown in Figure 19). Figure 21 is a cross-sectional view of the memory cell shown in Figure 19 (a cross-sectional view taken along the D-D cutting line shown in Figure 19). Figure 22 is a cross-sectional view of a memory cell of a non-volatile memory or non-volatile memory mounted on a semiconductor integrated circuit according to the sixth embodiment of this disclosure, corresponding to Figure 21. Figure 23 is a plan view of a memory cell of a non-volatile memory or non-volatile memory mounted on a semiconductor integrated circuit according to the seventh embodiment of this disclosure, corresponding to Figure 3. Figure 24 is a cross-sectional view of the memory cell shown in Figure 23 (a cross-sectional view taken along the E-E cutting line shown in Figure 23). Figure 25 is a cross-sectional view of the memory cell shown in Figure 23 (a cross-sectional view taken along the F-F cutting line shown in Figure 23). Figure 26 is a cross-sectional view of a memory cell of a non-volatile memory or non-volatile memory mounted on a semiconductor integrated circuit according to the eighth embodiment of this disclosure, corresponding to Figure 24. Figure 27 is a cross-sectional view corresponding to Figure 25 of the memory cell shown in Figure 26. Figure 28 is a cross-sectional view corresponding to Figure 25 of the memory cell of a non-volatile memory or non-volatile memory mounted on a semiconductor integrated circuit according to the ninth embodiment of this disclosure. Figure 29 is a diagram showing the relationship between the structure and application range of a plurality of capacitive elements in a memory cell of a non-volatile memory or non-volatile memory mounted on a semiconductor integrated circuit according to the tenth embodiment of this disclosure. Figure 30 is a first-step cross-sectional view illustrating the manufacturing method of one capacitive element shown in Figure 29. Figure 31 is a second-step cross-sectional view illustrating the manufacturing method of a capacitive element. Figure 32 is a third-step cross-sectional view illustrating the manufacturing method of a capacitive element. Figure 33 is a fourth-step cross-sectional view illustrating the manufacturing method of a capacitive element. Figure 34 is a fifth-step cross-sectional view illustrating the manufacturing method of a capacitive element. Figure 35 is a sixth-step cross-sectional view illustrating the manufacturing method of a capacitive element. Figure 36 is a seventh-step cross-sectional view illustrating the manufacturing method of a capacitive element.

[0014] The embodiments of this disclosure will be described in detail below with reference to the drawings. The description will be in the following order: 1. First Embodiment The first embodiment is a first example of applying the present technology to a non-volatile memory or a semiconductor integrated circuit equipped with such non-volatile memory. The first embodiment will describe the system configuration of the non-volatile memory, the circuit configuration of the memory cell, the planar configuration of the memory cell, and the cross-sectional configuration of the memory cell. 2. Second Embodiment The second embodiment is a second example of the non-volatile memory or semiconductor integrated circuit according to the first embodiment, in which the structure of the memory cell is changed. 3. Third Embodiment The third embodiment is a third example of the non-volatile memory or semiconductor integrated circuit according to the first or second embodiment, in which the structure of the memory cell is changed. 4. Fourth Embodiment The fourth embodiment is a fourth example of the non-volatile memory or semiconductor integrated circuit according to the third embodiment, in which the structure of the memory cell is changed. 5. Fifth Embodiment The fifth embodiment is a fifth example of the non-volatile memory or semiconductor integrated circuit according to the first embodiment, in which the structure of the memory cell is changed. 6. 10. The sixth embodiment is a sixth example of a non-volatile memory or semiconductor integrated circuit according to the fifth embodiment, in which the structure of the memory cell has been changed. 7. The seventh embodiment is a seventh example of a non-volatile memory or semiconductor integrated circuit according to the sixth embodiment, in which the structure of the memory cell has been changed. 8. The eighth embodiment is an eighth example of a non-volatile memory or semiconductor integrated circuit according to the seventh embodiment, in which the structure of the memory cell has been changed. 9. The ninth embodiment is a ninth example of a non-volatile memory or semiconductor integrated circuit according to the seventh or eighth embodiment, in which the structure of the memory cell has been changed. 10. The tenth embodiment is a tenth example illustrating an appropriate or inappropriate structure in the capacitive element of a memory cell. 11. Other embodiments

[0015] <1. First Embodiment> A non-volatile memory 2, or a semiconductor integrated circuit 1 equipped with a non-volatile memory 2, according to the first embodiment of the present disclosure will be described using Figures 1 to 12. Here, the arrow X direction shown as appropriate in the figures represents one planar direction of the non-volatile memory 2 or semiconductor integrated circuit 1 placed on a plane for convenience. The arrow Y direction represents another planar direction orthogonal to the arrow X direction. The arrow Z direction represents the upward direction orthogonal to the arrow X and arrow Y directions. In other words, the arrow X direction, arrow Y direction, and arrow Z direction coincide exactly with the X-axis, Y-axis, and Z-axis directions of a three-dimensional coordinate system, respectively. Note that these directions are illustrated to aid in understanding the explanation and do not limit the directions of this technology.

[0016] [System Configuration of Semiconductor Integrated Circuit 1 and Non-Volatile Memory 2] Figure 1 shows an example of the system configuration of a non-volatile memory 2 mounted on a semiconductor integrated circuit 1 according to the first embodiment. In this disclosure, the semiconductor integrated circuit 1 is constructed using a non-volatile memory 2, which is a single semiconductor device. Furthermore, in this disclosure, the semiconductor integrated circuit 1 is constructed by mounting a non-volatile memory 2, which is one functional block, and other functional blocks. Here, the non-volatile memory 2 will be described in detail as a main component.

[0017] As shown in Figure 1, the non-volatile memory 2 constructs a computing-in-memory that functions as a multiply-and-accumulate unit that performs operations to sequentially add the results of multiplication. The non-volatile memory 2 comprises an input / output circuit IN, a buffer memory BM, a control logic circuit CLC, a first driver DR1, a second driver DR2, a digital-to-analog converter DAC, an analog-to-digital converter ADC, and a memory cell array MA.

[0018] In the input / output circuit IN, information from outside is input to the non-volatile memory 2, and information is output from the non-volatile memory 2 to the outside. Here, "outside" includes circuits of other functional blocks mounted on the semiconductor integrated circuit 1 and external devices separate from the semiconductor integrated circuit 1. In the buffer memory BM, information input from the outside is stored. Also, in the buffer memory BM, information after the sum-of-accumulate operation is stored. The information stored in the buffer memory BM is digital information. In the digital-to-analog converter DAC, the information stored in the buffer memory BM is converted into analog information. In the analog-to-digital converter ADC, the information obtained by the sum-of-accumulate operation is converted into digital information.

[0019] Multiple memory cells (MCs) are arranged in the X and Y directions of the memory cell array (MA). In other words, the multiple memory cells (MCs) are arranged in a matrix. The memory cell array (MA) is constructed from these multiple memory cells (MCs).

[0020] The first driver DR1 is electrically connected to the signal line WL. The signal line WL extends in the direction of arrow Y in the memory cell array MA and is arranged in multiples at predetermined intervals in the direction of arrow X. The signal line WL extending in the direction of arrow Y is electrically connected to the input of the memory cell MC arranged in the direction of arrow Y. The analog-to-digital converter ADC is electrically connected to the signal line CL. The signal line CL extends in the direction of arrow Y substantially parallel to the signal line WL in the memory cell array MA and is arranged in multiples at predetermined intervals in the direction of arrow X. The signal line WL extending in the direction of arrow Y is electrically connected to the output of the memory cell MC arranged in the direction of arrow Y.

[0021] The second driver DR2 is electrically connected to a pair of signal lines IA and IAb, and is electrically connected to the digital-to-analog converter DAC through signal lines IA and IAb. Signal lines IA and IAb extend substantially parallel in the direction of arrow X in the memory cell array MA, and are arranged in multiples at predetermined intervals in the direction of arrow Y. Signal lines IA and IAb extending in the direction of arrow X are electrically connected to memory cells MC arranged in the direction of arrow X.

[0022] Although the wiring diagram is omitted, the control logic circuit CLC is electrically connected to the input / output circuit IN, buffer memory BM, first driver DR1, second driver DR2, digital-to-analog converter DAC, and analog-to-digital converter ADC. The control logic circuit CLC controls the operation of these circuits and is responsible for controlling the information writing, information reading, and information erasure operations of the non-volatile memory 2.

[0023] [Configuration of Memory Cell MC of Non-Volatile Memory 2] (1) Circuit Configuration of Memory Cell MC Figure 2 shows an example of the circuit configuration of the memory cell MC of the non-volatile memory 2 shown in Figure 1. As shown in Figure 2, the memory cell MC comprises a first insulated gate field effect transistor (IGFET) Qp and a second IGFET Qn. Here, "IGFET" is used in a sense that includes MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and MISFET (Metal Insulator Semiconductor Field Effect Transistor). Furthermore, the memory cell MC comprises a first capacitive element C1 and a second capacitive element C2.

[0024] The following will be described in detail. The first IGFET Qp has a p-channel conductivity type. This first IGFET Qp includes a channel formation region, a gate insulating film, a first floating gate electrode, a control gate electrode, and a pair of main electrodes used as a source region and a drain region. Here, the "p-channel conductivity type" corresponds to the "first channel conductivity type" according to the present disclosure.

[0025] The control gate electrode is disposed with a ferroelectric insulator interposed between it and the first floating gate electrode. The control gate electrode is electrically connected to the signal line WL. In other words, the first floating gate electrode is electrically coupled to a first capacitive element C1 including a ferroelectric insulator and is electrically connected to the signal line WL through the first capacitive element C1.

[0026] One of the pair of main electrodes (for example, the source region) is electrically connected to the signal line IA. The other of the pair of main electrodes (for example, the drain region) is an output. This output is electrically coupled to a second capacitive element C2 and is electrically connected to the signal line CL through the second capacitive element C2.

[0027] The second IGFET Qn has an n-channel conductivity type. This second IGFET Qn includes a channel formation region, a gate insulating film, a second floating gate electrode, a control gate electrode, and a pair of main electrodes used as a source region and a drain region. Here, the "n-channel conductivity type" corresponds to the "second channel conductivity type" according to the present disclosure.

[0028] The second floating gate electrode is integrally formed with and shared by the first floating gate electrode. The control gate electrode is disposed with a ferroelectric insulator interposed between it and the second floating gate electrode. The control gate electrode is electrically connected to the signal line WL. In other words, the first floating gate electrode and the second floating gate electrode shared by the first floating gate electrode are electrically connected in series to one first capacitive element C1 and are electrically connected to the signal line WL through the first capacitive element C1.

[0029] One of the pair of main electrodes (e.g., the source region) is electrically connected to the signal line IAb. The other of the pair of main electrodes (e.g., the drain region) is the output. This output is shared with the output of the first IGFET Qp, electrically coupled in series to a second capacitance element C2, and electrically connected to the signal line CL through the second capacitance element C2.

[0030] In other words, the memory cell MC is constructed using an inverter that combines a first IGFET Qp and a second IGFET Qn, which have a common input and a common output.

[0031] (2) Figure 3 of the memory cell MC device configuration shows an example of the planar configuration of the memory cell MC. Figure 4 shows an example of the cross-sectional configuration of the memory cell MC.

[0032] (2-1) As shown in the apparatus configuration diagrams 3 and 4 of the substrate 3, the non-volatile memory 2, or the semiconductor integrated circuit 1 equipped with the non-volatile memory 2, comprises the substrate 3 as a main component. In the first embodiment, a single-crystal Si substrate is used as the substrate 3. In addition to Si, the substrate 3 can also be one selected from Ge, III-V compound semiconductors, and oxide semiconductors. III-V compound semiconductors include, for example, GaAs, InAs, InGaAs, InP, GaP, or InGaP at least. Oxide semiconductors include, for example, InO, GaO, ZnO, InGaO, InZnO, InGaZnO, InWO, InAlZnO, CuO, SnO, and TiO at least.

[0033] (2-2) As shown in the apparatus configuration diagrams 3 and 4 of the first IGFET Qp, the first IGFET Qp is disposed in an n-type well region 31 formed on the main surface of the substrate 3 on the side of arrow Z, within a region surrounded by the element isolation region 4. The first IGFET Qp mainly comprises a channel formation region (n-type well region 31), a gate insulating film 5, a first floating gate electrode 61, a ferroelectric insulator 105, a control gate electrode 102, and a pair of main electrodes 7. Note that when the substrate 3 is set to n-type with an impurity density equivalent to that of the n-type well region 31, the first IGFET Qp may be disposed on the substrate 3.

[0034] The element isolation region 4 comprises a groove 41 and an embedded member 42. The groove 41 is excavated in the depth direction from the main surface of the n-type well region 31. The embedded member 42 is embedded in the groove 41. The embedded member 42 contains, for example, SiO ２ Insulating materials such as the above are used. In other words, the element isolation region 4 electrically isolates elements such as the first IGFET Qp and the second IGFET Qn, as well as between regions.

[0035] In the first IGFETQp, the gate insulating film 5 is disposed on the channel formation region. The gate insulating film 5 is made of, for example, SiO ２ Monolayer films such as SiN, or composite films combining these, are used.

[0036] The first floating gate electrode 61 is disposed on the gate insulating film 5. The first floating gate electrode 61 is formed of a gate electrode material such as polycrystalline Si. The first floating gate electrode 61 is entirely covered by the gate insulating film 5, a sidewall spacer (not indicated by numeral) formed on the side surface of the first floating gate electrode 61, and an interlayer insulating film 9 covering the first floating gate electrode 61. The sidewall spacer and the interlayer insulating film 9 are each made of SiO ２It is formed from insulating materials such as the above. In other words, the first floating gate electrode 61, including the second floating gate electrode 62 described later, is in an electrically floating state. To explain in more detail, the first floating gate electrode 61 (and the second floating gate electrode 62) are not electrically connected to the terminals of the transistor, resistive elements, power supply, etc., except for the first capacitive element C1 which is electrically coupled in series, the gate capacitance due to the gate insulating film 5, and the parasitic capacitance added to the first floating gate electrode 61.

[0037] The ferroelectric insulator 105 is arranged with a first floating gate electrode 61 (and a second floating gate electrode 62), an interlayer insulating film 9, and a first electrode 101 interposed between them. The first electrode 101 is electrically connected to the first floating gate electrode 61 (and the second floating gate electrode 62) through a first through-hole 9H formed in the interlayer insulating film 9 in the thickness direction. The first electrode 101 is formed as the lower electrode of the first capacitive element C1. The first electrode 101 is formed, for example, from a composite film in which TiN is laminated on Ti.

[0038] The ferroelectric insulator 105 is disposed on the first electrode 101. The ferroelectric insulator 105 is, for example, SiO as a dielectric. ２ Compared to that, it has a higher dielectric constant, and the amount of charge of the first capacitance element C1 can be increased. The ferroelectric insulator 105 is, for example, Hf １－ｘ Zr ｘ O ２ The condition (0 ≤ x < 1) can be used in practical applications.

[0039] The control gate electrode 102 is disposed on the ferroelectric insulator 105. The control gate electrode 102 is disposed opposite the first electrode 101 with the ferroelectric insulator 105 in between, and is formed as the second electrode, which is the upper electrode of the first capacitive element C1. The control gate electrode is made of, for example, TiN.

[0040] In other words, the first capacitance element C1 is constructed by stacking the first electrode 101, the ferroelectric insulator 105, and the control gate electrode (second electrode) 102 in the direction of arrow Z. The first capacitance element C1 is configured as an MFM capacitance element.

[0041] A pair of main electrodes 7 are arranged on both sides of the first floating gate electrode 61 in the gate length direction (the direction coinciding with the direction of arrow X). The main electrodes 7 are formed from p-type semiconductor regions having an impurity density higher than that of the p-type well region 32.

[0042] (2-3) Device Configuration of the Second IGFET Qn The second IGFET Qn is located adjacent to the first IGFET Qp on the opposite side of the direction of arrow Y, and is disposed in a p-type well region 32 formed on the main surface of the substrate 3 within a region surrounded by the element isolation region 4. The second IGFET Qn comprises a channel formation region (p-type well region 32), a gate insulating film 5, a second floating gate electrode 62, a ferroelectric insulator 105, a control gate electrode 102, and a pair of main electrodes 8 as its main components. Note that when the substrate 3 is set to be p-type with an impurity density equivalent to that of the p-type well region 32, the second IGFET Qn may be disposed on the substrate 3.

[0043] In the second IGFETQn, the gate insulating film 5 is arranged on the channel formation region, similar to the gate insulating film 5 of the first IGFETQp.

[0044] The second floating gate electrode 62 is disposed on the gate insulating film 5, similar to the first floating gate electrode 61. Furthermore, the second floating gate electrode 62 is formed on the same conductive layer as the first floating gate electrode 61, and is made of the same gate electrode material, and is integrally formed with the first floating gate electrode 61. In other words, the second floating gate electrode 62 is shared with the first floating gate electrode 61. Moreover, as described above, the second floating gate electrode 62 and the first floating gate electrode 61 are electrically floating.

[0045] The ferroelectric insulator 105 and the control gate electrode 102 are shared between the first floating gate electrode 61 and the second floating gate electrode 62. In other words, the first floating gate electrode 61 and the second floating gate electrode 62 are electrically coupled in series to a single first capacitive element C1.

[0046] A pair of main electrodes 8 are arranged on both sides of the second floating gate electrode 62 in the gate length direction (the direction coinciding with the direction of arrow X). The main electrodes 8 are formed from an n-type semiconductor region having a higher impurity density than the n-type well region 31.

[0047] (2-4) Device configuration including signal line WL Control gate electrode 102 of the first IGFET Qp and second IGFET Qn, i.e., the second electrode of the first capacitive element C1, is electrically connected to the wiring 11. The wiring 11 is used as a signal line WL. The wiring 11 is formed of a metallic material or alloy material such as Al, Al alloy, Cu, CuAl, etc.

[0048] One main electrode 7 of the first IGFET Qp is electrically connected to the contact region 81 through the wiring 11. The contact region 81 is located adjacent to the first IGFET Qp in the gate width direction (the direction corresponding to the arrow Y direction). The contact region 81 is located on the main surface of the n-type well region 31, has a higher impurity density than the n-type well region 31, and is electrically connected to the n-type well region 31.

[0049] One main electrode 8 of the second IGFET Qn is electrically connected to the contact region 71 through the wiring 11. The contact region 71 is located adjacent to the second IGFET Qn in the gate width direction (the direction corresponding to the arrow Y direction). The contact region 71 is located on the main surface of the p-type well region 32, has a higher impurity density than the p-type well region 32, and is electrically connected to the p-type well region 32.

[0050] (2-5) Circuit configuration in the information writing operation of a memory cell MC. Figure 5 shows an example of the circuit configuration in the information writing operation of a memory cell MC. Figure 6 shows an example of the equivalent circuit configuration in the information writing operation of the memory cell MC shown in Figure 5.

[0051] As shown in Figure 5, in the memory cell MC during information writing operation, for example, 0V is applied to signal line IA and 0V is applied to signal line IAb, and then the information writing voltage (program voltage) Vpgm is applied to signal line WL. At this time, as shown in Figure 6, the information writing characteristics of the memory cell MC are determined by the voltage distribution between the first capacitor element C1 and the capacitor Cfg, which are electrically coupled in series.

[0052] Here, capacitance Cfg is generated by the shared first floating gate electrode 61 and second floating gate electrode 62, the gate insulating film 5, and the n-type well region 31 and p-type well region 32 as channel formation regions. In other words, capacitance Cfg appears to have approximately twice the capacitance value compared to the case where each transistor has its own floating gate electrode. Therefore, since the capacitance value of capacitance Cfg can be increased, the voltage distributed to the first capacitance element C1 becomes larger, and the information writing characteristics can be improved. Furthermore, similarly, the information erasure characteristics can be improved.

[0053] (2-6) Regarding the size of the first capacitance element C1 of the memory cell MC, Figure 7 shows an example relationship between the information writing voltage Vpgm and the memory window with respect to the ratio of the sizes of the first IGFET Qp and second IGFET Qn of the memory cell MC to the size of the first capacitance element (MFM capacitance element) C1. Here, the horizontal axis is the information writing voltage Vpgm [V]. The vertical axis is the memory window [V]. In Figure 7, the code Ra is the data when the ratio of the sum of the sizes of the first IGFET Qp and second IGFET Qn / the size of the first capacitance element C1 ((area of ​​Qp + area of ​​Qn) / area of ​​C1) is "4". Similarly, the code Rb is the data when the size ratio is "9", and the code Rc is the data when the size ratio is "16".

[0054] As shown in Figure 7, the memory window expands as the information writing voltage Vpgm increases, and further expands as the size ratio increases. In other words, the smaller the size of the first capacitance element C1 is relative to the sizes of the first IGFET Qp and the second IGFET Qn, the larger the memory window can be. Here, the memory window is the difference between the threshold voltage after the information writing operation and the threshold voltage after the information erasure operation.

[0055] (2-7) Figure 8A shows an example relationship between the control gate voltage and output current of the memory cell MC according to the first embodiment, with respect to the respective threshold voltages of the first IGFET Qp and the second IGFET Qn. Figure 8B shows an example relationship between the control gate voltage and output current of the memory cell according to the comparative example. In both Figure 8A and Figure 8B, the horizontal axis is the gate voltage Vg [V], and the vertical axis is the output current (drain current) Id [A].

[0056] As shown in Figure 8B, the comparative memory cell is composed of an inverter comprising a pMOS having an MFMIS structure and an nMOS having an MFMIS structure. The MFM capacitance is coupled to the intermediate gate of the pMOS. In addition, an MFM capacitance is provided independently of the pMOS, and this MFM capacitance is coupled to the intermediate gate of the nMOS.

[0057] In Figure 8B, code WC1 represents the drain current with respect to the gate voltage during the pMOS information writing operation. Code EC1 represents the drain current with respect to the gate voltage during the pMOS information erasure operation. The pMOS exhibits variations in threshold voltage during both the information writing and erasure operations. On the other hand, code WC2 represents the drain current with respect to the gate voltage during the nMOS information writing operation. Code EC2 represents the drain current with respect to the gate voltage during the nMOS information erasure operation. Similarly, the nMOS exhibits variations in threshold voltage during both the information writing and erasure operations.

[0058] In contrast to the comparative example, as shown in Figure 8A, in the memory cell MC according to the first embodiment, the first floating gate electrode 61 of the first IGFET Qp and the second floating gate electrode 62 of the second IGFET Qn are shared. A first capacitive element C1 common to the first IGFET Qp and the second IGFET Qn is electrically connected in series to the first floating gate electrode 61 and the second floating gate electrode 62.

[0059] In Figure 8A, the symbol W1 represents the drain current with respect to the gate voltage during the information writing operation of the first IGFET Qp. The symbol E1 represents the drain current with respect to the gate voltage during the information erasure operation of the first IGFET Qp. The first IGFET Qp shows no variation in threshold voltage during both the information writing and information erasure operations. Similarly, the symbol W2 represents the drain current with respect to the gate voltage during the information writing operation of the second IGFET Qn. The symbol E2 represents the drain current with respect to the gate voltage during the information erasure operation of the second IGFET Qn. Similarly, the second IGFET Qn shows no variation in threshold voltage during both the information writing and information erasure operations.

[0060] Figure 9 shows an example relationship between the input voltage and output voltage of a memory cell MC. The horizontal axis represents the input voltage Vin [V], and the vertical axis represents the output voltage Vout [V]. As shown in Figure 9, the modulation of the threshold voltages of the first IGFET Qp and the second IGFET Qn are equivalent, so the inverting operation of the inverter can be reliably maintained.

[0061] [Information writing, reading, and erasing operations of non-volatile memory 2] (1) Information writing operation Figure 10 shows an example of the circuit configuration of the memory cell array MA in the information writing operation of the memory cell MC of non-volatile memory 2. The information writing operation is as follows. In each operation description, four memory cells MC1 to MC4 are shown for the sake of simplicity. The signal lines WL and CL connected to memory cell MC1 and memory cell MC2 are referred to as signal line WL1 and signal line CL1. The signal lines WL and CL connected to memory cell MC3 and memory cell MC4 are referred to as signal line WL2 and signal line CL2. The signal lines IA and IAb connected to memory cell MC1 and memory cell MC3 are referred to as signal line IA1 and signal line IAb1. The signal lines IA and IAb connected to memory cell MC2 and memory cell MC4 are referred to as signal line IA2 and signal line IAb2.

[0062] As shown in Figure 10, during the information writing operation of the memory cell MC1, 0V is applied to signal lines IA1 and IAb1. A 1 / 2 information writing voltage Vpgm is applied to signal lines IA2 and IAb2. Meanwhile, a 1 / 2 information writing voltage Vpgm is applied to signal line WL1. A 1 / 2 information writing voltage Vpgm is applied to signal lines CL1, WL2, and CL2. As a result, information such as "1" is written to the memory cell MC1.

[0063] (2) Information Readout Operation Diagram 11 shows an example of the circuit configuration of the memory cell array MA during the information readout operation of the memory cell MC. As shown in Figure 11, during the information readout operation of the memory cell MC1, a readout voltage is applied to signal line IA1 and signal line IAb1, respectively. A selection signal for the memory cell MC1 is applied to signal line WL1. When the information "1" is written to the memory cell MC1, the first IGFET Qp is turned on, and charge is accumulated in the second capacitance element C2 of the memory cell MC1 based on the readout voltage applied to signal line IA1.

[0064] During the information read operation of memory cell MC2, read voltages are applied to signal lines IA2 and IAb2, respectively. A selection signal for memory cell MC2 is applied to signal line WL1. When the information "0" is written to memory cell MC2, the second IGFET Qn turns on, and charge is accumulated in the second capacitance element C2 of memory cell MC2 based on the read voltage applied to signal line IAb2.

[0065] On signal line CL1, the charges stored in the second capacitance element C2 of memory cell MC1 and the second capacitance element C2 of memory cell MC2 are added together, and the signal obtained by summing up the charges is transferred.

[0066] (3) Information erasure operation Figure 12 shows an example of the circuit configuration of the memory cell array MA during the information erasure operation of the memory cell MC. As shown in Figure 12, during the information erasure operation of the memory cell MC1, the information erasure voltage Vera is applied to signal lines IA1 and IAb1. Half the information erasure voltage Vera is applied to signal lines IA2 and IAb2. Meanwhile, 0V is applied to signal line WL1. Half the information erasure voltage Vera is applied to signal lines CL1, WL2 and CL2. As a result, the information written to the memory cell MC1 is erased. That is, the information "0" is written to the memory cell MC1.

[0067] [Effects] As described above, the non-volatile memory 2 according to the first embodiment, or the semiconductor integrated circuit 1 equipped with the non-volatile memory 2, comprises a first IGFET Qp, a second IGFET Qn, and a first capacitive element C1, as shown in Figures 2 to 6. The first IGFET Qp has a first floating gate electrode 61 that is electrically floating and has a first channel conductivity type. The second IGFET Qn is integrally formed with the first floating gate electrode 61 and has a second floating gate electrode 62 that is electrically floating and has a second channel conductivity type opposite to the first channel conductivity type. The first capacitive element C1 is electrically connected in series with the first floating gate electrode 61 and the second floating gate electrode 62 and includes a ferroelectric insulator 105. A detailed explanation follows. The first IGFET Qp has a pair of main electrodes (first main electrodes) 7, one of which is electrically connected to a signal line IA (first power supply) and the other which is an output. The second IGFET Qn has a pair of main electrodes (second main electrodes) 8, one of which is electrically connected to a signal line IAb (second power supply) different from signal line IA, and the other which is an output. The first IGFET Qp and the second IGFET Qn constitute an inverter. As shown in Figure 4, an interlayer insulating film 9 is disposed on the first floating gate electrode 61 of the first IGFET Qp and on the second floating gate electrode 62 of the second IGFET Qn. The interlayer insulating film 9 has a first through-hole 9H that penetrates in the thickness direction. The first floating gate electrode 61 and the second floating gate electrode 62 are electrically coupled to the first capacitive element C1 through the first through-hole 9H.

[0068] In the non-volatile memory 2 or semiconductor integrated circuit 1 configured in this way, the first floating gate electrode 61 of the first IGFET Qp and the second floating gate electrode 62 of the second IGFET Qn are integrally formed. Therefore, the capacitance value of the capacitance Cfg formed by the first floating gate electrode 61 and the second floating gate electrode 62, the gate insulating film 5, and the channel formation region (n-type well region 31 and p-type well region 32) can be effectively increased, thereby significantly improving the information writing characteristics and information erasure characteristics of the memory cell MC. Furthermore, in the non-volatile memory 2 or semiconductor integrated circuit 1, since the first capacitance element C1 of the memory cell MC is commonly provided in the first IGFET Qp and the second IGFET Qn, variations in the threshold voltages of the first IGFET Qp and the second IGFET Qn can be effectively reduced, thereby significantly improving the inverter characteristics.

[0069] Furthermore, the non-volatile memory 2 constructs a compute-in-memory. Therefore, it is possible to realize a compute-in-memory that significantly improves both information writing and information erasure characteristics, as well as inverter characteristics.

[0070] <2. Second Embodiment> The non-volatile memory 2 or semiconductor integrated circuit 1 according to the second embodiment of the present disclosure will be described with reference to Figures 13 and 14. The second embodiment is a second example in which the structure of the memory cell MC is changed in the non-volatile memory 2 or semiconductor integrated circuit 1 according to the first embodiment. In the description of the second embodiment and subsequent embodiments, the same reference numerals are used for components that are the same as or substantially the same as components of the first embodiment, and redundant descriptions are omitted.

[0071] [Device Configuration of Memory Cell MC of Non-Volatile Memory 2] Figure 13 shows an example of the planar configuration of the non-volatile memory 2 according to the second embodiment, or the memory cell MC of the non-volatile memory 2 mounted on the semiconductor integrated circuit 1. Figure 14 shows an example of the cross-sectional configuration of the memory cell MC shown in Figure 13.

[0072] As shown in Figures 13 and 14, in the non-volatile memory 2, a contact region 81 located near the first IGFET Qp in the memory cell MC extends in the direction of arrow X. The first floating gate electrode 61 of the first IGFET Qp extends in the gate width direction within the extended portion of the contact region 81, and this extended portion 61E overlaps. An insulator 51 of the same layer as the gate insulating film 5 is disposed between the extended portion 61E and the contact region 81.

[0073] Similarly, a contact region 71 located near the second IGFET Qn extends in the direction of arrow X. The second floating gate electrode 62 of the second IGFET Qn extends in the gate width direction within the extended portion of the contact region 71, and this extended portion 62E overlaps with the contact region 71. An insulator 52, which is the same layer as the gate insulating film 5, is disposed between the extended portion 62E and the contact region 71.

[0074] Other components are the same as, or substantially the same as, those components of the non-volatile memory 2 or semiconductor integrated circuit 1 according to the first embodiment, so their explanation is omitted here.

[0075] [Effects and Effects] As described above, the non-volatile memory 2 or semiconductor integrated circuit 1 according to the second embodiment can obtain the same effects and effects as those obtained with the non-volatile memory 2 or semiconductor integrated circuit 1 according to the first embodiment.

[0076] Furthermore, in the memory cell MC of the non-volatile memory 2, as shown in Figures 13 and 14, the first floating gate electrode 61 extends in the gate width direction, and this extended portion 61E is arranged overlapping with the contact region 81 via an insulator 51. Also, in the memory cell MC, the second floating gate electrode 62 extends in the gate width direction, and this extended portion 62E is arranged overlapping with the contact region 71 via an insulator 52. With the non-volatile memory 2 or semiconductor integrated circuit 1 configured in this way, the capacity value of the capacity Cfg in the memory cell MC can be effectively increased, thereby further improving the information writing characteristics and information erasure characteristics of the memory cell MC. In this technology, the overlapping arrangement of the extended portion 61E and the contact region 81, and the overlapping arrangement of the extended portion 62E and the contact region 71 may be either one or the other.

[0077] <3. Third Embodiment> The non-volatile memory 2 or semiconductor integrated circuit 1 according to the third embodiment of the present disclosure will be described with reference to Figures 15 to 17. The third embodiment is a third example in which the structure of the memory cell MC is changed in the non-volatile memory 2 or semiconductor integrated circuit 1 according to the first or second embodiment.

[0078] [Circuit Configuration of Memory Cell Array MA of Non-Volatile Memory 2] Figure 15 shows an example of the circuit configuration of the memory cell array MA of the non-volatile memory 2 according to the third embodiment, or the non-volatile memory 2 mounted on the semiconductor integrated circuit 1. As shown in Figure 15, in the non-volatile memory 2, a plurality of memory cells MC, in this case two memory cells MC1 and memory cell MC2, are electrically connected in parallel. This will be explained in detail.

[0079] In memory cell MC1, the first floating gate electrode 61 of the first IGFET Qp and the second floating gate electrode 62 of the second IGFET Qn are integrally formed. In memory cell MC2, the first floating gate electrode 61 of the first IGFET Qp and the second floating gate electrode 62 of the second IGFET Qn are integrally formed. Furthermore, the first floating gate electrode 61 and the second floating gate electrode 62 of memory cell MC1 are integrally formed with the first floating gate electrode 61 and the second floating gate electrode 62 of memory cell MC2. In other words, a total of four pieces—two first floating gate electrode 61s and two second floating gate electrode 62s and two first floating gate electrode 61s and two second floating gate electrode 62s—are integrally formed. These first floating gate electrode 61s and second floating gate electrode 62s are electrically coupled in series to one first capacitive element C1.

[0080] Memory cell MC1 is electrically connected to signal lines IA1, IAb1, WL1, and CL1. The output of memory cell MC1 is electrically coupled to signal line CL1 via the second capacitance element C2. Meanwhile, memory cell MC2 is electrically connected to signal lines IA2, IAb2, WL1, and CL2. The output of memory cell MC2 is electrically coupled to signal line CL2 via the second capacitance element C2.

[0081] [Device Configuration of Memory Cells MC1 and MC2 of Non-Volatile Memory 2] Figure 16 shows an example of the planar configuration of memory cells MC1 and MC2 of non-volatile memory 2. Figure 17 shows an example of the perspective configuration of memory cells MC1 and MC2 shown in Figure 16.

[0082] As shown in Figures 16 and 17, the first IGFET Qp and second IGFET Qn of memory cell MC1 and the first IGFET Qp and second IGFET Qn of memory cell MC2 are sequentially arranged in the opposite direction to the Y direction. Here, the first IGFET Qp and second IGFET Qn are arranged linearly with their gate width direction aligned with the Y direction.

[0083] The first floating gate electrode 61 and the second floating gate electrode 62 are arranged directly in front of the first IGFET Qp and the second IGFET Qn in correspondence with their arrangement and are integrally formed. Furthermore, the first floating gate electrode 61 and the second floating gate electrode 62 extend across the contact region 71 and the contact region 81 between the memory cell MC1 and the memory cell MC2, and are arranged overlappingly in the contact region 71 and the contact region 81.

[0084] Other components are the same as, or substantially the same as, those components of the non-volatile memory 2 or semiconductor integrated circuit 1 according to the first embodiment, so their explanation is omitted here.

[0085] [Effects and Effects] As described above, the non-volatile memory 2 or semiconductor integrated circuit 1 according to the third embodiment can obtain the same effects and effects as those obtained with the non-volatile memory 2 or semiconductor integrated circuit 1 according to the first embodiment. Furthermore, the non-volatile memory 2 or semiconductor integrated circuit 1 according to the third embodiment can obtain the same effects and effects as those obtained with the non-volatile memory 2 or semiconductor integrated circuit 1 according to the second embodiment.

[0086] Furthermore, as shown in Figures 15 to 17, the first and second floating gate electrodes 61 and 62 of the memory cell MC1 and the first and second floating gate electrodes 62 of the memory cell MC2 are integrally formed in the non-volatile memory 2. Therefore, the capacitance value of the capacitance Cfg formed by the first and second floating gate electrodes 61 and 62, the gate insulating film 5, and the channel formation region (n-type well region 31 and p-type well region 32) can be effectively increased. The capacitance value appears to be approximately four times greater. Consequently, the information writing characteristics and information erasure characteristics of the memory cell MC1 and memory cell MC2 can be further improved. Note that in this technology, the first and second floating gate electrodes 61 and 62 of three or more memory cell MCs may be integrally formed.

[0087] <4. Fourth Embodiment> The fourth embodiment of the non-volatile memory 2 or semiconductor integrated circuit 1 according to the fourth embodiment of the present disclosure will be described with reference to Figure 18. The fourth embodiment is a fourth example in which the structure of the memory cell MC is changed in the non-volatile memory 2 or semiconductor integrated circuit 1 according to the third embodiment.

[0088] [Device configuration of the memory cell MC of the non-volatile memory 2] Figure 18 shows an example of the planar configuration of the non-volatile memory 2 according to the fourth embodiment, or the memory cell MC of the non-volatile memory 2 mounted on the semiconductor integrated circuit 1.

[0089] As shown in Figure 18, in the non-volatile memory 2, the arrangement of the contact areas 71 and 81 has been changed in the non-volatile memory 2 or semiconductor integrated circuit 1 according to the third embodiment. This will be explained in detail.

[0090] In memory cell MC1, a contact region 81 is provided adjacent to the first IGFET Qp in the gate length direction (the direction coinciding with the arrow X direction). This contact region 81 is electrically connected to the main electrode 7 of the first IGFET Qp through the wiring 11. In addition, in memory cell MC1, a contact region 71 is provided adjacent to the second IGFET Qn in the gate length direction (the direction coinciding with the arrow X direction). This contact region 71 is electrically connected to the main electrode 8 of the second IGFET Qn through the wiring 11.

[0091] Similarly, in memory cell MC2, a contact region 81 is provided adjacent to the first IGFET Qp in the gate length direction. This contact region 81 is electrically connected to the main electrode 7 of the first IGFET Qp through the wiring 11. In addition, in memory cell MC2, a contact region 71 is provided adjacent to the second IGFET Qn in the gate length direction. This contact region 71 is electrically connected to the main electrode 8 of the second IGFET Qn through the wiring 11.

[0092] Other components are the same as, or substantially the same as, those components of the non-volatile memory 2 or semiconductor integrated circuit 1 according to the third embodiment, so their explanation is omitted here.

[0093] [Effects and Effects] As described above, the non-volatile memory 2 or semiconductor integrated circuit 1 according to the fourth embodiment can obtain the same effects and effects as those obtained with the non-volatile memory 2 or semiconductor integrated circuit 1 according to the third embodiment.

[0094] <5. Fifth Embodiment> The non-volatile memory 2 or semiconductor integrated circuit 1 according to the fifth embodiment of the present disclosure will be described using Figures 19 to 21. The fifth embodiment is a fifth example in which the structure of the memory cell MC is changed in the non-volatile memory 2 or semiconductor integrated circuit 1 according to the first embodiment. Here, in particular, the structure of the second capacitance element C2 will be described.

[0095] [Device Configuration of Memory Cell MC of Non-Volatile Memory 2] Figure 19 shows an example of the planar configuration of the non-volatile memory 2 according to the fifth embodiment, or the memory cell MC of the non-volatile memory 2 mounted on the semiconductor integrated circuit 1. Figure 20 shows an example of the cross-sectional configuration of the memory cell MC, particularly the first capacitance element C1. Figure 21 shows an example of the cross-sectional configuration of the memory cell MC, particularly the second capacitance element C2.

[0096] As shown in Figures 19 to 21, and particularly in Figure 21, in the non-volatile memory 2, a second capacitive element C2 is provided which is electrically coupled in series with the output of the memory cell MC in the non-volatile memory 2 or semiconductor integrated circuit 1 according to the first embodiment. This will be explained in detail.

[0097] As shown in Figure 21, in the memory cell MC, a second through-hole (third through-hole) 921H formed in the interlayer insulating film 9 is provided on one of the main electrodes (outputs) 7 of the first IGFET Qp. Similarly, a second through-hole (fourth through-hole) 922H formed in the interlayer insulating film 9 is provided on one of the main electrodes (outputs) 8 of the second IGFET Qn. Both the second through-hole 921H and the second through-hole 922H are formed by penetrating the interlayer insulating film 9 in the thickness direction.

[0098] The second capacitance element C2 is formed comprising a third electrode 103, a dielectric 106, and a fourth electrode 104. The third electrode 103 is disposed on the interlayer insulating film 9. The third electrode 103 is electrically connected to the main electrode 7 through a second through hole 921H and is electrically connected to the main electrode 8 through a second through hole 922H. The third electrode 103 is formed in the same conductive layer as the first electrode 101 of the first capacitance element C1, and is made of the same electrode material. The dielectric 106 is disposed on the third electrode 103. Unlike the ferroelectric insulator 105, the dielectric 106 is made of, for example, SiO ２ The dielectric material is formed from a dielectric material such as SiN. The fourth electrode 104 is disposed on the dielectric 106. The fourth electrode 104 is formed in the same conductive layer as the control gate electrode (second electrode) 102 of the first capacitance element C1, and is made of the same electrode material.

[0099] The fourth electrode 104 of the second capacitance element C2 is electrically connected to the wiring 11. The wiring 11 is used as a signal line CL, or is electrically connected to the signal line CL.

[0100] Other components are the same as, or substantially the same as, those components of the non-volatile memory 2 or semiconductor integrated circuit 1 according to the first embodiment, so their explanation is omitted here.

[0101] [Effects and Effects] As described above, the non-volatile memory 2 or semiconductor integrated circuit 1 according to the fifth embodiment can obtain the same effects and effects as those obtained with the non-volatile memory 2 or semiconductor integrated circuit 1 according to the first embodiment.

[0102] <6. Sixth Embodiment> The non-volatile memory 2 or semiconductor integrated circuit 1 according to the sixth embodiment of the present disclosure will be described with reference to Figure 22. The sixth embodiment is a sixth example in which the structure of the memory cell MC is changed in the non-volatile memory 2 or semiconductor integrated circuit 1 according to the fifth embodiment.

[0103] [Device configuration of the memory cell MC of the non-volatile memory 2] Figure 22 shows an example of the cross-sectional configuration of the second capacitance element C2 of the memory cell MC of the non-volatile memory 2 according to the sixth embodiment, or the memory cell MC of the non-volatile memory 2 mounted on the semiconductor integrated circuit 1.

[0104] As shown in Figure 22, in the non-volatile memory 2, the second capacitance element C2 of the memory cell MC is formed of a ferroelectric insulator 105 with a higher dielectric constant than the dielectric 106, similar to the first capacitance element C1. Alternatively, the second capacitance element C2 may be formed by stacking the ferroelectric insulator 105 on the dielectric 106.

[0105] Other components are the same as, or substantially the same as, those components of the non-volatile memory 2 or semiconductor integrated circuit 1 according to the fifth embodiment, so their explanation is omitted here.

[0106] [Effects and Effects] As described above, the non-volatile memory 2 or semiconductor integrated circuit 1 according to the sixth embodiment can obtain the same effects and effects as those obtained with the non-volatile memory 2 or semiconductor integrated circuit 1 according to the fifth embodiment.

[0107] Furthermore, in the non-volatile memory 2, as shown in Figure 22, the second capacitance element C2 is formed of a ferroelectric insulator 105, similar to the first capacitance element C1. Therefore, by increasing the capacitance value of the second capacitance element C2, a noise margin can be effectively secured, thereby improving the accuracy of sum-of-accumulate operations.

[0108] Furthermore, in the non-volatile memory 2, as shown in Figure 22, the second capacitance element C2 is formed from a ferroelectric insulator 105, similar to the first capacitance element C1. Therefore, there is no need to manufacture the first capacitance element C1 and the second capacitance element C2 separately. In other words, the number of manufacturing steps in the production of the non-volatile memory 2 or the semiconductor integrated circuit 1 can be reduced. Moreover, since the number of manufacturing steps can be reduced, the manufacturing yield can be improved.

[0109] <7. Seventh Embodiment> The seventh embodiment of the present disclosure will be described using Figures 23 to 25. The seventh embodiment is a seventh example in which the structure of the memory cell MC is changed in the non-volatile memory 2 or semiconductor integrated circuit 1 according to the sixth embodiment.

[0110] [Device Configuration of Memory Cell MC of Non-Volatile Memory 2] Figure 23 shows an example of the planar configuration of the non-volatile memory 2 according to the seventh embodiment, or the memory cell MC of the non-volatile memory 2 mounted on the semiconductor integrated circuit 1. Figure 24 shows an example of the cross-sectional configuration of the memory cell MC, particularly the first capacitance element C1. Figure 25 shows an example of the cross-sectional configuration of the memory cell MC, particularly the second capacitance element C2.

[0111] As shown in Figures 23 to 25, in the non-volatile memory 2, the capacitance value of the second capacitance element C2 of the memory cell MC is increased. In other words, the capacitance value of the first capacitance element C1 is set small in order to improve the information writing characteristics and information erasing characteristics. In contrast, the capacitance value of the second capacitance element C2 is set larger than that of the first capacitance element C1 in order to improve the accuracy of the sum-of-accumulate operation. This will be explained in detail.

[0112] First, as described above, the second capacitance element C2 is formed comprising a third electrode 103, a ferroelectric insulator 105 (or dielectric 106), and a fourth electrode 104. The third electrode 103 is disposed along the inner walls of the second through-hole 921H and the second through-hole 922H, and the main electrode (output) 7 and main electrode (output) 8 that are exposed within the second through-hole 921H and the second through-hole 922H. The ferroelectric insulator 105 is disposed along the inner walls of the second through-hole 921H and the second through-hole 922H with the third electrode 103 interposed between them. The fourth electrode 104 is disposed on the ferroelectric insulator 105. In other words, a part of the second capacitance element C2 is disposed on the interlayer insulating film 9, and the other part of the second capacitance element C2 is disposed within the second through-hole 921H and the second through-hole 922H.

[0113] For example, the opening diameter W2 of the second through-hole 921H and the second through-hole 922H is formed to the sum of twice the thickness te3 of the third electrode 103, twice the thickness tf of the ferroelectric insulator 105, and the thickness te4 of the fourth electrode, as shown in the following formula <1>: W2 = (te3 × 2) + (tf × 2) + te4 …<1>

[0114] In contrast, the first capacitance element C1 is formed comprising a first electrode 101, a ferroelectric insulator 105, and a control gate electrode (second electrode) 102, and is configured not to form capacitance within the first through-hole 9H. Therefore, the opening diameter W1 of the first through-hole 9H is formed to be less than twice the thickness te3 of the third electrode 103, as shown in the following formula <2>: W1 < te3 × 2 …<2>

[0115] Other components are the same as, or substantially the same as, the components of the non-volatile memory 2 or semiconductor integrated circuit 1 according to the sixth embodiment, so their explanation is omitted here.

[0116] [Effects and Effects] As described above, the non-volatile memory 2 or semiconductor integrated circuit 1 according to the seventh embodiment can obtain the same effects and effects as those obtained with the non-volatile memory 2 or semiconductor integrated circuit 1 according to the sixth embodiment.

[0117] Furthermore, in the non-volatile memory 2, as shown in Figures 23 to 25, the second capacitance element C2 increases its capacitance value by utilizing the depth direction of the second through-holes 921H and 922H, respectively. This allows for effective securing of noise margin, thereby further improving the accuracy of sum-of-products operations.

[0118] <8. Eighth Embodiment> The eighth embodiment of the non-volatile memory 2 or semiconductor integrated circuit 1 according to the eighth embodiment of the present disclosure will be described with reference to Figures 26 and 27. The eighth embodiment is an eighth example in which the structure of the memory cell MC is changed in the non-volatile memory 2 or semiconductor integrated circuit 1 according to the seventh embodiment.

[0119] [Device Configuration of Memory Cell MC of Non-Volatile Memory 2] Figure 26 shows an example of the cross-sectional configuration of the memory cell MC of the non-volatile memory 2 according to the eighth embodiment, or the memory cell MC of the non-volatile memory 2 mounted on the semiconductor integrated circuit 1, particularly the first capacitance element C1. Figure 27 shows an example of the cross-sectional configuration of the memory cell MC, particularly the second capacitance element C2.

[0120] As shown in Figures 26 and 27, in the non-volatile memory 2, the capacitance value of the second capacitance element C2 of the memory cell MC is increased, similar to the memory cell MC of the non-volatile memory 2 according to the seventh embodiment.

[0121] In contrast, the first capacitance element C1 has a first electrode 101 and a ferroelectric insulator 105 formed within the first through-hole 9H, but does not have a control gate electrode (second electrode) 102 formed within the first through-hole 9H. Therefore, no capacitance of the first capacitance element C1 is formed within the first through-hole 9H. For example, the opening diameter W1 of the first through-hole 9H is formed to a dimension less than the sum of the thickness of the third electrode 103 (te3) plus the thickness of the ferroelectric insulator 105 (tf), as shown in the following equation <3>: W1 < te3 × 2 + tf …<3>

[0122] Other components are the same as, or substantially the same as, the components of the non-volatile memory 2 or semiconductor integrated circuit 1 according to the seventh embodiment, so their explanation is omitted here.

[0123] [Effects and Effects] As described above, the non-volatile memory 2 or semiconductor integrated circuit 1 according to the eighth embodiment can obtain the same effects and effects as those obtained with the non-volatile memory 2 or semiconductor integrated circuit 1 according to the seventh embodiment.

[0124] <9. Ninth Embodiment> The ninth embodiment of the present disclosure will be described with reference to Figure 28. The ninth embodiment is a ninth example in which the structure of the memory cell MC is changed in the non-volatile memory 2 or semiconductor integrated circuit 1 according to the seventh or eighth embodiment.

[0125] [Device configuration of the memory cell MC of the non-volatile memory 2] Figure 28 shows an example of the cross-sectional configuration of the second capacitance element C2 of the memory cell MC of the non-volatile memory 2 mounted on the semiconductor integrated circuit 1, according to the ninth embodiment.

[0126] As shown in Figure 28, in the non-volatile memory 2, the capacitance value of the second capacitance element C2 of the memory cell MC is increased, similar to the memory cell MC of the non-volatile memory 2 according to the seventh or eighth embodiment. Here, the third electrode 103, ferroelectric insulator 105, and fourth electrode 104 of the second capacitance element C2 are arranged in one of the second through holes 921H, thereby increasing the capacitance value of the second capacitance element C2. In the other second through hole 922H, only the third electrode 103 of the second capacitance element C2 is arranged, and it does not contribute to increasing the capacitance value of the second capacitance element C2.

[0127] The components in the second through-hole 921H and the components in the second through-hole 922H may be swapped.

[0128] Other components are the same as, or substantially the same as, the components of the non-volatile memory 2 or semiconductor integrated circuit 1 according to the seventh or eighth embodiment, so their explanation is omitted here.

[0129] [Effects and Effects] As described above, the non-volatile memory 2 or semiconductor integrated circuit 1 according to the ninth embodiment can obtain the same effects and effects as those obtained with the non-volatile memory 2 or semiconductor integrated circuit 1 according to the seventh or eighth embodiment.

[0130] <10. Tenth Embodiment> The tenth embodiment of the non-volatile memory 2 or semiconductor integrated circuit 1 according to the tenth embodiment of the present disclosure will be described using Figures 29 to 36. The tenth embodiment is the tenth example that describes an appropriate structure or an inappropriate structure for each of the first capacitance element C1 and the second capacitance element C2 of the memory cell MC.

[0131] [Regarding the Structure and Application Range of the Capacitance Element of the Memory Cell MC] Figure 29 shows an example of the relationship between the structures and application ranges of a plurality of capacitance elements in the memory cell MC of the non-volatile memory 2 according to the tenth embodiment, or the non-volatile memory 2 mounted on the semiconductor integrated circuit 1.

[0132] The capacitance element C shown in column A of FIG. 29 Ａ includes a lower electrode 107 disposed in a through-hole 93H formed in the interlayer insulating film 9, a ferroelectric insulator 108 (or dielectric) disposed on the interlayer insulating film 9, and an upper electrode 109 disposed on the ferroelectric insulator 108. This capacitance element C Ａ has a structure with a small capacitance value, so it is appropriate as the structure of the first capacitance element C1. Appropriateness is represented using the symbol "○". Also, the structure of the capacitance element C Ａ is inappropriate as the structure of the second capacitance element C2. Inappropriateness is represented using the symbol "×".

[0133] The capacitance element C shown in column B Ｂ disposes the lower electrode 107, the ferroelectric insulator 108, and the upper electrode 109 in the through-hole 93H and on the interlayer insulating film 9. This capacitance element C Ｂ has a structure with a large capacitance value, so it is appropriate as the structure of the first capacitance element C1. Also, the structure of the capacitance element C Ｂ is appropriate as the structure of the second capacitance element C2.

[0134] The capacitance element C shown in column C Ｃ disposes the lower electrode 107, the ferroelectric insulator 108, and the upper electrode 109 in the through-hole 93H and also disposes the lower electrode 107, the ferroelectric insulator 108, and the upper electrode 109 on the interlayer insulating film 9. This capacitance element C Ｃ has a structure with a large capacitance value, so it is appropriate as the structure of the first capacitance element C1. Also, the structure of the capacitance element C Ｃ is appropriate as the structure of the second capacitance element C2.

[0135] The capacitance element C shown in column D ＤIn this capacitive element C, the lower electrode 107 and ferroelectric insulator 108 are arranged in the through hole 93H, and the ferroelectric insulator 108 and upper electrode 109 are arranged on the interlayer insulating film 9. Ｄ The structure is suitable as the structure of the first capacitance element C1 because its capacitance value is small. Ｄ The structure of the second capacitance element C2 is unsuitable.

[0136] Capacitive element C shown in column E Ｅ In this capacitive element C, the lower electrode 107, ferroelectric insulator 108, and upper electrode 109 are arranged within the through hole 93H, and the ferroelectric insulator 108 and upper electrode 109 are arranged on the interlayer insulating film 9. Ｅ The structure is suitable as the structure of the first capacitance element C1 because its capacitance value is small. Ｅ The structure of the second capacitance element C2 is unsuitable.

[0137] Here, the capacitive element C Ｅ When the structure is applied as the structure of the first capacitance element C1, the first electrode 101 of the first capacitance element C1 is excavated from the upper end of the first through hole 9H and arranged along the inner wall of the first through hole 9H (see, for example, Figure 26). Ｅ When the structure is applied as the structure of the second capacitance element C2, the third electrode 103 of the second capacitance element C2 is excavated from the upper ends of the second through-hole 921H and the second through-hole 922H and arranged along the inner walls of the second through-hole 921H and the second through-hole 922H (see, for example, Figure 27). This excavation method will be explained later with reference to Figures 30 to 36.

[0138] Capacitive element C shown in column F Ｆ This is the aforementioned capacitive element C Ｂ This is an example of its application, in which a core insulator 110 is placed in the center of the through hole 93H. Ｆ The structure of the first capacitance element C is suitable because it has a large capacitance value. Ｆ The structure is appropriate as the structure of the second capacitance element C2.

[0139] Capacitive element C shown in column G ＧThis is the aforementioned capacitive element C Ｆ This is an example of its application, in which a core insulator 110 is placed in the center of the through hole 93H. Ｇ The structure is suitable as the structure of the first capacitance element C1 because its capacitance value is small. Ｇ The structure of the second capacitance element C2 is unsuitable.

[0140] [Method for excavating the lower electrode 107] Figures 30 to 36 show the aforementioned capacitive element C Ｆ (or capacitive element C) Ｇ This shows an example of a cross-sectional configuration of the process for explaining the manufacturing method of the capacitive element C. Ｆ The manufacturing method is as follows:

[0141] First, a through-hole 93H is formed in the interlayer insulating film 9 (see Figure 30). As shown in Figure 30, a lower layer electrode 107 is formed on the interlayer insulating film 9 along the inner wall of the through-hole 93H and the surface of the output exposed within the through-hole 93H. As shown in Figure 31, a mask 120 is formed to cover the lower layer electrode 107 and fill the inside of the through-hole 93H. For example, a photoresist is used for the mask 120. As shown in Figure 32, the mask 120 on the interlayer insulating film 9 is removed while the mask 120 inside the through-hole 93H remains.

[0142] As shown in Figure 33, the lower electrode 107 on the interlayer insulating film 9 is removed using the mask 120. For example, etching is used to remove the lower electrode 107. At this time, over-etching is performed, and the lower electrode 107 is excavated below the upper end of the through hole 93H. After this, as shown in Figure 34, the mask 120 is selectively removed.

[0143] As shown in Figure 35, a ferroelectric insulator 108 and an upper electrode 109 are sequentially formed on the lower electrode 107 along the inner wall of the through hole 93H and the surface of the output. The ferroelectric insulator 108 and the upper electrode 109 are also formed on the interlayer insulating film 9. As shown in Figure 36, the ferroelectric insulator 108 and the upper electrode 109 on the interlayer insulating film 9 are patterned to form a capacitive element C Ｆ A formation is created.

[0144] Other components are the same as, or substantially the same as, the components of the non-volatile memory 2 or semiconductor integrated circuit 1 according to any of the first to ninth embodiments, so their explanation is omitted here.

[0145] [Effects and Effects] As described above, the non-volatile memory 2 or semiconductor integrated circuit 1 according to the 10th embodiment can obtain the same effects and effects as those obtained by the non-volatile memory 2 or semiconductor integrated circuit 1 according to any of the 1st to 9th embodiments.

[0146] <11. Other Embodiments> This technology is not limited to the embodiments described above, and can be modified in various ways without departing from its essence. For example, this technology may be used to construct a non-volatile memory or semiconductor integrated circuit by combining two or more non-volatile memory or semiconductor integrated circuits according to any of the first to tenth embodiments. In addition, in this technology, two or more first capacitive elements in a memory cell may be electrically connected in series or in parallel to a first floating gate electrode and a second floating gate electrode.

[0147] The semiconductor integrated circuit according to the first embodiment of this disclosure comprises a first IGFET having a first floating gate electrode that is electrically floating and having a first channel conductivity type, a second IGFET integrally formed with the first floating gate electrode and having a second floating gate electrode that is electrically floating and having a second channel conductivity type opposite to that of the first channel conductivity type, and a first capacitive element electrically coupled in series to the first floating gate electrode and the second floating gate electrode and containing a ferroelectric insulator. In the semiconductor integrated circuit according to the first embodiment, the first IGFET has a pair of first main electrodes, one of which is electrically connected to a first power supply and the other which is an output. The second IGFET has a pair of second main electrodes, one of which is electrically connected to a second power supply different from the first power supply and the other which is an output. The first IGFET and the second IGFET constitute an inverter. Furthermore, in the semiconductor integrated circuit according to the first embodiment, an interlayer insulating film is disposed on the first floating gate electrode and the second floating gate electrode, and a first through-hole penetrating in the thickness direction is disposed in the interlayer insulating film. The first floating gate electrode and the second floating gate electrode are electrically coupled to the first capacitive element through the first through-hole. With this configuration, the information writing and erasing characteristics of the memory cell composed of the inverter and the first capacitive element can be significantly improved. Furthermore, the inverter characteristics can be significantly improved.

[0148] A semiconductor integrated circuit according to a second embodiment of this disclosure further comprises a second capacitance element electrically coupled in series to the output of the semiconductor integrated circuit according to the first embodiment. In the semiconductor integrated circuit according to the second embodiment, an interlayer insulating film is disposed on the output, and a second through-hole penetrating in the thickness direction is disposed in the interlayer insulating film. The output is electrically coupled to the second capacitance element through the second through-hole. With a semiconductor integrated circuit configured in this way, the accuracy of the sum-of-accumulate operation can be improved.

[0149] In the semiconductor integrated circuit according to the third embodiment of this disclosure, in the semiconductor integrated circuit according to the second embodiment, the first IGFET, the second IGFET, the first capacitance element, and the second capacitance element constitute a memory cell. The semiconductor integrated circuit according to the third embodiment includes a non-volatile memory constructed by arranging a plurality of memory cells. With a semiconductor integrated circuit configured in this way, it is possible to realize a non-volatile memory that can sufficiently improve information writing characteristics and information erasure characteristics, sufficiently improve inverter characteristics, and improve the accuracy of sum-of-accumulate operations.

[0150] <Configuration of this technology> This technology has the following configuration. According to this technology with the following configuration, the information writing characteristics and information erasure characteristics of a non-volatile memory or a semiconductor integrated circuit equipped with a non-volatile memory can be sufficiently improved.

[0151] (1) A semiconductor integrated circuit comprising: a first insulated gate field effect transistor having an electrically floating first floating gate electrode and a first channel conductivity type; a second insulated gate field effect transistor having a second floating gate electrode formed integrally with the first floating gate electrode and having a second channel conductivity type opposite to that of the first channel conductivity type; and a first capacitive element electrically coupled in series to the first floating gate electrode and the second floating gate electrode, and including a ferroelectric insulator. (1-1) The semiconductor integrated circuit according to (1), wherein the first capacitive element is a plurality of capacitive elements electrically connected in series. (1-2) The semiconductor integrated circuit according to (1), wherein the first capacitive element is a plurality of capacitive elements electrically connected in parallel. (1-3) The semiconductor integrated circuit according to (1), wherein the first floating gate electrode and the second floating gate electrode are shared.(2) The semiconductor integrated circuit according to (1), wherein the first insulated gate field-effect transistor has a pair of first main electrodes, one of which is electrically connected to a first power supply and the other of which is an output, and the second insulated gate field-effect transistor has a pair of second main electrodes, one of which is electrically connected to a second power supply different from the first power supply and the other of which is an output, and the first insulated gate field-effect transistor and the second insulated gate field-effect transistor constitute an inverter. (3) The semiconductor integrated circuit according to (1) or (2), wherein a contact region electrically connected to a substrate or a well region is disposed near at least one of the first insulated gate field-effect transistor and the second insulated gate field-effect transistor, and at least one of the first floating gate electrode and the second floating gate electrode extends in the gate width direction, and this extended portion is disposed overlapping the contact region via an insulator. (4) A semiconductor integrated circuit according to any one of (1) to (3), wherein a plurality of first insulated gate field-effect transistors are arranged, a plurality of second insulated gate field-effect transistors are arranged, and each of the first floating gate electrodes of the plurality of first insulated gate field-effect transistors and the second floating gate electrodes of the plurality of second insulated gate field-effect transistors are integrally formed. (5) A semiconductor integrated circuit according to any one of (1) to (4), wherein an interlayer insulating film is disposed on the first floating gate electrode and the second floating gate electrode, a first through hole is disposed in the interlayer insulating film that penetrates in the thickness direction, and the first floating gate electrode and the second floating gate electrode are electrically coupled to the first capacitive element through the first through hole.(6) The semiconductor integrated circuit according to (5), wherein the first capacitance element comprises a first electrode disposed on the interlayer insulating film, a ferroelectric insulator disposed on the first electrode, and a second electrode disposed on the ferroelectric insulator. (6-1) The semiconductor integrated circuit according to (5), wherein the first capacitance element comprises a first electrode disposed in the first through hole, a ferroelectric insulator disposed on the first electrode and on the interlayer insulating film, and a second electrode disposed on the ferroelectric insulator. (7) The semiconductor integrated circuit according to (6), wherein the first capacitance element comprises a first electrode disposed along the inner wall of the first through hole and the first floating gate electrode or the second floating gate electrode in the first through hole, a ferroelectric insulator disposed along the inner wall of the first through hole with the first electrode interposed, and a second electrode disposed on the ferroelectric insulator. (7-1) The semiconductor integrated circuit according to (7), wherein the second electrode is disposed along the inner wall of the first through hole with the first electrode and the ferroelectric insulator interposed between them. (7-2) The semiconductor integrated circuit according to (7) or (7-1), wherein the first electrode is disposed along the inner wall of the first through hole, excavated from the upper end of the first through hole. (8) The ferroelectric insulator is Hf. １－ｘ Zr ｘ O ２(1) The semiconductor integrated circuit according to any one of (1) to (7) above, wherein (0 ≤ x < 1). (9) The semiconductor integrated circuit according to (3) above, wherein the first insulated gate field-effect transistor and the second insulated gate field-effect transistor are disposed on one of the substrate or the well region selected from Si, Ge, III-V compound semiconductor and oxide semiconductor. (10) The semiconductor integrated circuit according to (2) above, further comprising a second capacitive element electrically coupled in series to the output. (11) The semiconductor integrated circuit according to (10) above, wherein an interlayer insulating film is disposed on the output, a second through hole penetrating in the thickness direction is disposed in the interlayer insulating film, and the output is electrically coupled to the second capacitive element through the second through hole. (12) The semiconductor integrated circuit according to (11), wherein the second capacitance element comprises a third electrode disposed on the interlayer insulating film, a dielectric disposed on the third electrode, and a fourth electrode disposed on the dielectric. (12-1) The semiconductor integrated circuit according to (12), wherein the second capacitance element comprises a third electrode disposed in the second through-hole, the dielectric disposed on the third electrode and on the interlayer insulating film, and a fourth electrode disposed on the dielectric. (13) The semiconductor integrated circuit according to (12), wherein the second capacitance element comprises the third electrode disposed along the inner wall of the second through-hole and the output within the second through-hole, the dielectric disposed along the inner wall of the second through-hole with the third electrode interposed, and a fourth electrode disposed on the dielectric. (13-1) The semiconductor integrated circuit according to (13), wherein the fourth electrode is disposed along the inner wall of the second through hole with the third electrode and the dielectric material interposed between them. (13-2) The semiconductor integrated circuit according to (13) or (13-1), wherein the third electrode is disposed along the inner wall of the second through hole, after being excavated from the upper end of the second through hole.(14) The semiconductor integrated circuit according to (2), further comprising a second capacitance element electrically coupled in series to the output and including a dielectric, wherein an interlayer insulating film is disposed on the first floating gate electrode, the second floating gate electrode and the output, the first capacitance element is electrically coupled to the first floating gate electrode or the second floating gate electrode through a first through-hole penetrating the interlayer insulating film in the thickness direction, the first capacitance element comprises a first electrode disposed on the interlayer insulating film, a ferroelectric insulator disposed on the first electrode, and a second electrode disposed on the ferroelectric insulator, the second capacitance element is electrically coupled to the output through a second through-hole penetrating the interlayer insulating film in the thickness direction, the second capacitance element comprises a third electrode disposed along the inner wall of the second through-hole and the output within the second through-hole, the dielectric disposed along the inner wall of the second through-hole with the third electrode interposed, and a fourth electrode disposed on the dielectric. (14-1) The semiconductor integrated circuit according to (14), wherein the diameter of the opening of the first through-hole is less than twice the thickness of the third electrode (diameter of the opening of the first through-hole < thickness of the third electrode × 2). (14-2) The semiconductor integrated circuit according to (14), wherein the diameter of the opening of the first through-hole is less than the total thickness of the dielectric material plus twice the thickness of the third electrode (diameter of the opening of the first through-hole < thickness of the third electrode × 2 + thickness of the dielectric material).(15) The semiconductor integrated circuit according to (2), further comprising a second capacitance element electrically coupled in series to the output and including a dielectric, wherein an interlayer insulating film is disposed on the first floating gate electrode, the second floating gate electrode and the output, the first capacitance element is electrically coupled to the first floating gate electrode or the second floating gate electrode through a first through-hole penetrating the interlayer insulating film in the thickness direction, the first capacitance element comprises the inner wall of the first through-hole and a first electrode disposed along the first floating gate electrode or the second floating gate electrode within the first through-hole, the ferroelectric insulator disposed along the inner wall of the first through-hole with the first electrode interposed, and a second electrode disposed on the ferroelectric insulator, the second capacitance element is electrically coupled to the output through a second through-hole penetrating the interlayer insulating film in the thickness direction, the second capacitance element comprises a third electrode disposed on the interlayer insulating film, the dielectric disposed on the third electrode, and a fourth electrode disposed on the dielectric. (15-1) The semiconductor integrated circuit according to (15), wherein the diameter of the opening of the second through-hole is less than twice the thickness of the first electrode (diameter of the second through-hole < twice the thickness of the first electrode). (15-2) The semiconductor integrated circuit according to (15), wherein the diameter of the opening of the second through-hole is less than twice the total thickness of the first electrode plus the thickness of the ferroelectric insulator (diameter of the second through-hole < twice the thickness of the first electrode + ferroelectric insulator).(16) The semiconductor integrated circuit according to (2), further comprising a second capacitance element electrically coupled in series to the output and including a dielectric, wherein an interlayer insulating film is disposed on the first main electrode and the second main electrode, the interlayer insulating film has a third through hole that penetrates in the thickness direction in the region of the first main electrode, the interlayer insulating film has a fourth through hole that penetrates in the thickness direction in the region of the second main electrode, the first main electrode is electrically coupled to the second capacitance element through the third through hole, the second main electrode is electrically coupled to the second capacitance element through the fourth through hole, and the second capacitance element comprises a third electrode disposed along at least one inner wall of the third through hole and the fourth through hole, a dielectric disposed along the one inner wall with the third electrode interposed, and a fourth electrode disposed on the dielectric. (16-1) The semiconductor integrated circuit according to (16), wherein the diameter of the other opening of the third through-hole and the fourth through-hole is less than twice the thickness of the third electrode (diameter of the third through-hole or the fourth through-hole < twice the thickness of the third electrode). (16-2) The semiconductor integrated circuit according to (16), wherein the diameter of the other opening of the third through-hole and the fourth through-hole is less than twice the total thickness of the third electrode plus the thickness of the dielectric (diameter of the third through-hole or the fourth through-hole < twice the thickness of the third electrode + dielectric). (17) The semiconductor integrated circuit according to any one of (10) to (16), wherein the dielectric is a ferroelectric insulator. (18) The semiconductor integrated circuit according to any one of (10) to (17), wherein the first insulated-gate field-effect transistor, the second insulated-gate field-effect transistor, the first capacitive element, and the second capacitive element constitute a memory cell, and a non-volatile memory is constructed by arranging a plurality of the memory cells. (19) The semiconductor integrated circuit according to (18), wherein the non-volatile memory constitutes a computing in memory.

[0152] This application claims priority based on Japanese Patent Application No. 2024-176612, filed with the Japan Patent Office on 8 October 2024, and all contents of that application are incorporated herein by reference.

[0153] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A semiconductor integrated circuit comprising: a first insulated gate field-effect transistor having a first floating gate electrode that is electrically floating and having a first channel conductivity type; a second insulated gate field-effect transistor having a second floating gate electrode formed integrally with the first floating gate electrode and having a second channel conductivity type opposite to that of the first channel conductivity type; and a first capacitive element containing a ferroelectric insulator, electrically coupled in series to the first floating gate electrode and the second floating gate electrode.

2. The semiconductor integrated circuit according to claim 1, wherein the first insulated-gate field-effect transistor has a pair of first main electrodes, one of which is electrically connected to a first power supply and the other of which is an output, and the second insulated-gate field-effect transistor has a pair of second main electrodes, one of which is electrically connected to a second power supply different from the first power supply and the other of which is an output, and the first insulated-gate field-effect transistor and the second insulated-gate field-effect transistor constitute an inverter.

3. The semiconductor integrated circuit according to claim 1, wherein a contact region electrically connected to a substrate or well region is disposed near at least one of the first insulated gate field-effect transistor and the second insulated gate field-effect transistor, and at least one of the first floating gate electrode and the second floating gate electrode extends in the gate width direction, with the extended portion overlapping the contact region via an insulator.

4. The semiconductor integrated circuit according to claim 1, wherein a plurality of first insulated-gate field-effect transistors are arranged, a plurality of second insulated-gate field-effect transistors are arranged, and each of the first floating gate electrodes of the plurality of first insulated-gate field-effect transistors and the second floating gate electrodes of the plurality of second insulated-gate field-effect transistors are integrally formed.

5. The semiconductor integrated circuit according to claim 1, wherein an interlayer insulating film is disposed on the first floating gate electrode and the second floating gate electrode, a first through-hole penetrating in the thickness direction is disposed in the interlayer insulating film, and the first floating gate electrode and the second floating gate electrode are electrically coupled to the first capacitive element through the first through-hole.

6. The semiconductor integrated circuit according to claim 5, wherein the first capacitive element comprises a first electrode disposed on the interlayer insulating film, a ferroelectric insulator disposed on the first electrode, and a second electrode disposed on the ferroelectric insulator.

7. The semiconductor integrated circuit according to claim 6, wherein the first capacitive element comprises the first electrode disposed along the inner wall of the first through-hole and the first floating gate electrode or the second floating gate electrode within the first through-hole, the ferroelectric insulator disposed along the inner wall of the first through-hole with the first electrode interposed therebetween, and the second electrode disposed on the ferroelectric insulator.

8. The ferroelectric insulator is Hf １－ｘ Zr ｘ O ２ The semiconductor integrated circuit according to claim 1, wherein (0 ≤ x < 1).

9. The semiconductor integrated circuit according to claim 3, wherein the first insulated gate field-effect transistor and the second insulated gate field-effect transistor are disposed on one of the substrates or well regions selected from Si, Ge, III-V compound semiconductors and oxide semiconductors.

10. The semiconductor integrated circuit according to claim 2, further comprising a second capacitive element electrically coupled in series with the output.

11. The semiconductor integrated circuit according to claim 10, wherein an interlayer insulating film is disposed on the output, a second through-hole penetrating in the thickness direction is disposed in the interlayer insulating film, and the output is electrically coupled to the second capacitive element through the second through-hole.

12. The semiconductor integrated circuit according to claim 11, wherein the second capacitance element comprises a third electrode disposed on the interlayer insulating film, a dielectric disposed on the third electrode, and a fourth electrode disposed on the dielectric.

13. The semiconductor integrated circuit according to claim 12, wherein the second capacitance element comprises the inner wall of the second through-hole, the third electrode disposed along the output within the second through-hole, the dielectric disposed along the inner wall of the second through-hole with the third electrode interposed therebetween, and the fourth electrode disposed on the dielectric.

14. A semiconductor integrated circuit according to claim 2, further comprising a second capacitance element electrically coupled in series to the output, the second capacitance element comprising an interlayer insulating film disposed on the first floating gate electrode, the second floating gate electrode, and the output, the first capacitance element being electrically coupled to the first floating gate electrode or the second floating gate electrode through a first through-hole penetrating the interlayer insulating film in the thickness direction, the first capacitance element comprising a first electrode disposed on the interlayer insulating film, a ferroelectric insulator disposed on the first electrode, and a second electrode disposed on the ferroelectric insulator, the second capacitance element being electrically coupled to the output through a second through-hole penetrating the interlayer insulating film in the thickness direction, the second capacitance element comprising a third electrode disposed along the output on the inner wall of the second through-hole, the dielectric disposed along the inner wall of the second through-hole with the third electrode interposed, and a fourth electrode disposed on the dielectric.

15. A semiconductor integrated circuit according to claim 2, further comprising a second capacitance element electrically coupled in series to the output and including a dielectric, wherein an interlayer insulating film is disposed on the first floating gate electrode, the second floating gate electrode, and the output, the first capacitance element is electrically coupled to the first floating gate electrode or the second floating gate electrode through a first through-hole penetrating the interlayer insulating film in the thickness direction, the first capacitance element comprises the inner wall of the first through-hole and a first electrode disposed along the first floating gate electrode or the second floating gate electrode within the first through-hole, the ferroelectric insulator disposed along the inner wall of the first through-hole with the first electrode interposed, and a second electrode disposed on the ferroelectric insulator, the second capacitance element is electrically coupled to the output through a second through-hole penetrating the interlayer insulating film in the thickness direction, and the second capacitance element comprises a third electrode disposed on the interlayer insulating film, the dielectric disposed on the third electrode, and a fourth electrode disposed on the dielectric.

16. The semiconductor integrated circuit according to claim 2, further comprising a second capacitance element electrically coupled in series to the output and including a dielectric, wherein an interlayer insulating film is disposed on the first main electrode and the second main electrode, the interlayer insulating film has a third through-hole that penetrates in the thickness direction in the region of the first main electrode, the interlayer insulating film has a fourth through-hole that penetrates in the thickness direction in the region of the second main electrode, the first main electrode is electrically coupled to the second capacitance element through the third through-hole, the second main electrode is electrically coupled to the second capacitance element through the fourth through-hole, and the second capacitance element comprises a third electrode disposed along the inner wall of at least one of the third through-hole and the fourth through-hole, a dielectric disposed along the one inner wall with the third electrode interposed, and a fourth electrode disposed on the dielectric.

17. The semiconductor integrated circuit according to claim 10, wherein the dielectric is a ferroelectric insulator.

18. The semiconductor integrated circuit according to claim 10, wherein the first insulated-gate field-effect transistor, the second insulated-gate field-effect transistor, the first capacitive element, and the second capacitive element constitute a memory cell, and the integrated circuit comprises a non-volatile memory constructed by arranging a plurality of the memory cells.

19. The semiconductor integrated circuit according to claim 18, wherein the non-volatile memory constitutes a compute-in-memory.

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