Driving method, driving module and display apparatus

Abstract

Provided in the present disclosure are a driving method, a driving module and a display apparatus. The driving method is applied to a pixel circuit. A display cycle comprises N display sub-cycles, and an nth display sub-cycle comprises an nth light emission preparation phase and an nth light emission phase that are arranged in sequence, wherein N is an integer greater than 1, n is a positive integer less than or equal to N, and the nth light emission preparation phase comprises at least one reset time period. The driving method comprises: during reset time periods, a first reset circuit writing a first initial voltage into a first electrode of a light-emitting element under the control of a first reset control signal; and when the luminous brightness of the light-emitting element is less than or equal to a brightness threshold value in a display cycle, setting the time interval between the start time of a first reset time period and the end time of an nth light emission preparation phase to be greater than a pre-charging time threshold value within the nth light emission preparation phase. The present disclosure can mitigate the problems of ghosting and brightening.

Description

Driving method, driving module and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a driving method, a driving module, and a display device. Background Technology

[0002] To further improve the power consumption of mobile display products, tandem devices are used (tandem devices are high-efficiency OLED devices formed by connecting and stacking multiple OLED (organic light-emitting diode) devices in series with conductive layers). This reduces the current flowing through the tandem device while achieving the same brightness, thus lowering power consumption. However, the introduction of tandem devices introduces greater crosstalk, requiring isolation designs to reduce its impact. But this isolation design leads to short circuits between the conductive layer and the cathode at the isolation points, resulting in abnormal light emission paths at low grayscale levels. Furthermore, the increased crosstalk from the dual-layer devices causes these abnormal paths to also emit light, resulting in low-grayscale ghosting and brightening issues.

[0003] Summary of the Invention

[0004] In one aspect, this disclosure provides a driving method applied to a pixel circuit, the pixel circuit including a driving circuit, a first light-emitting control circuit, a light-emitting element, and a first reset circuit; the first light-emitting control circuit is used to control the connection or disconnection between a first terminal of the driving circuit and a first electrode of the light-emitting element under the control of a light-emitting control signal provided by a light-emitting control terminal; the first reset circuit is used to control the connection or disconnection between a first initial voltage terminal and a first electrode of the light-emitting element under the control of a first reset control signal provided by a first reset control terminal; the second electrode of the light-emitting element is electrically connected to the first voltage terminal; the display cycle includes N display sub-cycles, the nth display sub-cycle including a nth pre-light-emitting stage and an nth light-emitting stage set sequentially, N being an integer greater than 1, and n being a positive integer less than or equal to N; the nth pre-light-emitting stage includes at least one reset time period; the driving method includes:

[0005] During the nth light-emitting stage, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the first terminal of the driving circuit to disconnect from the first electrode of the light-emitting element;

[0006] During the reset time period, under the control of the first reset control signal, the first reset circuit writes the first initial voltage provided by the first initial voltage terminal into the first electrode of the light-emitting element;

[0007] During at least a portion of the time period included in the nth luminescence stage, the first luminescence control circuit, under the control of the luminescence control signal, controls the first terminal of the driving circuit to connect with the first electrode of the luminescence element;

[0008] When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the first reset time period and the end time of the nth preparation light-emitting stage is set to be greater than the pre-charge time threshold during the nth preparation light-emitting stage.

[0009] Optionally, the pre-charge time threshold is greater than or equal to 20 lines of scan time but less than the duration of the nth preparation emission stage.

[0010] Optionally, the brightness threshold is less than or equal to 150 nits.

[0011] Optionally, the pixel circuit further includes a second reset circuit, which, under the control of a second reset control signal provided by the second reset control terminal, controls the connection or disconnection between the second initial voltage terminal and the reset terminal of the driving circuit; the reset terminal includes a first terminal and / or a second terminal of the driving circuit; the driving method includes:

[0012] During the reset time period, under the control of the second reset control signal, the second reset circuit writes the second initial voltage provided by the second initial voltage terminal into the reset terminal of the drive circuit.

[0013] Optionally, the first reset control terminal and the second reset control terminal are the same control terminal.

[0014] Optionally, the pixel circuit further includes a second light-emitting control circuit, which, under the control of the light-emitting control signal, controls the connection or disconnection between the second voltage terminal and the second terminal of the driving circuit; the driving method includes:

[0015] During the nth light-emitting stage, the second light-emitting control circuit, under the control of the light-emitting control signal, controls the second voltage terminal to disconnect from the second terminal of the driving circuit;

[0016] During at least a portion of the time period included in the nth luminescence stage, the second luminescence control circuit, under the control of the luminescence control signal, controls the connection between the second voltage terminal and the second terminal of the driving circuit.

[0017] Optionally, the driving method includes:

[0018] In the nth light-emitting stage, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the first terminal of the driving circuit to connect with the first electrode of the light-emitting element, and the second light-emitting control circuit, under the control of the light-emitting control signal, controls the second voltage terminal to connect with the second terminal of the driving circuit.

[0019] Optionally, in the nth luminescence stage, the luminescence control signal is a PWM signal.

[0020] Optionally, the nth light-emitting preparation stage includes an nth reset time period; the driving method includes:

[0021] During the nth reset time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first electrode of the light-emitting element;

[0022] When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the nth reset time period and the end time of the nth preparation light-emitting stage is set to be greater than the pre-charging time threshold.

[0023] Optionally, the nth light-emitting preparation stage includes a first reset time period and an nth second reset time period set sequentially; the driving method includes:

[0024] During the nth first reset time period and the nth second reset time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first electrode of the light-emitting element;

[0025] When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the nth first reset time period and the end time of the nth preparation luminous stage is set to be greater than the pre-charge time threshold.

[0026] Optionally, N is less than or equal to the threshold number of emission times.

[0027] Optionally, the threshold for the number of light emission events is less than 7.

[0028] In a second aspect, embodiments of this disclosure provide a driving module applied to a pixel circuit, the pixel circuit including a driving circuit, a first light-emitting control circuit, a light-emitting element, and a first reset circuit; the first light-emitting control circuit is used to control the connection or disconnection between a first terminal of the driving circuit and a first electrode of the light-emitting element under the control of a light-emitting control signal provided by a light-emitting control terminal; the first reset circuit is used to control the connection or disconnection between a first initial voltage terminal and a first electrode of the light-emitting element under the control of a first reset control signal provided by a first reset control terminal; the second electrode of the light-emitting element is electrically connected to the first voltage terminal; the display cycle includes N display sub-cycles, the nth display sub-cycle including a nth pre-light-emitting stage and an nth light-emitting stage set sequentially, N being an integer greater than 1, and n being a positive integer less than or equal to N; the nth pre-light-emitting stage includes at least one reset time period;

[0029] The driving module includes a light emission control signal generation circuit and a first reset control signal generation circuit;

[0030] The light emission control signal generation circuit is used to provide the light emission control signal to the light emission control terminal, such that in the nth light emission preparation stage, the first light emission control circuit, under the control of the light emission control signal, controls the first terminal of the driving circuit to disconnect from the first electrode of the light emission element, and causes the first light emission control circuit, under the control of the light emission control signal, to connect the first terminal of the driving circuit to the first electrode of the light emission element during at least a portion of the time period included in the nth light emission stage.

[0031] The first reset control signal generation circuit is further configured to provide the first reset control signal to the first reset control terminal, so that during the reset time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage provided by the first initial voltage terminal into the first electrode of the light-emitting element.

[0032] When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the first reset time period and the end time of the nth preparation light-emitting stage is greater than the pre-charge time threshold during the nth preparation light-emitting stage.

[0033] Optionally, the pre-charge time threshold is greater than or equal to 20 lines of scan time but less than the duration of the nth preparation emission stage.

[0034] Optionally, the brightness threshold is less than or equal to 120 nits.

[0035] Optionally, the pixel circuit further includes a second reset circuit, which is used to control the connection or disconnection between the second initial voltage terminal and the reset terminal of the driving circuit under the control of the second reset control signal provided by the second reset control terminal; the reset terminal includes the first terminal and / or the second terminal of the driving circuit;

[0036] The drive module also includes a second reset control signal generation circuit;

[0037] The second reset control signal generation circuit is used to provide a second reset control signal to the second reset control terminal, so that during the reset time period, the second reset circuit, under the control of the second reset control signal, writes the second initial voltage provided by the second initial voltage terminal into the reset terminal of the drive circuit.

[0038] Optionally, the first reset control terminal and the second reset control terminal are the same control terminal.

[0039] Optionally, the pixel circuit further includes a second light-emitting control circuit, which is used to control the connection or disconnection between the second voltage terminal and the second terminal of the driving circuit under the control of the light-emitting control signal.

[0040] The light emission control signal generation circuit is further configured to, by providing the light emission control signal, cause the second light emission control circuit, under the control of the light emission control signal, to disconnect the second voltage terminal from the second terminal of the driving circuit, and cause the second light emission control circuit, under the control of the light emission control signal, to connect the second voltage terminal to the second terminal of the driving circuit during at least a portion of the time period included in the nth light emission stage.

[0041] Optionally, the light emission control signal generation circuit is further configured to provide the light emission control signal such that, in the nth light emission stage, the first light emission control circuit controls the first terminal of the driving circuit to connect with the first electrode of the light emission element under the control of the light emission control signal, and the second light emission control circuit controls the second voltage terminal to connect with the second terminal of the driving circuit under the control of the light emission control signal.

[0042] Optionally, the light emission control signal generation circuit is further configured to control the light emission control signal to be a PWM signal during the nth light emission stage.

[0043] Optionally, the nth light-emitting preparation stage includes the nth reset time period;

[0044] The first reset control signal generation circuit is further configured to provide a first reset control signal, such that during the nth reset time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first electrode of the light-emitting element;

[0045] When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the nth reset time period and the end time of the nth preparation light-emitting stage is greater than the pre-charging time threshold.

[0046] Optionally, the nth light-emitting stage includes a first reset time period and a second reset time period set sequentially.

[0047] The first reset control signal generation circuit is further configured to provide a first reset control signal, such that during the nth first reset time period and the nth second reset time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first electrode of the light-emitting element;

[0048] When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the nth first reset time period and the end time of the nth preparation light-emitting stage is greater than the pre-charging time threshold.

[0049] In a third aspect, embodiments of this disclosure provide a display device, including a pixel circuit and the aforementioned driving module; the pixel circuit includes a driving circuit, a first light-emitting control circuit, a light-emitting element, and a first reset circuit;

[0050] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the first terminal of the driving circuit and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the first terminal of the driving circuit and the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0051] The first reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the first initial voltage terminal and the first electrode of the light-emitting element under the control of the first reset control signal provided by the first reset control terminal.

[0052] The driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential at its control terminal;

[0053] The second electrode of the light-emitting element is electrically connected to the first voltage terminal.

[0054] Optionally, the pixel circuit further includes a second reset circuit;

[0055] The second reset circuit is used to control the connection or disconnection between the second initial voltage terminal and the reset terminal of the drive circuit under the control of the second reset control signal provided by the second reset control terminal;

[0056] The reset terminal includes the first terminal of the driving circuit and / or the second terminal of the driving circuit.

[0057] Optionally, the pixel circuit further includes a second light-emitting control circuit;

[0058] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the second voltage terminal, and the second terminal of the driving circuit, respectively, and is used to control the connection or disconnection between the second voltage terminal and the second terminal of the driving circuit under the control of the light-emitting control signal.

[0059] Optionally, the pixel circuit further includes a third reset circuit, a compensation control circuit, a data writing circuit, and an energy storage circuit;

[0060] The third reset circuit is electrically connected to the third reset control terminal and the third initial voltage terminal respectively. The third reset circuit is also electrically connected to the first terminal or the control terminal of the driving circuit. The third reset circuit is used to control the writing of the third initial voltage provided by the third initial voltage terminal to the first terminal or the control terminal of the driving circuit under the control of the third reset control signal provided by the third reset control terminal.

[0061] The compensation control circuit is electrically connected to the first scanning end, the control end of the driving circuit, and the first end of the driving circuit, respectively, and is used to control the connection or disconnection between the control end of the driving circuit and the first end of the driving circuit under the control of the first scanning signal provided by the first scanning end.

[0062] The data writing circuit is electrically connected to the second scanning end, the data line and the second end of the driving circuit, respectively, and is used to control the connection or disconnection between the data line and the second end of the driving circuit under the control of the second scanning signal provided by the second scanning end;

[0063] The energy storage circuit is electrically connected to the control terminal of the drive circuit to maintain the potential of the control terminal of the drive circuit.

[0064] Optionally, the light-emitting element is a multilayer series light-emitting element. Attached Figure Description

[0065] Figure 1 is a structural diagram of at least one embodiment of the pixel circuit;

[0066] Figure 2 is a structural diagram of at least one embodiment of the pixel circuit;

[0067] Figure 3 is a structural diagram of at least one embodiment of the pixel circuit;

[0068] Figure 4 is a structural diagram of at least one embodiment of the pixel circuit;

[0069] Figure 5 is a structural diagram of at least one embodiment of the pixel circuit;

[0070] Figure 6 is a structural diagram of at least one embodiment of the pixel circuit;

[0071] Figure 7 is a structural diagram of at least one embodiment of the pixel circuit;

[0072] Figure 8 is a circuit diagram of at least one embodiment of the pixel circuit;

[0073] Figure 9 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 8;

[0074] Figure 10 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 8;

[0075] Figure 11 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 8;

[0076] Figure 12 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 8;

[0077] Figure 13 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 8;

[0078] Figure 14 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 8;

[0079] Figure 15 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0080] Figure 16 is a structural diagram of the drive module according to at least one embodiment of the present disclosure. Detailed Implementation

[0081] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0082] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0083] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0084] The driving method described in this embodiment is applied to a pixel circuit, which includes a driving circuit, a first light-emitting control circuit, a light-emitting element, and a first reset circuit. The first light-emitting control circuit, under the control of a light-emitting control signal provided by a light-emitting control terminal, controls the connection or disconnection between a first terminal of the driving circuit and a first electrode of the light-emitting element. The first reset circuit, under the control of a first reset control signal provided by a first reset control terminal, controls the connection or disconnection between a first initial voltage terminal and the first electrode of the light-emitting element. The second electrode of the light-emitting element is electrically connected to the first voltage terminal.

[0085] The display cycle includes N display sub-cycles. The nth display sub-cycle includes the nth preparation light-emitting stage and the nth light-emitting stage, which are set sequentially. N is an integer greater than 1, and n is a positive integer less than or equal to N. The nth preparation light-emitting stage includes at least one reset time period.

[0086] The driving method includes:

[0087] During the nth light-emitting stage, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the first terminal of the driving circuit to disconnect from the first electrode of the light-emitting element;

[0088] During the reset time period, under the control of the first reset control signal, the first reset circuit writes the first initial voltage provided by the first initial voltage terminal into the first electrode of the light-emitting element;

[0089] During at least a portion of the time period included in the nth luminescence stage, the first luminescence control circuit, under the control of the luminescence control signal, controls the first terminal of the driving circuit to connect with the first electrode of the luminescence element;

[0090] When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the first reset time period and the end time of the nth preparation light-emitting stage is set to be greater than the pre-charge time threshold during the nth preparation light-emitting stage.

[0091] In the driving method described in this embodiment, when the luminance of the light-emitting element is less than or equal to a luminance threshold during the display cycle, in the nth preparation light-emitting stage, the time interval between the start time of the first reset time period and the end time of the nth preparation light-emitting stage is set to be greater than the pre-charging time threshold, so as to increase the pre-charging time for pre-charging the first electrode of the light-emitting element with the first initial voltage, so that the light-emitting element can light up normally and improve the problem of ghosting.

[0092] In at least one embodiment of this disclosure,

[0093] During the nth light-emitting stage, the first light-emitting control circuit, under the control of the control signal, controls the first terminal of the driving circuit to disconnect from the first electrode of the light-emitting element, so as to control the light-emitting element not to emit light.

[0094] During at least a portion of the time period included in the nth luminescence stage, the first luminescence control circuit, under the control of the luminescence control signal, controls the first terminal of the driving circuit to connect with the first electrode of the luminescence element, so that the driving circuit can drive the luminescence element to emit light.

[0095] At least one embodiment of this disclosure can be applied to mobile phones, automotive display products, foldable display products, and large-size display products.

[0096] Optionally, the display period can be one frame.

[0097] Optionally, the pre-charge time threshold is greater than or equal to 20 lines of scan time but less than the duration of the nth preparation emission stage.

[0098] Optionally, the brightness threshold is less than or equal to 150 nits. For example, the brightness threshold can be 60 nits, 65 nits, 70 nits, 75 nits, 80 nits, 90 nits, 100 nits, 110 nits, or 120 nits, but is not limited thereto. In specific implementation, the brightness threshold can be selected according to the actual situation.

[0099] In at least one embodiment of this disclosure, the brightness threshold may be greater than or equal to 40 nits and less than or equal to 150 nits, but is not limited thereto.

[0100] In at least one embodiment of this disclosure, the light-emitting element can be a multilayer series light-emitting element, for example, the light-emitting element can be a double-layer series light-emitting element.

[0101] Optionally, the light-emitting element can be a tandem device. A tandem device is a series-connected light-emitting element. A tandem device is a high-efficiency OLED device structure formed by connecting and stacking multiple OLED (organic light-emitting diode) devices in series through a conductive layer.

[0102] As shown in Figure 1, L1 is a dual-layer OLED connected in series. L1 includes two OLEDs connected in series. The light-emitting layers of the two OLEDs connected in series each have capacitance. At low brightness / low grayscale, the equivalent internal resistance of L1 is large, close to the resistance of the short circuit of the conductive layer. This causes the current to pass through the first path LJ1, the second path LJ2, and the third path LJ3 simultaneously. The higher the proportion of the current flowing through the second path LJ2, the higher the brightness (the second path LJ2 is a micro-short circuit path and does not need to fill the capacitor. At this time, the current is large, resulting in high brightness). Since the green light-emitting element needs to fill the larger capacitor, the overshoot current of the green light-emitting element is the largest, and the brightness is the largest, resulting in a greenish tint.

[0103] In Figure 1, C1 is the first capacitor, C2 is the second capacitor, R1 is the first resistor, R2 is the second resistor, R3 is the third resistor, C3 is the third capacitor, and LC is the crosstalk OLED (the crosstalk OLED can be a green OLED).

[0104] LJ1 is the normal light-emitting path, LJ2 is the short-circuit path (the short-circuit path is the isolation trench micro-short-circuit path between the conductive layer of the two interconnected OLEDs and the cathode of L1), LJ3 is the crosstalk path, and LJ2 and LJ3 are abnormal light-emitting paths.

[0105] In Figure 1, the one labeled V1 is the power supply.

[0106] Based on the above problems, in at least one embodiment of this disclosure, when the luminous brightness of the light-emitting element is less than or equal to the brightness threshold during the display cycle, in the nth preparation light-emitting stage, the time interval between the start time of the first reset time period and the end time of the nth preparation light-emitting stage is set to be greater than the pre-charging time threshold. By increasing the pre-charging time of the first electrode of the light-emitting element, the normal light-emitting path can be lit up better, thus improving the problem of ghosting and brightening.

[0107] As shown in Figure 2, at least one embodiment of the pixel circuit includes a driving circuit 10, a first light-emitting control circuit 11, a light-emitting element E1, and a first reset circuit 12.

[0108] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the second terminal of the driving circuit 10 is electrically connected to the second node N2, and the first terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is used to generate a driving current to drive the light-emitting element E1 under the control of the potential of the first node N1.

[0109] The first light-emitting control circuit 11 is electrically connected to the light-emitting control terminal EM, the first terminal of the driving circuit 10 and the first pole of the light-emitting element E1, respectively, and is used to control the first terminal of the driving circuit 10 to connect or disconnect from the first pole of the light-emitting element E1 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0110] The first reset circuit 12 is electrically connected to the first reset control terminal RH, the first initial voltage terminal I1, and the first electrode of the light-emitting element E1, respectively. Under the control of the first reset control signal provided by the first reset control terminal RH, it controls the connection or disconnection between the first initial voltage terminal I1 and the first electrode of the light-emitting element E1. The first initial voltage terminal I1 is used to provide the first initial voltage Vinit1.

[0111] The second electrode of the light-emitting element E1 is electrically connected to the first voltage terminal V1;

[0112] Optionally, the first voltage terminal can be a low voltage terminal.

[0113] In at least one embodiment of this disclosure, the pixel circuit further includes a second reset circuit, which is configured to control the connection or disconnection between the second initial voltage terminal and the reset terminal of the driving circuit under the control of a second reset control signal provided by the second reset control terminal; the reset terminal includes a first terminal and / or a second terminal of the driving circuit; the driving method includes:

[0114] During the reset time period, under the control of the second reset control signal, the second reset circuit writes the second initial voltage provided by the second initial voltage terminal into the reset terminal of the drive circuit.

[0115] In a specific implementation, the pixel circuit may further include a second reset circuit. During the reset period, under the control of the second reset control signal, the second reset circuit writes the second initial voltage provided by the second initial voltage terminal into the reset terminal of the driving circuit. The reset terminal of the driving circuit includes the first terminal and / or the second terminal of the driving circuit, so as to improve the hysteresis phenomenon of the driving transistor included in the driving circuit and improve the image retention problem.

[0116] Optionally, the first reset control terminal and the second reset control terminal are the same control terminal to reduce the number of control terminals used.

[0117] As shown in Figure 3, based on at least one embodiment of the pixel circuit shown in Figure 2, the at least one embodiment of the pixel circuit may further include a second reset circuit 31.

[0118] The second reset circuit 31 is electrically connected to the second reset control terminal RC2, the second initial voltage terminal I2 and the second terminal of the drive circuit 10, respectively, and is used to control the connection or disconnection between the second initial voltage terminal I2 and the second terminal of the drive circuit 10 under the control of the second reset control signal provided by the second reset control terminal RC2.

[0119] The second initial voltage terminal I2 is used to provide the second initial voltage Vinit2.

[0120] As shown in Figure 4, based on at least one embodiment of the pixel circuit shown in Figure 2, the at least one embodiment of the pixel circuit may further include a second reset circuit 31.

[0121] The second reset circuit 31 is electrically connected to the second reset control terminal RC2, the second initial voltage terminal I2 and the first terminal of the drive circuit 10, respectively, and is used to control the connection or disconnection between the second initial voltage terminal I2 and the first terminal of the drive circuit 10 under the control of the second reset control signal provided by the second reset control terminal RC2.

[0122] The second initial voltage terminal I2 is used to provide the second initial voltage Vinit2.

[0123] In at least one embodiment of this disclosure, the pixel circuit further includes a second light-emitting control circuit, which is used to control the connection or disconnection between the second voltage terminal and the second terminal of the driving circuit under the control of the light-emitting control signal; the driving method includes:

[0124] During the nth light-emitting stage, the second light-emitting control circuit, under the control of the light-emitting control signal, controls the second voltage terminal to disconnect from the second terminal of the driving circuit;

[0125] During at least a portion of the time period included in the nth luminescence stage, the second luminescence control circuit, under the control of the luminescence control signal, controls the connection between the second voltage terminal and the second terminal of the driving circuit.

[0126] In a specific implementation, the pixel circuit may further include a second light-emitting control circuit. In the nth light-emitting preparation stage, under the control of the light-emitting control signal, the second light-emitting control circuit controls the second voltage terminal to disconnect from the second terminal of the driving circuit, thereby disconnecting the light-emitting path. During at least a portion of the time period included in the nth light-emitting stage, under the control of the light-emitting control signal, the second light-emitting control circuit controls the second voltage terminal to connect with the second terminal of the driving circuit, so that the driving circuit can drive the light-emitting element to emit light.

[0127] Optionally, the second voltage terminal can be a power supply voltage terminal.

[0128] As shown in Figure 5, based on at least one embodiment of the pixel circuit shown in Figure 3, the at least one embodiment of the pixel circuit further includes a second light-emitting control circuit 51.

[0129] The second light-emitting control circuit 51 is electrically connected to the light-emitting control terminal EM, the second voltage terminal V2, and the second terminal of the driving circuit 10, respectively, and is used to control the connection or disconnection between the second voltage terminal V2 and the second terminal of the driving circuit 10 under the control of the light-emitting control signal.

[0130] In at least one embodiment of this disclosure, the driving method includes:

[0131] In the nth light-emitting stage, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the first terminal of the driving circuit to connect with the first electrode of the light-emitting element, and the second light-emitting control circuit, under the control of the light-emitting control signal, controls the second voltage terminal to connect with the second terminal of the driving circuit.

[0132] In a specific implementation, during the nth luminescence stage, the first luminescence control circuit and the second luminescence control circuit turn on the luminescence path so that the driving circuit can drive the luminescence element to emit light.

[0133] Optionally, in the nth luminescence stage, the luminescence control signal is a PWM (Pulse Width Modulation) signal.

[0134] In a specific implementation, during the nth light-emitting stage, the light-emitting control signal can be a PWM signal, so that the number of pulses of the light-emitting control signal during the display cycle is not much different from that in related technologies.

[0135] In at least one embodiment of this disclosure, the nth light-emitting preparation stage includes an nth reset time period; the driving method includes:

[0136] During the nth reset time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first electrode of the light-emitting element;

[0137] When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the nth reset time period and the end time of the nth preparation light-emitting stage is set to be greater than the pre-charging time threshold.

[0138] In specific implementation, each light-emitting stage may include a reset time period. The nth light-emitting stage may include the nth reset time period. When the light-emitting brightness of the light-emitting element is less than or equal to the brightness threshold during the display cycle, the time interval between the start time of the nth reset time period and the end time of the nth light-emitting stage is greater than the pre-charging time threshold. This is to increase the pre-charging time of the first electrode of the light-emitting element during low-brightness display and improve the problem of ghosting and brightness.

[0139] In at least one embodiment of this disclosure, the nth light-emitting preparation stage includes an nth first reset time period and an nth second reset time period set sequentially; the driving method includes:

[0140] During the nth first reset time period and the nth second reset time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first electrode of the light-emitting element;

[0141] When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the nth first reset time period and the end time of the nth preparation luminous stage is set to be greater than the pre-charge time threshold.

[0142] In specific implementation, each light-emitting stage may include two reset time periods. The nth light-emitting stage may include a first reset time period and a second reset time period set sequentially. When the light-emitting brightness of the light-emitting element is less than or equal to the brightness threshold during the display cycle, the time interval between the start time of the nth first reset time period and the end time of the nth light-emitting stage is set to be greater than the pre-charging time threshold, and the number of times the first electrode of the light-emitting element is reset is increased. In low-brightness display, the pre-charging time of the first electrode of the light-emitting element is increased to improve the problem of ghosting and brightening.

[0143] In at least one embodiment of this disclosure, N is less than or equal to a threshold number of emission times.

[0144] In related technologies, N can be equal to 12. However, in at least one embodiment of this disclosure, reducing N can help to increase the pre-charging time of the first electrode of the light-emitting element before emitting light in each display sub-cycle. For example, N can be equal to 3, 4, or 6, but is not limited thereto.

[0145] Optionally, the threshold for the number of light emission events is less than 7.

[0146] As shown in Figure 6, based on at least one embodiment of the pixel circuit shown in Figure 5, the at least one embodiment of the pixel circuit may further include a compensation control circuit 61, a data writing circuit 62, a third reset circuit 63, and an energy storage circuit 60.

[0147] The compensation control circuit 61 is electrically connected to the first scanning terminal GN, the first node N1 and the third node N3 respectively, and is used to control the connection or disconnection between the first node N1 and the third node N3 under the control of the first scanning signal provided by the first scanning terminal GN.

[0148] The data writing circuit 62 is electrically connected to the second scanning terminal GP, the data line DL and the second node N2 respectively, and is used to write the data voltage provided by the data line DL into the second node N2 under the control of the second scanning signal provided by the second scanning terminal GP.

[0149] The third reset circuit 63 is electrically connected to the third reset control terminal RP, the third initial voltage terminal I3 and the third node N3 respectively, and is used to control the connection or disconnection between the third initial voltage terminal I3 and the third node N3 under the control of the third reset control signal provided by the third reset control terminal RP.

[0150] The energy storage circuit 60 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1.

[0151] As shown in Figure 7, based on at least one embodiment of the pixel circuit shown in Figure 5, the at least one embodiment of the pixel circuit may further include a compensation control circuit 61, a data writing circuit 62, a third reset circuit 63, and an energy storage circuit 60.

[0152] The compensation control circuit 61 is electrically connected to the first scanning terminal GN, the first node N1 and the third node N3 respectively, and is used to control the connection or disconnection between the first node N1 and the third node N3 under the control of the first scanning signal provided by the first scanning terminal GN.

[0153] The data writing circuit 62 is electrically connected to the second scanning terminal GP, the data line DL and the second node N2 respectively, and is used to write the data voltage provided by the data line DL into the second node N2 under the control of the second scanning signal provided by the second scanning terminal GP.

[0154] The third reset circuit 63 is electrically connected to the third reset control terminal RP, the third initial voltage terminal I3 and the first node N1 respectively, and is used to control the connection or disconnection between the third initial voltage terminal I3 and the first node N1 under the control of the third reset control signal provided by the third reset control terminal RP.

[0155] The energy storage circuit 60 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1.

[0156] As shown in Figure 8, based on at least one embodiment of the pixel circuit shown in Figure 6, the driving circuit includes a driving transistor T0, the first reset circuit includes a first transistor T1, the first light-emitting control circuit includes a second transistor T2, the second reset circuit includes a third transistor T3, the second light-emitting control circuit includes a fourth transistor T4, the compensation control circuit includes a fifth transistor T5, the data writing circuit includes a sixth transistor T6, the third reset circuit includes a seventh transistor T7, the energy storage circuit includes a storage capacitor Cst, and the light-emitting element is a double-layer series organic light-emitting diode O1.

[0157] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0158] The gate of T1 is electrically connected to the first reset control terminal RH, the source of T1 is electrically connected to the first initial voltage terminal I1, the drain of T1 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS; the first initial voltage terminal I1 is used to provide the first initial voltage Vinit1.

[0159] The gate of T2 is electrically connected to the light-emitting control terminal EM, the source of T2 is electrically connected to the third node N3, and the drain of T2 is electrically connected to the anode of O1.

[0160] The gate of T3 is electrically connected to the first reset control terminal RH, the source of T3 is electrically connected to the second initial voltage terminal I2, and the drain of T3 is electrically connected to the second node N2; the second initial voltage terminal I2 is used to provide the second initial voltage Vinit2;

[0161] The gate of T4 is electrically connected to the light-emitting control terminal EM, the source of T4 is electrically connected to the power supply voltage terminal VDD, and the drain of T4 is electrically connected to the second node N2.

[0162] The gate of T5 is electrically connected to the first scan terminal GN, the source of T5 is electrically connected to the first node N1, and the drain of T5 is electrically connected to the third node N3.

[0163] The gate of T6 is electrically connected to the second scan terminal GP, the source of T6 is electrically connected to the data line DL, and the drain of T6 is electrically connected to the second node N2.

[0164] The gate of T7 is electrically connected to the third reset control terminal RP, the source of T7 is electrically connected to the third initial voltage terminal I3, and the drain of T7 is electrically connected to the third node N3.

[0165] The first terminal of Cst is electrically connected to the first node N1, and the second terminal of Cst is electrically connected to the power supply voltage terminal VDD.

[0166] In at least one embodiment of the pixel circuit shown in Figure 8, T5 is an n-type transistor, and T0, T1, T2, T3, T4, T6 and T7 are all p-type transistors. The pixel circuit is an LTPO (Low Temperature Polycrystalline Oxide) pixel circuit.

[0167] In at least one embodiment shown in Figure 8, the first reset control terminal and the second reset control terminal are the same control terminal, the first voltage terminal can be a low voltage terminal, and the second voltage terminal can be a power supply voltage terminal.

[0168] When at least one embodiment of the pixel circuit shown in Figure 8 is in operation, one frame time may include three display sub-cycles, and each display sub-cycle may include a preparation light-emitting stage and a light-emitting stage set sequentially.

[0169] As shown in Figure 9, the first display sub-cycle includes a first pre-light-emitting stage SZ1 and a first light-emitting stage SE1 set sequentially; the first pre-light-emitting stage SZ1 includes a first reset time period SR1;

[0170] During the first reset time period SR1, RH provides a low voltage signal, T1 and T3 are turned on, I1 provides a first initial voltage Vinit1 to the anode of O1 to clear the residual charge on the anode of O1 and precharge the anode of O1, and I2 provides a second initial voltage Vinit2 to N2 to improve the hysteresis phenomenon of T0 and improve the afterimage.

[0171] In the first pre-light-emitting stage SZ1, EM provides a high voltage signal, T2 and T4 are turned off, VDD is disconnected from N2, and N3 is disconnected from the anode of O1, thus disconnecting the light-emitting path;

[0172] In the first light-emitting stage SE1, EM provides a low voltage signal, T2 and T4 are turned on, VDD is connected to N2, and N3 is connected to the anode of O1, so that T0 can drive O1 to emit light;

[0173] During this frame time, the luminance of O1 is less than or equal to 75 nits. The time interval between the start time of the first reset time period SR1 and the end time of the first light-up preparation stage SZ1 is set to 895H. This is to increase the pre-charging time of the anode of O1 before the first light-up stage SE1, increase the lighting speed of the first path, increase the light emission of the normal display path, thereby reducing the influence of abnormal display paths (abnormal display paths include the second and third paths) and improving the problem of ghosting and brightening. Here, 1H is the scanning time of one line.

[0174] As shown in Figure 9, the duration of the first light-emitting stage SZ1 is 916H, the duration of the first reset time period SR1 is 4H, the duration of the first light-emitting stage SE1 is 92H, and the time interval between the start time of the first light-emitting stage SZ1 and the start time of the first reset time period SR1 is 21H.

[0175] As shown in Figure 10, when at least one embodiment of the pixel circuit shown in Figure 8 is working, the first light-emitting stage SZ1 may include a first initialization time period SC1 and a first write time period SX1 set sequentially, and the first reset time period SR1 may be set after the first write time period SX1.

[0176] During the first initialization period SC1, EM provides a high voltage signal, GN provides a high voltage signal, RP provides a low voltage signal, GP provides a high voltage signal, RH provides a high voltage signal, T5 is turned on, T7 is turned on, and I3 provides a third initial voltage Vinit3 to N1 so that T0 can be turned on when the first write period SX1 begins.

[0177] During the first write time period SX1, EM provides a high voltage signal, GN provides a high voltage signal, RP provides a high voltage signal, GP provides a low voltage signal, RH provides a high voltage signal, T5 is enabled, T6 is enabled, and DL provides the data voltage Vdata to N2;

[0178] At the start of the first write time period SX1, T0 is turned on, and Vdata charges Cst through T6, T0 and T5, changing the potential of N1 until the potential of N1 becomes Vdata+Vth, at which point T0 is turned off to perform data voltage writing and threshold voltage compensation; where Vth is the threshold voltage of T0.

[0179] During the first reset period SR1, EM provides a high voltage signal, GN provides a low voltage signal, RP provides a high voltage signal, GP provides a high voltage signal, RH provides a low voltage signal, T1 and T3 are turned on, and T2, T4, T5, T6 and T7 are all turned off.

[0180] As shown in Figure 11, when at least one embodiment of the pixel circuit shown in Figure 8 is working, one frame time may include a first display sub-cycle F1, a second display sub-cycle F2, and a third display sub-cycle F3 set sequentially; the first display sub-cycle F1 includes a first pre-light emission stage SZ1 and a first light emission stage SE1, the second display sub-cycle F2 includes a second pre-light emission stage SZ2 and a second light emission stage SE2, and the third display sub-cycle F3 includes a third pre-light emission stage SZ3 and a third light emission stage SE3;

[0181] The first pre-light emission stage SZ1 includes a first reset time period SR1, the second pre-light emission stage SZ2 includes a second reset time period SR2, and the third pre-light emission stage SZ3 includes a third reset time period SR3.

[0182] In the first pre-light emission stage SZ1, the second pre-light emission stage SZ2, and the third pre-light emission stage SZ3, EM provides a high voltage signal, T2 and T4 are turned off, VDD is disconnected from N2, and N3 is disconnected from the anode of O1.

[0183] In the first light-emitting stage SE1, the second light-emitting stage SE2, and the third light-emitting stage SE3, EM provides a low voltage signal, T2 and T4 are turned on, VDD is connected to N2, and N3 is connected to the anode of O1.

[0184] During the first reset time period SR1, the second reset time period SR2, and the third reset time period SR3, RH provides a low voltage signal, T1 and T3 are turned on, I1 provides the first initial voltage Vinit1 to the anode of O1 to clear the residual charge on the anode of O1 and precharge the anode of O1, and I2 provides the second initial voltage Vinit2 to N2 to improve the hysteresis phenomenon of T0 and improve the afterimage.

[0185] During this frame time, the luminance of O1 is less than or equal to 75 nits. The time interval between the start time of the first reset time period SR1 and the end time of the first pre-light-up phase SZ1 is set to 895H. This increases the pre-charging time of the anode of O1 before the first light-up phase SE1, thereby increasing the start-up speed of the first path and increasing the luminance of the normal display path. The time interval between the start time of the second reset time period SR2 and the end time of the second pre-light-up phase SZ2 is also set to 895H. This increases the time for pre-charging the anode of O1 before the second light-up phase SE2. The pre-charging time of the anode of O1 is increased to improve the start-up speed of the first path and increase the light emission of the normal display path. The time interval between the start time of the third reset time period SR3 and the end time of the third light emission preparation stage SZ3 is set to 895H. This is to increase the pre-charging time of the anode of O1 before the third light emission stage SE3, thereby increasing the start-up speed of the first path and increasing the light emission of the normal display path. This reduces the influence of abnormal display paths (abnormal display paths include the second and third paths) and improves the problem of ghosting and brightening. Here, 1H is the scan time of one line.

[0186] In at least one embodiment of the pixel circuit shown in Figure 8, during operation, data writing and threshold voltage compensation may not be performed in the second and third pre-light-emitting stages, and T1 and T3 are controlled to be turned on during the corresponding reset time periods.

[0187] As shown in Figure 11, the duration of the first light-emitting stage SZ1 is 916H, the duration of the first reset time period SR1 is 4H, the duration of the first light-emitting stage SE1 is 92H, and the time interval between the start time of the first light-emitting stage SZ1 and the start time of the first reset time period SR1 is 21H.

[0188] The duration of the second pre-light-emitting phase SZ2 is 916H, the duration of the second reset time period SR2 is 4H, the duration of the second light-emitting phase SE2 is 92H, and the time interval between the start time of the second pre-light-emitting phase SZ2 and the start time of the second reset time period SR2 is 21H.

[0189] The duration of the third pre-light-emitting stage SZ3 is 916H, the duration of the third reset time period SR3 is H, the duration of the third light-emitting stage SE3 is 92H, and the time interval between the start time of the third pre-light-emitting stage SZ3 and the start time of the third reset time period SR3 is 21H.

[0190] The duration of the first display sub-cycle can be 1008 hours, the duration of the second display sub-cycle can be 1008 hours, and the duration of the third display sub-cycle can be 1008 hours.

[0191] In at least one embodiment shown in Figure 11, a frame time is set to include three display sub-cycles (in related art, a frame time includes twelve display sub-cycles) to facilitate increasing the time for pre-charging the anode of O1 before each light emission stage, thereby improving the problem of ghosting and brightening.

[0192] When at least one embodiment of the pixel circuit shown in Figure 8 is in operation, one frame time may include three display sub-cycles, and each display sub-cycle may include a preparation light-emitting stage and a light-emitting stage set sequentially.

[0193] As shown in Figure 12, the first display sub-cycle includes a first pre-light-emitting stage SZ1 and a first light-emitting stage SE1 set sequentially; the first pre-light-emitting stage SZ1 includes a first reset time period SR1.

[0194] During the first reset time period SR1, RH provides a low voltage signal, T1 and T3 are turned on, I1 provides a first initial voltage Vinit1 to the anode of O1 to clear the residual charge on the anode of O1 and precharge the anode of O1, and I2 provides a second initial voltage Vinit2 to N2 to improve the hysteresis phenomenon of T0 and improve the afterimage.

[0195] In the first pre-light-emitting stage SZ1, EM provides a high voltage signal, T2 and T4 are turned off, VDD is disconnected from N2, and N3 is disconnected from the anode of O1, thus disconnecting the light-emitting path;

[0196] During this frame time, the luminance of O1 is less than or equal to 75 nits. The time interval between the start time of the first reset time period SR1 and the end time of the first light-up preparation stage SZ1 is set to 895H. This increases the pre-charging time of the anode of O1 before the first light-up stage SE1, thereby increasing the start-up speed of the first path, increasing the light emission of the normal display path, and reducing the influence of abnormal display paths (abnormal display paths include the second and third paths), thus improving the problem of ghosting and brightening. Here, 1H is the scan time of one line.

[0197] In the first light-emitting stage SE1, the light-emitting control signal provided by EM is a PWM signal;

[0198] The first luminous phase SE1 includes the first luminous time period SF1, the first interval time period SJ1, the second luminous time period SF2, the second interval time period SJ2, the third luminous time period SF3, the third interval time period SJ3, and the fourth luminous time period SF4, which are set sequentially.

[0199] During the first emission period SF1, the second emission period SF2, the third emission period SF3, and the fourth emission period SF4, EM provides a low voltage signal, T2 and T4 are turned on, VDD is connected to N2, and N3 is connected to the anode of O1 to conduct the emission path.

[0200] During the first time interval SJ1, the second time interval SJ2, and the third time interval SJ3, EM provides a high voltage signal, T2 and T4 are turned off, VDD is disconnected from N2, and N3 is disconnected from the anode of O1, thus disconnecting the light-emitting path.

[0201] The duration of the first luminescence period SF1 is 42 hours, the duration of the second luminescence period SF2 and the duration of the third luminescence period SF3 are both 4 hours, the duration of the fourth luminescence period SF4 is 30 hours, the duration of the first interval period SJ1 is 20 hours, the duration of the second interval period SJ2 and the duration of the third interval period SJ3 are both 4 hours.

[0202] The duration of the first reset time period SR1 is 4 hours, and the time interval between the start time of the first light-emitting stage SZ1 and the start time of the first reset time period SR1 is 21 hours.

[0203] In at least one embodiment of the pixel circuit shown in Figure 8, the operation process of the pixel circuit in the second and third display sub-cycles can be the same as that in the first display sub-cycle.

[0204] As shown in Figure 12, at least one embodiment of the pixel circuit shown in Figure 8 can ensure that the duty cycle of the light emission control signal is the same as that in related technologies by setting the light emission control signal to a PWM signal in each light emission stage.

[0205] In Figures 12 and 13, to clearly illustrate the various time periods included in the luminescence stage, the duration of each pre-luminescence stage is drawn as relatively short. In reality, the duration of each pre-luminescence stage is much longer.

[0206] When at least one embodiment of the pixel circuit shown in Figure 8 is in operation, one frame time may include three display sub-cycles, and each display sub-cycle may include a preparation light-emitting stage and a light-emitting stage set sequentially.

[0207] As shown in Figure 13, the first display sub-cycle includes a first pre-light-emitting stage SZ1 and a first light-emitting stage SE1 set sequentially; the first pre-light-emitting stage SZ1 includes a first first reset time period SR11 and a first second reset time period SR12;

[0208] During the first reset time period SR11 and the first reset time period SR12, RH provides a low voltage signal, T1 and T3 are turned on, I1 provides a first initial voltage Vinit1 to the anode of O1 to clear the residual charge on the anode of O1 and precharge the anode of O1, and I2 provides a second initial voltage Vinit2 to N2 to improve the hysteresis phenomenon of T0 and improve the afterimage.

[0209] In the first pre-light-emitting stage SZ1, EM provides a high voltage signal, T2 and T4 are turned off, VDD is disconnected from N2, and N3 is disconnected from the anode of O1, thus disconnecting the light-emitting path;

[0210] Within this frame time, the luminance of O1 is less than or equal to 75 nits. The time interval between the start time of the first reset time interval SR11 and the end time of the first pre-light emission stage SZ1 is set to 879H. This increases the pre-charging time of the anode of O1 before the first light emission stage SE1, thereby increasing the start-up speed of the first path, increasing the light emission of the normal display path, and reducing the influence of abnormal display paths (including the second and third paths), thus improving the problem of ghosting and brightening. Here, 1H is the scan time of one line. Furthermore, by increasing the number of reset time intervals included in each pre-light emission stage, the number of times the anode of O1 is reset is increased, which helps to strengthen the pre-charging and reset effect of the anode of O1.

[0211] In the first light-emitting stage SE1, the light-emitting control signal provided by EM is a PWM signal;

[0212] The first luminous phase SE1 includes the first luminous time period SF1, the first interval time period SJ1, the second luminous time period SF2, the second interval time period SJ2, the third luminous time period SF3, the third interval time period SJ3, and the fourth luminous time period SF4, which are set sequentially.

[0213] During the first emission period SF1, the second emission period SF2, the third emission period SF3, and the fourth emission period SF4, EM provides a low voltage signal, T2 and T4 are turned on, VDD is connected to N2, and N3 is connected to the anode of O1 to conduct the emission path.

[0214] During the first time interval SJ1, the second time interval SJ2, and the third time interval SJ3, EM provides a high voltage signal, T2 and T4 are turned off, VDD is disconnected from N2, and N3 is disconnected from the anode of O1, thus disconnecting the light-emitting path.

[0215] The duration of the first luminescence period SF1 is 42 hours, the duration of the second luminescence period SF2 and the duration of the third luminescence period SF3 are both 4 hours, the duration of the fourth luminescence period SF4 is 30 hours, the duration of the first interval period SJ1 is 20 hours, the duration of the second interval period SJ2 and the duration of the third interval period SJ3 are both 4 hours.

[0216] The duration of the first reset time period SR11 and the duration of the first reset time period SR12 are 4 hours. The time interval between the start time of the first light-up preparation stage SZ1 and the start time of the first reset time period SR11 is 21 hours. The time interval between the end time of the first reset time period SR12 and the end time of SZ1 is 7 hours. The duration of the first light-up preparation stage SZ1 is 900 hours. The duration of the first display sub-cycle is 1008 hours.

[0217] In at least one embodiment of the pixel circuit shown in Figure 8, the operation process of the pixel circuit in the second and third display sub-cycles can be the same as that in the first display sub-cycle.

[0218] When at least one embodiment of the pixel circuit shown in Figure 8 is in operation, one frame time may include twelve display sub-cycles, and each display sub-cycle may include a preparation light-emitting stage and a light-emitting stage set sequentially.

[0219] Figure 14 shows the first display sub-cycle F1, the second display sub-cycle F2, the third display sub-cycle F3, and the fourth display sub-cycle F4 included in one frame time; the first display sub-cycle includes a first pre-light emission stage SZ1 and a first light emission stage SE1 set sequentially, the second display sub-cycle includes a second pre-light emission stage SZ2 and a second light emission stage SE2 set sequentially, the third display sub-cycle includes a third pre-light emission stage SZ3 and a third light emission stage SE3 set sequentially, and the fourth display sub-cycle includes a fourth pre-light emission stage SZ4 and a fourth light emission stage SE4 set sequentially.

[0220] The first pre-light emission stage SZ1 includes a first reset time period SR1, the second pre-light emission stage SZ2 includes a second reset time period SR2, the third pre-light emission stage SZ3 includes a third reset time period SR3, and the fourth pre-light emission stage SZ4 includes a fourth reset time period SR4.

[0221] During the first reset time period SR1, the second reset time period SR2, the third reset time period SR3, and the fourth reset time period SR4, RH provides a low voltage signal, T1 and T3 are turned on, I1 provides the first initial voltage Vinit1 to the anode of O1 to clear the residual charge on the anode of O1 and precharge the anode of O1, and I2 provides the second initial voltage Vinit2 to N2 to improve the hysteresis phenomenon of T0 and improve the afterimage.

[0222] In the first pre-light emission stage SZ1, the second pre-light emission stage SZ2, the third pre-light emission stage SZ3, and the fourth pre-light emission stage SZ4, EM provides a high voltage signal, T2 and T4 are turned off, VDD is disconnected from N2, and N3 is disconnected from the anode of O1, thus disconnecting the light emission path.

[0223] During this frame time, the luminance of O1 is less than or equal to 75 nits. The time interval between the start time of the first reset time period SR1 and the end time of the first pre-light emission stage SZ1 is set to 225H. The time interval between the start time of the second reset time period SR2 and the end time of the second pre-light emission stage SZ2 is set to 225H. The time interval between the start time of the third reset time period SR3 and the end time of the third pre-light emission stage SZ3 is set to 225H. The time interval between the start time of the fourth reset time period SR4 and the end time of the fourth pre-light emission stage SZ4 is set to 225H. This is to increase the luminance of O1 before the first light emission stage SE1. The pre-charging time of the anode of O1 is increased before the second light-emitting stage SE2, before the third light-emitting stage SE3, and before the fourth light-emitting stage SE4. This increases the lighting speed of the first path, increases the light emission of the normal display path, thereby reducing the influence of abnormal display paths (abnormal display paths include the second and third paths) and improving the problem of ghosting. Here, 1H is the scan time of one line. By increasing the number of reset time periods included in each light-emitting stage, the number of times the anode of O1 is reset is increased, which helps to strengthen the pre-charging and reset effect of the anode of O1.

[0224] The time interval between the start time of the first pre-light emission stage SZ1 and the start time of the first reset time period SR1 is 21H; the time interval between the start time of the second pre-light emission stage SZ2 and the start time of the second reset time period SR2 is 21H; the time interval between the start time of the third pre-light emission stage SZ3 and the start time of the third reset time period SR3 is 21H; and the time interval between the start time of the fourth pre-light emission stage SZ4 and the start time of the fourth reset time period SR4 is 21H.

[0225] The duration of the first reset time period SR1, the duration of the second reset time period SR2, the duration of the third reset time period SR3, and the duration of the fourth reset time period SR4 can all be 4 hours.

[0226] The duration of the first luminescence stage SE1, the second luminescence stage SE2, the third luminescence stage SE3, and the fourth luminescence stage SE4 can all be 16 hours.

[0227] In at least one embodiment of the pixel circuit shown in Figure 8, the operation process of the pixel circuit in the fifth to twelfth display sub-cycles can be the same as that in the first display sub-cycle.

[0228] The driving module described in this embodiment is applied to a pixel circuit, which includes a driving circuit, a first light-emitting control circuit, a light-emitting element, and a first reset circuit. The first light-emitting control circuit, under the control of a light-emitting control signal provided by a light-emitting control terminal, controls the connection or disconnection between the first terminal of the driving circuit and the first electrode of the light-emitting element. The first reset circuit, under the control of a first reset control signal provided by a first reset control terminal, controls the connection or disconnection between the first initial voltage terminal and the first electrode of the light-emitting element. The second electrode of the light-emitting element is electrically connected to the first voltage terminal. The display cycle includes N display sub-cycles, where the nth display sub-cycle includes a sequentially set nth pre-light-emitting stage and an nth light-emitting stage, where N is an integer greater than 1 and n is a positive integer less than or equal to N. The nth pre-light-emitting stage includes at least one reset time period.

[0229] As shown in Figure 15, the driving module includes a light emission control signal generation circuit 151 and a first reset control signal generation circuit 152.

[0230] The light emission control signal generation circuit 151 is electrically connected to the light emission control terminal EM and is used to provide the light emission control signal to the light emission control terminal EM, so that in the nth light emission preparation stage, the first light emission control circuit controls the first terminal of the driving circuit to disconnect from the first electrode of the light emission element under the control of the light emission control signal, and controls the first terminal of the driving circuit to connect with the first electrode of the light emission element under the control of the light emission control signal during at least a part of the time period included in the nth light emission stage.

[0231] The first reset control signal generation circuit 152 is electrically connected to the first reset control terminal RH and is used to provide the first reset control signal to the first reset control terminal RH so that during the reset time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage provided by the first initial voltage terminal into the first pole of the light-emitting element.

[0232] When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the first reset time period and the end time of the nth preparation light-emitting stage is greater than the pre-charge time threshold during the nth preparation light-emitting stage.

[0233] In this embodiment of the disclosure, when the luminance of the light-emitting element is less than or equal to a luminance threshold during the display cycle, the time interval between the start time of the first reset time period and the end time of the nth preparation light-emitting stage is greater than a pre-charging time threshold, so as to increase the pre-charging time for pre-charging the first electrode of the light-emitting element with the first initial voltage, so that the light-emitting element can light up normally and improve the problem of ghosting.

[0234] Optionally, the pre-charge time threshold is greater than or equal to 20 lines of scan time but less than the duration of the nth preparation emission stage.

[0235] Optionally, the brightness threshold is less than or equal to 150 nits.

[0236] Furthermore, the brightness threshold may be greater than or equal to 40 nits and less than or equal to 150 nits, but is not limited thereto.

[0237] In at least one embodiment of this disclosure, the pixel circuit further includes a second reset circuit, which is used to control the connection or disconnection between the second initial voltage terminal and the reset terminal of the driving circuit under the control of a second reset control signal provided by the second reset control terminal; the reset terminal includes a first terminal of the driving circuit and / or a second terminal of the driving circuit;

[0238] As shown in Figure 16, based on at least one embodiment shown in Figure 15, the drive module further includes a second reset control signal generation circuit 161;

[0239] The second reset control signal generation circuit 161 is electrically connected to the second reset control terminal RC2 and is used to provide a second reset control signal to the second reset control terminal RC2, so that during the reset time period, the second reset circuit, under the control of the second reset control signal, writes the second initial voltage provided by the second initial voltage terminal into the reset terminal of the drive circuit.

[0240] In a specific implementation, the pixel circuit may further include a second reset circuit. During the reset period, under the control of the second reset control signal, the second reset circuit writes the second initial voltage provided by the second initial voltage terminal into the reset terminal of the driving circuit. The reset terminal of the driving circuit includes the first terminal and / or the second terminal of the driving circuit, so as to improve the hysteresis phenomenon of the driving transistor included in the driving circuit and improve the image retention problem.

[0241] Optionally, the first reset control terminal and the second reset control terminal are the same control terminal to reduce the number of control terminals used.

[0242] In at least one embodiment of this disclosure, the pixel circuit further includes a second light-emitting control circuit, which is used to control the connection or disconnection between the second voltage terminal and the second terminal of the driving circuit under the control of the light-emitting control signal.

[0243] The light emission control signal generation circuit is further configured to, by providing the light emission control signal, cause the second light emission control circuit, under the control of the light emission control signal, to disconnect the second voltage terminal from the second terminal of the driving circuit, and cause the second light emission control circuit, under the control of the light emission control signal, to connect the second voltage terminal to the second terminal of the driving circuit during at least a portion of the time period included in the nth light emission stage.

[0244] In at least one embodiment of this disclosure, the light emission control signal generation circuit is further configured to provide the light emission control signal such that, in the nth light emission stage, the first light emission control circuit controls the first terminal of the driving circuit to connect with the first electrode of the light emission element under the control of the light emission control signal, and the second light emission control circuit controls the second voltage terminal to connect with the second terminal of the driving circuit under the control of the light emission control signal.

[0245] In at least one embodiment of this disclosure, the light emission control signal generation circuit is further configured to control the light emission control signal to be a PWM signal during the nth light emission stage.

[0246] In at least one embodiment of this disclosure, the nth light-emitting preparation stage includes an nth reset time period;

[0247] The first reset control signal generation circuit is further configured to provide a first reset control signal, such that during the nth reset time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first electrode of the light-emitting element;

[0248] When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the nth reset time period and the end time of the nth preparation light-emitting stage is greater than the pre-charging time threshold.

[0249] In at least one embodiment of this disclosure, the nth light-emitting stage includes an nth first reset time period and an nth second reset time period set sequentially.

[0250] The first reset control signal generation circuit is further configured to provide a first reset control signal, such that during the nth first reset time period and the nth second reset time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first electrode of the light-emitting element;

[0251] When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the nth first reset time period and the end time of the nth preparation light-emitting stage is greater than the pre-charging time threshold.

[0252] The display device described in this embodiment includes a pixel circuit and the aforementioned driving module; the pixel circuit includes a driving circuit, a first light-emitting control circuit, a light-emitting element, and a first reset circuit;

[0253] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the first terminal of the driving circuit and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the first terminal of the driving circuit and the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0254] The first reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the first initial voltage terminal and the first electrode of the light-emitting element under the control of the first reset control signal provided by the first reset control terminal.

[0255] The driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential at its control terminal;

[0256] The second electrode of the light-emitting element is electrically connected to the first voltage terminal.

[0257] In at least one embodiment of this disclosure, the pixel circuit further includes a second reset circuit;

[0258] The second reset circuit is used to control the connection or disconnection between the second initial voltage terminal and the reset terminal of the drive circuit under the control of the second reset control signal provided by the second reset control terminal;

[0259] The reset terminal includes the first terminal of the driving circuit and / or the second terminal of the driving circuit;

[0260] In at least one embodiment of this disclosure, the pixel circuit further includes a second light-emitting control circuit;

[0261] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the second voltage terminal, and the second terminal of the driving circuit, respectively, and is used to control the connection or disconnection between the second voltage terminal and the second terminal of the driving circuit under the control of the light-emitting control signal.

[0262] In at least one embodiment of this disclosure, the pixel circuit further includes a third reset circuit, a compensation control circuit, a data writing circuit, and an energy storage circuit;

[0263] The third reset circuit is electrically connected to the third reset control terminal and the third initial voltage terminal respectively. The third reset circuit is also electrically connected to the first terminal or the control terminal of the driving circuit. The third reset circuit is used to control the writing of the third initial voltage provided by the third initial voltage terminal to the first terminal or the control terminal of the driving circuit under the control of the third reset control signal provided by the third reset control terminal.

[0264] The compensation control circuit is electrically connected to the first scanning end, the control end of the driving circuit, and the first end of the driving circuit, respectively, and is used to control the connection or disconnection between the control end of the driving circuit and the first end of the driving circuit under the control of the first scanning signal provided by the first scanning end.

[0265] The data writing circuit is electrically connected to the second scanning end, the data line and the second end of the driving circuit, respectively, and is used to control the connection or disconnection between the data line and the second end of the driving circuit under the control of the second scanning signal provided by the second scanning end;

[0266] The energy storage circuit is electrically connected to the control terminal of the drive circuit to maintain the potential of the control terminal of the drive circuit.

[0267] Optionally, the light-emitting element can be a multi-layer series light-emitting element, for example, the light-emitting element can be a double-layer series light-emitting element.

[0268] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A driving method applied to a pixel circuit, the pixel circuit comprising a driving circuit, a first light-emitting control circuit, a light-emitting element, and a first reset circuit; the first light-emitting control circuit is used to control the connection or disconnection between a first terminal of the driving circuit and a first electrode of the light-emitting element under the control of a light-emitting control signal provided by a light-emitting control terminal; the first reset circuit is used to control the connection or disconnection between a first initial voltage terminal and a first electrode of the light-emitting element under the control of a first reset control signal provided by a first reset control terminal; the second electrode of the light-emitting element is electrically connected to the first voltage terminal; the display cycle comprises N display sub-cycles, the nth display sub-cycle comprising a nth pre-light-emitting stage and an nth light-emitting stage set sequentially, where N is an integer greater than 1 and n is a positive integer less than or equal to N; The nth light-emitting preparation stage includes at least one reset time period; the driving method includes: During the nth light-emitting stage, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the first terminal of the driving circuit to disconnect from the first electrode of the light-emitting element; During the reset time period, under the control of the first reset control signal, the first reset circuit writes the first initial voltage provided by the first initial voltage terminal into the first electrode of the light-emitting element; During at least a portion of the time period included in the nth luminescence stage, the first luminescence control circuit, under the control of the luminescence control signal, controls the first terminal of the driving circuit to connect with the first electrode of the luminescence element; When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the first reset time period and the end time of the nth preparation light-emitting stage is set to be greater than the pre-charge time threshold during the nth preparation light-emitting stage.

2. The driving method as described in claim 1, wherein, The pre-charging time threshold is greater than or equal to 20 lines of scan time but less than the duration of the nth preparation emission stage.

3. The driving method as described in claim 1, wherein, The brightness threshold is less than or equal to 150 nits.

4. The driving method as described in claim 1, wherein, The pixel circuit further includes a second reset circuit, which, under the control of a second reset control signal provided by the second reset control terminal, controls the connection or disconnection between the second initial voltage terminal and the reset terminal of the driving circuit; the reset terminal includes a first terminal and / or a second terminal of the driving circuit; the driving method includes: During the reset time period, under the control of the second reset control signal, the second reset circuit writes the second initial voltage provided by the second initial voltage terminal into the reset terminal of the drive circuit.

5. The driving method as described in claim 4, wherein, The first reset control terminal and the second reset control terminal are the same control terminal.

6. The driving method as described in claim 4, wherein, The pixel circuit further includes a second light-emitting control circuit, which, under the control of the light-emitting control signal, controls the connection or disconnection between the second voltage terminal and the second terminal of the driving circuit; the driving method includes: During the nth light-emitting stage, the second light-emitting control circuit, under the control of the light-emitting control signal, controls the second voltage terminal to disconnect from the second terminal of the driving circuit; During at least a portion of the time period included in the nth luminescence stage, the second luminescence control circuit, under the control of the luminescence control signal, controls the connection between the second voltage terminal and the second terminal of the driving circuit.

7. The driving method as described in claim 6, wherein, The driving method includes: In the nth light-emitting stage, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the first terminal of the driving circuit to connect with the first electrode of the light-emitting element, and the second light-emitting control circuit, under the control of the light-emitting control signal, controls the second voltage terminal to connect with the second terminal of the driving circuit.

8. The driving method as described in claim 6, wherein, In the nth luminescence stage, the luminescence control signal is a PWM signal.

9. The driving method according to any one of claims 6 to 8, wherein, The nth light-emitting preparation stage includes an nth reset time period; the driving method includes: During the nth reset time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first electrode of the light-emitting element; When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the nth reset time period and the end time of the nth preparation light-emitting stage is set to be greater than the pre-charging time threshold.

10. The driving method according to any one of claims 6 to 8, wherein, The nth light-emitting preparation stage includes a first reset time period and an nth second reset time period set sequentially; the driving method includes: During the nth first reset time period and the nth second reset time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first electrode of the light-emitting element; When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the nth first reset time period and the end time of the nth preparation luminous stage is set to be greater than the pre-charge time threshold.

11. The driving method according to any one of claims 1 to 8, wherein, N is less than or equal to the threshold number of light emission times.

12. The driving method as described in claim 11, wherein, The threshold for the number of light emission events is less than 7.

13. A driving module applied to a pixel circuit, the pixel circuit comprising a driving circuit, a first light-emitting control circuit, a light-emitting element, and a first reset circuit; the first light-emitting control circuit is used to control the connection or disconnection between a first terminal of the driving circuit and a first electrode of the light-emitting element under the control of a light-emitting control signal provided by a light-emitting control terminal; the first reset circuit is used to control the connection or disconnection between a first initial voltage terminal and a first electrode of the light-emitting element under the control of a first reset control signal provided by a first reset control terminal; the second electrode of the light-emitting element is electrically connected to the first voltage terminal; the display cycle includes N display sub-cycles, the nth display sub-cycle including a nth pre-light-emitting stage and an nth light-emitting stage set sequentially, N being an integer greater than 1, and n being a positive integer less than or equal to N; the nth pre-light-emitting stage includes at least one reset time period; The driving module includes a light emission control signal generation circuit and a first reset control signal generation circuit; The light emission control signal generation circuit is used to provide the light emission control signal to the light emission control terminal, such that in the nth light emission preparation stage, the first light emission control circuit, under the control of the light emission control signal, controls the first terminal of the driving circuit to disconnect from the first electrode of the light emission element, and causes the first light emission control circuit, under the control of the light emission control signal, to connect the first terminal of the driving circuit to the first electrode of the light emission element during at least a portion of the time period included in the nth light emission stage. The first reset control signal generation circuit is further configured to provide the first reset control signal to the first reset control terminal, so that during the reset time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage provided by the first initial voltage terminal into the first initial voltage terminal. The first electrode of the light-emitting element; When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the first reset time period and the end time of the nth preparation light-emitting stage is greater than the pre-charge time threshold during the nth preparation light-emitting stage.

14. The drive module as described in claim 13, wherein, The pre-charging time threshold is greater than or equal to 20 lines of scan time but less than the duration of the nth preparation emission stage.

15. The drive module as described in claim 13, wherein, The brightness threshold is less than or equal to 150 nits.

16. The drive module as described in claim 13, wherein, The pixel circuit further includes a second reset circuit, which is used to control the connection or disconnection between the second initial voltage terminal and the reset terminal of the driving circuit under the control of the second reset control signal provided by the second reset control terminal; the reset terminal includes the first terminal and / or the second terminal of the driving circuit. The drive module also includes a second reset control signal generation circuit; The second reset control signal generation circuit is used to provide a second reset control signal to the second reset control terminal, so that during the reset time period, the second reset circuit, under the control of the second reset control signal, writes the second initial voltage provided by the second initial voltage terminal into the reset terminal of the drive circuit.

17. The drive module as described in claim 16, wherein, The first reset control terminal and the second reset control terminal are the same control terminal.

18. The drive module as described in claim 16, wherein, The pixel circuit further includes a second light-emitting control circuit, which is used to control the connection or disconnection between the second voltage terminal and the second terminal of the driving circuit under the control of the light-emitting control signal. The light emission control signal generation circuit is further configured to, by providing the light emission control signal, cause the second light emission control circuit, under the control of the light emission control signal, to disconnect the second voltage terminal from the second terminal of the driving circuit, and cause the second light emission control circuit, under the control of the light emission control signal, to connect the second voltage terminal to the second terminal of the driving circuit during at least a portion of the time period included in the nth light emission stage.

19. The drive module as described in claim 18, wherein, The light emission control signal generation circuit is further configured to provide the light emission control signal so that, in the nth light emission stage, the first light emission control circuit controls the first terminal of the driving circuit to connect with the first electrode of the light emission element under the control of the light emission control signal, and the second light emission control circuit controls the second voltage terminal to connect with the second terminal of the driving circuit under the control of the light emission control signal.

20. The drive module as claimed in claim 18, wherein, The light emission control signal generation circuit is also used to control the light emission control signal to be a PWM signal during the nth light emission stage.

21. The drive module according to any one of claims 18 to 20, wherein, The nth light-emitting preparation stage includes the nth reset time period; The first reset control signal generation circuit is further configured to provide a first reset control signal, such that during the nth reset time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first electrode of the light-emitting element; When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the nth reset time period and the end time of the nth preparation light-emitting stage is greater than the pre-charging time threshold.

22. The drive module according to any one of claims 18 to 20, wherein, The nth light-emitting stage includes a first reset time period and a second reset time period set sequentially. The first reset control signal generation circuit is further configured to provide a first reset control signal, such that during the nth first reset time period and the nth second reset time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first electrode of the light-emitting element; When the luminance of the light-emitting element is less than or equal to the luminance threshold during the display cycle, the time interval between the start time of the nth first reset time period and the end time of the nth preparation light-emitting stage is greater than the pre-charging time threshold.

23. A display device, comprising a pixel circuit and a driving module as described in any one of claims 13 to 22; the pixel circuit comprising a driving circuit, a first light-emitting control circuit, a light-emitting element, and a first reset circuit; The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the first terminal of the driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the first terminal of the driving circuit and the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal. open; The first reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the first initial voltage terminal and the first electrode of the light-emitting element under the control of the first reset control signal provided by the first reset control terminal. The driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential at its control terminal; The second electrode of the light-emitting element is electrically connected to the first voltage terminal.

24. The display device as claimed in claim 23, wherein, The pixel circuit also includes a second reset circuit; The second reset circuit is used to control the connection or disconnection between the second initial voltage terminal and the reset terminal of the drive circuit under the control of the second reset control signal provided by the second reset control terminal; The reset terminal includes the first terminal of the driving circuit and / or the second terminal of the driving circuit.

25. The display device as claimed in claim 23, wherein, The pixel circuit also includes a second light-emitting control circuit; The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the second voltage terminal, and the second terminal of the driving circuit, respectively, and is used to control the connection or disconnection between the second voltage terminal and the second terminal of the driving circuit under the control of the light-emitting control signal.

26. The display device according to any one of claims 23 to 25, wherein, The pixel circuit also includes a third reset circuit, a compensation control circuit, a data writing circuit, and an energy storage circuit; The third reset circuit is electrically connected to the third reset control terminal and the third initial voltage terminal respectively. The third reset circuit is also electrically connected to the first terminal or the control terminal of the driving circuit. The third reset circuit is used to control the writing of the third initial voltage provided by the third initial voltage terminal into the first terminal or the control terminal of the driving circuit under the control of the third reset control signal provided by the third reset control terminal. The compensation control circuit is electrically connected to the first scanning end, the control end of the driving circuit, and the first end of the driving circuit, respectively, and is used to control the connection or disconnection between the control end of the driving circuit and the first end of the driving circuit under the control of the first scanning signal provided by the first scanning end. The data writing circuit is connected to the second scanning terminal, the data line, and the second terminal of the driving circuit. An electrical connection is provided to control the connection or disconnection between the data line and the second terminal of the drive circuit under the control of the second scan signal provided by the second scan terminal. The energy storage circuit is electrically connected to the control terminal of the drive circuit to maintain the potential of the control terminal of the drive circuit.

27. The display device according to any one of claims 23 to 25, wherein, The light-emitting element is a multilayer series light-emitting element.

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