Amplitude demodulation implementation method applied to secondary radar

Abstract

An amplitude demodulation implementation method applied to a secondary radar, the method comprising: performing frequency mixing on a reply signal to obtain an intermediate frequency signal; quantizing the intermediate frequency signal; performing quadrature demodulation on the quantized intermediate frequency signal to obtain a digital amplitude value, and using a piecewise linear calculation method to obtain a logarithmic digital amplitude. The logarithmic compression processing function of the secondary radar for a reply signal is implemented by an FPGA; after intermediate frequency digitization of the reply signal, a digital amplitude value is obtained via quadrature demodulation; and the digital amplitude value is processed in the FPGA by using a piecewise linear calculation method to approximate a logarithmic conversion characteristic, so as to obtain a logarithmic digital amplitude, which is very simple.

Description

An Amplitude Demodulation Implementation Method for Secondary Radar

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411435410.9, filed on October 15, 2024, entitled “A Low-Cost Amplitude Demodulation Implementation Method for Secondary Radar,” which is incorporated herein by reference in its entirety. Technical Field

[0003] This application relates to the field of secondary radar technology, and in particular to an amplitude demodulation implementation method for secondary radar. Background Technology

[0004] In today's rapidly developing civil aviation industry, secondary radar, as a crucial piece of air traffic control equipment, plays an indispensable role in airspace surveillance and ensuring flight safety. Therefore, secondary radar must possess high measurement accuracy, ensure accurate reception and processing of response signals, and meet high-precision amplitude extraction requirements.

[0005] Under normal circumstances, secondary radar must be able to detect all response signals across the entire dynamic range of signal strength, from the maximum possible signal strength of -20dBm to the minimum possible signal strength of -90dBm, a voltage difference of 3000 times. Therefore, traditional secondary radar uses logarithmic detection circuits to logarithmically compress the received response signals. The use of logarithmic detection circuits increases both hardware costs and board space, and the performance parameters of logarithmic detection circuits are easily affected by temperature, environment, and other factors, making performance tuning extremely difficult.

[0006] Summary of the Invention

[0007] Traditional methods for processing response signals from secondary radar require logarithmic detection circuits, increasing hardware costs and board space. Furthermore, the performance parameters of logarithmic detection circuits are easily affected by temperature and environmental factors, making performance tuning extremely difficult. This application proposes an amplitude demodulation method for secondary radar, which delegates the logarithmic compression processing of the response signal to an FPGA. After the response signal is digitized at intermediate frequency, a digital amplitude value is obtained through quadrature demodulation. The digital amplitude is calculated in the FPGA using a piecewise linear method to approximate the logarithmic transformation characteristics, resulting in a very simple logarithmic digital amplitude.

[0008] This application discloses an amplitude demodulation implementation method for secondary radar, which includes:

[0009] Step 1: Mix the response signal to obtain the intermediate frequency signal;

[0010] Step 2: Perform A / D quantization on the intermediate frequency signal;

[0011] Step 3: Perform quadrature demodulation on the quantized intermediate frequency signal to obtain the digital amplitude value, and use a piecewise linear calculation method to obtain the logarithmic digital amplitude.

[0012] Further, step 1 includes:

[0013] The local oscillator is mixed with the response signal received by the secondary radar to obtain the intermediate frequency signal of the required frequency.

[0014] Further, step 2 includes:

[0015] Based on the frequency, bandwidth, and amplitude range of the intermediate frequency (IF) signal, select the required A / D chip; based on the frequency and bandwidth of the IF signal, select the required sampling frequency, quantize the IF signal, and obtain the A / D quantized value.

[0016] Further, step 3 includes:

[0017] Step 31: The FPGA generates local digital sine and cosine carriers through DDS; the local digital sine and cosine carriers are multiplied by the A / D quantization value of the intermediate frequency signal respectively, and digital mixing is performed. After digital mixing, the components are filtered to obtain the I-channel in-phase component and the Q-channel quadrature component.

[0018] Step 32: Calculate the intermediate frequency signal amplitude based on the I-channel in-phase component and the Q-channel quadrature component;

[0019] Step 33: Based on the data correspondence between the intermediate frequency signal amplitude value and the logarithmic amplitude value, a lookup table is created. A piecewise linear calculation method is used to approximate the logarithmic conversion characteristics. Based on the lookup table, corrections and compensations are made to obtain the logarithmic amplitude value.

[0020] Further, step 32 includes:

[0021] The amplitude of the intermediate frequency signal can be calculated using the following formula:

[0022] Wherein, powerdbamp is the amplitude value of the intermediate frequency signal.

[0023] Further, step 33 includes:

[0024] Step 331: Divide the intermediate frequency signal amplitude value powerdbamp into K value intervals. In the first value interval, find the mapping relationship between the logarithmic digital amplitude corresponding to the response signal. The corresponding logarithmic amplitude value is indexed by the intermediate frequency signal amplitude value and the corresponding logarithmic amplitude value is arrayed as array element. Construct a lookup table look_table with P elements to map the intermediate frequency signal amplitude value to the logarithmic amplitude value.

[0025] Step 332: For the second value interval to the Kth value interval, determine the array index according to the intermediate frequency signal amplitude value, find the corresponding logarithmic amplitude value, select the correction value, and obtain the required logarithmic amplitude value.

[0026] Furthermore, in step 331, the intermediate frequency signal amplitude value powerdbamp is divided into K equal value intervals in ascending order, with no overlap between each value interval.

[0027] Furthermore, the mapping relationship between the intermediate frequency signal amplitude value (powerdbamp) and the corresponding logarithmic digital amplitude of the response signal is expressed as:

[0028] The logarithmic amplitude value is logamp = 20 * lg(powerdbamp), where powerdbamp is the amplitude value of the intermediate frequency signal.

[0029] Furthermore, the intermediate frequency signal amplitude value powerdbamp is approximated as m*2. n Then the voltage amplitude value is ulogamp:

[0030] ulogamp=20*lg(powerdbamp)≈20*lg(m*2 n )=20*lg(m)+20*lg(2 n )=20*lg(m)+20*n*lg2≈20*lg(m)+6*n

[0031] Wherein, the voltage amplitude value ulogamp is equal to the logarithmic amplitude value logamp, and m and n are both positive integers.

[0032] Further, step 332 includes:

[0033] For the i-th value period, the quotient obtained by dividing powerdbamp by 2n is used as the index value of the base lookup table to find the corresponding logarithmic magnitude value. At this time, n = i-1, the correction value is 6*n, and the sum of the found logarithmic magnitude value and the correction value is the final required logarithmic magnitude value.

[0034] Due to the adoption of the above technical solution, this application has the following advantages:

[0035] 1. The traditional processing method for secondary radar response signals requires the use of logarithmic detection circuits. This application entrusts the logarithmic compression processing function of secondary radar response signals to FPGA. After the response signal is digitized at intermediate frequency, the digital amplitude value is obtained through quadrature demodulation. The digital amplitude is calculated in the FPGA using a piecewise linear calculation method to approximate the logarithmic conversion characteristics and obtain the logarithmic digital amplitude. This is very simple and does not require the use of logarithmic detection circuits, saving hardware costs and reducing board space.

[0036] 2. The performance parameters of the logarithmic detection circuit used in the traditional processing method of secondary radar response signals are easily affected by temperature, environment, etc., and the performance index debugging process is very difficult. This application adopts digital processing method as much as possible for the amplitude processing of secondary radar response signals, and replaces the complicated analog circuit debugging with FPGA software. The debugging process is very simple, and the performance index fully meets the measurement accuracy requirements and is not affected by external conditions such as temperature and environment. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0038] Figure 1 is a schematic flowchart of an amplitude demodulation implementation method for secondary radar according to an embodiment of this application;

[0039] Figure 2 is a schematic block diagram of the radio frequency receiving front-end unit according to an embodiment of this application;

[0040] Figure 3 is an A / D quantization circuit diagram of an embodiment of this application. Detailed Implementation

[0041] The present application will be further described in conjunction with the accompanying drawings and embodiments. The described embodiments are only some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of the present application.

[0042] Traditional methods for processing response signals from secondary radar require logarithmic detection circuits, which increase hardware costs and board space. Furthermore, the performance parameters of logarithmic detection circuits are easily affected by temperature and environmental factors, making performance tuning extremely difficult. This application proposes an amplitude demodulation method for secondary radar, which delegates the logarithmic compression processing of the response signal to an FPGA. After the response signal is digitized at intermediate frequency, a digital amplitude value is obtained through quadrature demodulation. The digital amplitude is calculated in the FPGA using a piecewise linear method to approximate the logarithmic transformation characteristics, resulting in a very simple logarithmic digital amplitude.

[0043] Referring to Figure 1, this application provides an embodiment of an amplitude demodulation method applied to secondary radar, which includes:

[0044] Step 1: Mix the response signal to obtain the intermediate frequency signal;

[0045] Step 2: Perform A / D (analog-to-digital) quantization on the intermediate frequency signal;

[0046] Step 3: Perform quadrature demodulation on the quantized intermediate frequency signal to obtain the digital amplitude value, and use a piecewise linear calculation method to obtain the logarithmic amplitude value.

[0047] In this embodiment, step 1 includes:

[0048] The local oscillator is mixed with the response signal received by the secondary radar to obtain the intermediate frequency signal of the required frequency.

[0049] Specifically, referring to Figure 2, the input 1090MHz RF signal is filtered and amplified, then mixed with the 1160MHz local oscillator signal generated by the local oscillator unit to generate an intermediate frequency (IF) signal of 70MHz. After passing through an IF filter with an 8MHz bandwidth, the IF signal is output.

[0050] In this embodiment, step 2 includes:

[0051] Based on the frequency, bandwidth, and amplitude range of the intermediate frequency (IF) signal, select the required A / D chip; based on the frequency and bandwidth of the IF signal, select the required sampling frequency, quantize the IF signal, and obtain the A / D quantized value. Figure 3 shows an A / D chip, model AD9265BCPZ-125.

[0052] In this embodiment, step 3 includes:

[0053] Step 31: The FPGA generates local digital sine and cosine carriers through DDS (internal direct frequency synthesizer); the local digital sine and cosine carriers are multiplied by the A / D quantization value of the intermediate frequency signal respectively, and digital mixing is performed. After digital mixing, the components are passed through filters to obtain the I-path in-phase component and the Q-path quadrature component; the filter can be a low-pass filter.

[0054] Step 32: Calculate the intermediate frequency signal amplitude based on the I-channel in-phase component and the Q-channel quadrature component;

[0055] Step 33: Based on the data correspondence between the intermediate frequency signal amplitude value and the logarithmic amplitude value, a lookup table is created. A piecewise linear calculation method is used to approximate the logarithmic conversion characteristics. Based on the lookup table, corrections and compensations are made to obtain the logarithmic amplitude value.

[0056] In this embodiment, step 32 includes:

[0057] The amplitude of the intermediate frequency signal can be calculated using the following formula:

[0058] Wherein, powerdbamp is the amplitude value of the intermediate frequency signal.

[0059] In this embodiment, step 33 includes:

[0060] Step 331: Divide the intermediate frequency signal amplitude value powerdbamp into K value intervals. In the first value interval, find the mapping relationship between the logarithmic amplitude value and the corresponding logarithmic amplitude value. The corresponding logarithmic amplitude value is indexed by the intermediate frequency signal amplitude value and the corresponding logarithmic amplitude value is arrayed as an array element. Construct a lookup table look_table with P elements to map the intermediate frequency signal amplitude value to the logarithmic amplitude value.

[0061] Step 332: For the second value interval to the Kth value interval, determine the array index according to the intermediate frequency signal amplitude value, find the corresponding logarithmic amplitude value, select the correction value, and obtain the required logarithmic amplitude value.

[0062] In this embodiment, in step 331, the intermediate frequency signal amplitude value powerdbamp is divided into K equal value intervals in ascending order, with no overlap between each value interval.

[0063] In this embodiment, in step 331:

[0064] The power gain of the response signal is:

[0065] Among them, V recv V is the effective value of the voltage amplitude of the intermediate frequency signal after the response signal conversion. refTo respond to the effective value of the voltage amplitude of the intermediate frequency reference signal after the reference signal conversion, while the effective value of the voltage of the sine wave signal is... Where VPP is the peak-to-peak value of the sinusoidal signal, and the required logarithmic amplitude conversion is... Therefore, the logarithmic amplitude value is logamp = 20lg(powerdbamp), where powerdbamp is the amplitude value of the intermediate frequency signal.

[0066] In principle, obtaining 20lg(powerdbamp) on an FPGA can only be done by looking up a table. However, the range of powerdbamp values ​​is too large, and constructing a lookup table requires too many resources and is too laborious to implement. This application's embodiment uses a piecewise linear calculation method to approximate the logarithmic transformation characteristics, approximating the intermediate frequency signal amplitude value powerdbamp as m*2. n Then the voltage amplitude value ulogamp=20*lg(powerdbamp)≈20*lg(m*2 n )=20*lg(m)+20*lg(2 n )=20*lg(m)+20*n*lg2≈20*lg(m)+6*n

[0067] Wherein, the voltage amplitude value ulogamp is equal to the logarithmic amplitude value logamp, and m and n are both positive integers.

[0068] In this embodiment, step 332 includes:

[0069] For the i-th value period, divide powerdbamp by 2 n The obtained quotient is used as the index value of the base lookup table to find the corresponding logarithmic magnitude value. At this time, n = i-1, the correction value is 6*n, and the sum of the found logarithmic magnitude value and the correction value is the final required logarithmic magnitude value.

[0070] Specifically, this application provides a more specific technical solution, which includes:

[0071] Using 0 ≤ powerdbamp ≤ 255 as the baseline, find the mapping relationship between the logarithmic digital amplitude and the low-power response signal. That is, for intermediate frequency (IF) signal amplitude values ​​within [0, 255], construct a baseline lookup table of 256 elements for the mapping relationship between IF signal amplitude values ​​and logarithmic amplitude values, with IF signal amplitude values ​​as array indices and corresponding logarithmic amplitude values ​​as array elements: look_table = [a0, a1, a2, a3… a255]. For other IF signal amplitude values ​​greater than or equal to 256, powerdbamp is calculated piecewise linearly according to the intervals [256, 511], [512, 1023], [1024, 2047], [2048, 4095], [4096, 8191]… First, determine the interval where the powerdbamp value falls; when it is within [256, 511], divide by 2. 1 The obtained quotient is used as the index value of the base lookup table to find the corresponding logarithmic magnitude value. At this time, n=1, the correction value is 6*1, and the sum of the two is the final required logarithmic magnitude value; when it is in [512,1023], divide by 2. 2 The obtained quotient is used as the index value of the base lookup table to find the corresponding logarithmic magnitude value. At this time, n=2, the correction value is 6*2, and the sum of the two is the final required logarithmic magnitude value; when it is in the range [1024,2047], divide by 2. 3 The obtained quotient is used as the index value of the reference lookup table to find the corresponding logarithmic magnitude value. At this time, n=3, the correction value is 6*3, and the sum of the two is the final required logarithmic magnitude value. The rest are calculated in the same way to obtain the logarithmic magnitude value in the entire dynamic range, which greatly reduces the FPGA resource consumption and the workload of program developers.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and not to limit them. Although this application has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of this application. Any modifications or equivalent substitutions that do not depart from the scope of this application should be covered within the protection scope of the claims of this application.

Claims

1. A method for amplitude demodulation applied to secondary radar, comprising: Step 1: Mix the response signal to obtain the intermediate frequency signal; Step 2: Perform A / D quantization on the intermediate frequency signal; Step 3: Perform quadrature demodulation on the quantized intermediate frequency signal to obtain the digital amplitude value, and use a piecewise linear calculation method to obtain the logarithmic digital amplitude.

2. The amplitude demodulation implementation method for secondary surveillance radars according to claim 1, wherein, Step 1 includes: The local oscillator is mixed with the response signal received by the secondary radar to obtain the intermediate frequency signal of the required frequency.

3. The amplitude demodulation implementation method for secondary surveillance radars according to claim 1, wherein, Step 2 includes: Based on the frequency, bandwidth, and amplitude range of the intermediate frequency (IF) signal, select the required A / D chip; based on the frequency and bandwidth of the IF signal, select the required sampling frequency, quantize the IF signal, and obtain the A / D quantized value.

4. The amplitude demodulation implementation method for secondary surveillance radars according to claim 1, wherein, Step 3 includes: Step 31: The FPGA generates local digital sine and cosine carriers through DDS; the local digital sine and cosine carriers are multiplied by the A / D quantization value of the intermediate frequency signal respectively, and digital mixing is performed. After digital mixing, the components are filtered to obtain the I-channel in-phase component and the Q-channel quadrature component. Step 32: The FPGA calculates the intermediate frequency signal amplitude based on the I-channel in-phase component and the Q-channel quadrature component; Step 33: The FPGA creates a lookup table based on the data correspondence between the intermediate frequency signal amplitude value and the logarithmic amplitude value. It then uses a piecewise linear calculation method to approximate the logarithmic conversion characteristics and performs corrections and compensations based on the lookup table to obtain the logarithmic amplitude value.

5. The amplitude demodulation implementation method for secondary surveillance radars according to claim 4, wherein, Step 32 includes: The intermediate frequency signal amplitude value is calculated by the following formula: Wherein, powerdbamp is the amplitude value of the intermediate frequency signal.

6. The amplitude demodulation implementation method for secondary surveillance radars according to claim 4, wherein, Step 33 includes: Step 331: Divide the intermediate frequency signal amplitude value powerdbamp into K value intervals. In the first value interval, find the mapping relationship between the logarithmic digital amplitude corresponding to the response signal. The corresponding logarithmic amplitude value is indexed by the intermediate frequency signal amplitude value and the corresponding logarithmic amplitude value is arrayed as array element. Construct a lookup table look_table with P elements to map the intermediate frequency signal amplitude value to the logarithmic amplitude value. Step 332: For the second value interval to the Kth value interval, determine the array index according to the intermediate frequency signal amplitude value, find the corresponding logarithmic amplitude value, select the correction value, and obtain the required logarithmic amplitude value.

7. The amplitude demodulation implementation method for secondary surveillance radars according to claim 6, wherein, In step 331, the intermediate frequency signal amplitude value powerdbamp is divided into K equal value intervals in ascending order, with no overlap between each value interval.

8. A low-cost amplitude demodulation implementation method for secondary surveillance radars according to claim 6 or 7, wherein, The mapping relationship between the intermediate frequency signal amplitude value (powerdbamp) and the corresponding logarithmic digital amplitude of the response signal is expressed as: The logarithmic amplitude value is logamp = 20 * lg(powerdbamp), where powerdbamp is the amplitude value of the intermediate frequency signal.

9. The amplitude demodulation implementation method for secondary surveillance radars according to claim 8, wherein, The amplitude value of the intermediate frequency signal, powerdbamp, is approximately represented as m*2. n Then the voltage amplitude value is ulogamp: ulogamp=20*lg(powerdbamp)≈20*lg(m*2 n )=20*lg(m)+ 20*lg(2 n )=20*lg(m)+20*n*lg2≈20*lg(m)+6*n Among them, the voltage amplitude value ulogamp is equal to the logarithmic amplitude value logamp, and both m and n are positive. Integer.

10. The amplitude demodulation implementation method for secondary surveillance radars according to claim 9, wherein, Step 332 includes: For the ith value, divide powerdbamp by 2 n The resulting quotient is used as an index value to look up the corresponding log magnitude value in the reference look-up table. At this point, n = i - 1, and the correction value is 6*n. The sum of the log magnitude value looked up and the correction value is the final log magnitude value required.

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