Wafer backside alignment mark and manufacturing method therefor

Abstract

Provided in the embodiments of the present disclosure are a wafer backside alignment mark and a manufacturing method therefor, and a wafer backside dicing method, a wafer backside photolithography method, and a preparation method for a semiconductor device. The manufacturing method comprises: providing a wafer, which is provided with dies and scribe lines on the frontside thereof; in a peripheral region of the frontside of the wafer, manufacturing an array of blind holes corresponding to the scribe lines, wherein the hole depth of each blind hole is greater than a first thickness; performing a thinning treatment on a central region of the backside of the wafer, and manufacturing a metal layer in the thinned central region of the backside of the wafer; and grinding a peripheral region of the backside of the wafer, such that the array of blind holes in the peripheral region is completely exposed, so as to form a wafer backside alignment mark that is visible on the backside of the wafer and can be used for wafer backside scribing or photolithography. By using the manufactured wafer backside alignment mark, processes including wafer backside dicing or wafer backside photolithography can be executed on the backside of a wafer, thereby addressing the lack of effective wafer backside alignment marks in the related art during a related fabrication process on the backside of a wafer.

Description

Wafer back side alignment marks and their fabrication method Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a wafer back alignment mark and its fabrication method, a wafer back dicing method, a wafer back photolithography method, and a semiconductor device fabrication method. Background Technology

[0002] A wafer is a silicon wafer used to manufacture silicon semiconductor circuits. Its raw material is silicon. Silicon ingots are wire-cut and polished into bare wafers with a thickness of about 1 mm. The bare wafers are then processed through front-end and back-end processes to form wafers with chips. These wafers are then diced into dies in a certain way. The diced dies are packaged to form chips. Finally, the packaged chips are tested.

[0003] In wafer fabrication processes, such as wafer dicing or photolithography, corresponding alignment marks need to be set on the wafer.

[0004] Taking wafer dicing as an example, wafer dicing is an essential process in chip packaging, dividing the finished wafer into individual dies according to die size and reserved dicing lanes. As die size and thickness decrease, as well as wafer dicing lane width decreases, the impact of the dicing process on die quality becomes increasingly prominent.

[0005] Generally, chips are separated from the wafer by dicing along the scribe lines on the front side. However, in some specialized packaging processes, such as wafer-level packaging (WLP), the presence of opaque epoxy resin makes it difficult to effectively identify the scribe lines on the front side during dicing, resulting in challenging alignment. Therefore, it becomes necessary to start dicing from the back side of the wafer. Since there are no scribe lines on the back side, aligning the dicing blade located on the back side with the scribe lines on the front side becomes a challenging problem. Summary of the Invention

[0006] In view of the lack of the above-mentioned related technologies, the purpose of this disclosure is to provide a wafer back-side alignment mark and its fabrication method, a wafer back-side dicing method, a wafer back-side photolithography method, and a semiconductor device fabrication method, to solve the problem of the lack of effective wafer back-side alignment marks in the related technologies when performing related processes on the wafer back side.

[0007] The first aspect of this disclosure provides a method for fabricating alignment marks on the back side of a wafer, comprising the following steps:

[0008] A wafer is provided, wherein the front side of the wafer is provided with dies and crisscrossing dicing channels;

[0009] An array of blind vias corresponding to the scribe lines is formed in the edge region of the front side of the wafer. In the blind via array, each scribe line includes at least two blind vias, and the depth of the blind vias is greater than the first thickness.

[0010] The middle region of the back side of the wafer is thinned, and a metal layer is formed in the middle region of the thinned back side of the wafer, wherein the thickness of the middle region after forming the metal layer is a first thickness; and

[0011] The edge region on the back side of the wafer is ground to fully expose the array of blind vias in the edge region, forming a wafer back side alignment mark that can be used for wafer dicing or photolithography on the back side of the wafer.

[0012] In some examples of the first aspect, creating an array of blind vias corresponding to the scribe lines in the edge region of the front side of the wafer includes: creating at least two blind vias along each scribe line in the edge region of the front side of the wafer.

[0013] In some examples of the first aspect, blind vias are created in the edge region of the front side of the wafer by laser drilling or etching.

[0014] In some examples of the first aspect, the edge region is the area within 4 millimeters of the outer edge of the wafer.

[0015] In some examples of the first aspect, fabricating a metal layer in the middle region of the back side of the thinned wafer includes depositing a metal layer in the layout region on the back side of the wafer using a sputtering or evaporation process.

[0016] In some examples of the first aspect, after the edge region on the back side of the wafer is ground, the step height difference between the edge region and the middle region of the wafer is less than or equal to 10 micrometers.

[0017] A second aspect of this disclosure provides a wafer back-side alignment mark, which is fabricated on the wafer using the wafer back-side alignment mark fabrication method described above.

[0018] The third aspect of this disclosure provides a method for dicing the back side of a wafer, comprising the following steps: fabricating a back side alignment mark on the wafer using the method described above; and performing a dicing process on the back side of the wafer using the back side alignment mark.

[0019] The fourth aspect of this disclosure provides a wafer photolithography method, comprising the following steps: fabricating a wafer back-side alignment mark on a wafer using the wafer back-side alignment mark fabrication method as described above; and performing photolithography on the wafer back-side using the wafer back-side alignment mark.

[0020] The fifth aspect of this disclosure provides a method for fabricating a semiconductor device, the method comprising processing a wafer using the wafer backside alignment mark fabrication method as described above.

[0021] This disclosure provides a wafer back-side alignment mark and its fabrication method, a wafer back-side dicing method, a wafer back-side photolithography method, and a semiconductor device fabrication method. The wafer back-side alignment mark fabrication method includes: providing a wafer with dies and crisscrossing scribe lines on its front side; fabricating an array of blind vias corresponding to the scribe lines in the edge region of the wafer's front side, wherein each scribe line includes at least two blind vias, and the depth of each blind via is greater than a first thickness; thinning the middle region of the wafer back side and fabricating a metal layer in the thinned middle region of the wafer back side; and grinding the edge region of the wafer back side to fully expose the blind via array in the edge region, forming a wafer back-side alignment mark visible on the wafer back side for wafer dicing or photolithography. Thus, the fabricated wafer back-side alignment mark enables processes including wafer dicing or wafer photolithography to be performed on the wafer back side, solving the problem of the lack of effective wafer back-side alignment marks in related technologies when performing related processes on the wafer back side. Attached Figure Description

[0022] Figure 1 shows a schematic flowchart of a method for fabricating alignment marks on the back side of a wafer according to an embodiment of the present disclosure.

[0023] Figures 2A to 6B are schematic diagrams of the structure in each step of the fabrication method of the alignment mark on the back side of the wafer in Figure 1.

[0024] Figure 7 shows a schematic flowchart of a wafer back-side dicing method according to an embodiment of the present disclosure.

[0025] Figure 8 shows a schematic diagram of the structure for forming dicing marking lines based on the various through-holes shown on the back side of the wafer in Figure 6B in the wafer back-side dicing method of this disclosure.

[0026] Figure 9 shows a schematic flowchart of the wafer back-side photolithography method of this disclosure in one embodiment. Detailed Implementation

[0027] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the information disclosed herein. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this disclosure can be modified or changed according to different viewpoints and application modules without departing from the spirit of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be combined with each other.

[0028] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, so that those skilled in the art to which this disclosure pertains can readily implement it. This disclosure may be embodied in many different forms and is not limited to the embodiments described herein.

[0029] In this disclosure, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic represented in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in any one or a group of embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples represented in this disclosure, as well as the features of those different embodiments or examples.

[0030] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this disclosure, "a set" means two or more, unless otherwise explicitly specified.

[0031] For the purpose of clarity, devices unrelated to the description are omitted, and the same or similar components throughout the specification are given the same reference numerals.

[0032] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0033] While the terms first, second, etc., are used in some examples herein to refer to various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, first interface and second interface, etc., are used. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, step, operation, element, module, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, modules, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0034] The technical terms used herein are for reference only to specific embodiments and are not intended to limit the scope of this disclosure. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. The word "comprising" as used in this specification means to specify a particular characteristic, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other characteristics, regions, integers, steps, operations, elements, and / or components.

[0035] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the message of the present disclosure, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0036] In related technologies, alignment marks are mostly placed on the front side of the wafer. Because the back side of the wafer is encapsulated by molding compound or covered by other opaque materials, it is quite difficult to perform corresponding process technology from the back side of the wafer.

[0037] This disclosure provides a wafer back-side alignment mark and its fabrication method, a wafer back-side dicing method, a wafer back-side photolithography method, and a semiconductor device fabrication method. The wafer back-side alignment mark fabrication method includes: providing a wafer with dies and crisscrossing scribe lines on its front side; fabricating an array of blind vias corresponding to the scribe lines in the edge region of the wafer's front side, wherein each scribe line includes at least two blind vias, and the depth of each blind via is greater than a first thickness; thinning the middle region of the wafer back side to the first thickness, and fabricating a metal layer in the thinned middle region of the wafer back side; and grinding the edge region of the wafer back side to fully expose the blind via array in the edge region, forming a wafer back-side alignment mark. Thus, the fabricated wafer back-side alignment mark allows for the execution of processes including wafer back-side dicing or wafer back-side photolithography on the wafer back side, solving the problem of the lack of effective wafer back-side alignment marks in related technologies when performing related processes on the wafer back side.

[0038] This embodiment provides a method for fabricating a wafer back-side alignment mark, which is used to fabricate a wafer back-side alignment mark that can be displayed on the back side of the wafer.

[0039] Please refer to Figure 1, which shows a schematic flowchart of a method for fabricating alignment marks on the back side of a wafer according to this disclosure in one embodiment.

[0040] As shown in Figure 1, the method for fabricating the alignment marks on the back side of the wafer in this embodiment may include the following steps:

[0041] Step S101: Provide a wafer with dies and crisscrossing dicing channels arranged on the front side of the wafer.

[0042] As shown in Figure 2A, a wafer 100 is provided, which includes a central region and an edge region surrounding the central region. The edge region is a region within 4 mm of the outer edge of the wafer. Specifically, the edge region may be, for example, a ring-shaped region with a width of 4 mm, but is not limited thereto, and the dimension of the edge region from the outer edge of the wafer may be varied in other ways.

[0043] A die array is arranged in the device area on the front side of the wafer. The die array includes a plurality of dies 101 arranged in a regular manner. A dicing channel 102 is provided between adjacent dies 101, thereby forming a crisscrossing dicing channel 102.

[0044] Step S103: A blind via array corresponding to the scribe line is fabricated in the edge region of the front side of the wafer. In the blind via array, each scribe line includes at least two blind vias, and the depth of the blind vias is greater than the first thickness.

[0045] As shown in Figures 3A and 3B, an array of blind vias corresponding to the scribe lines 102 is formed on the edge region of the front side of the wafer 100. In the blind via array, at least two blind vias 103 are included for each scribe line 102, that is, at least two blind vias 103 are provided along each scribe line or its extension.

[0046] Therefore, in step S103, creating an array of blind vias corresponding to the scribe lines in the edge region of the wafer front side includes: creating at least two blind vias along each scribe line in the edge region of the wafer front side.

[0047] In some embodiments, blind vias are formed in the edge region of the front side of the wafer by laser drilling or etching. The blind vias have a preset depth and diameter. The depth of the blind via is greater than a first thickness, and the diameter of the blind via can be equivalent to the width of the scribe line. For example, the diameter of the blind via can be greater than or equal to the width of the scribe line, or the diameter of the blind via can be less than or equal to the width of the scribe line.

[0048] Step S105: Thin the middle region on the back side of the wafer and fabricate a metal layer in the middle region on the back side of the wafer after thinning. The thickness of the middle region after fabricating the metal layer is the first thickness.

[0049] Furthermore, step S105 may further include the following steps:

[0050] First, the middle region on the back side of wafer 100 is thinned to form the cross-sectional structure shown in Figure 4A.

[0051] After thinning the middle region of the back side of wafer 100, the structure shown in Figure 4B can be observed when viewed from the back side of the wafer.

[0052] Next, a metal layer 104 is fabricated in the middle region of the back side of the thinned wafer 100 to form the cross-sectional structure shown in Figure 5A.

[0053] In some embodiments, the metal layer may be formed on the surface of the middle region on the back side of the wafer using processes such as evaporation or sputtering.

[0054] It should be noted that the thickness of the middle region after the metal layer is made is the first thickness. That is, the sum of the thickness of the middle region after thinning and the thickness of the metal layer is the first thickness.

[0055] After a metal layer 104 is fabricated in the middle region of the back side of wafer 100, the structure shown in Figure 5B can be observed when viewed from the back side of the wafer.

[0056] Step S107: Grind the edge region on the back side of the wafer to fully expose the blind via array in the edge region and form a wafer back side alignment mark.

[0057] As shown in the cross-sectional structure of Figure 6A, the edge region on the back side of wafer 100 is ground until the bottom of each blind hole in the blind hole array is ground away, so that each blind hole is ground open to form a through hole and exposed.

[0058] After grinding the edge region of the back side of wafer 100 until each via is exposed, the structure shown in Figure 6B can be observed from the back side of the wafer.

[0059] It is worth noting that when grinding the edge region on the back side of wafer 100, to avoid damaging the metal layer 104 fabricated in the layout area on the back side of wafer 100, the grinding does not reach the metal layer 104. The thickness of the edge region on the back side of wafer 100 after grinding is greater than the first thickness. Specifically, when viewed from the back side of wafer 100, the edge region on the back side of wafer 100 after grinding protrudes from the metal layer 104, that is, there is a step between the edge region on the back side of wafer 100 after grinding and the metal layer 104. In some examples, the step height difference is, for example, less than or equal to 10 micrometers (as shown in Figure 6A).

[0060] In this way, the vias formed by drilling through the blind vias in the edge region on the back of the wafer can be used as alignment marks on the back of the wafer. Subsequently, based on the alignment marks on the back of the wafer, processes such as wafer back scribing or wafer back photolithography can be performed on the wafer.

[0061] This disclosure provides a method for fabricating a wafer back-side alignment mark, comprising: providing a wafer with dies and crisscrossing scribe lines on its front side; fabricating a blind via array corresponding to the scribe lines in the edge region of the front side of the wafer, wherein the depth of each blind via in the blind via array is greater than a first thickness; thinning the middle region of the back side of the wafer, fabricating a metal layer in the middle region of the thinned back side of the wafer, wherein the thickness of the middle region after the metal layer is fabricated is the first thickness; and grinding the edge region of the back side of the wafer to fully expose the blind via array in the edge region, forming a wafer back-side alignment mark appearing on the back side of the wafer. Thus, the fabricated wafer back-side alignment mark allows for the execution of processes including wafer dicing or wafer photolithography on the back side of the wafer, solving the problem of the lack of effective wafer back-side alignment marks in related technologies when performing related processes on the back side of the wafer.

[0062] Another aspect of this embodiment provides a wafer back alignment mark manufactured by the aforementioned wafer back alignment mark manufacturing method. The wafer back alignment mark can correspond to the dicing track on the front side of the wafer and can be displayed on the back side of the wafer, thereby being applicable to wafer-level packaging processes such as wafer back dicing or wafer back photolithography performed from the back side of the wafer.

[0063] This embodiment also provides a wafer back-side dicing method. Please refer to Figure 7, which shows a flowchart of the wafer back-side dicing method in one embodiment.

[0064] As shown in Figure 7, the wafer backside dicing method includes the following steps:

[0065] Step S201: Provide a wafer with dies and crisscrossing dicing channels arranged on the front side of the wafer.

[0066] Step S203: A blind via array corresponding to the scribe line is fabricated in the edge region of the front side of the wafer. In the blind via array, each scribe line includes at least two blind vias, and the depth of the blind vias is greater than the first thickness.

[0067] Step S205: Thin the middle region on the back side of the wafer and fabricate a metal layer in the middle region on the back side of the wafer after thinning. The thickness of the middle region after fabricating the metal layer is the first thickness.

[0068] Step S207: Grind the edge region on the back side of the wafer to fully expose the blind via array in the edge region and form a wafer back side alignment mark.

[0069] Step S209: Using the alignment marks on the back of the wafer, perform dicing from the back of the wafer.

[0070] In step S209, as shown in Figure 8, the exposed vias on the back side of wafer 100 are used as alignment marks on the back side of the wafer. By connecting the corresponding vias in the longitudinal and transverse positions to form straight lines, crisscrossing dicing marks 105 can be formed on the back side of wafer 100, which are consistent with the dicing tracks on the front side of wafer 100. Subsequently, these crisscrossing dicing marks 105 can be used to perform back-side dicing on the wafer, thereby cutting and separating the individual dies on the wafer.

[0071] This embodiment further provides a wafer back-side photolithography method. Please refer to Figure 9, which shows a flowchart of the wafer back-side photolithography method in one embodiment.

[0072] As shown in Figure 9, the wafer back-side photolithography method includes the following steps:

[0073] Step S301: Provide a wafer with dies and crisscrossing dicing channels arranged on the front side of the wafer.

[0074] Step S303: A blind via array corresponding to the dicing track is formed in the edge region of the front side of the wafer. In the blind via array, at least two blind vias are included for each dicing track, and the depth of the blind vias is greater than the first thickness.

[0075] Step S305: Thin the middle region on the back side of the wafer and fabricate a metal layer in the middle region on the back side of the wafer after thinning. The thickness of the middle region after fabricating the metal layer is the first thickness.

[0076] Step S307: Grind the edge region on the back side of the wafer to fully expose the blind via array in the edge region and form a wafer back side alignment mark.

[0077] Step S309: Photolithography is performed from the back of the wafer using alignment marks on the back side of the wafer.

[0078] Of course, the present disclosure also provides a method for fabricating a semiconductor device, wherein the semiconductor fabrication method includes the step of fabricating a wafer back alignment mark on a wafer using the aforementioned method for fabricating wafer back alignment marks.

[0079] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the protection scope of this disclosure.

Claims

1. A method for fabricating alignment marks on the back side of a wafer, characterized in that, Includes the following steps: A wafer is provided, wherein the front side of the wafer is provided with dies and crisscrossing dicing channels; An array of blind vias corresponding to the scribe lines is formed in the edge region of the front side of the wafer. In the blind via array, each scribe line includes at least two blind vias, and the depth of the blind vias is greater than the first thickness. The middle region of the back side of the wafer is thinned, and a metal layer is formed in the middle region of the thinned back side of the wafer, wherein the thickness of the middle region after forming the metal layer is a first thickness; and The edge region on the back side of the wafer is ground to fully expose the array of blind vias in the edge region, forming a wafer back side alignment mark that can be used for wafer dicing or photolithography on the back side of the wafer.

2. The method of claim 1, wherein Fabricating a blind via array corresponding to the scribe line in the edge region of the front side of the wafer includes: Along each dicing track, at least two blind vias are made in the edge region of the front side of the wafer.

3. The method of claim 1 or 2, wherein Blind holes are created in the edge region of the front side of the wafer by laser drilling or etching.

4. The method of claim 1, wherein the backside alignment mark is formed by a process comprising: The edge region is the area within 4 millimeters of the outer edge of the wafer.

5. The method of claim 1, wherein the backside alignment mark is formed by a process comprising: Fabricating a metal layer in the middle region of the back side of the thinned wafer includes depositing a metal layer in the patterned area on the back side of the wafer using a sputtering or evaporation process.

6. The method of claim 1, wherein After grinding the edge region on the back side of the wafer, the step height difference between the edge region and the middle region of the wafer is less than or equal to 10 micrometers.

7. A wafer backside alignment mark, characterized by, The wafer back alignment mark is fabricated on the wafer using the wafer back alignment mark fabrication method as described in any one of claims 1 to 6.

8. A wafer backside dicing method characterized by, Includes the following steps: A wafer back-side alignment mark is fabricated on a wafer using the method for fabricating wafer back-side alignment marks as described in any one of claims 1 to 6; and The wafer is diced using the alignment marks on the back side of the wafer.

9. A wafer backside lithography method, characterized by, Includes the following steps: A wafer back-side alignment mark is fabricated on a wafer using the method for fabricating wafer back-side alignment marks as described in any one of claims 1 to 6; and The wafer is photolithographically processed using the alignment marks on the back side.

10. A method of manufacturing a semiconductor device, characterized by, The method for fabricating the semiconductor device includes processing the wafer using the method for fabricating wafer backside alignment marks as described in any one of claims 1 to 6.

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