Semiconductor device and preparation method for semiconductor device

Abstract

A semiconductor device and a preparation method for a semiconductor device. The semiconductor device comprises a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bit line connection line, and a second bit line connection line. The first semiconductor structure comprises a sense amplifier circuit. The second semiconductor structure is connected to the first semiconductor structure by means of bonding, and comprises a first memory cell. The third semiconductor structure is connected to the second semiconductor structure by means of bonding, and comprises a second memory cell. The first bit line connection line is associated with the first memory cell, and the second bit line connection line is associated with the second memory cell. The first bit line connection line and the second bit line connection line are comparatively coupled to each other by means of the sense amplifier circuit, and a length difference between the first bit line connection line and the second bit line connection line is less than or equal to 2 microns. The coupling capacitance between adjacent bit lines can be reduced, cross-talk resilience can be improved, the time delay difference between signal transmissions can be reduced, and the stability and reliability of the device can be improved.

Description

Semiconductor devices and methods for fabricating semiconductor devices

[0001] This application claims priority to Chinese Patent Application No. 202411455777.7, filed on October 18, 2024, entitled "Semiconductor Device and Method for Fabrication of Semiconductor Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of integrated circuit technology, and in particular to a semiconductor device and a method for fabricating a semiconductor device. Background Technology

[0003] Recently, with the increasing multifunctionality of information and communication devices, there is a need or expectation for high-density, high-capacity, and highly integrated storage devices. This has led to the proposal to use vertical-channel transistors to increase storage device density, and to vertically stack multiple layers of storage devices to improve capacity and integration.

[0004] However, vertically stacked memory architectures may require complex and crowded wiring designs to connect memory cells to logic control circuits, such as sense amplifier circuits. Two bit lines coupled to each other in the same sense amplifier circuit may have different signal transmission time delays due to differences in length. Especially in high-speed circuits, even small differences can lead to data read errors, affecting the stability and reliability of the circuit. Summary of the Invention

[0005] Based on this, the present application provides a semiconductor device and a method for fabricating a semiconductor device, which has the advantages of high density, high capacity and high integration, small length difference between two bit lines coupled in the same sensing amplifier circuit, and strong anti-interference ability.

[0006] In a first aspect, this application provides a semiconductor device according to some embodiments, characterized in that it comprises:

[0007] A first semiconductor structure, the first semiconductor structure including a sense amplifier circuit;

[0008] A second semiconductor structure is connected to the first semiconductor structure by bonding, and the second semiconductor structure includes a first memory cell.

[0009] A third semiconductor structure is connected to the second semiconductor structure by bonding, and the third semiconductor structure includes a second memory cell;

[0010] The first bit line connection line is associated with the first memory cell.

[0011] The second bit line connection line is associated with the second memory cell;

[0012] The first bit line connection and the second bit line connection are comparatively coupled to each other through the sense amplifier circuit;

[0013] The length difference between the first bit line connecting line and the second bit line connecting line is less than or equal to 2 micrometers.

[0014] In some embodiments, the first memory cell includes a first memory array and a second memory array, wherein the first memory array and the second memory array are on the same horizontal plane;

[0015] The second memory cell includes a third memory array and a fourth memory array, which are on the same horizontal plane;

[0016] The third storage array is close to the first storage array, and the fourth storage array is close to the second storage array.

[0017] In some embodiments, the first bit line connection is associated with the first memory array;

[0018] The second bit line connection is associated with the third memory array.

[0019] In some embodiments, the first bit line connection is associated with the first memory array;

[0020] The second bit line connection is associated with the fourth memory array.

[0021] In some embodiments, the first memory cell includes a first bit line, a first transistor, and a first capacitor, wherein the first capacitor, the first transistor, and the first bit line are stacked along a direction perpendicular to the second semiconductor structure.

[0022] The second memory cell includes a second bit line, a second transistor, and a second capacitor, wherein the second bit line, the second transistor, and the second capacitor are stacked along a direction perpendicular to the third semiconductor structure;

[0023] The first bit line connection line is connected to the first bit line;

[0024] The second bit line connection line is connected to the second bit line.

[0025] In some embodiments, the second semiconductor structure includes a side adjacent to the first semiconductor structure and a side adjacent to the third semiconductor structure;

[0026] The third semiconductor structure includes a side close to the second semiconductor structure and a side away from the second semiconductor structure;

[0027] The first bit line is located on the side of the second semiconductor structure closest to the third semiconductor structure;

[0028] The second bit line is located on the side of the third semiconductor structure closest to the second semiconductor structure.

[0029] In some embodiments, the first semiconductor structure further includes a first interconnect structure located on the side of the first semiconductor structure close to the second semiconductor structure, the first interconnect structure being connected to a sensing amplifier circuit and bonded to the second semiconductor structure;

[0030] The second semiconductor structure further includes a second interconnect structure located on the side of the second semiconductor structure close to the first semiconductor structure, and the second interconnect structure is bonded to the first semiconductor structure;

[0031] The second semiconductor structure further includes a third interconnect structure, the third interconnect structure including a first through connector, a first bit line connector and a first contact, the first through connector being connected to the second interconnect structure, the first bit line connector being connected to the first bit line and the first through connector respectively, and the first contact being located on the side of the second semiconductor structure close to the third semiconductor structure, being connected to the first through connector and bonded to the third semiconductor structure;

[0032] The third semiconductor structure further includes a fourth interconnect structure, which includes a second through connector, a second bit line connector, and a second contact. The second contact is located on the side of the third semiconductor structure close to the second semiconductor structure and is bonded to the first contact. The second bit line connector is connected to the second bit line and the second contact, respectively. The second through connector is connected to the second contact.

[0033] In some embodiments, the positions where the multiple first bit line connectors connect to the multiple first bit lines are staggered;

[0034] The positions where the multiple second bit line connectors connect to the multiple second bit lines are staggered.

[0035] In some embodiments, the effective length of the first bit line connector is equal to the effective length of the second bit line connector coupled to the same sense amplifier circuit.

[0036] In some embodiments, the third semiconductor structure further includes a lead-out structure located on the side of the third semiconductor structure away from the second semiconductor structure and connected to the second through connector.

[0037] Secondly, according to some embodiments, this application also provides a method for fabricating a semiconductor device, comprising:

[0038] A first semiconductor structure is provided, and a sense amplifier circuit is formed in the first semiconductor structure;

[0039] A second semiconductor structure is provided, in which a first memory cell is formed;

[0040] A third semiconductor structure is provided, in which a second memory cell is formed;

[0041] A third semiconductor structure is formed on the second semiconductor structure by bonding.

[0042] A second semiconductor structure is formed on the first semiconductor structure by bonding.

[0043] A first bit line connection is formed, and the first bit line connection is associated with the first memory cell;

[0044] A second bit line connection is formed, which is associated with the second memory cell;

[0045] The first bit line connection and the second bit line connection are comparatively coupled to each other through the sense amplifier circuit;

[0046] The length difference between the first bit line connecting line and the second bit line connecting line is less than or equal to 2 micrometers.

[0047] In some embodiments, providing a first semiconductor structure includes:

[0048] A first substrate is provided, on which the sense amplifier circuit and the first interconnect structure are formed;

[0049] Forming the first memory cell in the second semiconductor structure includes:

[0050] A second substrate is provided, on which a first bit line, a first transistor, and a first capacitor are formed, the first bit line, the first transistor, and the first capacitor being stacked in the vertical direction;

[0051] Forming a second memory cell in the third semiconductor structure includes:

[0052] A third substrate is provided on which a second bit line, a second transistor, and a second capacitor are formed, the second bit line, the second transistor, and the second capacitor being stacked in the vertical direction.

[0053] In some embodiments, forming a third semiconductor structure on the second semiconductor structure by bonding includes:

[0054] A first carrier disk and a second carrier disk are formed on the second semiconductor structure and the third semiconductor structure, respectively;

[0055] Flip the second semiconductor structure and the third semiconductor structure, and remove the second substrate and the third substrate;

[0056] A first wire connector and a first contact are formed in the second semiconductor structure;

[0057] A second bit line connector and a second contact are formed in the third semiconductor structure;

[0058] The second semiconductor structure is flipped to bond the second semiconductor structure and the third semiconductor structure.

[0059] In some embodiments, forming a second semiconductor structure on the first semiconductor structure by bonding includes:

[0060] Remove the first carrier disk and form a first through connector and a second interconnect structure in the second semiconductor;

[0061] The second semiconductor structure is flipped to bond the second semiconductor structure to the first semiconductor structure.

[0062] In some embodiments, after the second semiconductor and the first semiconductor structure are bonded, the structure further includes:

[0063] Remove the third carrier disk and form a second through connector and lead-out structure in the third semiconductor structure.

[0064] The semiconductor structure and its fabrication method provided in this application have at least the following beneficial effects:

[0065] The semiconductor device and its fabrication method provided in this application, wherein the first semiconductor structure, the second semiconductor structure and the third semiconductor structure are vertically stacked in the semiconductor device, which can improve the storage density and integration of the semiconductor device. The two bit lines coupled to each other in the same sensing amplifier circuit are respectively associated with the second memory cell and the third memory cell, which can reduce the coupling capacitance of adjacent bit lines and improve the anti-crosstalk capability. At the same time, the length difference of the connection line of the two bit lines is less than or equal to 2 micrometers, which can effectively prevent different signal transmission time delays and improve the stability and reliability of the circuit. Attached Figure Description

[0066] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0067] Figure 1 is a schematic cross-sectional view of a semiconductor device provided in an embodiment of this application;

[0068] Figure 2 is a schematic cross-sectional view of another semiconductor device provided in an embodiment of this application;

[0069] Figure 3 is a schematic diagram of a partially enlarged cross-sectional view of the semiconductor structure described in Figure 1;

[0070] Figure 4 is a simplified three-dimensional schematic diagram of a portion of the semiconductor structure described in Figure 1;

[0071] Figures 5A, 5B, 5C, 6A, 6B, 7A, 7B, 8 and 9 illustrate a manufacturing process for forming the semiconductor structure shown in Figure 3 according to an embodiment of this application.

[0072] Explanation of reference numerals in the attached figures: 101: First substrate; 102, 102A, 120B: Sensing amplifier circuit; 103, 103A, 103B: First interconnect structure; 1: First semiconductor structure; 201: Second substrate; 2021: First bit line; 2022: First transistor; 2023: First capacitor; 203: First carrier disk; 2041: First bit line connector; 2042: First contact; 2043: First through connector; 2044: Second interconnect structure; 2: Second semiconductor structure; 202A: First memory Array; 202B: Second memory array; 204A, 204B: First bit line connection; 301: Third substrate; 3021: Second bit line; 3022: Second transistor; 3023: Second capacitor; 303: Second carrier disk; 3041: Second bit line connector; 3042: Second contact; 3043: Second through connector; 305: Lead-out structure; 3: Third semiconductor structure; 302A: Third memory array; 302B: Fourth memory array; 304A, 304B: Second bit line connection. Detailed Implementation

[0073] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of this application more thorough and complete.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0075] It should be understood that when an element or layer is referred to as "on," "adjacent to," or "connected to," it may be directly on, adjacent to, or connected to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, a first doped region may be referred to as a second doped region, and similarly, a second doped region may be referred to as a first doped region; the first doped region and the second doped region are different doped regions.

[0076] Spatial relation terms such as “on top of” can be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, the element or feature described as “on top of” will be oriented “below” other elements or features. Therefore, the exemplary term “on top of” can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0077] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0078] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this application, thus allowing for the anticipation of variations in the shown shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.

[0079] Figure 1 is a schematic cross-sectional view of a semiconductor device provided in an embodiment of this application. In some embodiments, the semiconductor device includes a first semiconductor structure 1, a second semiconductor structure 2, a third semiconductor structure 3, first bit line connection lines 204A and 204B, and second bit line connection lines 304A and 304B. The first semiconductor structure 1 includes sense amplifier circuits 102A and 102B. The second semiconductor structure 2 is bonded to the first semiconductor structure 1 and includes first memory cells 202A and 202B. The third semiconductor structure 3 is bonded to the second semiconductor structure 2 and includes a second memory cell 302A. A, 302B, the first bit line connection lines 204A, 204B are associated with the first memory cells 202A, 202B, and the second bit line connection lines 304A, 304B are associated with the second memory cells 302A, 302B. The first bit line connection lines 204A, 204B and the second bit line connection lines 304A, 304B are coupled to each other through sense amplifier circuits 102A, 102B, and the length difference between the first bit line connection lines 204A, 204B and the second bit line connection lines 304A, 304B is less than or equal to 2 micrometers. The vertical stacking of the first semiconductor structure 1, the second semiconductor structure 2, and the third semiconductor structure 3 can improve the storage density and integration of semiconductor devices. The two bit lines coupled to each other in the same sensing amplifier circuit 102A, 102B are respectively associated with the second memory cell 202A, 202B and the third memory cell 302A, 302B. This can reduce the coupling capacitance of adjacent bit lines and improve the anti-crosstalk capability. At the same time, the length difference of the connection line between the two bit lines is less than or equal to 2 micrometers, which can effectively reduce the delay difference of signal transmission time and improve the stability and reliability of the circuit.

[0080] In some embodiments of this application, the first semiconductor structure 1, the second semiconductor structure 2, and the third semiconductor structure 3 are fabricated separately and then vertically stacked by wafer bonding, chip bonding, or chip-wafer bonding. The first substrate of the first semiconductor structure 1 can be a single-crystal silicon wafer, a polycrystalline silicon wafer, a germanium-silicon wafer, a sapphire wafer, a silicon carbide wafer, a silicon-on-insulator wafer, a germanium-on-insulator wafer, a glass wafer, a III-V compound wafer (e.g., silicon nitride or gallium arsenide), an oxide semiconductor wafer, or other wafers on which semiconductor devices are formed. In addition to forming a sense amplifier circuit, it can also form a word line driver circuit, a power supply circuit, a clock circuit, and various interface circuits and other control circuits. The second semiconductor structure 2 and the third semiconductor structure 3 respectively include first memory cells 202A and 202B and second memory cells 302A and 302B. In general, the second semiconductor structure 2 and the third semiconductor structure 3 can be interchanged. The names second semiconductor structure 2 and third semiconductor structure 3 are only for distinction and are not particularly limited. The substrates of the second semiconductor structure 2 and the third semiconductor structure 3 can be single-crystal silicon wafers, polycrystalline silicon wafers, germanium-silicon wafers, sapphire wafers, silicon carbide wafers, silicon-on-insulator wafers, germanium-on-insulator wafers, glass wafers, III-V compound wafers (such as silicon nitride or gallium arsenide), oxide semiconductor wafers, or other wafers with memory cells formed thereon. The memory cells can be dynamic random access memory (DRAM), ferroelectric memory, resistive random access memory (RRAM), magnetic random access memory (MRMH), or other memory cells. This application uses a dynamic random access memory cell as an example for illustration.

[0081] In some embodiments of this application, the first bit line connection lines 204A and 204B and the second bit line connection lines 304A and 304B are comparatively coupled to each other through the sense amplifier circuits 102A and 102B. The first bit line connection lines 204A and 204B and the second bit line connection lines 304A and 304B are conductive wirings connecting the bit lines and the sense amplifier circuits 102A and 102B. Their length is the shortest distance for charge transfer from the sense amplifier circuits 102A and 102B to the bit lines. The sense amplifier circuits 102A and 102B transmit the amplified signals to the bit lines through the bit line connection lines, thereby controlling the memory cells. The first bit line connection lines 204A and 204B are associated with the first memory cell, and the second bit line connection lines 304A and 304B are associated with the second memory cell. This reduces the coupling capacitance between adjacent bit lines and prevents signal crosstalk between adjacent bit lines, thereby improving signal integrity and reliability. The length difference between the first bit line connectors 204A and 204B and the second bit line connectors 304A and 304B is less than or equal to 2 micrometers, and can be 1.8 micrometers, 1.5 micrometers, 1.3 micrometers, 1 micrometer, 0.8 micrometers, or other values ​​less than 2 micrometers. The smaller the length difference, the smaller the time delay difference in signal transmission within the bit line connectors, resulting in a lower probability of data reading errors and improved circuit stability and reliability. The first bit line connectors 204A and 204B and the second bit line connectors 304A and 304B are formed by connecting multiple wiring layers, each segment being a conductive material, such as at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), or ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), and metal silicides. The materials used in each wiring layer can be the same or different.

[0082] Referring again to FIG1, in some embodiments, the first memory cell includes a first memory array 202A and a second memory array 202B, the first memory array 202A and the second memory array 202B being on the same horizontal plane. The second memory cell includes a third memory array 302A and a fourth memory array 302B, the third memory array 302A and the fourth memory array 302B being on the same horizontal plane. The first memory cell is located within a first semiconductor structure 2, and the second memory cell is located within a third semiconductor structure 3. The first memory array 202A and the second memory array 202B are stacked vertically with the third memory array 302A and the fourth memory array 302B. The third memory array 302A overlaps with the first memory array 202A vertically, and the fourth memory array 302B overlaps with the second memory array 202B vertically.

[0083] Referring again to FIG1, in some embodiments, a first bit connection 204A is led out from the sense amplifier circuit 102A and associated with the first memory array 202A; a second bit connection 304A, comparatively coupled to the first bit connection 204A, is led out from the sense amplifier circuit 102A and associated with the second memory array 302A; a first bit connection 204B is led out from the sense amplifier circuit 102B and associated with the first memory array 202B; and a second bit connection 304A, comparatively coupled to the first bit connection 204B, is led out from the sense amplifier circuit 102B and associated with the first memory array 202B. Bit line connection 304B is led out from the sensing amplifier circuit 102B and associated with the second memory array 302B. The third memory array 302A overlaps with the first memory array 202A in the vertical direction, and the fourth memory array 302B overlaps with the second memory array 202B in the vertical direction. The first bit line connection 202A and the second bit line connection 302A are arranged in parallel, and the first bit line connection 202B and the second bit line connection 302B are arranged in parallel. The bit line connection circuits in the second semiconductor structure 2 and the third semiconductor structure 3 can be fabricated using the same process, reducing manufacturing costs.

[0084] Figure 2 is a schematic cross-sectional view of another semiconductor device provided in an embodiment of this application. In some embodiments, the first bit connection line 204A is led out from the sense amplifier circuit 102A and associated with the first memory array 202A. The second bit connection line 304A, which is relatively coupled to the first bit connection line 204A, is led out from the sense amplifier circuit 102A and associated with the second memory array 302B. The first bit connection line 204B is led out from the sense amplifier circuit 102B and associated with the first memory array 202B. The second bit connection line 304A, which is relatively coupled to the first bit connection line 204B, is associated with the second memory array 302B. 04B is led out from the sensing amplifier circuit 102B and associated with the second memory array 302A. The third memory array 302A overlaps with the first memory array 202A in the vertical direction, and the fourth memory array 302B overlaps with the second memory array 202B in the vertical direction. The routing directions of the first bit line connection line 202A and the second bit line connection line 302A are different, and the routing directions of the first bit line connection line 202B and the second bit line connection line 302B are different. The second bit line connection lines 302A and 302B are arranged in a crisscrossing and detour within the third semiconductor structure 3, which can reduce the coupling effect of bit lines between adjacent memory arrays, improve anti-interference ability, and enhance the stability and reliability of semiconductor devices.

[0085] Figure 3 is a schematic diagram of a partially enlarged cross-sectional view of the semiconductor structure described in Figure 1. In some embodiments, the first memory cell includes a first bit line 2021, a first transistor 2022, and a first capacitor 2023, which are stacked vertically. The second memory cell includes a second bit line 3021, a second transistor 3022, and a second capacitor 3023, which are stacked vertically. The first bit line connection line is connected to the first bit line 2021, and the second bit line connection line is connected to the second bit line 3021. The first bit line 2021 is connected to the first transistor 2022 arranged perpendicular to the cross-sectional direction, and the second bit line 3021 is connected to the second transistor 3022 arranged perpendicular to the cross-sectional direction. The first bit line 2021 and the second bit line 3021 are made of materials with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) xThe transistors used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The first transistor 2022 and the second transistor 3022 are vertical channel transistors. The channel material can be one or more of the following semiconductor materials: silicon (Si), polycrystalline silicon (p-Si), amorphous silicon (a-Si), indium gallium zinc oxide (In-Ga-Zn-O, IGZO) multi-component compounds, zinc oxide (ZnO), ITO, titanium dioxide (TiO2), and molybdenum disulfide (MoS2). The gate can be a single-gate, double-gate, triple-gate, or ring-gate. The gate material is a conductive material, such as at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO2). x ), iridium (Ir), iridium oxide (IrO) x Materials include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The first capacitor 2023 and the second capacitor 3023 are used for information storage and can be cylindrical capacitors, box capacitors, barrel capacitors, blade capacitors, or other shaped capacitor structures. Similarly, capacitors can also be ferroelectric storage capacitors, phase-change memory, resistive switching memory, magnetic switching memory, and other types of storage units.

[0086] Referring again to Figure 3, in some embodiments, the second semiconductor structure 2 includes a side close to the first semiconductor structure 1 and a side close to the third semiconductor structure 3. The third semiconductor structure 3 includes a side close to the second semiconductor structure 2 and a side away from the second semiconductor structure 2. The first bit line 2021 is located on the side of the second semiconductor structure 1 close to the third semiconductor structure 3, and the second bit line 3021 is located on the side of the third semiconductor structure 3 close to the second semiconductor structure 2. The first semiconductor structure 1 and the second semiconductor structure 2 are stacked in such a way that the first bit line 2021 and the second bit line 3021 are as close in physical distance as possible. This helps to reduce the length difference between the first bit line connection line and the second bit line connection line that are relatively coupled to each other in the same sensing amplifier circuit, shortens the signal transmission time delay difference, and improves the stability and reliability of the circuit.

[0087] Referring again to FIG3, in some embodiments, the first semiconductor structure 1 further includes a first interconnect structure 103, which is located on the side of the first semiconductor structure 1 closest to the second semiconductor structure 2. The first interconnect structure 103 is connected to the sense amplifier circuit 102 and bonded to the second semiconductor structure 2. The second semiconductor structure 2 further includes a second interconnect structure 2044, which is located on the side of the second semiconductor structure 2 closest to the first semiconductor structure 1 and bonded to the first semiconductor structure 1. The second semiconductor structure 2 further includes a third interconnect structure, which includes a first through connector 2043, a first line connector 2041, and a first contact 2042. The first through connector 2043 is connected to the second interconnect structure 2044. The first line connector 2041 is connected to the first line 2021 and the first through connector 2043, respectively. The first contact 2042 is located on the side of the second semiconductor structure 2 closest to the third semiconductor structure 3, connected to the first through connector 2043, and bonded to the third semiconductor structure 3. The third semiconductor structure 3 also includes a fourth interconnect structure, which includes a second through connector 3043, a second bit line connector 3041, and a second contact 3042. The second contact 3042 is located on the side of the third semiconductor structure 3 close to the second semiconductor structure 2 and is bonded to the first contact 2042. The second bit line connector 3041 is connected to the second bit line 3021 and the second contact 3042 respectively. The second through connector 3043 is connected to the second contact 3042.

[0088] Referring again to Figure 3, in some embodiments, the first interconnect structure 103 is connected to the sense amplifier circuit 102 and then bonded to the second semiconductor structure 2. The first interconnect structure 103 may include a multilayer wiring structure, such as 2, 3, 4 or more layers. Through the first interconnect structure 103, peripheral circuits on the first semiconductor structure 1, such as the sense amplifier circuit 102, word line driver circuit, power supply circuit, clock circuit, and various interface circuits and other peripheral control circuits, can be connected to the second semiconductor structure 2 and the third semiconductor structure 3, thereby improving storage density and integration. The material of the first interconnect structure 103 is a conductive material, such as at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), and metal silicides. The materials used for each layer of wiring in the first interconnect structure 103 can be the same or different.

[0089] Referring again to Figure 3, in some embodiments, the second interconnect structure 2044 and the third interconnect structure including the first through connector 2043, the first line connector 2041, and the first contact 2042 are located within the second semiconductor structure 2. The second interconnect structure 2044 is located on the side of the second semiconductor structure 2 closest to the first semiconductor structure 1 and is connected to the first semiconductor structure 1 by bonding. The second interconnect structure 2044 may contain a multilayer wiring structure, such as 2 layers, 3 layers, 4 layers, or more. The control signals of the peripheral circuits in the first semiconductor structure 1 are transmitted to the second semiconductor structure 2 and the third semiconductor structure 3 through the second interconnect structure 2044. The material of the second interconnect structure 2044 is a material with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), and metal silicides. The materials used for each layer of wiring in the second interconnect structure 2044 can be the same or different. A first through-connector 2043 connects to the second interconnect structure 2044, transmitting control signals to the first bit line 2021, the gate of the first transistor 2022, and the third semiconductor structure 3. The length and material of the first through-connector 2043 are set as needed. The first bit connection line 2041 connects to the first bit line 2021 and the first through-connector 2043, respectively. A first contact 2042 is located on the side of the second semiconductor structure 2 closest to the third semiconductor structure 3, bonded to the third semiconductor structure, and connected to the first through-connector 2043 within the second semiconductor structure 2. This can include a multi-layer wiring structure, such as 2, 3, 4, or more layers. The materials of the first through connector 2043, the first line connector 2041, and the first contact 20424 are conductive materials, such as at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The materials of the first through connector 2043, the first line connector 2041, and the first contact 2042 can be the same or different.

[0090] Referring again to Figure 3, in some embodiments, the second contact 3042 is located on the side of the third semiconductor structure 3 closest to the second semiconductor structure 2 and is bonded to the first contact 2042. The second contact 3042 may contain a multilayer wiring structure, such as 2, 3, 4 or more layers. Control signals from the peripheral circuits in the first semiconductor structure 1 are transmitted to the third semiconductor structure 3 through the second contact 3042. The material of the second contact 3042 is a conductive material, such as at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), and metal silicides. The material of each layer of wiring in the second contact 3042 can be the same or different. The second bit line connector 3041 is connected to the second bit line 3021 and the second contact 3042 respectively, and performs signal control on the second bit line 3021. The second through connector 3043 is connected to the second contact 3042 and can connect the second transistor 3022 and the second capacitor 3023. The materials of the second contact 3042, the second bit line connector 3041, and the second through connector 3043 are conductive materials, such as at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The materials of the second contact 3042, the second bit line connector 3041, and the second through connector 3043 can be the same or different.

[0091] Referring again to Figure 3, in some embodiments, the third semiconductor structure 3 further includes a lead-out structure 305, located on the side of the third semiconductor structure 3 away from the second semiconductor structure 2, and connected to the second through-connector 3043. The lead-out structure 305, connected to the second through-connector 3043, allows power or other control signals from outside the semiconductor device to be transmitted to the peripheral control circuit via the second through-connector 3043, the second contact 3042, the first contact 2042, the first through-connector 2043, the second interconnect structure 2044, and the first interconnect structure 103. The peripheral control circuit then transmits control signals to the memory array via the first interconnect structure 103, the second interconnect structure 2044, the first through-connector 2043, the first bit line connector 2041, the first contact 2042, the second contact 3042, and the second bit line connector 3041. The lead-out structure 305 can be a single layer or multiple layers. The material of the lead-out structure 305 is a conductive material, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), metal silicides, etc.

[0092] Referring again to Figure 3, and in conjunction with Figures 1 and 2, in some embodiments, the first bit line connecting lines 204A and 204B include a first interconnect structure 103, a second interconnect structure 2044, a first through connector 2043, and a first bit line connector 2041; the second bit line connecting lines 304A and 304B include a first interconnect structure 103, a second interconnect structure 2044, a first through connector 2043, a first contact 2042, a second contact 3042, and a second bit line connector 3041. In some embodiments, the first bit connection lines 204A and 204B include a second interconnect structure 2044, a first through connector 2043, and a first bit connector 2041; the second bit connection lines 304A and 304B include a second interconnect structure 2044, a first through connector 2043, a first contact 2042, a second contact 3042, and a second bit connector 3041. That is, the first bit connection lines 204A and 204B and the second bit connection lines 304A and 304B are only located in the conductor portions of semiconductor structure 2 and semiconductor structure 3. The length difference between the first bit line connecting lines 204A and 204B and the second bit line connecting lines 304A and 304B can be understood as the optimal conductive length of the first contact 2042 and the second contact 3042. Since the first contact 2042 and the second contact 3042 are connected together by bonding, the conductive length is relatively short, which can effectively reduce the length difference between the first bit line connecting lines 204A and 204B and the second bit line connecting lines 304A and 304B, shorten the time delay difference of signal transmission, and improve the stability and reliability of the circuit.

[0093] Figure 4 is a simplified, three-dimensional schematic diagram of a portion of the semiconductor structure described in Figure 1. In some embodiments, the second semiconductor structure 2 and the third semiconductor structure 3 are stacked to improve storage density. The second semiconductor structure 2 includes a first bit line 2021, a first transistor 2022, and a first capacitor 2023, which are stacked along a third direction (e.g., the Z direction). The second semiconductor structure 3 includes a second bit line 3021, a second transistor 3022, and a third capacitor 3023, which are stacked along a third direction (e.g., the Z direction). A first bit line connection 204A is connected to the first bit line 2021 via a first bit line connector 2041, and a second bit line connection 304A is connected to the second bit line 3021 via a second bit line connector 3041.

[0094] Referring again to Figure 4, in some embodiments, multiple first bit lines 2021 extend along a first direction (e.g., the X direction) and are spaced apart along a second direction (e.g., the Y direction). Multiple first bit line connectors 2041 are correspondingly connected to the first bit lines 2021, and the connection positions are staggered in the first direction (e.g., the X direction). This can increase the process window of the first bit line connectors 2041 and reduce the coupling effect between the first bit line connectors 2041, thereby improving the stability and reliability of the circuit. Similarly, multiple second bit lines 3021 extend along a first direction (e.g., the X direction) and are spaced apart along a second direction (e.g., the Y direction). Multiple second bit line connectors 3041 are correspondingly connected to the second bit lines 3021, and the connection positions are staggered in the first direction (e.g., the X direction). By comparing the positions where the first bit line connector 2041 and the first bit line 2021 are connected and the positions where the second bit line connector 3041 and the second bit line 3021 are connected in the same sensing amplifier circuit, if they overlap in the vertical direction (e.g., the Z direction), or if the lengths of the first bit line connector 2041 and the second bit line connector 3041 extending along the first direction (e.g., the X direction) are equal, the difference in length between the first bit line connector 204A and the second bit line connector 304A extending along the first direction (e.g., the X direction) can be minimized.

[0095] Figures 5A, 5B, 5C, 6A, 6B, 7A, 7B, 8, and 9 illustrate a manufacturing process for forming the semiconductor structure shown in Figure 3, according to an embodiment of this application. It should be understood that the operations shown in the manufacturing process method are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously or in a different order than that shown in the figures.

[0096] Referring to FIG. 5A, in some embodiments, a first substrate 101 is provided, on which a sensing amplifier circuit 102, a word line driver circuit, a power supply circuit, a clock circuit, and various interface circuits and other peripheral control circuits are formed, and a first interconnect line 103 is formed on the peripheral circuit. Referring to FIG. 5B and FIG. 5C, in some embodiments, a second substrate 201 and a third substrate 301 are provided, respectively, on which a first memory cell and a second memory cell are formed, respectively. The first memory cell includes a first bit line 2021, a first transistor 2022, and a first capacitor 2023, which are stacked in a vertical direction. The second memory cell includes a second bit line 3021, a second transistor 3022, and a second capacitor 3023, which are stacked in a vertical direction. The first substrate 101, the second substrate 201, and the third substrate 301 can be a single-crystal silicon substrate, a polycrystalline silicon substrate, a germanium-silicon substrate, a sapphire substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, a III-V compound substrate (such as silicon nitride or gallium arsenide), an oxide semiconductor substrate, or other substrates on which memory cells are formed. The first substrate 101, the second substrate 201, and the third substrate 301 can be the same or different. The first memory cell and the second memory cell are interchangeable and have no essential difference.

[0097] Referring to Figures 6A and 6B, in some embodiments, a first carrier disk 203 and a second carrier disk 303 are formed on the second semiconductor structure 2 and the third semiconductor structure 3, respectively. The first carrier disk 203 and the second carrier disk 303 can be a single-crystal silicon substrate, a polycrystalline silicon substrate, a germanium-silicon substrate, a sapphire substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, a III-V compound substrate (e.g., silicon nitride or gallium arsenide), an oxide semiconductor substrate, or other substrates on which memory cells are formed. The first carrier disk 203 and the second carrier disk 303 can be the same or different.

[0098] Referring to Figures 7A and 7B, in some embodiments, the second semiconductor structure 2 and the third semiconductor structure 3 are flipped, and the second semiconductor substrate 201 and the third semiconductor substrate 301 are cut and ground away to expose the first bit line 2021 and the second bit line 3021, respectively. A first bit line connector 2041 and a first contact 2042 are formed in the second semiconductor structure 2. The first bit line connector 2041 is connected to the bit line, and the first contact 2042 is connected to the first bit line connector 2041. A second bit line connector 3041 and a second contact 3042 are formed in the third semiconductor structure 3. The second bit line connector 3041 is connected to the second bit line 3021, and the second contact 3042 is connected to the second bit line connector 3041. The materials of the first wire connector 2041, the first contact 2042, the second wire connector 3041, and the second contact 3042 are conductive materials, such as at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The materials of the first line connector 2041, the first contact 2042, the second line connector 3041, and the second contact 3042 can be the same or different.

[0099] Referring to Figure 8, in some embodiments, the second semiconductor structure 2 is flipped to bond the second semiconductor structure 2 and the third semiconductor structure 3, i.e., the first contact 2042 and the second contact 3042 are connected by bonding. The first carrier disk 203 is removed, and a first through-connector 2043 and a second interconnect structure 2044 are formed in the second semiconductor structure 2. The first through-connector 2043 is connected to the first line connector 2041 and the first contact 2042, respectively, and the second interconnect structure 2044 is connected to the first through-connector 2043. The materials of the first through-connector 2043 and the second interconnect structure 2044 are materials with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), and ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The materials of the first through connector 2043 and the second interconnect structure 2044 can be the same or different.

[0100] Referring to Figure 9, in some embodiments, the bonding of the second semiconductor structure 2 and the third semiconductor structure 3 is flipped, so that the second semiconductor structure 2 is bonded to the first semiconductor structure 1, that is, the first interconnect structure 103 and the second interconnect structure 2044 are connected by bonding. The second carrier disk 303 is removed, and a second through connector 3043 and a lead-out structure 305 are formed in the third semiconductor structure. The second through connector 3043 is connected to the second contact 3042, and the lead-out structure 305 is located on the surface of the third semiconductor structure and connected to the second through connector 3043. The materials of the second through connector 3043 and the lead-out structure 305 are materials with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The materials of the second through connector 3043 and the lead-out structure 305 can be the same or different.

[0101] By using interconnect structures and through-connects in the second semiconductor structure 2 and the third semiconductor structure 3 respectively, the through-silicon via (TSV) process can be eliminated, reducing manufacturing complexity and resulting in semiconductor devices with smaller footprints and higher storage density. Furthermore, by cutting and grinding the back sides of the second and third semiconductor structures 2 and 3 to expose the bit lines, the overall thickness of the second and third semiconductor structures 3 is minimized. Bit line connectors and back-end interconnects are then formed on the bit lines, improving the integration density of the semiconductor device.

[0102] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0103] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor device, comprising: A first semiconductor structure (1) includes a sensing amplifier circuit (102); A second semiconductor structure (2) is connected to the first semiconductor structure (1) by bonding, and the second semiconductor structure (2) includes a first memory cell; A third semiconductor structure (3) is connected to the second semiconductor structure (2) by bonding, and the third semiconductor structure (3) includes a second memory cell; The first bit line connection (204A, 204B) is associated with the first memory cell; The second bit line connection (304A, 304B) is associated with the second memory cell; The first bit line connection (204A, 204B) and the second bit line connection (304A, 304B) are comparatively coupled to each other through the sense amplifier (102) circuit; The length difference between the first bit line connecting line (204A, 204B) and the second bit line connecting line (304A, 304B) is less than or equal to 2 micrometers.

2. The semiconductor device according to claim 1, wherein, The first memory unit includes a first memory array (202A) and a second memory array (202B), and the first memory array (202A) and the second memory array (202B) are on the same horizontal plane; The second memory unit includes a third memory array (302A) and a fourth memory array (302B), which are on the same horizontal plane; The third storage array (302A) is close to the first storage array (202A), and the fourth storage array (302B) is close to the second storage array (202B).

3. The semiconductor device according to claim 2, wherein, The first bit line connection lines (204A, 204B) are associated with the first memory array (202A); The second bit line connection (304A, 304B) is associated with the third memory array (302A).

4. The semiconductor device according to claim 2, wherein, The first bit line connection lines (204A, 204B) are associated with the first memory array (202A); The second bit line connection (304A, 304B) is associated with the fourth memory array (302B).

5. The semiconductor device according to any one of claims 1-4, wherein, The first memory cell includes a first bit line (2021), a first transistor (2022), and a first capacitor (2023), wherein the first capacitor (2023), the first transistor (2022), and the first bit line (2021) are stacked in a vertical direction; The second memory cell includes a second bit line (3021), a second transistor (3022), and a second capacitor (3023), which are stacked vertically. The first bit line connecting lines (204A, 204B) are connected to the first bit line (2021); The second bit line connecting lines (304A, 304B) are connected to the second bit line (3021).

6. The semiconductor device according to claim 5, wherein, The second semiconductor structure (2) includes a side close to the first semiconductor structure (1) and a side close to the third semiconductor structure (3); The third semiconductor structure (3) includes a side close to the second semiconductor structure (2) and a side away from the second semiconductor structure (2); The first bit line (2021) is located on the side of the second semiconductor structure (2) close to the third semiconductor structure (3); The second bit line (3021) is located on the side of the third semiconductor structure (3) close to the second semiconductor structure (2).

7. The semiconductor device according to claim 6, wherein, The first semiconductor structure (1) further includes a first interconnect structure (103), which is located on the side of the first semiconductor structure (1) close to the second semiconductor structure (2). The first interconnect structure (103) is connected to the sensing amplifier circuit (102) and bonded to the second semiconductor structure (2). The second semiconductor structure (2) further includes a second interconnect structure (2044), which is located on the side of the second semiconductor structure (2) close to the first semiconductor structure (1), and the second interconnect structure (2044) is bonded to the first semiconductor structure (1); The second semiconductor structure (2) further includes a third interconnect structure, which includes a first through connector (2043), a first bit line connector (2041), and a first contact (2042). The first through connector (2043) is connected to the second interconnect structure (2044). The first bit line connector (2041) is connected to the first bit line (2021) and the first through connector (2043) respectively. The first contact (2042) is located on the side of the second semiconductor structure (2) close to the third semiconductor structure (3), connected to the first through connector (2043), and bonded to the third semiconductor structure (3). The third semiconductor structure (3) further includes a fourth interconnect structure, which includes a second through connector (3043), a second bit line connector (3041), and a second contact (3042). The second contact (3042) is located on the side of the third semiconductor structure (3) close to the second semiconductor structure (2) and is bonded to the first contact (2042). The second bit line connector (3041) is connected to the second bit line (3021) and the second contact (3042) respectively. The second through connector (3043) is connected to the second contact (3042).

8. The semiconductor device according to claim 7, characterized in that, The positions where the multiple first bit line connectors (2041) and the multiple first bit lines (2021) are connected are staggered; The positions where the multiple second bit line connectors (3041) and the multiple second bit lines (3021) are connected are staggered.

9. The semiconductor device according to claim 7 or 8, wherein, The effective length of the first bit line connector (2041) is equal to the effective length of the second bit line connector (3041) coupled to the same sense amplifier circuit (102).

10. The semiconductor device according to claim 7, wherein, The third semiconductor structure (3) further includes a lead-out structure (305), which is located on the side of the third semiconductor structure (3) away from the second semiconductor structure (2) and is connected to the second through connector (3041).

11. A method for fabricating a semiconductor device, comprising: A first semiconductor structure (1) is provided, and a sense amplifier circuit (102) is formed in the first semiconductor structure (1); A second semiconductor structure (2) is provided, in which a first memory cell is formed; A third semiconductor structure (3) is provided, in which a second memory cell is formed; A third semiconductor structure (3) is formed on the second semiconductor structure (2) by bonding; A second semiconductor structure (2) is formed on the first semiconductor structure (1) by bonding; Form the first bit line connection (204A, 204B), which is associated with the first memory cell; A second bit line connection (304A, 304B) is formed, and the second bit line connection (304A, 304B) is associated with the second memory cell; The first bit line connection (204A, 204B) and the second bit line connection (304A, 304B) are comparatively coupled to each other through the sense amplifier circuit (102); The length difference between the first bit line connecting line (204A, 204B) and the second bit line connecting line (304A, 304B) is less than or equal to 2 micrometers.

12. The method for fabricating a semiconductor device according to claim 11, wherein, A first semiconductor structure (1) is provided, and a sense amplifier circuit (102) is formed in the first semiconductor structure (1), comprising: A first substrate (101) is provided, on which the sense amplifier circuit (102) and the first interconnect structure (103) are formed; Forming a first memory cell in the second semiconductor structure (2) includes: A second substrate (201) is provided, on which a first bit line (2021), a first transistor (2022) and a first capacitor (2023) are formed, wherein the first bit line (2021), the first transistor (2022) and the first capacitor (2023) are stacked in the vertical direction; Forming a second memory cell in the third semiconductor structure (3) includes: A third substrate (301) is provided, on which a second bit line (3021), a second transistor (3022), and a second capacitor (3023) are formed, the second bit line (3021), the second transistor (3022), and the second capacitor (3023) being stacked in the vertical direction.

13. The method for fabricating a semiconductor device according to claim 12, wherein forming a third semiconductor structure (3) on the second semiconductor structure (2) by bonding comprises: A first carrier disk (203) and a second carrier disk (303) are formed on the second semiconductor structure (2) and the third semiconductor structure (3), respectively; Flip the second semiconductor structure (2) and the third semiconductor structure (3) to remove the second substrate (201) and the third substrate (301); A first line connector (2041) and a first contact (2042) are formed in the second semiconductor structure (2); A second bit line connector (3041) and a second contact (3042) are formed in the third semiconductor structure (3); The second semiconductor structure (2) is flipped so that the second semiconductor structure (2) and the third semiconductor structure (3) are bonded.

14. The method for fabricating a semiconductor device according to claim 13, wherein forming a second semiconductor structure (2) on the first semiconductor structure (1) by bonding comprises: Remove the first carrier disk and form a first through connector (2043) and a second interconnect structure (2044) in the second semiconductor structure (2); The second semiconductor structure (2) is flipped so that the second semiconductor structure (2) and the first semiconductor structure (1) are bonded together.

15. The method for fabricating a semiconductor device according to claim 14, further comprising, after the second semiconductor structure (2) and the first semiconductor structure (1) are bonded: Remove the third carrier disk and form a second through connector (3043) and a lead-out structure (305) in the third semiconductor structure (3).

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