Method for planarization of optoelectronic arrangement and optoelectronic arrangement

Abstract

The invention concerns a method of planarization of an optoelectronic arrangement to achieve a homogeneously thinned layer of semiconductor material with a thickness in the sub-micrometer range between the active layer and the light emission surface. A protruding structure is thereby employed to demarcate the desired planarization depth. An optoelectronic arrangement processed using the described method is also disclosed.

Description

[0001] 2024PF00605

[0002] METHOD FOR PLANARIZATION OF OPTOELECTRONIC ARRANGEMENT AND OPTOELECTRONIC ARRANGEMENT

[0003] The present application claims priority from DE patent application DE 10 2024 130 053 . 1 dated October 16 , 2024 , the disclosure of which is incorporated herein by reference in its entirety . The present invention concerns a method for planarization of a doped semiconductor layer of an optoelectronic arrangement to obtain homogeneous layer thicknesses , in particular, thicknesses in the sub-micrometer range . The invention further concerns an optoelectronic arrangement manufactured using the disclosed method .

[0004] BACKGROUND

[0005] The light emission of a micro-LED ( pLED) critically depends on the geometrical design of the emitter . One of the crucial parameters is the distance between the emitting surface , typically either a multi- quantum-well layer or a pn-j unction, and the surface , typically an n- doped semiconductor layer . In thin-film LEDs this interface often needs to be thinned down from a thicker epi-stack . Further, thickness variations over the wafer due to process tolerances of the thinning process are problematic , as they result in non-uniform emission characteristics and device performance .

[0006] For example , for InGaN pLEDs configured to emit radiation comprising wavelengths within the blue and green regions of the electromagnetic spectrum, epi buffer layers are essential and cannot be omitted during device manufacture . Typical epitaxy thicknesses are in the order of 5 pm . For thin film pLEDs , these buffer layers need to be removed after wafer bonding to enhance light extraction properties . Final thicknesses lower than 500 nm are considered optimal . Homogeneous thinning of a 5 pm epitaxy stack on a full wafer to a suitable thickness , for instance , to 100 nm is highly challenging and requires a method suited for mass production .

[0007] It is an obj ect of the present application to provide a method and device design in which the thickness of the semiconductor can be precisely controlled, maintaining a monolithic emitter array, thus 2024PF00605 allowing production of highly efficient ]1LED arrays with enhanced light extraction efficiency, directed light emission and greater uniformity of device performance .

[0008] SUMMARY OF THE INVENTION

[0009] This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

[0010] The inventors propose a chemical mechanical planarization ( CMP ) method characterized by high-precision control of the amount of thinning and independent of the initial thickness of the epitaxial layer . The proposed method guarantees high homogeneity across the wafer . In the proposed method, protruding stop structures are used for CMP while maintaining a common n-side of single emitters . As a result , thinning of the semiconductor can be precisely controlled over the full wafer .

[0011] An additional advantage in the use of the protruding structures is that self-aligned optical outcoupling structures such as micro-lenses can be created on the semiconductor layers .

[0012] While the description of the invention contained herein presents an exemplary optoelectronic system with a specific design, the proposed method is generally applicable for monolithic pLED arrays of different structural design . Furthermore , the proposed method may be implemented in optoelectronic arrangements comprising optoelectronic devices having any desired material composition, including but not limited to semiconductor nitrides , phosphides and / or arsenides .

[0013] The proposed method comprises a step of providing a carrier substrate with a plurality of optoelectronic devices . In some aspects , the plurality of optoelectronic devices is epitaxially grown on a growth substrate and subsequently bonded to the carrier substrate using any suitable transfer and / or bonding process , after which the growth substrate is removed to expose a first doped layer of the plurality of optoelectronic devices . The carrier substrate is in some aspects provided with additional circuitry, depending on the desired application of the optoelectronic devices . In some aspects , the carrier 2024PF00605 substrate comprises a complementary metal oxide semiconductor ( CMOS ) wafer . In other aspects , the carrier substrate comprises a display substrate . The material , structure and dimensions of the carrier substrate is selected based on the desired functionality .

[0014] Each of the plurality of optoelectronic devices comprises a semiconductor mesa stack characterized by an active layer arranged between a first and a second doped semiconductor layer . Typically, the first doped layer , defined herein as a doped semiconductor layer arranged on a surface of the active layer facing away from the carrier substrate , comprises n-doped material , while the second doped layer , defined herein as a doped semiconductor layer arranged between the carrier substrate and the active layer , comprises p-doped material . The proposed principle is however not restricted to the aforementioned sequence of semiconductor layers within the mesa stack .

[0015] In some aspects of the proposed invention, the step of epitaxially growing the plurality of optoelectronic devices comprises an initial step of providing a growth substrate . The material selection and preparation of the growth substrate depends on the semiconductor material selected for the optoelectronic device structure . Typical growth substrates for epitaxial growth of nitride-based semiconductor devices include sapphire , silicon and bulk Il l-nitride compounds . The growth substrate is in some aspects subj ected to preparatory processes including but not limited to annealing, polishing , growth of buffer layers , and / or structuring .

[0016] In a subsequent step, a semiconductor layer stack is epitaxially grown on the growth substrate , said semiconductor layer stack comprising an active layer arranged between a first doped layer and a second doped layer . In some aspects , the active layer comprises a multi-quantum well structure , wherein alternate quantum well and quantum barrier layers comprising material characterized by different bandgap . In other aspects , the active layer comprises a PN-j unction formed between the first doped layer and the second doped layer . In some aspects , at least one of the first and / or second doped layer comprise a plurality of sublayers whose composition and structure is dependent on desired 2024PF00605 functionality . Such sublayers may include , for instance , current blocking layers , cladding layers , current spreading layers and so on . In some aspects , additional functional layers may be deposited on the semiconductor layer stack, including but not limited to transparent conductive oxide layers and protective layers .

[0017] Thereafter , a plurality of semiconductor mesa stacks is produced in the epitaxially grown semiconductor layer stack . Suitable wet and / or dry etching processes are applied to achieve desired mesa dimensions and geometry . The depth of etching is selected such that the resultant mesa sidewalls extend through the second doped layer and the active layer, and partially through the first doped layer . In particular , the first doped layer of the plurality of semiconductor mesa stacks comprises a plurality of physically isolated second regions adj acent to the active layer of each of the plurality of semiconductor mesa stacks , and a continuous first region of semiconductor material connecting the plurality of mesa stacks , such that the plurality of optoelectronic devices formed from the semiconductor layer stack is electrically connected through the continuous first region of the first doped layer .

[0018] In a subsequent step, at least one first electrically isolating, e . g . dielectric material is deposited on and around the plurality of semiconductor mesa stacks , enclosing the semiconductor mesa stacks and extending laterally to cover the exposed surface of the first region of the first doped layer . In this regard, the expression "dielectric" shall be used synonymously with the expressions "isolating" or "electrically isolating" if not noted otherwise . When using epitaxial regrowth as passivation, the regrown material is electrically isolating, e . g . due to a larger bandgap and the like , but may not necessarily consists of material usually referred to as dielectric material . Still , any dielectric material is also electrically isolating and the s killed person may choose the material with the appropriate electrical characteristics .

[0019] In some aspects , the first isolating, e . g . dielectric material forms a substantially uniform layer deposited by a process such as atomic layer 2024PF00605 deposition such that the semiconductor mesa stacks are enclosed . In other aspects , the first isolating , e . g . dielectric material is patterned to form specific geometrical profiles around the plurality of mesa stacks . Additionally, or alternatively, in some aspects a second dielectric material is deposited on the first dielectric material , patterned and etched such that isolated mesa stacks enclosed within material of the second dielectric material are laterally surrounded by exposed surfaces of the first isolating , e . g . dielectric material . Examples of geometric profiles include partially or fully inclined sidewalls , parabolic or otherwise curved sidewalls , stepped sidewalls , etc . The first isolating , e . g . dielectric material comprises , in some aspects , at least one of epitaxially regrown semiconductor layer, A12O3, AIN, HfO2, or any other material suitable for atomic layer deposition processes . The first isolating , e . g . dielectric material in some aspects comprises a layer with a thickness between 5 nm and 500 nm and in particular less than 200 nm for ALD processes . In case regrowth process is used, the thickness may range up to 500 nm . In other aspects , the first dielectric material comprises a plurality of sublayers of different materials . The second dielectric material may comprise SiO2, Nb2O5or any other suitable dielectric material . In particular, the second dielectric material is selected such that it can be selectively etched with respect to the first dielectric material , allowing formation of desired geometries along the mesa sidewalls without removing or otherwise damaging the first dielectric material .

[0020] In some aspects , a patterned mask is arranged on the surface of the plurality of semiconductor stacks prior to deposition of the first and optional second dielectric material , such that each of the plurality of semiconductor mesa stacks comprises at least one opening in the first and optional second dielectric material through which the second doped layer can be electrically contacted, and such that the semiconductor stack further comprises at least one opening in the first dielectric material through which a surface of the continuous first region of the first doped layer is exposed . Thereafter , an etching process , e . g . plasma or reactive ion etching, is conducted to form at least one cavity extending into the continuous first region of the 2024PF00605 first doped layer . In other aspects , an etching process is conducted after deposition of the first and the optional second dielectric material to facilitate electrical contact to the second doped layer and to form at least one cavity extending into the continuous first region of the first doped layer . The depth of the at least one cavity is substantially equal to a desired final thickness of the first doped layer after a subsequent thinning process , in particular, a thinning process involving chemical mechanical planarization (CMP ) . The depth of the at least one cavity is in some aspects less than 500 nm, and, in particular, less than 300 nm, and, more particularly, less than 100 nm .

[0021] The geometry and positioning of the at least one cavity extending into the continuous first region of the first doped region may take a variety of possible forms . In some aspects , the at least one cavity comprises a substantially uniform cross section, wherein in top view, the at least one cavity may comprise at least one of a circular , rectangular , square , diamond, annulus sector or other regular or irregular shape . In other aspects , the at least one cavity comprises a cross section that varies with height , wherein the at least one cavity may comprise inclined, parabolic, curved or stepped sidewalls , or combinations thereof .

[0022] Thereafter , at least one protruding structure is deposited in the at least one cavity extending into the continuous first region of the first doped layer . The height of the at least one protruding structure is such that the at least one protruding structure is at a vertical distance from the first dielectric layer . In particular, the height of the at least one protruding structure is less than the depth of the at least one cavity extending into the continuous first region of the first doped layer . Possible deposition methods include , but are not limited to sputtering or thermal evaporation .

[0023] The at least one protruding structure serves as a stop pillar during subsequent thinning of the first region of the first doped layer after removal of the growth substrate . The at least one protruding structure comprises a material different from the first doped layer, and 2024PF00605 comprises , m some aspects , at least one dielectric material including but not limited to SiO2, SiN, Si , Nb2O5and / or A12O3. In other aspects , the at least one protruding structure comprises at least one metallic material including but not limited to Au, Ni , Ti , Pt , Al , W and / or Ge . In some aspects , the at least one protruding structure comprises a plurality of sublayers comprising a plurality of materials , wherein the plurality of materials may comprise dielectric material , metallic material or a combination thereof .

[0024] In a subsequent step, at least one first electrical contact is deposited within the at least one cavity extending into the first region of the first doped semiconductor layer, and further extending through the at least one opening in the first dielectric material such that a surface of the first electrical contact facing away from the at least one protruding structure is vertically distanced from a surface of the first dielectric material facing away from the first doped layer . In particular , the at least one first electrical contact is arranged in contact with the at least one protruding structure . In some aspects , the at least one first electrical contact comprises a grid laterally adj acent to and / or surrounding at least some of the plurality of semiconductor mesa stacks .

[0025] In some aspects , a conductive reflective layer is arranged on a surface of the second dielectric to achieve improved light extraction characteristics . A dielectric fill material is deposited to laterally enclose and electrically isolate the plurality of semiconductor mesa stacks and part of the at least one first electrical contact extending through the first dielectric material . Thereafter , a surface of the dielectric fill material facing away from the first doped layer is patterned and a plurality of electrically isolated second electrical contacts are deposited to provide electrical contact to the second doped layer of each of the plurality of semiconductor mesa stacks . In other aspects , the surface of the dielectric fill material facing away from the first doped layer is thinned and planarized to expose a surface of the conductive reflective layer, such that the conductive reflective layer comprises the plurality of second electrical contacts . 2024PF00605

[0026] In some aspects comprising a conductive reflective layer , an additional sublayer of second dielectric material is deposited to laterally surround and enclose the conductive reflective layer prior to deposition of the dielectric fill material . In some such aspects comprising an additional sublayer of second dielectric material , the at least one first electrical contact is deposited such that it extends partially along sidewalls of laterally adj acent semiconductor mesa stacks comprising second dielectric material . Such a configuration is advantageous for achieving improved current spreading within the first electrical contact . An isolator is in some aspects arranged below the first electrical contact to enhance electrical isolation from the second electrical contacts of the plurality of optoelectronic devices .

[0027] The plurality of optoelectronic devices thus formed as a semiconductor layer stack comprising a plurality of semiconductor mesa stacks is thereafter bonded to the carrier substrate such that the plurality of second electrical contacts is arranged in contact with a plurality of corresponding third electrical contacts on a surface of the carrier substrate . Thereafter the growth substrate is removed .

[0028] In a subsequent step according to the proposed principle , the first region of the first doped layer is subj ected to a first planarization process at least to a depth corresponding to an upper surface of the at least one protruding structure , in particular , through a chemical mechanical planarization (CMP ) process . To achieve this , the protruding structure comprises a different material from the first doped layer , allowing its detection during the first planarization process . In some aspects , the at least one protruding structure is detected through monitoring of output power characteristics of the CMP apparatus during the first planarization process . Suitable design of the at least one protruding structure , in particular , the total cross-sectional area and positioning is necessary to ensure that the deviation in the output power occurring due to a transition from a surface consisting of material of the first doped layer to a surface further comprising material of the at least one protruding structure is detectable by the control system of the CMP apparatus . In other aspects , the presence of the at least one protruding structure at the upper surface of the first 2024PF00605 doped layer during the planarization process is alternatively or additionally detected through optical measurement .

[0029] In some aspects of the proposed method, subsequent to the first planarization process , the first region of the first doped layer is selectively etched such that the upper surface of the first doped layer is vertically below an upper surface of at least protruding structure , and vertically above an upper surface of the at least one first electrical contact . The first region of the first doped layer of the plurality of optoelectronic devices thus comprises a continuous , electrically connected sublayer , wherein the at least one first electrical contact is embedded within material of the first doped layer .

[0030] Subsequently, a third dielectric material is deposited on the upper surface of the first doped layer such that the at least one protruding structure is partially embedded in material of the first doped layer and partially embedded in material of the third dielectric material , wherein the upper surface of the at least one protruding structure is submerged below an upper surface of the third dielectric material . The third dielectric material comprises a material different from the at least one protruding structure , in particular , such that the at least one protruding structure is selectively etchable with respect to the third dielectric material . Suitable materials include but are not limited to SiOx, Nb2O5, TiOxand SiN . In some aspects , the third dielectric material is applied as a coating . Thereafter , a second planarization process is performed on the third dielectric material to a depth corresponding to the upper surface of the at least one protruding structure , such that the upper surface of the at least one protruding structure is coplanar with the upper surface of the third dielectric material .

[0031] In a next step according to some aspects of the proposed principle , a selective etching process is carried out to remove material of the at least one protruding structure , such that an upper surface of the at least one first electrical contact surface is exposed . Thereafter, in some aspects , the upper surface of the third dielectric material is rounded such that a curved profile is achieved . Such rounding may be 2024PF00605 accomplished by any suitable chemical or mechanical process , or combination thereof . A subsequent selective etching step is then performed to remove the third dielectric material and part of the first doped layer, such that the curved profile previously formed on the third dielectric material is transferred to the first doped layer . In some aspects , the etching depth is selected such that sidewalls of the at least one first electric contact are exposed, said sidewalls being surrounded by material of the first doped layer . In other aspects , the etching depth and curvature of the third dielectric material are selected such that sidewalls of the at least one first electric contact remain fully embedded within material of the first doped layer, and only the upper surface of the at least one first electric contact is exposed .

[0032] In other aspects of the proposed method, subsequent to the first planarization process , selective etching is carried out to remove material of the at least one first protruding structure , such that an upper surface of the at least one first electrical contact is exposed . Thereafter , a dry etching process is carried out , wherein the process parameters are selected to produce a plurality of inclined facets in the first region of the first doped layer . In particular , the dry etching process is carried out such that the first region of the first doped layer of each of the plurality of optoelectronic devices comprises inclined sidewalls , said inclined sidewalls extending vertically from an upper surface of the first doped layer to a plane corresponding to an upper surface of the at least one first electrical contact . The etching depth is limited to ensure that the first doped layer of the plurality of optoelectronic devices remains physically and electrically connected, forming a substantially continuous surface punctuated by the at least one first electrical contact . A subsequent etching process is performed, with parameters selected to produce a desired profile for an outcoupling optical structure , in particular , a rounded shape . In some aspects , the subsequent etching process involves coating the upper surface of the first doped layer comprising inclined sidewalls with a third dielectric material , which is subj ected to a structuring process , for example , a rounding process to produce a desired curvature . The said rounding process may be achieved by any 2024PF00605 suitable chemical or mechanical process , or combination thereof . In some aspects , the structured third dielectric material forms at least one outcoupling structure . In other aspects , a subsequent etching process is conducted to remove the third dielectric material and part of the first doped layer , transferring the structured, in particular , curved profile from the third dielectric material to the first doped layer, thereby forming at least one outcoupling structure within the first doped layer .

[0033] In some aspects of the proposed method, the at least one protruding structure comprises a plurality of regions comprising a plurality of materials with different mechanical characteristics , wherein a first region of the at least one protruding structure is arranged in contact with the at least one first electrical contact , and subsequent regions are arranged in a vertical stack such that a vertical cross section comprises a sequence of sublayers comprising a plurality of materials . In such aspects , a plurality of planarization and / or etching processes may be performed to thin, shape and / or structure the first doped layer , with a top surface of at least some regions of the at least one protruding structure being used to control the termination of at least one of the plurality of planarization and / or etching processes . In some aspects , the different regions of the at least one protruding structure are used to trigger adj ustments in process parameters during at least one planarization process . Such adj ustments may be necessary to avoid damage to the optoelectronic device as the thickness of the first doped layer is reduced, in particular, as the overall thickness of the first doped layer is reduced below the micrometer range . Implementation of at least one of the planarization processes as a plurality of steps in the above described manner may additionally be advantageously used for other purposes , for example , to facilitate in-process inspection at critical thicknesses , thereby allowing repeatable and controllable scheduling of quality control measures during thinning of the first doped layer , or for coordination of surface structuring processes requiring a multi-step approach .

[0034] In some aspects , at least part of the at least one protruding structure in contact with the at least one first electrical contact is retained 2024PF00605 m the processed semiconductor stack . The cross-sectional area of the retained part of the at least one protruding structure is in some aspects smaller than the cross-sectional area of the at least one first electrical contact to facilitate electrical connection to the first doped layer . The retained region of the at least one protruding structure is in some aspects used in positioning and / or alignment of at least one outcoupling structure along the direction of light emission of the plurality of optoelectronic devices . Such outcoupling structures include but are not limited to optical lenses , photonic crystals , optical filters , wavelength converters and so on . The alignment of such outcoupling structures may involve formation of corresponding cavities in the outcoupling structures for positioning and alignment of the outcoupling structures in relation to the upper surface of the first doped layer . In other aspects , alignment is achieved by using the at least one protruding structure for demarcating lateral boundaries , allowing positioning and alignment of outcoupling structures without formation of corresponding cavities therein .

[0035] Further aspects of the proposed invention relate to an optoelectronic arrangement . In some aspects , the optoelectronic arrangement comprises a carrier substrate comprising a plurality of electrical contact surfaces on which a plurality of optoelectronic devices is arranged . The plurality of optoelectronic devices comprises a plurality of semiconductor mesa stacks , wherein each of the plurality of semiconductor mesa stacks comprises a second doped layer, an active layer and a second region of a first doped layer surrounded by a first dielectric material which forms the mesa sidewalls . The first dielectric material further extends laterally to surround each of the plurality of semiconductor mesa stacks . The plurality of semiconductor mesa stacks each further comprise a first region of a first doped layer which is physically and electrically connected to corresponding first regions of a first doped layer of laterally adj acent semiconductor mesa stacks , thereby resulting in a substantially continuous first region of the first doped layer , wherein at least part of the first region of the first doped layer is in contact with the first dielectric .

[0036] SHORT DESCRIPTION OF THE DRAWINGS 2024PF00605

[0037] Further aspects and embodiments in accordance wrth the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which

[0038] Figure 1 shows an exemplary optoelectronic arrangement in accordance with some aspects of the proposed principle ;

[0039] Figure 2 illustrates a step in a method for processing an optoelectronic arrangement in accordance with some aspects of the proposed principle ;

[0040] Figure 3 illustrates a step in a method for processing an optoelectronic arrangement in accordance with some aspects of the proposed principle ;

[0041] Figures 4A to 4G show some exemplary configurations of optoelectronic arrangements during a processing step in some aspects of the proposed method;

[0042] Figure 5 illustrates a top view of an optoelectronic arrangement during a processing step in accordance with some aspects of the proposed method;

[0043] Figures 6A to 6G and Figures 7A to 7G illustrate cross-sectional views along different planes shown in Figure 5 during exemplary steps in a method for processing an optoelectronic arrangement according to some aspects of the proposed principle ;

[0044] Figures 8A to 8E illustrate steps in the processing of an optoelectronic device according to some aspects of the proposed method;

[0045] Figure 9 illustrates an intermediate processing step during a processing step according to some aspects of the proposed method .

[0046] DETAILED DESCRIPTION

[0047] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can 2024PF00605 14 be displayed enlarged or reduced in size to emphasize individual aspects. It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado, without this contradicting the principle according to the invention. Some aspects show a regular structure or form. It should be noted that in practice slight differences and deviations from the ideal form may occur without, however, contradicting the inventive idea.

[0048] In addition, the individual figures and aspects are not necessarily shown in the correct size, nor do the proportions between individual elements have to be essentially correct. Some aspects are highlighted by showing them enlarged. However, terms such as "above", "over", "below", "under" "larger", "smaller" and the like are correctly represented with regard to the elements in the figures. So it is possible to deduce such relations between the elements based on the figures .

[0049] In Figure 1, an optoelectronic arrangement processed according to an aspect of the proposed method is illustrated. The optoelectronic arrangement comprises a plurality of optoelectronic devices (100) arranged on a carrier substrate (200) . Each of the plurality of optoelectronic devices (100) comprises a semiconductor mesa stack (130) having a first doped layer (102) , an active layer (103) and a second doped layer (104) . The first doped layer (102) comprises a first region (102a) and a second region (102b) . The first doped layer (102) comprises a thickness less than 1 pm, in particular, less than 800 nm, and more particularly, less than 500 nm. However, in some aspects, the first doped layer (102) comprises a larger thickness, up to 5pm. when using certain techniques during the etching process, a minimum thickness of about 10 nm to 15 nm can be achieved. A first electrical contact (108) is arranged in contact with the first region (102a) of the first doped layer. In some aspects the first electrical contact (108) laterally surrounds each of the plurality of semiconductor stacks (130) at least partly, forming an interrupted grid structure. The second doped layer (104) , the active layer (103) and the second region (102b) of the first doped layer (102) form a semiconductor mesa stack. A first isolating 2024PF00605 layer, e.g. dielectric (112) , is arranged along the sidewalls and bottom of the semiconductor mesa stack (130) and extends laterally outwards to surround the mesa stack. In the illustrated aspect, at least some of the plurality of optoelectronic devices further comprise a transparent conductive oxide layer (105) . The bottom surface of the first dielectric comprises an opening through which an electrical connection to the second doped layer (104) can be achieved. A second isolating layer, e.g. dielectric material (111) , is arranged in contact with the first isolating layer (112) along the bottom and sidewalls of the mesa stack (130) . The second isolating layer in some aspects comprises inclined sidewalls. In other aspects, not herein illustrated, the second isolating layer comprises curved, parabolic or stepped sidewalls, or combinations thereof. A conductive reflective layer (106) is arranged on the surface of the second isolating layer, or a third isolating layer which is placed on the surface of the second isolating layer, following the profile of the sidewalls thereof. In this way, emission characteristics of the optoelectronic devices can be enhanced. The conductive reflective material (106) is via the TCO layer (105) additionally electrically connected to the second doped layer (104) . A second electrical contact (107) is in some aspects arranged on a surface of the conductive reflective layer (106) facing away from the active layer (103) , and in contact with one of the plurality of interconnection electrodes (201) in the carrier substrate (200) . The second doped layer (104) is thereby electrically contacted via a second electrical contact comprising at least one of the second electrical contact (107) and / or the conductive reflective layer (106) and / or the TCO layer (105) . A dielectric fill material (110) is arranged surrounding each of the plurality of semiconductor mesa stacks, enhancing electrical isolation between adjacent semiconductor mesa stacks.

[0050] Figure 2 illustrates some aspects of a method of processing an optoelectronic arrangement in accordance with the proposed principle. An optoelectronic device (100) arranged on a carrier substrate (200) is provided. The first doped layer (102) of the optoelectronic device is to be thinned and planarized to a depth Dpi, such that an upper surface of the first doped layer (102) corresponds to a desired planarization plane (121) . To achieve the desired depth of 2024PF00605 16 planarization substantially homogeneously over the entire surface of the first doped layer, at least one protruding structure (109) is provided, said protruding structure embedded within the first doped layer, and comprising a height DP2and a width WP. The at least one protruding structure (109) is arranged on an upper surface of the first electrical contact (108) , said first electrical contact being embedded partially within the first doped layer (102) to a first depth d2and partially within the dielectric fill material (110) to a second depth d2. The first electrical contact (108) comprises a width Wc, which is in some aspects smaller than the widthPof the at least one protruding structure. In particular, in some aspects, the at least one protruding structure (109) comprises at least one lateral dimensionPwhich is smaller than at least one corresponding lateral dimension Wcof the first electrical contact. In some aspects, the sidewalls of the first electrical contact are tapered, such that at least one lateral dimension of the first electrical contact increases with decreasing distance from the carrier substrate. The height DP2of the at least one protruding structure (109) and the first depth d2to which the first electric contact is embedded within the first doped layer are suitably selected, in particular, where the proposed method is used to process an optoelectronic arrangement with a curved top surface, as illustrated in Figure 1. Furthermore, in aspects where the at least one protruding structure (109) is retained within the optoelectronic arrangement, for instance, to facilitate positioning and / or alignment of outcoupling structures, the dimensions DP2andPof the at least one protruding structure are selected to optimally achieve the desired functionality.

[0051] In some aspects of the proposed method, the first electrical contact (108) is arranged such that a first region of the first electrical contact embedded within the first region (102a) of the first doped layer comprises a smaller depth than a second region of the first electrical contact embedded within the dielectric fill material (110) . In some such aspects, the second dielectric material (111) comprises a first sublayer (Illa) and a second sublayer (111b) arranged to laterally enclose the conductive reflective layer (106) . The sidewalls of the second region of the first electrical contact (108) are in some such aspects arranged adjacent to and following the geometric 2024PF00605 configuration of the sidewalls of the second dielectric material (111) . In other aspects, the second dielectric material (111) and the first electric contact (108) are separated by dielectric fill material (110) .

[0052] A variety of positioning and geometric configuration options for the at least one protruding structure are presented in Figures 4A to 4G. In figure 4A, one protruding structure (109) is centrally positioned between four optoelectronic devices (100) arranged in a square grid formation. The protruding structure (109) comprises a circular crosssection. The cross-sectional area and material of the protruding structure are configured to allow detection of the presence of the protruding structure at an upper surface of the first doped layer of the optoelectronic device (100) during a planarization process.

[0053] In other aspects, a plurality of protruding structures (109) is arranged between adjacent optoelectronic devices, as illustrated in Figures 4B and 4C, said plurality of protruding structures comprising rectangular cross-sections, as illustrated in Figure 4B, or circular cross-sections, as illustrated in Figure 4C. Figures 4A to 4C illustrate aspects of the proposed method comprising optoelectronic devices (100) with rectangular cross-sections. The proposed method is however not limited thereto, thus the plurality of optoelectronic devices may comprise at least one of a variety of cross-sections including but not limited to circular, hexagonal, triangular or diamond shapes .

[0054] Aspects comprising optoelectronic devices with a circular cross-section are illustrated in Figures 4D to 4G. Some such aspects, illustrated in Figures 4D and 4E comprise a protruding structure arranged between four surrounding optoelectronic devices, with the protruding structure comprising a circular and a diamond cross section respectively.

[0055] In some aspects, as shown in Figure 4F, the first electrical contact

[0056] (108) is deposited to form a ring-shaped structure surrounding each of the plurality of optoelectronic devices (100) , said ring-shaped structures being interconnected. The at least one protruding structure

[0057] (109) is then deposited to fill in the area between the connected ring- 2024PF00605 shaped structures forming the first electrical contact ( 109 ) . Such a configuration allows for greater surface area of the protruding structure , which enhances detection of the protruding structure during the planarization process . In some aspects , a plurality of protruding structures ( 109 ) is deposited in a specific pattern to allow formation of outcoupling structures in the optoelectronic device surface following further processing steps , in particular, etching processes .

[0058] In other aspects , as shown in Figure 4G, a plurality of protruding structures ( 109 ) is arranged to form annulus sectors laterally separated from the optoelectronic devices ( 100 ) by connected rings formed by the first electrical contact ( 108 ) .

[0059] Figures 6A to 6G and Figures 7A to 7G illustrate steps in the processing of an optoelectronic arrangement according to some aspects of the proposed principle . Figures 6A to 6G represent a sectional view along plane A-A through the at least one protruding structure ( 109 ) , shown in Figure 5 , whereas Figures 7A to 7G illustrate sectional views taken along plane B-B as shown in Figure 5 .

[0060] In Figures 6A and 7A, a plurality of optoelectronic devices arranged on a carrier substrate is illustrated . The plurality of optoelectronic devices comprises a substantially continuous first region ( 102a ) of a first doped layer ( 102 ) , within which at least one protruding structure ( 109 ) is embedded and laterally enclosed . The horizontal cross- sectional view shown in Figure 7A illustrates the substantially continuous first region ( 102a ) of the first doped layer . A first electrical contact ( 108 ) provides electrical connection to the plurality of optoelectronic devices through the connected first doped layer . A first planarization step, in particular , involving chemical mechanical planarization is performed on the first doped layer to achieve a predetermined distance hx2between the active layer ( 103 ) and the upper surface ( 121 ) of the first doped layer . The depth of planarization is dependent on the height of the protruding structure ( 109 ) , wherein the planarization process is configured to detect the presence of material of the protruding structure at an upper surface of the first doped layer . In some aspects , such detection is achieved 2024PF00605 19 by monitoring output power characteristics from the planarization apparatus, wherein the required output power for thinning and planarization is dependent on material characteristics of the surface being thinned. In other aspects, optical measurement approaches may alternatively or additionally be employed to detect the presence of the protruding structure (109) at the upper surface of the first doped layer, signalling the achievement of the desired depth of planarization .

[0061] In a subsequent step according to some aspects of the proposed method, a selective etching process is carried out, illustrated in Figures 6B and 7B. The etching process is configured to further reduce the thickness of the planarized surface such that an upper surface (122) of the first doped layer (102) is lower than an upper surface (123) of the at least one protruding surface (109) . The thickness of the first region of the first doped layer is however configured such that the first region of the first doped layer remains substantially continuous, with an upper surface (121) of the first doped layer being above an upper surface (124) of the first electrical contact (108) . In some aspects, the exposed part of the protruding structure (109) above the upper surface (122) of the first doped layer is used as for positioning and / or alignment of outcoupling structures arranged on the emission surface of the plurality of optoelectronic devices .

[0062] In other aspects, illustrated in Figures 6C and 7C, a third dielectric material (113) is deposited on the first doped layer, enclosing the at least one protruding structure. In some aspects, the third dielectric material comprises at least one of SiOx, Nb2O5, TiOxor SiN. In a subsequent step, illustrated in Figures 6D and 7D, the third dielectric material is subjected to a second planarization process, wherein the at least one protruding structure (109) is used to control the final thickness of the third dielectric material such that an upper surface (125) of the planarized third dielectric material is coplanar with an upper surface (123) of the protruding structure (109) . In some aspects, the planarized third dielectric material serves as an outcoupling structure, in particular, as an optical element. Additional elements, such as protective layers, optical filters, wavelength converters, and 2024PF00605 20 so on, may be deposited thereon m subsequent processes , depending on the desired application . The third dielectric material may also be structured to achieve specific emission characteristics and to enhance output performance of the optoelectronic arrangement .

[0063] In some aspects of the proposed method, a subsequent selective etching is performed to remove the at least one protruding structure , as illustrated in Figures 6E and 7E , such that an upper surface of the first electrical contact ( 108 ) is exposed . Subsequent to removal of the at least one protruding structure , structuring of the third dielectric material may be performed to achieve desired optical characteristics . Access to the first electrical contact ( 108 ) is achieved through a cavity ( 116 ) formed after removal of the at least one protruding structure . In particular , the upper surface of the third dielectric material is rounded in some aspects to form a curvature , as shown in Figure 6F . The geometry of the curvature is such that a cross section taken along plane A-A shown in Figure 5 comprises a smaller radius of curvature in comparison to a cross-section taken along plane B-B, such that an upper surface ( 126 ) of the rounded third dielectric material may appear planar, as shown in Figure 7 F, due to a significantly larger radius of curvature . The third dielectric material may in such aspects serve as an optical lens , wherein the positioning and alignment of the optical elements in relation to the optoelectronic devices is achieved through the at least one protruding elements . In other aspects , the third dielectric material serves as a structured template , allowing transfer of the desired geometric profile to the underlying first doped layer . In such aspects , a subsequent etching process is performed, removing the third dielectric material and transferring the curvature formed thereon to the first doped layer , such that the structured first doped layer forms the desired outcoupling structures , as illustrated in Figures 6G and 7G .

[0064] An alternative aspect related to processing of the proposed optoelectronic arrangement is illustrated in Figures 8A to 8E . In a first planarization step , illustrated in Figure 8A, the first doped layer ( 102 ) is subj ected to a planarization process wherein the planarization depth is configured such that an upper surface of the 2024PF00605 21 first doped layer is substantially coplanar with an upper surface of the at least one protruding structure ( 109 ) . In a subsequent step , shown in Figure 8B , a selective etching process is conducted to remove material of the at least one protruding structure ( 109 ) . Thereafter , a second etching process , in particular, a dry etching process , is conducted, wherein the process parameters may be configured to produce inclined facets , as illustrated in Figure 8C . In some aspects , a third dielectric material is deposited on the first doped layer, wherein the third dielectric material may be structured to form a structured upper surface , which in some aspects comprises a curvature , as illustrated in Figure 8D . This may be particularly advantageous where an optimal geometric profile for achieving the desired output performance comprises complex curvature which may be more reliably and more efficiently implemented through deposition of a dielectric coating . In other aspects , the coating additionally or alternatively serves as a protective layer . Alternatively, the third dielectric material may serve as a structured mas k, providing a template during a subsequent etching process , wherein the surface profile of the third dielectric material is transferred to the upper surface of the first doped layer , as shown in Figure 8E .

[0065] In other aspects , subsequent to the removal of the at least one protruding structure , as illustrated in Figure 8B , a dry etching process configured to produce a curved upper surface in the first doped layer is directly performed .

[0066] Figure 9 shows an embodiment of the at least one protruding structure according to the proposed principle , wherein the at least one protruding structure comprises a plurality of regions ( 109a, 109b ) along a vertical axis , wherein the plurality of regions comprises different materials . Multi-step planarization processes with different planarization depths ( 121a , 121b ) can thereby be implemented, wherein a first planarization depth ( 121a ) corresponds to an upper surface of a first region ( 109a ) of the at least one protruding structure , and at least one second planarization depth ( 121b ) corresponds to an upper surface of a second region ( 109b ) of the at least one protruding structure . In other aspects , the material of at least one second region 2024PF00605 22

[0067] ( 109b ) of the at least one protruding structure is selected such that optimal mechanical bonding characteristics between the at least one protruding structure and the first electrical contact ( 108 ) are achieved . Additionally, or alternatively, in aspects where the at least 5 one protruding structure is retained within the optoelectronic arrangement for positioning and / or alignment of at least one outcoupling structure , the material of at least one first region ( 109a ) of the at least one protruding structure is selected for optimal mechanical bonding properties with respect to the material of the said0 at least one outcoupling structure . 5

[0068] 2024PF00605

[0069] LIST OF REFERENCES

[0070] 100 optoelectronic device

[0071] 102 first doped layer

[0072] 102a first region of first doped layer

[0073] 102b second region of first doped layer

[0074] 103 active layer

[0075] 104 second doped layer

[0076] 105 transparent conductive layer

[0077] 106 conductive reflective layer

[0078] 107 second electrical contact

[0079] 108 first electrical contact

[0080] 109 protruding structure

[0081] 110 dielectric fill material

[0082] 111 second dielectric material

[0083] 112 first dielectric material

[0084] 113 third dielectric material

[0085] 116 cavity

[0086] 121 planarization plane

[0087] 122 planarized upper surface of first doped layer

[0088] 123 upper surface of protruding structure

[0089] 124 upper surface of first electrical contact

[0090] 125 planarized upper surface of third dielectric material

[0091] 126 rounded upper surface of third dielectric material

[0092] 127 rounded upper surface of first doped layer

[0093] 128 inclined surfaces in first doped layer

[0094] 130 semiconductor mesa stack

[0095] 200 carrier substrate

[0096] 201 interconnection electrodes

Claims

2024PF00605 24CLAIMS1. Method of processing an optoelectronic arrangement, comprising the steps :- Providing a carrier substrate (200) with a plurality of optoelectronic devices (100) , each of the plurality of optoelectronic devices comprising: o a semiconductor mesa stack (130) comprising an active layer (103) arranged between a first doped layer (102) and a second doped layer (104) ; o an electrical connection to the second doped layer, comprising at least one of o a transparent conductive layer (105) , in particular, ITO; and / or o a conductive reflective layer (106) ; and / or o a second electrical contact (107) .■ wherein a first region (102a) of the first doped layer of the plurality of optoelectronic devices extends vertically and laterally from a plurality of second regions (102b) of the first doped layer of the plurality of optoelectronic devices to form a substantially continuous sublayer, and■ wherein a first electrical contact (108) is arranged in contact with the first region (102a) of the first doped layer, and■ wherein at least one protruding structure (109) comprising a material different from the first doped layer and / or the first electrical contact is arranged within the first region (102a) of the first doped layer such that it is at least partially embedded within the first region (102a) of the first doped layer .- Thinning the first region of the first doped layer in a first planarization process at least to a depth DP1corresponding to an upper surface of the at least one protruding structure (109) , such that at least part of the first region (102a) of the first doped layer remains after planarization, said first region (102a) forming an electrical connection between at least some of the plurality of optoelectronic devices .2024PF006052 . Method according to claim 1 , wherein at least one first electrical contact ( 108 ) is arranged in contact with the first region ( 102a ) of the first doped layer and / or at least one first electrical contact is arranged laterally adj acent to and at least partly surrounding each of the plurality of semiconductor mesa stacks .3 . Method according to any of the preceding claims , wherein a depth of thinning during at least one first planarization process is controlled by a signal corresponding to a detection of material of the at least one protruding structure at an upper surface of the first doped layer, wherein the detection of the material of the at least one protruding structure involves at least one of : detecting a change in the electrical characteristics , in particular one of the output power and voltage of the planarization tool during planarization and / or use of optical measurement .4 . Method according to any of the preceding claims , further comprising a step of selectively etching material of the first region of the first doped layer such that an upper surface of the first doped layer is along a plane vertically above the first electrical contact , such that the at least one protruding surface is exposed to a depth less than or equal to the height of the at least one protruding surface .5 . Method according to claim 4 , further comprising a step of arranging at least one optical element in contact with the at least one protruding structure such that the at least one optical element is positioned and / or aligned using the at least one protruding structure .6 . Method according to claim 4 , further comprising the steps :Depositing a third dielectric material on the surface of the first doped layer such that the at least one protruding structure is covered by material of the third dielectric material ;2024PF00605 26Performing a second planarization process at least to a depth corresponding to the upper surface of the at least one protruding structure ;Selectively etching to remove material of the at least one protruding structure and optionally, to expose the first electrical contact ;Structuring the third dielectric material to form a plurality of outcoupling structures , in particular, rounded surfaces , corresponding to the plurality of semiconductor mesa stacks , wherein the plurality of outcoupling structures are connected to form a substantially continuous layer .7 . Method according to any of claims 1 to 3 , further comprising the steps :Selectively etching to remove material of the at least one protruding structure ;Performing a dry etch to produce a structured upper surface of the first region of the first doped layer .8 . Method according to claim 7 , wherein the structured upper surface of the first region of the first doped layer comprises at least one of :- a plurality of interconnected curvatures ;- a plurality of inclined facets extending vertically into the first doped layer .9 . Method according to claim 7 , further comprising a step of depositing a third dielectric layer on the structured upper surface of the first doped layer such that a plurality of outcoupling structures , in particular , rounded structures corresponding to the plurality of semiconductor mesa stacks is formed .10 . Method according to any of claims 6 or 9 , further comprising a step of etching through the third dielectric layer such that the upper surface of the first doped layer comprises a plurality of outcoupling structures , wherein a surface profile of the plurality2024PF00605 of outcoupling structures is transferred from the th rd dielectric layer to the first doped layer .11 . Method according to any of the preceding claims , wherein a thickness of the first region of the first doped layer after the first planarization process is between 50 nm and 500 nm, in particular , between 75 nm and 300 nm, in particular , between 100 nm and 150 nm .12 . Method according to any of the preceding claims , wherein the first contact layer is arranged such that a lower surface of the first electrical contact is at a depth substantially below an interface between the active layer and the first doped layer , in particular , at a depth corresponding to a surface of the semiconductor stack facing away from the first doped layer .13 . Method according to any of the preceding claims wherein the at least one protruding structure comprises at least one of : o A dielectric material , and / or o A metal ; and / or; wherein the at least one protruding structure comprises a first region comprising a first material and a second region comprising a second material , wherein the second region is in contact with the first electrical contact , and wherein an interface between the first region and the second region is substantially parallel to the upper surface of the first electrical contact .14 . Method according to claims 7 and 13 , wherein the step of selectively etching to remove material of the at least one protruding structure is performed such that only the first material is removed .15 . Method according to claim 14 , wherein at least one of the first or the second planarization processes is conducted in at least two phases , wherein a first planarization phase is performed at least to a depth corresponding to an upper surface of the first region of the at least one protruding structure , and wherein a second planarization phase is performed at least to a depth corresponding2024PF00605 28 to an upper surface of the second region of the at least one protruding structure.

16. Method according to any of the preceding claims, wherein the first dielectric layer is disposed through an atomic layer deposition process .

17. Optoelectronic arrangement comprising:- A first doped layer (102) comprising a first region (102a) and a plurality of second regions (102b) , wherein the first region (102a) forms a substantially continuous sublayer;- A plurality of laterally isolated semiconductor mesa stacks (130) arranged on the first region (102a) of the first doped layer, each comprising: o a second region (102b) of the first doped layer; o An active layer (103) arranged on a surface of the second region of the first doped layer;- A second doped layer (104) arranged on a surface of the active layer facing away from the active layer;- A plurality of electrical connections to the second doped layer (104) , each electrical connection corresponding to one of the plurality of semiconductor mesa stacks, wherein each of the plurality of electrical connections comprises at least one of : o a conductive and in particular reflective layer (106) , and / or o a transparent conductive layer (105) , and / or o a second electrical contact (107) ;- A first electrically isolating layer (112) arranged on the sidewalls of the plurality of semiconductor mesa stacks and partially on a surface of each of the plurality of semiconductor mesa stacks facing away from the first doped layer, extending to laterally surround the plurality of semiconductor mesa stacks along a plane corresponding to an interface between the first region and the plurality of second regions of the first doped layer;- A first electrical contact (108) arranged in contact with the first doped layer, in particular, with the first region (102a)2024PF00605 29 of the first doped layer , wherein an upper surface of the first electrical contact is below or coplanar with an upper surface of the first doped layer facing away from the plurality of semiconductor mesa stacks , and wherein the first electrical contact is embedded within material of the first isolation, e . g . dielectric layer ( 112 ) ;- At least one protruding structure ( 109 ) arranged on the upper surface of the first electrical contact ;- At least one outcoupling structure aligned in position by the at least one protruding structure , wherein the at least one outcoupling structure is arranged along a main emission direction of at least some of the light emitting devices .18 . Optoelectronic arrangement according to claim 17 , further comprising a carrier substrate ( 200 ) comprising a plurality of interconnection electrodes ( 201 ) , wherein each of the plurality of interconnection electrodes ( 201 ) is arranged in contact with one of the plurality of second electrical contacts .19 . Optoelectronic arrangement according to claim 17 , wherein the at least one protruding structure comprises one of the following crosssections :Circular;Rectangular ;Square ;Hexagonal ; and / or wherein the at least one protruding structure comprises at least one of : o A dielectric material , and / or o A metal ; and / or wherein a plurality of protruding structures is arranged to partially surround at least one of the plurality of semiconductor mesa stacks at a lateral distance from the at least one semiconductor mesa stack .2024PF0060520 . Optoelectronic arrangement according to claim 17 , further comprising a second dielectric material arranged such that each of the plurality of semiconductor mesa stacks is encapsulated within the second dielectric material ; and / or wherein sidewalls of the second dielectric material comprise one of :An inclination angle excluding 90 ° ,A curvature , orA parabolic profile ; and optionally wherein the conductive reflective layer ( 106 ) is at least partly arranged along the sidewalls of the second dielectric material .21 . Optoelectronic arrangement according to claim 20 , further comprising a dielectric fill layer ( 110 ) encapsulating and electrically isolating the reflective layers of adj acent semiconductor stacks .22 . Optoelectronic arrangement according to any of claims 17 to 21 , wherein the first isolating material comprises a thickness less than 500 nm; and / or the first electrically isolating layer comprises at least one of A12O3, HfO2and / or AIN; and / or the second dielectric material comprises at least one of SiO2, SiN or Nb2O5.23 . Optoelectronic arrangement according to any of claims 17 to 22 , wherein the at least one outcoupling structure is formed from at least one of :- the first region of the first doped layer- a third dielectric material .

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