Analog-to-digital converter and signal processing device

Abstract

A pulse signal conversion unit (10) converts an input signal into a pulse signal having a pulse length corresponding to the magnitude of the input signal. A measurement unit (20) measures a first edge time difference between a pair of edges of the pulse signal. A division unit (28) divides the data using the first edge time difference by a second edge time difference in the cycle of a reference clock.

Description

AD Converter and Signal Processing Device Cross - Reference to Related Applications

[0001] This application is based on Japanese Application No. 2024 - 182607 filed on October 18, 2024, the contents of which are incorporated herein by reference.

[0002] This disclosure relates to an AD converter and a signal processing device.

[0003] In recent years, various sensors have been installed in vehicles, and high precision, high reliability, and environmental resistance performance are required. On the other hand, in terms of cost, it is essential to achieve the same level as consumer products in order to gain an advantage in competition. To balance these trade - offs, the applicant has set the goal of digitizing sensors as the optimal solution and has been developing the technology of a time - resolution digital - type AD converter. This technology is called TAD: Time - based analog to digital Converter.

[0004] Conventionally, the applicant has proposed a time - difference digital conversion circuit to measure the width time between the edges of a measurement target pulse as accurately as possible (see, for example, Patent Document 1). According to the technology described in this Patent Document 1, a TDC (Time to Digital Converter) measures, in a time - division manner, the first edge time difference between a pair of edges of a current waveform as the measurement target pulse and the second edge time difference of the period of a reference clock, and a division unit calculates a division result obtained by dividing the first edge time difference by the second edge time difference. By calculating the ratio of the first edge time difference of a pair of edges of the measurement target to the period of the reference clock by the division unit, the width time between the edges of the pulse to be measured, which compensates for the influence of the period variation of the reference clock, can be measured as accurately as possible.

[0005] Japanese Patent Application Laid - Open No. 2022 - 25424

[0006] Conventionally, the applicant has provided AD conversion technology using the time - difference digital conversion circuit related to Patent Document 1. However, for example, it is desired to consume less power during operation, and performance improvement specialized for specific applications is desired, and further performance improvement is desired.

[0007] The purpose of this disclosure is to provide an AD converter and signal processing device with improved performance.

[0008] According to one aspect of this disclosure, the present invention relates to an AD converter that converts an analog input signal into a digital signal. The pulse signal conversion unit converts the input signal into a pulse signal with a pulse length corresponding to the magnitude of the input signal. The measurement unit measures the first edge time difference between a pair of edges of the pulse signal. The division unit of the measurement unit divides the data using the first edge time difference by the second edge time difference of the period of the reference clock. This allows for further performance improvement.

[0009] Furthermore, according to another aspect of this disclosure, when applied to a column AD converter provided for each column of an image sensor, the second edge time difference of the period of the reference clock is measured once per scan of the image sensor. This reduces the frequency of measurement of the second edge time difference of the period of the reference clock, and allows for performance improvement specifically tailored to applications such as image sensors.

[0010] Furthermore, according to another aspect of this disclosure, if the measurement unit measures the second edge time difference once for every multiple measurements of the first edge time difference, it is preferable to determine an interpolated value for the first edge time difference at the time the second edge time difference is measured based on the first edge time difference measured before or after that time, and interpolate it. In this case, even if time is required when measuring the second edge time difference, the first edge time difference can be interpolated, thereby eliminating missing values ​​in the continuously periodic data and further improving performance.

[0011] Furthermore, according to another aspect of this disclosure, if the pulse signal conversion unit is configured to operate using power between the power supply and ground, generate a ramp signal, and output a pulse signal by comparing the ramp signal with an input signal, the switching unit may be configured to enable or disable the function of the pulse signal conversion unit while preventing through-current between the power supply and ground. This allows the function of the pulse signal conversion unit to be disabled during periods when it is not needed, thereby reducing power consumption and improving performance.

[0012] The above-mentioned objectives and other objectives, features and advantages of this disclosure will become clearer from the following detailed description with reference to the attached drawings. The drawings are as follows: Figure 1 is an electrical configuration diagram of the AD converter in the first embodiment; Figure 2 is an electrical configuration diagram of the time-difference digital conversion circuit in the first embodiment; Figure 3 is an electrical configuration diagram of the image sensor in the first embodiment; Figure 4 is a specific example of the pulse signal conversion unit in the first embodiment; Figure 5 is an electrical configuration diagram of the reference clock generation unit in the first embodiment; Figure 6 is an electrical configuration diagram of the TDC in the first embodiment; Figure 7 is an electrical configuration diagram of the RDL in the first embodiment; Figure 8 is a state change diagram in the first embodiment; Figure 9 is an electrical configuration diagram of the latch and encoder in the first embodiment; Figure 10 is the first electrical configuration diagram of the pulse width and time acquisition circuit in the first embodiment; Figure 11 is the second electrical configuration diagram of the pulse width and time acquisition circuit in the first embodiment; and Figure 12 is the frequency of the reference clock in the first embodiment. Figure 13 is the first electrical configuration diagram of the period acquisition circuit of the reference clock in the first embodiment, Figure 14 is the electrical configuration diagram of the measurement frequency changing circuit in the first embodiment, Figure 15 is the electrical configuration diagram of the divider in the first embodiment, Figure 16 is the electrical configuration diagram of the division circuit in the first embodiment, Figure 17 is the truth table of the divider in the first embodiment, Figure 18 is the overall timing chart in the first embodiment, Figure 19 is the timing chart of a part of the whole in the first embodiment, Figure 20 is an explanatory diagram of the measurement timing of the reference time in the first embodiment, Figure 21 is an explanatory diagram of the measurement timing of the reference time in the second embodiment, Figure 22 is a part of a specific example of the pulse signal conversion unit in the third embodiment, and Figure 23 is a part of a specific example of the pulse signal conversion unit in the third embodiment.

[0013] Several embodiments of this disclosure will be described below with reference to the drawings. In each embodiment, the same parts may be denoted by the same reference numerals and their descriptions may be omitted.

[0014] (First Embodiment) The AD converter 1 shown in Figures 1 and 2 represents a signal processing device that converts an analog input signal Vin into digital, and mainly comprises a pulse signal conversion unit 10 and a time-difference digital conversion unit 20 as a measurement unit. The AD converter 1 is applied, for example, to a column AD converter provided for each column of the image sensor 100 shown in Figure 3. The image sensor 100 shown in Figure 3 comprises a pixel array 101 with a pixel circuit for each pixel, a horizontal scanning circuit 102 for horizontal scanning, an ADC group 103 for AD conversion of the sense signal sensed from the pixels, and a vertical scanning circuit 104 for vertical scanning. The image sensor 100 corresponds to a signal processing device. The ADC group 103 provides an AD converter 1 for each column in order to perform analog-to-digital conversion when scanning the pixels provided in the pixel array 101.

[0015] Each A / D converter 1 in the ADC group 103 digitally converts the level of each pixel at high speed, but in order to meet the demands for higher image quality in recent years, it is necessary to increase the processing speed per scan. For example, if the required time width of the output digital data of the A / D converter 1 constituting the ADC group 103 is shorter than or equal to the period of the reference clock SCLK, it may not be possible to meet the demand for higher speed.

[0016] Conventional AD converters determine their resolution according to the clock frequency of the reference clock SCLK. Therefore, even when using the reference clock SCLK, there is a limit to the resolution of the AD conversion depending on the frequency of the reference clock SCLK, which limits the ability to increase the bit depth or speed. In this application, the pulse signal PAW is detected using the pulse signal conversion unit 10 and the time-difference digital conversion unit 20 described below. In this embodiment, the resolution of the AD conversion is increased and the speed is improved by using the time-difference digital conversion unit 20.

[0017] The pulse signal conversion unit 10 shown in Figure 1 is configured to convert an analog input signal Vin into a pulse signal with a pulse length corresponding to the magnitude of the input signal Vin. The pulse signal conversion unit 10 operates using a power supply between the power supply and ground, generates a ramp signal, and outputs a pulse signal by comparing the ramp signal with the input signal Vin. The ramp signal represents a voltage that increases or decreases in a roughly linear fashion with respect to time, and a specific example of the electrical configuration is shown in Figure 4.

[0018] As shown in Figure 4, the pulse signal conversion unit 10 includes a pre-stage circuit 10a in which a control switch 10d is connected between the input and output of the operational amplifier 10c, and a comparator 10b in the subsequent stage. The pre-stage circuit 10a is configured by connecting the operational amplifier 10c, a resistor R, a capacitor C, and a control switch 10d in the illustrated configuration.

[0019] The pre-amplifier circuit 10a inputs a reference voltage Vr to the inverting input terminal of the operational amplifier 10c via a resistor R. The non-inverting input terminal of the operational amplifier 10c is connected to ground potential. A capacitor C is connected between the inverting input terminal and the output terminal of the operational amplifier 10c. The pre-amplifier circuit 10a can receive a control signal S1 from an external clear circuit CC (see Figure 1) to the control switch 10d. When the control signal S1 is input as an ON command to the control switch 10d, the control switch 10d turns ON and outputs a constant high voltage to the comparator 10b. In this case, the pulse signal conversion unit 10 becomes inactive, and the comparator 10b outputs a pulse signal PAW by comparing it with the input signal Vin.

[0020] On the other hand, when the control signal S1 is input as an off command to the control switch 10d, the control switch 10d is turned off and the preceding circuit 10a operates as an integrating circuit. At this time, the pulse signal conversion unit 10 operates actively. The time constant based on the resistor R and capacitor C is set for a long period of time, and when the preceding circuit 10a operates as an integrating circuit, it generates a ramp signal that increases approximately linearly with respect to time changes and outputs it to the subsequent comparator 10b.

[0021] The comparator 10b compares the ramp signal with the input signal Vin and outputs a pulse signal PAW only while the input signal Vin exceeds the ramp signal. This allows the pulse signal conversion unit 10 to convert and output a pulse signal PAW with a pulse length corresponding to the magnitude of the analog input signal Vin. Furthermore, the control signal S1 is input as an ON command to the control switch 10d, which resets the integral operation of the preceding circuit 10a.

[0022] <Description of the configuration of the time-difference digital conversion unit 20> The time-difference digital conversion unit 20 shown in Figures 1 and 2 is a circuit that operates mainly by inputting the pulse signal PAW and the reference clock SCLK to be measured, and enables the digital conversion of the width of the pulse signal PAW to be measured.

[0023] Although the relationship between the length of the pulse signal PAW and the period of the reference clock SCLK is not considered, this embodiment describes a configuration in which the pulse signal PAW is set to approximately the same length as the period of the reference clock SCLK.

[0024] The time-difference digital conversion unit 20 shown in Figures 1 and 2 comprises a TDC control circuit 21, a TDC 24 (Time to Digital Converter), a TDC input circuit 24a, latches 25, 26, and 27 as holding units, a divider 28, and a clear circuit CC. The TDC control circuit 21 receives the pulse signal PAW to be measured, a reference clock SCLK used to measure the width of the pulse signal PAW, and an all-clear signal ALLCLR from the clear circuit CC to instruct the state to be all clear.

[0025] The frequency of the reference clock SCLK is set to a relatively low frequency, for example, around 10 MHz, but this reference clock SCLK can also be generated by the reference clock generation unit 42 shown in Figure 5. The reference clock generation unit 42 generates the reference clock SCLK using a master clock MCLK with a low frequency of about 10 kHz, which is about 1 / 1000th of the reference clock SCLK.

[0026] As shown in Figure 5, the reference clock generation unit 42 comprises an arithmetic circuit 43, a control circuit 44, a ring oscillator 45, a DCO 46, and a second TDC 47. The control circuit 44 receives the master clock MCLK as input and divides the master clock MCLK to generate a divided signal BC1. The divided signal BC1 is a pulse signal that occurs, for example, once every 1000 pulses of the master clock MCLK. The control circuit 44 then outputs the divided signal BC1 to the second TDC 47 and outputs signal BC2 to the ring oscillator 45. At this time, the control circuit 44 controls the enabling / disabling of the ring oscillator 45's function based on the clock generation control signal CNTCLK, and intermittently drives the ring oscillator 45. When the clock generation control signal CNTCLK is input, the control circuit 44 outputs the frequency divider signal BC1 to the second TDC 47 approximately once every 1000 times the master clock MCLK, thereby obtaining the output DOUT. In addition, the control circuit 44 continuously outputs the necessary number of reference clocks SCLK once every 100 times the master clock MCLK. In other words, the ring oscillator 45 is not always operating, and the second TDC 47 is also not always operating. As a result, power consumption can be reduced.

[0027] The control circuit 44 outputs signal BC2 to the ring oscillator 45 only when the reference clock generation unit 42 is in operation, and when the operation is disabled, it outputs no frequency divider signal BC1 to the second TDC 47 and no signal BC2 to the ring oscillator 45. The ring oscillator 45 consists of a number of inverting circuits connected in a ring shape, and when signal BC2 is input, the inverting operation of each inverting circuit sequentially delays the pulse signal and causes it to circulate.

[0028] The second TDC 47 converts the phase difference (i.e., period) from one rising edge to the next of the master clock MCLK into a binary digital value DOUT, based on delay signals sequentially output from predetermined inverting circuits constituting the ring oscillator 45. The electrical configuration of this second TDC 47 is the same as that of the TDC 24 shown in Figure 1. The description of the second TDC 47 is omitted as the TDC 24 will be described later. The arithmetic circuit 43 generates command data DIN, which represents the output period of the reference clock SCLK, by dividing the binary digital value DOUT obtained by the second TDC 47 by a predetermined value. The decimal part can be fine-tuned by changing the output DIN of the arithmetic circuit 43 by ±1. The description of the configuration at this time is omitted, but for example, the circuit described in Japanese Patent Application Publication No. 7-283722 can be used. The reset signal CST shown in Figure 5 corresponds to the reset signal of the digital control oscillator circuit shown in Japanese Patent Application Publication No. 7-183800, and in this application, it indicates a signal for resetting the DCO 46.

[0029] DCO stands for Digitally Controlled Oscillator. When data is input to the DCO 46, it outputs a pulse train with a time difference corresponding to the data. Based on the command data DIN output from the arithmetic circuit 43 and the delay signals sequentially output from the ring oscillator 45, the DCO 46 digitally outputs the required number of reference clocks SCLK corresponding to the master clock MCLK.

[0030] With this reference clock generation unit 42, the control circuit 44 can output the reference clock SCLK when it is outputting signal BC2, and can stop outputting the reference clock SCLK when it is not outputting signal BC2. As a result, power consumption can be reduced when the function of the reference clock generation unit 42 is disabled.

[0031] According to this configuration, a 10 MHz reference clock SCLK can be easily and instantly generated from a 10 kHz master clock MCLK. Furthermore, power consumption can be reduced, improving ease of manufacturing. In addition, by intermittently driving the reference clock generation unit 42 and using it as the reference clock SCLK of the AD converter 1, as described below, power consumption can be significantly reduced.

[0032] Alternatively, the reference clock SCLK output by the DCO 46 may be used directly. However, in the configuration shown in Figure 5, the reference clock SCLK may be generated by storing the frequency control data output DIN in the memory 48 and inputting it to the DCO 46. The reference clock generation unit 42 can reduce power consumption by referencing the memory 48 and outputting a digital waveform. The reference clock generation unit 42 can be driven intermittently, further reducing power consumption. Also, as shown in Figure 5, the PWD generation circuit 49 generates a control signal PWD by inputting both the master clock MCLK and the reference clock SCLK. This control signal PWD is used to output the reference clock SCLK only for the required period (see, for example, T0 in Figure 18).

[0033] The TDC24 shown in Figure 1 includes, for example, an RDL31 (Ring Delay Line) as a delay circuit, a counter 32, a latch and encoder 33, latches 34 and 35, and a subtractor 36, as shown in Figure 6. The RDL31 is constructed by connecting a NAND gate 37, which is an inverting delay element for activation, and, for example, 30 NOT gates 38 in a ring shape, as shown in Figure 7. A signal PA is input to one of the NAND gates 37. Hereafter, the NAND gate 37 and NOT gate 38 will be described as "inverting delay elements" as needed. However, the TDC24 in Figure 6 is just one example of a TDC.

[0034] Here, the common connection nodes of the ring-shaped inversion delay elements 37 and 38 are defined as nodes N1...N16, as shown in Figure 7. One NAND gate 37 is connected between adjacent nodes N16 and N1, and two NOT gates 38 are connected between the other adjacent nodes N1-N2, N2-N3, ..., N15-N16. Since the delay time of the NAND gate 37 is slightly longer than that of the other inversion delay element, the NOT gate 38, only one NAND gate 37 is configured between adjacent nodes N16 and N1.

[0035] Figure 6 shows two NOT gates 38 combined as a single forward-rotation delay element DU. As shown in Figure 7, the RDL 31 also includes a gate 39 that acquires the delay signals from the forward-rotation delay elements DU from nodes N1...N16, shapes the waveforms, and outputs them as digital levels R1...R16.

[0036] When the signal PA = "1" is continuously input to the NAND gate 37, the signal "1" is transmitted sequentially through the forward rotation delay element DU, as shown in the state change in Figure 8. Then, when the signal "1" circulates through the forward rotation delay element DU connected in a ring, it completes one full rotation and reaches the input of the NAND gate 37. At this point, the NAND gate 37 outputs "0", and thereafter, the forward rotation delay element DU sequentially transmits the signal "0".

[0037] Furthermore, when the signal "0" circulates through the forward-rotating delay element DU, which is connected in a ring, it completes one full rotation and reaches the input of the NAND gate 37. This returns it to its initial state. This operation is repeated as long as the signal PA = "1", and the RDL 31 changes 32 states by outputting digital levels R1...R16 through the waveform shaping gate 39. One full rotation is completed when all 32 states have changed.

[0038] The latch-and-encoder 33 is composed of 16 DFFs 40 and encoders 41, as partially shown in Figure 9. Each DFF 40 receives the digital levels R1...R16 related to the output of the forward rotation delay element DU as a D input and is latched by the same latch signal PB.

[0039] The encoder 41 takes the Q output of 16 DFFs 40 as input and encodes it, encoding 32 states based on digital levels R1...R16 into 5 bits. As a result, the latch-and-encoder 33 can acquire phase information obtained by dividing the rotation time of the RDL 31 into 32 parts.

[0040] The edge cycle time by RDL31 is set to be sufficiently shorter than the period of the reference clock SCLK. In this embodiment, the time resolution of TDC24 is assumed to be 200 ps.

[0041] The counter 32 shown in Figure 6 counts the number of laps in the RDL 31 and is composed of, for example, a 17-bit counter. For details, see Japanese Patent Publication No. 6-283984. Latch 34 latches the count value of counter 32. Latch 35 latches 22-bit data DTp, which is the sum of the 17-bit data of latch 34 and the 5-bit data of latch and encoder 33. The latch signals of latch and encoder 33, latch 34 and 35 all consist of a latch signal PB. Subtractor 36 subtracts the latch data of latch 35 from the data DTp and outputs 22-bit data DT. This subtractor 36 is provided to remove digital noise and to compare the previous measurement value with the current measurement value, and may be provided as needed.

[0042] Furthermore, unless any edge signal is input to the RDL31, the NAND gate 37 and NOT gate 38 do not change their respective outputs, and therefore, each inverting delay element 37 and 38 maintains a stable logic output state without consuming power. In this state, the RDL31 can maintain a low-power state, which consumes less power than its normal operating state, and the other circuits of the TDC24, namely the counter 32, latch and encoder 33, latches 34 and 35, can similarly maintain a low-power state.

[0043] The TDC24 returns from a low-power state to a normal operating state when it receives some kind of signal edge, such as a pulse signal PAW corresponding to the pulse signal PAW of the object to be measured (described later), or a pulse signal PAB corresponding to the period of the reference clock SCLK. When the input is interrupted, the TDC24's internal circuit output digital level stabilizes, which suppresses power consumption, and it returns from a normal operating state to a low-power state.

[0044] The TDC control circuit 21 includes a width time acquisition circuit 50 of the pulse signal PAW illustrated in FIGS. 10 and 11, and a period measurement circuit 70 of the reference clock SCLK illustrated in FIGS. 12 and 13. The width time acquisition circuit 50 of the pulse signal PAW includes a main circuit 51 that mainly acquires the width time of the pulse signal PAW, and a slave circuit 52 that operates dependently in response to the output of the main circuit 51.

[0045] As shown in FIG. 10, the main circuit 51 includes DFFs 53a...53d connected in four-stage cascade, AND gates 54 and 55, a first delay circuit 56, and an OR gate 57. The D input of the first-stage DFF 53a is pulled up, and the pulse signal PAW is positively input to the clock terminal. The pulse signal PAW is negatively input to the clock terminal of the second-stage DFF 53b. The D input of the second-stage DFF 53b is positively input to each of the AND gates 54 and 55, and the Q output of the DFF 53b is negatively input to each of the AND gates 54 and 55. As a result, the AND gate 54 outputs a pulse PAW1 having a width from the rising input timing to the falling input timing of the pulse signal PAW.

[0046] A first delay circuit 56 is interposed between the second-stage DFF 53b and the negative input of the AND gate 55. The AND gate 55 corresponds to a first pulse output unit that outputs the pulse signal PAW corresponding to a pair of edges of the pulse signal PAW to be measured to the TDC 24 as a signal PA. The AND gate 55 outputs a pulse signal PAW having a width from the rising input timing to the falling input timing + the first delay time Delay1 of the first delay circuit 56 of the pulse signal PAW to the TDC control circuit 21. The first delay circuit 56 corresponds to a first delay unit that extends the width of the pulse signal PAW output by the AND gate 55 by the first delay time Delay1. The first delay circuit 56 is a timing adjustment circuit provided to set the output stop timing of the pulse signal PAW after the output of the TDC 24 is latched by the pulse signal PB1W.

[0047] The reference clock SCLK is negatively input to the clock terminal of the third-stage DFF 53c, and the reference clock SCLK is positively input to the clock terminal of the fourth-stage DFF 53d. The Q output of the fourth-stage DFF 53d is input to the clear terminal of the first-stage DFF 53a through the OR gate 57. The clear signal CLR is input to the OR gate 57, and the clear signal CLR is also input to the clear terminals of the second-stage to fourth-stage DFFs 53b... 53d. As a result, after the main circuit 51 detects the pulse PAW1 corresponding to the width of the pulse signal PAW, the Q output of the first-stage DFF 53a can be cleared.

[0048] As shown in FIG. 11, the slave circuit 52 includes a plurality of serially connected DFFs 58a... 58h, AND gates 59, 60, and OR gates 61 and 62. The D input of the first-stage DFF 58a is pulled up, and the pulse PAW1 is negatively input to the clock terminal. The first-stage DFF 58a has a configuration corresponding to a first latch output unit that outputs a pulse signal PB1W corresponding to the edge that occurs later among the pair of edges of the pulse signal PAW to be measured, and the Q output of the first-stage DFF 58a is output as the pulse signal PB1W.

[0049] The reference clock SCLK is input to the clock terminals of the second-stage to seventh-stage DFFs 58b... 58g. The second, fourth, and sixth-stage DFFs 58b, 58d, and 58f receive the rising edge of the reference clock SCLK as a trigger and output the D input to the Q output. The third, fifth, and seventh-stage DFFs 58c, 58e, and 58g receive the falling edge of the reference clock SCLK as a trigger and output the D input to the Q output. Therefore, when the reference clock SCLK is input to the clock terminals of each of the DFFs 58b... 58g, each time the rising edge is input to the second, fourth, and sixth-stage DFFs 58b, 58d, and 58f and the falling edge is input to the third, fifth, and seventh-stage DFFs 58c, 58e, and 58g, the pulse PAW1 clock-input to the first-stage DFF 58a can be sequentially shifted.

[0050] The D input of the fifth stage DFF 58e is positively input to AND gate 59, and the Q output of DFF 58e is negatively input to AND gate 59. As a result, AND gate 59 can acquire pulse PB2W, which is pulse PAW1 delayed by one reference clock SCLK. Similarly, the D input of the seventh stage DFF 58g is positively input to AND gate 60, and the Q output of DFF 58g is negatively input to AND gate 60. As a result, AND gate 60 can acquire pulse PB3W, which is pulse PAW1 further delayed by one reference clock SCLK.

[0051] Furthermore, the clock terminal of the eighth stage DFF 58h is also negatively input to the reference clock SCLK. The D input of the eighth stage DFF 58h is positively input to the OR gate 61, and the Q output of the seventh stage DFF 58g is also positively input to the OR gate 61. Therefore, the OR gate 61 can detect that the pulse PAW1 has shifted to the eighth stage DFF 58h as the signal PBSTW.

[0052] The Q output of the third-stage DFF 58c is input to the clear terminal of the first-stage DFF 58a via the OR gate 62. The clear signal CLR is input to the OR gate 62, and the clear signal CLR is also input to the clear terminals of the second to eighth-stage DFFs 58b...58h. As a result, the dependent circuit 52 can clear the Q output of the first-stage DFF 58a after detecting the pulse PAW1.

[0053] After the OR gate 61 detects the signal PBSTW, the period measurement circuit 70 for the reference clock SCLK starts operating. The period measurement circuit 70 for the reference clock SCLK comprises a main circuit 71 that primarily acquires the period of the reference clock SCLK, and a dependent circuit 72 that operates dependently based on the output of the main circuit 71.

[0054] As shown in Figure 12, the main circuit 71 comprises four cascaded DFFs 73a...73d, AND gates 74 and 75, a second delay circuit 76, and an OR gate 77. The D input of the first-stage DFF 73a receives the signal PBSTW output by the OR gate 61 shown in Figure 10, and the clock terminal receives a positive input of the reference clock SCLK. The clock terminal of the second-stage DFF 73b receives a positive input of the reference clock SCLK. The D input of the second-stage DFF 73b is positively input to each AND gate 74 and 75, and the Q output of the DFF 73b is negatively input to each AND gate 74 and 75. As a result, the AND gate 74 outputs a pulse signal PAB1 with a width from the timing of the rising edge input of the reference clock SCLK to the timing of the falling edge input.

[0055] A second delay circuit 76 is interposed between the Q output of the second stage DFF 73b and the negative input of the AND gate 75. The AND gate 75 is configured as a second pulse output section that outputs a pulse signal PAB corresponding to the period of the reference clock SCLK to the TDC 24. It outputs a pulse signal PAB with a width equal to the timing from the rising edge input of the reference clock SCLK to the falling edge input plus the second delay time Delay2 of the second delay circuit 76.

[0056] The second delay circuit 76 is configured to be a second delay section that extends the period width of the reference clock SCLK output by the AND gate 75 by a second delay time Delay2. The second delay circuit 76 is a timing adjustment circuit provided to stop the output of the pulse signal PAB after the output of TDC24 has been latched by the pulse signal PB1B.

[0057] The clock terminal of the third stage DFF73c is negatively input with the reference clock SCLK, and the clock terminal of the fourth stage DFF73d is positively input with the reference clock SCLK. The Q output of the fourth stage DFF73d is input to the clear terminal of the first stage DFF73a via the OR gate 77. As a result, the main circuit 71 can clear the Q output of the first stage DFF73a after detecting the pulse signal PAB1 corresponding to the width of the reference clock SCLK.

[0058] As shown in Figure 13, the dependent circuit 72 comprises multiple cascaded DFFs 78a...78g, AND gates 79, 80, and OR gate 81. The D input of the first-stage DFF 78a is pulled up, and the pulse signal PAB1 is negatively input to the clock terminal. The first-stage DFF 78a is configured to be a second latch output section that outputs a pulse signal PB1B corresponding to a later edge among the edges that define the period of the reference clock SCLK, and the Q output of the first-stage DFF 78a is output as the pulse signal PB1B.

[0059] The clock terminals of the DFF78b...78g from the second to the seventh stage are input to the reference clock SCLK. The DFF78b, 78d, and 78f of the second, fourth, and sixth stages receive the rising edge of the reference clock SCLK as a trigger and output a D input as a Q output. The DFF78c, 78e, and 78g of the third, fifth, and seventh stages receive the falling edge of the reference clock SCLK as a trigger and output a D input as a Q output. Therefore, when the reference clock SCLK is input to the clock terminals of each DFF78b...78g, each time a rising edge is input to the DFF78b, 78d, and 78f of the second, fourth, and sixth stages, and a falling edge is input to the DFF78c, 78e, and 78g of the third, fifth, and seventh stages, the pulse signal PAB1 input to the DFF78a of the first stage can be shifted sequentially.

[0060] The D input of the fifth stage DFF78e is positively input to AND gate 79, and the Q output of DFF78e is negatively input to AND gate 79. As a result, AND gate 79 can obtain pulse PB2B, which is the pulse signal PAB1 delayed by one reference clock SCLK. Similarly, the D input of the seventh stage DFF78g is positively input to AND gate 80, and the Q output of DFF78g is negatively input to AND gate 80. As a result, AND gate 80 can output pulse PB3W, which is pulse PB2B further delayed by one reference clock SCLK.

[0061] The overall configuration will be explained by referring back to the reference drawings in Figures 1 and 2. As described above, when the TDC control circuit 21 receives the pulse signal PAW and the reference clock SCLK as input, it sequentially outputs the pulse signals PAW, PAB, PB1W...PB3W, PB1B...PB3B according to the logic described above. As shown in Figures 1 and 2, the TDC input circuit 24a is equipped with OR gates 22 and 23 and a measurement frequency changing circuit 29.

[0062] A measurement frequency changing circuit 29 is configured between the output terminal of the pulse signal PAB of the TDC control circuit 21 and the OR gate 22, and between the output terminals of the pulse signals PB1B...PB3B of the TDC control circuit 21 and the OR gate 23. In principle, the OR gate 22 is configured to input signal PA, which is the logical OR of pulse signals PAW and PAB, to the TDC 24, and the OR gate 23 is configured to input pulse signals PB1W...PB3W, PB1B...PB3B and the clear signal CLR, and output the latch signal PB to the TDC 24. However, the measurement frequency changing circuit 29 is configured to allow the number of measurements of the period of the reference clock SCLK to be changed.

[0063] The measurement frequency changing circuit 29 illustrated in Figure 14 is configured by combining a counter 29a and AND gates 29b...29e in the illustrated form, and is a circuit that can reduce the measurement frequency, which is the ratio of the number of measurements of the period of the reference clock SCLK to the number of measurements of the width time of the pulse signal PAW, to less than 1.

[0064] Counter 29a counts each time the pulse signal PAW is input, and outputs "1" when it has counted a predetermined number of times. Counter 29a outputs "0" during other periods. Each AND gate 29b...29e is provided as an enable / disable switch circuit that switches whether or not to input each pulse signal PAB, PB1B...PB3B as the signals PA and PB of TDC24 based on the output level "0" or "1" of counter 29a.

[0065] Each time the pulse signal PAW is input to counter 29a a predetermined number of times, the output level of counter 29a changes from "0" to "1", and returns to "0" during other periods. Therefore, each time the pulse signal PAW occurs a predetermined number of times, the AND gates 29b...29e pass through each pulse signal PAB, PB1B...PB3B. The pulse signals PAB, PB1B...PB3B are outputs of the period measurement circuit 70 of the reference clock SCLK. Therefore, for (a predetermined number of times - 1) times out of the number of times the pulse signal PAW occurs, the AND gates 29b...29e block the pulse signals PAB, PB1B...PB3B, and the measurement of the period of the reference clock SCLK by TDC 24 can be stopped. As a result, the period of the reference clock SCLK can be measured once each time the width time of the pulse signal PAW is measured a predetermined number of times. In this case, the number of periodic measurements of the reference clock SCLK by TDC24 can be reduced, thereby shortening the operating time of TDC24 and lowering power consumption.

[0066] On the other hand, the latch 25 shown in Figures 1 and 2 latches the output of TDC 24 using the edge of pulse PB2W as a latch signal. At this time, the latch 25 holds the measurement result from TDC 24, which measures the width and time of the pulse signal PAW.

[0067] Latch 26 latches the output of TDC24 using the edge of pulse PB2B after it has passed through the AND gate 29d of the measurement frequency change circuit 29 as the latch signal. Latch 26 holds the measurement result from TDC24, which measures the period of the reference clock SCLK. However, if pulse PB2B does not pass through the AND gate 29d, no latch signal is input to latch 26. In this case, latch 26 holds the output of TDC24 that was measured in advance previously, i.e., the data of the period of the reference clock SCLK that was measured in advance previously. Note that the concept in Figure 2 is that a time gap is created when pulse signals PAB, PB1B...PB3B are not input. Therefore, by inputting pulse signals PAW, PB1W...PB3W to TDC24 during this time gap, the pulse signal PAW, which has a longer measurement time, can be digitized, and the slew rate of pulse signal PAW can be improved.

[0068] The divider 28, which functions as a division unit, calculates the quotient Q (Q3:Q0) and remainder R (R3:R0) when the dividend A (A3:A0) is divided by the divisor B (B3:B0). As shown in Figure 15, it is configured by combining division circuits 82 in a matrix.

[0069] Each division circuit 82 is configured by combining NAND gates 83...93, NOR gate 94, and NOT gates 95 and 96 in the illustrated form, as shown in Figure 16, and the truth table is as shown in Figure 17. The configuration of the division circuit 82 is general, and a detailed explanation of its operation is omitted. The divider 28 can be any circuit configuration as long as it is a circuit that can divide dividend A by divisor B and calculate at least to the decimal part.

[0070] The characteristic functions and operations using the basic configuration described above will be explained with reference to the timing charts shown in Figures 18 and 19. In the wake-down state, where power consumption is extremely low, the clear circuit CC outputs the control signal S1 to the pulse signal conversion unit 10 as an ON command signal for the control switch 10d. Then, as described above, the pulse signal conversion unit 10 outputs the pulse signal PAW.

[0071] When the TDC control circuit 21 receives the pulse signal PAW, no clock input is provided to the DFF 58a shown in Figure 11 while an H level is being input. Therefore, the TDC control circuit 21 does not output each of the pulse signals PAW, PAB, PB1W...PB3W, PB1B...PB3B. At this time, since signals PA and PB are not input to the TDC 21, no signals are input to the RDL 31 either.

[0072] When no start pulse signal PA or latch signal PB is input to the TDC24, the output state of each inversion delay element 37, 38 does not change, and it can maintain a low-power consumption state that is lower than the normal operating state. Therefore, the time-difference digital conversion unit 20 can maintain a low-power consumption state when no pulse signal PAW to be measured is input.

[0073] Furthermore, in this embodiment, the TDC control circuit 21 is configured to receive pulse input from the reference clock SCLK only when necessary. Specifically, in the wake-down state, which has extremely low power consumption, the clear circuit CC outputs a control signal S1 to the control circuit 44, causing the control circuit 44 to stop outputting the frequency divider signal BC1 and signal BC2, resulting in no output. As mentioned above, the second TDC 47 operates similarly to the TDC 21, thus maintaining a low power consumption state. Also, since the ring oscillator 45 does not output a command digital signal to the DCO 46, neither the DCO 46 nor the reference clock SCLK outputs a digital signal. Consequently, the reference clock SCLK also does not output, thus enabling low power consumption.

[0074] Conversely, in the wake-up state after activation, the clear circuit CC sets the control signal PWD to a high level. The clear circuit CC outputs the control signal S1 to the pulse signal conversion unit 10 as an off command signal for the control switch 10d. Then, as described above, the pulse signal conversion unit 10 converts and outputs a pulse signal PAW with a pulse length corresponding to the magnitude of the analog input signal Vin.

[0075] The control circuit 44 continuously outputs the required number of reference clock SCLK. As shown in Figure 18, the reference clock SCLK only needs to be output for a predetermined number of times (12 times in the example in Figure 18). The PWD generation circuit 49, as described above, adjusts the period T0 during which the control signal PWD is at a high level. As a result, the DCO 46 is stopped after outputting for a predetermined number of times (for example, 12 times).

[0076] As shown in the overall flow in Figure 18, if the period T0 during which the control signal PWD is at the H level is set to be significantly shorter than the period during which the control signal PWD is at the L level, then the TDC 24 will maintain a low power consumption state during periods other than T0. In addition, the reference clock generation unit 42 can also generally maintain a low power consumption state, and can maintain an extremely low power consumption state for a long period of time.

[0077] When the TDC control circuit 21 receives the rising edge of the pulse signal PAW to be measured, it returns to its normal operating state. Upon receiving the pulse signal PAW, the pulse signal PAW width and time acquisition circuit 50 shown in Figure 10 outputs a pulse PAW1 of the same length as the pulse signal PAW, as well as the pulse signal PAW itself. When the OR gate 22 passes the pulse signal PAW through to the TDC 24 as a signal PA which will be the start pulse, the TDC 21 starts digitally converting the time width from the timing of the rising edge of the pulse signal PAW. The TDC 21 acquires a digital value corresponding to the integer digits using a 17-bit counter 32, and a digital value corresponding to the decimal digits using a latch and encoder 33, and digitally converts these values ​​to a total of 22 bits and outputs them to the latch 35 and subtractor 36.

[0078] The TDC control circuit 21 outputs the rising edge of pulse signal PAW at timing t1 in Figure 19, and simultaneously outputs the rising edge of pulse PAW1. After the time elapsed of pulse PAW1, when the DFF 58a of the dependent circuit 52 shown in Figure 11 receives the falling edge of pulse PAW1 as a negative input, it outputs the rising edge of pulse signal PB1W at timing t2 in Figure 19.

[0079] The pulse signal PAW width and time acquisition circuit 50 shown in Figure 10 is provided with a first delay circuit 56. The TDC control circuit 21 latches the pulse signal PAW, which has been extended by the first delay circuit 56, with the pulse signal PB1W from the Q output of the DFF 58a, and stops the output of the pulse signal PAW by the AND gate 55 after the first delay time Delay1 has elapsed.

[0080] Therefore, TDC24 can reliably input the pulse signal PB1W as a latch signal PB at timing t2 before the pulse signal PAW falls at timing t3. TDC24 can reliably measure the width time of pulse PAW1 as a digital value. When TDC24 latches the pulse signal PAW with the pulse signal PB1W, the data change settles down after a short time elapsed.

[0081] The dependent circuit 52 outputs pulse signal PB1W, and then sequentially outputs pulses PB2W and PB3W. Pulse PB2W is input to the latch 25 shown in Figures 1 and 2. Therefore, the latch 25 can hold the width time of pulse PAW1, which is the output of TDC 24, as the dividend DB at timing t4 when pulse PB2W is input. At this time, the pulse signal PAW width time acquisition circuit 50 can acquire the length between edges of the pulse signal PAW to be measured as the first edge time difference.

[0082] The dependent circuit 52 outputs pulse PB3W and also outputs signal PBSTW. Then, the period measurement circuit 70 of the reference clock SCLK shown in Figures 12 and 13 starts operating. Subsequently, when the TDC control circuit 21 receives the rising edge of the reference clock SCLK, the period measurement circuit 70 of the reference clock SCLK shown in Figure 12 outputs the edge of pulse signal PAB1, which has the same length as the period of the reference clock SCLK, and also outputs the edge of pulse signal PAB.

[0083] As described above, the measurement frequency changing circuit 29 shown in Figure 14 passes through pulse signals PAB, PB1B...PB3B at predetermined intervals of pulse signal PAW generation by the TDC control circuit 21. When the measurement frequency changing circuit 29 passes through pulse signals PAB, PB1B...PB3B, the OR gate 22 passes through pulse signal PAB and inputs it to TDC 24 as signal PA, which becomes the start pulse. Then TDC 24 starts digital conversion of the time width from the rising edge of pulse signal PAB. TDC 24 performs digital conversion corresponding to integer digits using a 17-bit counter 32 and digital conversion corresponding to 5 bits of decimal digits using a latch and encoder 33, and digitally converts these values ​​to a total of 22 bits and outputs them to the latch 35 and subtractor 36.

[0084] The TDC control circuit 21 outputs the rising edge of pulse signal PAB and the rising edge of pulse signal PAB1 at timing t5 in Figure 19. After the time has elapsed for pulse signal PAB1, when the DFF 78a of the dependent circuit 72 shown in Figure 13 receives the falling edge of pulse signal PAB1 as a negative input, the DFF 78a outputs the rising edge of pulse signal PB1B as a latch signal at timing t6.

[0085] The period measurement circuit 70 of the reference clock SCLK shown in Figure 12 is provided with a second delay circuit 76. The TDC control circuit 21 latches the pulse signal PAB extended by the second delay circuit 76 with the pulse signal PB1B from the DFF 78a, and stops the output of the pulse signal PAB by the AND gate 75 after the second delay time Delay2 has elapsed.

[0086] Therefore, TDC24 can reliably input the pulse signal PB1B as a latch signal PB at timing t6 before the pulse signal PAB falls at timing t7. This allows TDC24 to reliably convert the width time of the pulse signal PAB1 to digital. When TDC24 latches the pulse signal PAB with the pulse signal PB1B, the data change settles down after a short time elapsed.

[0087] The dependent circuit 72 outputs pulse signal PB1B, and then sequentially outputs pulses PB2B and PB3B. Pulse PB2B is input to the latch 26 shown in Figure 1. Therefore, the latch 26 can hold the width time of pulse signal PAB1, which is the output of TDC 24, as the divisor DA at the timing t8 when pulse PB2B is input. At this time, the reference clock SCLK period measurement circuit 70 can measure the period of the reference clock SCLK as the second edge time difference.

[0088] The divider 28 divides the dividend DB by the divisor DA to at least one decimal place. When the dependent circuit 72 outputs pulse PB3B, pulse PB3B is input to latch 27. Latch 27 holds the division result of the divider 28. This makes it possible to calculate the ratio of the width time of the pulse signal PAW to the period of the reference clock SCLK at the time of measurement.

[0089] The width time of the pulse signal PAW being measured and the period of the reference clock SCLK tend to fluctuate in the same direction due to PVT variations such as power supply voltage changes and temperature changes. Therefore, by calculating the ratio of the width time of the pulse signal PAW to the period of the reference clock SCLK using the divider 28, it is possible to calculate the width time of the pulse signal PAW being measured while compensating for the effects of period fluctuations of the reference clock SCLK.

[0090] Furthermore, by calculating the ratio of the width time of the pulse signal PAW to the period of the reference clock SCLK, the effects of fluctuations due to PVT variations in the reference clock SCLK can also be compensated for. Also, since the width time of the pulse signal PAW is measured before the reference clock SCLK, it is no longer necessary to continuously measure changes in the period of the reference clock SCLK. The TDC control circuit 21 and TDC 24 return to a low-power state when they have finished measuring the width time of the pulse signal PAW and the period of the reference clock SCLK.

[0091] Furthermore, if the measurement frequency changing circuit 29 interrupts the pulse signals PAB, PB1B...PB3B, even if the latch 25 holds the width time of the pulse signal PAW as the dividend at timing t4, the pulse signals PAB, PB1B...PB2B are not input to TDC 24 and latch 26 at timings t5 to t9, so the latch 26 holds the time data of the period of the previously measured reference clock SCLK.

[0092] The divider 28 can divide the width time of the pulse signal PAW by the period of the reference clock SCLK, which was measured previously and is held in advance in the latch 26. Conceptually, if pulse signals PAB, PB1B...PB3B are not input, a time gap occurs. By inputting pulse signals PAW, PB1W...PB3W to the TDC 24 during this time gap, the pulse signal PAW, which will have a longer measurement time, can be digitized, and the measurement slew rate of the pulse signal PAW can be improved.

[0093] The AD converter 1 of this embodiment is applied to a column AD converter provided for each column of the image sensor 100. As shown in the lower part of Figure 20, the column AD converter of the image sensor 100 acquires signals A1 to A96 from multiple pixels for one row during one scan and continuously converts these signals A1 to A96 into digital signals. For this reason, it is preferable to measure the second edge time difference of the period of the reference clock SCLK once per scan of the image sensor 100. This reduces the measurement frequency of the second edge time difference of the period of the reference clock SCLK compared to the number of measurements of the width time of the pulse signal PAW, and improves performance specifically for applications such as the image sensor 100.

[0094] As described above, according to this embodiment, the pulse signal conversion unit 10 converts the input signal Vin into a pulse signal PAW with a pulse length corresponding to the magnitude of the input signal Vin, the time difference digital conversion unit 20 measures the first edge time difference between a pair of edges of the pulse signal, and the divider 28 divides the first edge time difference by the second edge time difference of the period of the reference clock SCLK. This further improves performance.

[0095] (Second Embodiment) The second embodiment will be described with reference to Figure 21. For example, as shown in Figure 21, the frequency of measuring the period of the reference clock SCLK compared to the number of measurements of the first edge time difference of the width time of the pulse signal PAW may be set to once every multiple measurements (for example, once every 1000 measurements), that is, the period of the reference clock SCLK may be measured once every multiple measurements (for example, 1000 times) of the width time of the pulse signal PAW by TDC24.

[0096] In this case, the time-difference digital conversion unit 20 may not be able to measure the width and time of the pulse signal PAW while measuring the reference clock SCLK. In this case, the time-difference digital conversion unit 20 may use the first edge time difference measured before or after the point in time as the interpolated value for the missing value that occurred in this case. Alternatively, the time-difference digital conversion unit 20 may use the average or median of one or more measured values ​​of the first edge time difference measured before or after the point in time as the interpolated value. This allows the missing value of the first edge time difference to be interpolated. Furthermore, for example, even in the application of a normal AD converter 1, if the input signal Vin to be measured changes continuously, a slight gap may not have any effect. In such applications, the missing value may be left as is.

[0097] According to the second embodiment, if the time-difference digital conversion unit 20 measures the second edge time difference once each time it measures the first edge time difference multiple times, it is preferable to determine an interpolated value for the first edge time difference at the time the second edge time difference is measured based on the first edge time difference measured before or after that time, and then interpolate it. In this case, even if it takes a considerable amount of time periodically to measure the second edge time difference, for example, missing values ​​in the first edge time difference can be interpolated, so that missing values ​​can be eliminated in continuously periodic data, and performance can be further improved.

[0098] (Third Embodiment) The third embodiment will be described with reference to Figures 22 and 23. In the third embodiment, another configuration example of the pulse signal conversion unit 110 will be described. Another configuration example of the pulse signal conversion unit 110 is shown in Figures 22 and 23.

[0099] The pulse signal conversion unit 110 also converts the analog input signal Vin into a pulse signal with a pulse length corresponding to the magnitude of the input signal Vin. The pulse signal conversion unit 110 operates using a power supply between power supply V1 and ground, generates a ramp signal, and outputs a pulse signal by comparing the ramp signal with the input signal Vin. The pulse signal conversion unit 110 comprises a ramp signal generation unit 110a shown in Figure 22 and a comparator unit 110b shown in Figure 23.

[0100] As shown in Figure 22, the lamp signal generation unit 110a is configured by connecting a power supply V1, p-channel type MOS transistors M1 to M5, M8, n-channel type MOS transistors M6, M7, M9, M10, M11, capacitors C1 and C2, resistor Ra, and an externally controllable switch SW1 as a switching unit in the illustrated configuration. Power supply V1 indicates a constant voltage power supply. The wiring of the specific example shown in Figure 22 is easy for those skilled in the art to understand, so a written explanation is omitted, but at least the switch SW1 is provided to prevent through-current between the power supply V1 application node and the ground node, and it is sufficient that the operation of the lamp signal generation unit 110a can be switched on or off by turning the switch SW1 on or off.

[0101] Switch SW1 is supplied with a control signal PWD from the PWD generation circuit 49 as an on / off command, and is configured to switch the power supply V1 on and off. Switch SW1 is off while the control signal PWD is held at the "L" level. While switch SW1 is off, no current flows through resistor Ra and MOS transistor M10, and therefore no current flows through MOS transistor M11. As a result, MOS transistors M1 to M4 are all inoperable. Since MOS transistors M2 and M4 are off, power supply V1 is not supplied to capacitor C3 through MOS transistors M5 to M7.

[0102] In this case, the reset signal RESET is held at the "L" level. When the reset signal RESET is held at the "L" level, MOS transistor M8 turns on and MOS transistor M9 turns off. Then, power supply V1 is applied to the gates of MOS transistors M5 and M7, causing MOS transistor M5 to turn off and MOS transistor M7 to turn on. On the other hand, since the gate of MOS transistor M6 is supplied with an "L" level, MOS transistor M6 turns off. Therefore, the ramp signal generation unit 110a holds its output LMPOut at ground potential.

[0103] When the control signal PWD changes to the "H" level, switch SW1 turns on. When switch SW1 is turned on, a reference current flows through resistor Ra to MOS transistor M10. When current flows through MOS transistor M10, current flows through the current-mirror-connected MOS transistor M11, and further, current flows through MOS transistors M1 and M2. Furthermore, since a low potential is applied to the gates of MOS transistors M3 and M4, current also flows through MOS transistors M3 and M4. As a result, current can be supplied from power supply V1 to MOS transistors M5 to M7 through MOS transistors M2 and M4.

[0104] Under these conditions, when the reset signal RESET changes to the "H" level, MOS transistor M8 turns off and MOS transistor M9 turns on. Here, the reset signal RESET is a signal that changes from "L" to "H" at the timing when the output LMPOut of the ramp signal starts. Then, ground voltage is applied to the gates of MOS transistors M5 and M7, and MOS transistor M5 turns on and MOS transistor M7 turns off.

[0105] On the other hand, since an "H" level is applied to the gate of MOS transistor M6, MOS transistor M6 turns on. As a result, current is supplied from the power supply V1 through MOS transistors M2 and M4 to M6 to capacitor C3, and the ramp signal generation unit 110a outputs a ramp signal as output LMPOut that rises approximately linearly with respect to the change in time. Subsequently, when the reset signal RESET changes to an "L" level, the charge accumulated in capacitor C3 is discharged, thereby resetting the integral operation.

[0106] The comparator unit 110b shown in Figure 23 comprises a current source supply switching unit 111, a main comparator unit 112, and an output unit 113. The current source supply switching unit 111 is configured by connecting a switch S2, a resistor Rb, and n-channel type MOS transistors M15, M16, and M21 as shown in the diagram. MOS transistors M21 and M15 are in current mirror connection, and MOS transistors M21 and M16 are also in current mirror connection.

[0107] The current source supply switching unit 111 is configured to allow the supply of a reference current from the power supply V4 through the resistor Rb to be switched on and off by a switch S2. A switch SW2 is provided as a switching unit to prevent through-current between the application node and the ground node of the power supply V4, and it is sufficient that the operation of the comparator unit 110b can be switched on or off by turning the switch SW2 on or off. When the switch SW2 is off, the current source supply switching unit 111 does not supply bias current to the main comparator unit 112 and the output unit 113. When the switch SW2 is turned on, a reference current can be supplied from the power supply V4 through the resistor Rb to the MOS transistor M21. As a result, the current source supply switching unit 111 can supply bias from the MOS transistors M15 and M16, which are currently mirror-connected to the MOS transistor M21, to the main comparator unit 112 and the output unit 113, respectively.

[0108] The main comparator section 112 comprises a differential pair 112a and an active load 112b connected to each other. The differential pair 112a is configured by connecting n-channel type MOS transistors M13 and M14 as shown in the diagram. The active load 112b is configured by current mirroring p-channel type MOS transistors M12 and M17.

[0109] The gate of one MOS transistor M13 constituting the differential pair 112a is input with the input signal Vin, and the gate of the other MOS transistor M14 is input with the output LMPOut of the preceding ramp signal generation unit 110a. The connection node between the differential pair 112a and the active load 112b is connected to the gate of a p-channel type MOS transistor M19 constituting the output unit 113, and a pulse signal PAW can be output from the drain of the MOS transistor M19. Therefore, the main comparator unit 112 and the output unit 113 output the comparison result of comparing the input signal Vin and the output LMPOut of the ramp signal generation unit 110a as the pulse signal PAW.

[0110] Therefore, the comparator unit 110b compares the ramp signal with the input signal Vin and outputs a pulse signal PAW only while the input signal Vin is greater than the ramp signal. As a result, the pulse signal conversion unit 110 can convert and output a pulse signal PAW with a pulse length corresponding to the magnitude of the analog input signal Vin.

[0111] In this third embodiment as well, the pulse signal conversion unit 110 can convert and output a pulse signal PAW with a pulse length corresponding to the magnitude of the analog input signal Vin. The pulse signal conversion unit 110 is configured to operate using power supplies between power supply V1 and ground and power supply V4 and ground, generate a ramp signal, and output a pulse signal by comparing the ramp signal with the input signal Vin. With this pulse signal conversion unit 110, switches SW1 and SW2 switch the function of the pulse signal conversion unit 110 on or off while preventing through-current between power supply V1 and ground and power supply V4 and ground.

[0112] As a result, during periods when the pulse signal conversion unit 110 is not needed, in this case, during the period when the control signal PWD = "L", the function of the pulse signal conversion unit 110 can be disabled, thereby reducing power consumption and further improving performance. Since switches SW1 and SW2 are controlled simultaneously, power consumption is reduced by turning off both switches SW1 and SW2. Other methods may also be used to configure bias cutting. In addition, to reduce power consumption of the lamp signal generation unit 110a, comparator unit 110b, etc., which constitute the analog circuit part during standby, it is sufficient that no through-current flows between the power supply and ground, and the analog circuit part may be isolated from the power supply and ground using various switches. In this case as well, power consumption can be reduced.

[0113] (Other Embodiments) This disclosure is not limited to the embodiments described above, and can be modified or expanded as shown below, for example. In the embodiments described above, an application to the AD converter 1 that performs column AD conversion of an image sensor 100 was described, but it is not limited thereto. For example, it can be applied to signal processing devices that operate on battery power and use the AD converter 1 when performing predetermined processing, such as portable devices, IoT devices, and mobile terminals. Furthermore, in recent years, energy harvesting technology, which extracts small amounts of energy from various environments and converts it into electricity for use, has been proposed, and this can be applied to signal processing devices that use the AD converter 1 for signal processing in such technologies, as well as to signal processing devices that use the AD converter 1 for applications such as wind power generation.

[0114] While the TDC24 using the RDL31 as a delay circuit was shown as a way to measure the time difference, it is not limited to this. Also, in the above embodiment, a method was described in which the delay time is generated by the signal propagation delay of the gate, for example, by using a NAND gate 37 and a NOT gate 38 as inverting delay elements, but it is not limited to this, and any delay circuit that can measure the time difference may be used to construct the system.

[0115] While the description of measuring the time difference between a pair of edges of the pulse signal PAW being measured refers to measuring the time difference between the rising edge and the falling edge of the pulse, the method is not limited to this and may also be applied to measuring the time difference between the falling edge and the rising edge of the pulse. Furthermore, while the description of using the data of the first edge time difference itself as the division target as the time difference between a pair of edges of the pulse signal PAW is not limited to this and may also be used as the division target as "data using the first edge time difference". For example, an upper limit voltage Vinmax and a lower limit voltage Vinmin may be generated from an analog input signal Vin, and pulse signals PAWMAX and PAWMIN with pulse lengths corresponding to the magnitudes of the upper limit voltage Vinmax and lower limit voltage Vinmin may be generated, and the data of the edge time difference of these pulse signals PAWMAX and PAWMIN may be used as the division target as "data using the first edge time difference". In other words, this can be applied to a configuration in which the first edge time difference, obtained by processing the upper limit voltage Vinmax and lower limit voltage Vinmin into pulse signals PAWMAX and PAWMIN, is divided by the second edge time difference of the pulse signal PAB.

[0116] This application includes, in addition to the technical disclosures described in the claims, the following technical details: [1] An AD converter for converting an analog input signal into a digital signal, comprising: a pulse signal conversion unit (10) that converts the input signal into a pulse signal with a pulse length corresponding to the magnitude of the input signal; and a measurement unit (20) that measures a first edge time difference between a pair of edges of the pulse signal and converts it into a digital value, wherein the measurement unit comprises a division unit (28) that divides the data using the first edge time difference by a second edge time difference corresponding to the period of a reference clock.

[0117] [2] The AD converter of [1], applied to a column AD converter provided for each column of an image sensor, wherein the measurement unit measures the second edge time difference of the period of the reference clock once per scan of the image sensor, and the division unit divides the data using the first edge time difference by the second edge time difference measured once per scan of the image sensor.

[0118] [3] The AD converter according to [1] or [2], wherein each time the measuring unit measures the first edge time difference multiple times, the second edge time difference is measured once, and the first edge time difference at the time the second edge time difference is measured is interpolated by determining an interpolated value based on the first edge time difference measured before or after that time.

[0119] [4] The AD converter of any one of [1] to [3], wherein the pulse signal conversion unit is configured to operate using power between the power supply and ground, generate a ramp signal, compare the ramp signal with the input signal and output the pulse signal, and includes a switching unit (SW1, SW2) to enable / disable the function of the pulse signal conversion unit while preventing through-current between the power supply and ground.

[0120] [5] An AD converter according to any one of [1] to [4], comprising: a ring oscillator (45) that outputs a command digital value to a DCO that digitally outputs the reference clock; and a control circuit (44) that controls the enabling / disabling of the function of the ring oscillator and intermittently drives the ring oscillator.

[0121] [6] A signal processing device using an AD converter for converting an analog input signal into a digital signal, wherein the AD converter comprises a pulse signal conversion unit (10; 110) for converting the input signal into a pulse signal with a pulse length corresponding to the magnitude of the input signal, and a measurement unit (20) for measuring a first edge time difference between a pair of edges of the pulse signal and converting it into a digital value, and the measurement unit comprises a division unit (28) for dividing the data using the first edge time difference by a second edge time difference corresponding to the period of a reference clock, and the signal processing device uses the AD converter when performing a predetermined process.

[0122] The reference numerals in parentheses in the claims indicate the correspondence with the specific means described in the embodiments described above as one aspect of the present disclosure, and do not limit the technical scope of the present disclosure. Embodiments in which some of the embodiments described above are omitted to the extent that the problem is solved can also be considered embodiments. Furthermore, any conceivable embodiment can be considered an embodiment, as long as it does not deviate from the essence specified by the wording in the claims.

[0123] Furthermore, although this disclosure is described in accordance with the embodiments described above, it is understood that it is not limited to those embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include one, more, or fewer of those elements, fall within the scope and concept of this disclosure.

Claims

1. An AD converter for converting an analog input signal into a digital signal, comprising: a pulse signal conversion unit (10; 110) that converts the input signal into a pulse signal with a pulse length corresponding to the magnitude of the input signal; and a measurement unit (20) that measures a first edge time difference between a pair of edges of the pulse signal and converts it into a digital value, wherein the measurement unit comprises a division unit (28) that divides the data using the first edge time difference by a second edge time difference corresponding to the period of a reference clock.

2. The AD converter according to claim 1, applied to a column AD converter provided for each column of an image sensor, wherein the measurement unit measures the second edge time difference of the period of the reference clock once per scan of the image sensor, and the division unit divides the data using the first edge time difference by the second edge time difference measured once per scan of the image sensor.

3. The AD converter according to claim 1, wherein each time the measuring unit measures the first edge time difference multiple times, it measures the second edge time difference once, and interpolates the first edge time difference at the time the second edge time difference is measured by determining an interpolated value based on the first edge time difference measured before or after that time.

4. The AD converter according to claim 1, wherein the pulse signal conversion unit is configured to operate using a power supply between the power supply and ground, generate a ramp signal, compare the ramp signal with the input signal and output the pulse signal, and comprises a switching unit (SW1, SW2) that switches the function of the pulse signal conversion unit on or off while preventing through-current between the power supply and ground.

5. The AD converter according to claim 1, comprising: a ring oscillator (45) that outputs a command digital value to a DCO that digitally outputs the reference clock; and a control circuit (44) that controls the enabling / disabling of the function of the ring oscillator and intermittently drives the ring oscillator.

6. A signal processing device using an AD converter for converting an analog input signal into a digital signal, wherein the AD converter comprises a pulse signal conversion unit (10; 110) that converts the input signal into a pulse signal with a pulse length corresponding to the magnitude of the input signal, and a measurement unit (20) that measures a first edge time difference between a pair of edges of the pulse signal and converts it into a digital value, and the measurement unit comprises a division unit (28) that divides the data using the first edge time difference by a second edge time difference corresponding to the period of a reference clock, and the signal processing device uses the AD converter when performing a predetermined process.

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