Semiconductor devices including electrodes over interconnects, and methods of forming same

Abstract

Semiconductor devices are disclosed. The devices include a substrate, an interconnect layer disposed over the substrate, and an interconnect disposed within the interconnect layer. Additionally, the devices include a conductive cap material disposed directly over the interconnect, and a bottom electrode disposed directly over a portion of the conductive cap material. The bottom electrode is electrically coupled to the interconnect via the conductive cap material. Additionally, the bottom electrode is formed from a plurality of distinct conductive materials.

Description

011-2325W001SEMICONDUCTOR DEVICES INCLUDING ELECTRODES OVER INTERCONNECTS,AND METHODS OF FORMING SAMECROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 708,629, filed October 17, 2024, the entirety of which is hereby incorporated herein by this reference.BACKGROUND

[0002] The disclosure relates generally to semiconductor devices, and more particularly, to semiconductor devices including electrodes formed over interconnects, and methods of forming the semiconductor devices including the electrodes.

[0003] Semiconductor electrodes and interconnects are essential components in integrated circuits, enabling the flow of electrical signals between transistors and other functional blocks. Electrodes serve as the interface for charge injection or collection, often made from materials like heavily doped polysilicon or metal silicides. Interconnects, typically composed of metal lines and vias, create an intricate network that links these components across multiple layers of the chip. As device dimensions have shrunk, the performance and reliability of interconnects have become critical to overall chip functionality, influencing signal delay, power consumption, and thermal behavior.

[0004] Copper has become the preferred material for interconnects in modem semiconductor devices due to its superior electrical conductivity and resistance to electromigration compared to earlier materials like aluminum. However, copper also presents several challenges, particularly in terms of diffusion. Copper atoms can migrate into surrounding dielectric materials or the silicon substrate, which can degrade the electrical performance of the device or even cause failure. This diffusion is especially problematic because copper readily contaminates silicon, potentially creating deep-level traps that interfere with device operation.

[0005] To mitigate copper diffusion, barrier layers are deposited between the copper and at least some of the surrounding materials. These barriers prevent copper atoms from penetrating into the dielectric or substrate layers while maintaining adhesion and integrity during thermal cycles. However, as device geometries continue to scale down, forming these barrier layers thin enough to preserve performance without compromising effectiveness becomes increasingly difficult. Thus, creating semiconductor devices that include copper interconnects011-2325W001 remains a key challenge in semiconductor manufacturing, requiring innovations in materials and deposition techniques to ensure both electrical performance and long-term reliability.BRIEF DESCRIPTION

[0006] A first aspect of the disclosure provides a semiconductor device including a substrate; an interconnect layer disposed over the substrate; an interconnect disposed within the interconnect layer; a conductive cap material disposed directly over the interconnect; and a bottom electrode disposed directly over a portion of the conductive cap material, the bottom electrode electrically coupled to the interconnect via the conductive cap material.

[0007] A second aspect of the disclosure provides a method of manufacturing a semiconductor device. The method includes selectively depositing a conductive cap material directly over an interconnect, the interconnect disposed within an interconnect layer disposed over a substrate; depositing a first bottom electrode layer directly over the conductive cap material and a surface of the interconnect layer; depositing at least one distinct bottom electrode layer over the first bottom electrode layer; depositing a hard mask layer directly over the at least one distinct bottom electrode layer; depositing a lithography stack directly over the hard mask layer; and etching the lithography stack, the hard mask layer, the at least one distinct bottom electrode layer, and the first bottom electrode layer to form a bottom electrode over the conductive cap material.

[0008] The illustrative aspects of the present disclosure are designed to solve the problems herein described and / or other problems not discussed.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] These and other features of this disclosure will be more readily understood from the following detailed description of the various aspects of the disclosure taken in conjunction with the accompanying drawings that depict various embodiments of the disclosure, in which:

[0010] FIG. 1 shows a cross-sectional view of a semiconductor device including a bottom electrode formed over a conductive cap material and an interconnect, according to embodiments of the disclosure.

[0011] FIGS. 2-10 show cross-sectional views of a semiconductor device undergoing various processes for forming a bottom electrode over a conductive cap material and an interconnect, according to embodiments of the disclosure.

[0012] FIG. 11 shows a cross-sectional view of a semiconductor device includinga bottom electrode formed over a conductive cap material and an interconnect, according to additional embodiments of the disclosure.

[0013] FIG. 12 shows a flow chart illustrating processes for forming a semiconductor device including a bottom electrode formed over a conductive cap material and an interconnect, according to embodiments of the disclosure.

[0014] It is noted that the drawings of the disclosure are not to scale. The drawings are intended to depict only typical aspects of the disclosure and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings.DETAILED DESCRIPTION

[0015] As an initial matter, in order to clearly describe the current disclosure it will become necessary to select certain terminology when referring to and describing relevant components within the disclosure. When doing this, if possible, common industry terminology will be used and employed in a manner consistent with its accepted meaning. Unless otherwise stated, such terminology should be given a broad interpretation consistent with the context of the present application and the scope of the appended claims. Those of ordinary skill in the art will appreciate that often a particular component may be referred to using several different or overlapping terms. What may be described herein as being a single part may include and be referenced in another context as consisting of multiple components. Alternatively, what may be described herein as including multiple components may be referred to elsewhere as a single part.

[0016] As discussed herein, the disclosure relates generally to semiconductor devices, and more particularly, to semiconductor devices including electrodes formed over interconnects, and methods of forming the semiconductor devices including the electrodes.

[0017] These and other embodiments are discussed below with reference to FIGS. 1 -12. However, those skilled in the art will readily appreciate that the detailed description given herein with respect to these Figures is for explanatory7purposes only and should not be construed as limiting.

[0018] FIG. 1 shows cross-sectional view of a semiconductor module or device. In the exemplary embodiment, semiconductor device 100 includes a portion of a larger semiconductor structure. As discussed herein, semiconductor device 100 includes electrode(s) formed over an interconnect.

[0019] Semiconductor device 100 includes a substrate 102. Substrate 102 includes011-2325W001 or forms a base layer or layers of semiconductor device 100 that are formed from semiconducting material(s) and / or are formed from any suitable module, material, or material compositions that includes semiconducting properties / characteristic. In the exemplary embodiment shown in FIG. 1 , substrate 102 is formed from a plurality of layers that may be patterned and / or materials disposed over one another. Specifically, substrate 102 includes a silicon (Si) base layer 104, a silicon dioxide (SiCh) layer 106 disposed and / or formed directly over base layer 104. Additionally in the exemplary embodiment, substrate 102 includes a silicon nitride (SiN) layer 108 disposed and / or formed directly over SiO2 layer 106.

[0020] In other exemplary embodiments, substrate 102 is formed from indium phosphide (InP) or Indium gallium arsenide (InGaAs), or any other suitable materials or compositions consisting essentially of one or more compound semiconductors. For example, substrate 102 can be provided as a bulk substrate or as part of a silicon-on-insulator (SOI) wafer. Additionally, or alternatively, substrate 102 may be formed from, for example, silicon (Si), silicon carbide (SiC), germanium (Ge), germanium oxide (GeO), cadmium zinc telluride (CdZnTe), gallium nitride (GaN), or gallium arsenide (GaAs). Furthermore, substrate 102 may be fabricated as a layer or multiple layers of semiconductor material, substances or materials consisting essentially of one or more compound semiconductors having a composition defined by the formula AlXlGaX2InX3AsYlPY2NY3SbY4, where XI, X2, X3, Yl, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Other suitable substances can include II-VI compound semiconductors having a composition ZnAlCdA2SeBlTeB2, where Al, A2, Bl, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being atotal mole quantity).

[0021] Semiconductor device 100 also includes an interconnect layer 110 disposed over substrate 102. In the exemplary embodiment shown in FIG. 1, interconnect layer 110 is disposed and / or formed directly over SiN layer 108 of substrate 102. Interconnect layer 1 10 is disposed, deposited, patterned, and / or formed over substrate 102 using any suitable material deposition technique and / or process including, but not limited to, lithography, reactive ion etch (RIE), chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), chemical mechanical planarization (CMP), and the like. Additionally, interconnect layer 110 is formed from any suitable, dielectric material included within semiconductor device 100. For example, as shown in FIG. 1, interconnect layer 110 is formed from silicon dioxide (SiCh).011-2325W001

[0022] Interconnect layer 110 included in semiconductor device 100 also includes at least one interconnect 112 formed therein. More specifically, and in the exemplary embodiment interconnect 112 extends through interconnect layer 110, as well as silicon nitride (SiN) layer 108 and at least a portion of silicon dioxide (SiCh) layer 106 of substrate 102. In other exemplary embodiments, interconnect 112 extends through interconnect layer 110 and ends at, contacts, and / or is disposed over silicon nitride (SiN) layer 108 of substrate 102. Interconnect 112 included in interconnect layer 110 is formed from any suitable conductive material to facilitate the electrical connection and / or communication with various components (e. , vias, memory component, threshold switches) included within semiconductor device 100. In exemplary embodiments, interconnect 112 formed from a material or material compound including, but not limited to, Copper (Cu), cobalt (Co), iron (Fe), nickel (Ni), silver (Ag), and the like. Additionally, interconnect 112 is formed within interconnect layer 110 using any suitable material removal and / or deposition techniques. Although a single interconnect 112 is shown in FIG. 1, it is to be understood that semiconductor device 100 can include more interconnects formed therein.

[0023] A conductive cap material 118 is disposed over the interconnect 112. More specifically, and as shown in FIG. 1, conductive cap material 118 is disposed directly over interconnect 112 formed in interconnect layer 110 and is electrically coupled to interconnect 112. In exemplary' embodiments, conductive cap material 118 is selectively formed, disposed, and / or positioned only over interconnect 112, and / or does extend beyond interconnect 112 to cover any portion of interconnect layer 110. Furthermore, conductive cap material 118 also defines a surface 120 within semiconductor device 100 that is substantially planar with a surface of interconnect layer 110. Conductive cap material 118 also includes a thickness and / or height between approximately 5 nanometers (nm) and approximately 20 nm. In a non-limiting example, conductive cap material 118 is formed from ruthenium (Ru). In other exemplary embodiments, conductive cap material 118 is formed from any other suitable material including similar conductive and / or diffusion blocking properties and / or characteristics as ruthenium (Ru) including, but not limited to, tungsten (W), iridium (Ir), titanium nitride (TiN), tantalum nitride (TaN) and the like. Conductive cap material 118 is disposed, deposited, and / or formed over interconnect 112 using any suitable material deposition technique and / or process including, but not limited to, self-assembly monolayer (SAM) deposition, lithography, reactive ion etch (RIE), chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), chemical mechanical planarization (CMP), and the like.

[0024] conductive cap material 118As shown in FIG. 1, semiconductor device 100011-2325W001 also includes a botom electrode 122 positioned over interconnect 112. More specifically, and in the exemplary embodiment, bottom electrode 122 is disposed directly over, is formed directly on, contacts, and / or covers at least a portion conductive cap material 118 disposed directly over interconnect 1 12 formed in interconnect layer 110. As shown, conductive cap material 1 18 is positioned between interconnect 112 and botom electrode 122 within semiconductor device 100. At least a portion of conductive cap material 118 is exposed and / or remains uncovered by botom electrode 122 of semiconductor device 100. Additionally, botom electrode 122 is substantially aligned with and / or positioned over interconnect 112 included in interconnect layer 110. Botom electrode 122 is formed and / or disposed directly over at least a portion of conductive cap material 118 using any suitable material deposition and / or material removal processes, as discussed herein (see e.g., FIGS. 5-10).

[0025] Botom electrode 122 is formed from and / or includes at least one distinct conductive material positioned over conductive cap material 118 and / or interconnect 112. In exemplary embodiments, the at least one distinct conductive material positioned over conductive cap material 118 and / or interconnect 112 includes two distinct conductive materials 124, 126. That is. at least one of the distinct conductive materials 124, 126 are distinct from conductive cap material 118 disposed directly over interconnect 1 12. In a non-limiting example, at least first distinct conductive material 124 is distinct from conductive cap material 118, while second distinct conductive material 126 is distinct from or the same as conductive cap material 118. As shown in FIG. 1, the first distinct conductive material 124 forming botom electrode 122 includes a titanium (Ti) layer disposed directly over a portion of conductive cap material 118, and a second distinct conductive material 126 includes a titanium nitride (TiN) layer disposed directly over the first distinct conductive material 124 formed from titanium (Ti) layer. As such, the titanium (Ti) layer forming the first distinct conductive material 124 is disposed, formed, and / or positioned between conductive cap material 1 18 and the second conductive material 126 e.g., titanium nitride (TiN)) forming botom electrode. In the example, the titanium (Ti) layer and the titanium nitride (TiN) layer forming the distinct conductive material 124, 126 collectively form botom electrode 122 within semiconductor device 100. As discussed herein (see, FIG. 11), the conductive material(s) forming botom electrode 122 can be formed from additional suitable materials and / or combinations of materials.

[0026] Semiconductor device 100 also includes a hard mask layer 128 disposed over botom electrode 122. More specifically, and in the exemplary embodiment shown in FIG. 1, hard mask layer 128 is disposed directly over, is formed directly on. and / or covers titanium011-2325W001 nitride (TiN) forming second distinct conductive material 126 of bottom electrode 122. As shown, hard mask layer 128 is also substantially aligned with interconnect 112 and / or conductive cap material 118. Hard mask layer 128 is formed and / or disposed directly over bottom electrode 122 using any suitable material deposition and / or material removal processes, as discussed herein. Additionally in the exemplary' embodiments, hard mask layer 128 is formed from any suitable electrically conductive material exhibiting an electrically induced volatile resistance change including, but not limited to, silicon nitride (SiN). silicon dioxide (SiCh). aluminum oxide (A12O3), or the like.

[0027] In the exemplary embodiments, semiconductor device 100 also includes an alignment trench 130 formed therein. More specifically, alignment trench 130 is formed directly in and / or extends at least partially through interconnect layer 110, adjacent to interconnect 112. Alignment trench 130 facilitates the alignment of bottom electrode 122. hard mask layer 128, and additional portions or layers used to form semiconductor device 100 with conductive cap material 118 and / or interconnect 112, respectively. As shown in FIG. 1, at least a portion of the distinct conductive materials 124, 126 used to form bottom electrode 122 over conductive cap material 118 are also disposed and / or formed within alignment trench 130 subsequent to the formation of bottom electrode 122.

[0028] It is to be understood that semiconductor device 100 can include additional and / or distinct components and / or elements formed over and in electrical communication with interconnect 112 via conductive cap material 118 and bottom electrode 122. For example, semiconductor device 100 can include, but is not limited to, through vias, memory elements (e.g., ReRAM, PCM, FeRAM, MRAM), threshold switches, and similar elements formed over and in electrical communication with interconnect 112 via conductive cap material 118 and bottom electrode 122.

[0029] FIGS. 2-10 show various processes for forming semiconductor device 100 therein. More specifically, FIGS. 2-10 show cross-sectional views of semiconductor device 100 undergoing various processes to form semiconductor device 100 including interconnect 112, conductive cap material 118, and bottom electrode 122 over conductive cap material 118 / interconnect 112. It is understood that similarly numbered and / or named components may function in a substantially similar fashion. Redundant explanation of these components has been omitted for brevity.

[0030] FIG. 2 shows a cross-sectional view of substrate 102, and interconnect layer 110. In the exemplary embodiment, interconnect layer 110 is disposed directly over and / or on topPage ? of 22011-2325W001 of SiN layer 108 included within substrate 102. Additionally, as shown, interconnect layer 110 includes interconnect 112 disposed and / or formed therein. Interconnect 112 is formed within interconnect layer 110 using any suitable material removal and / or deposition techniques. For example, after depositing material forming interconnect layer 1 10 over SiN layer 108 of substrate 102, a portion of the material is removed from interconnect layer 110 and at least a portion of substrate 102 (e.g., via an etching process), and copper (cu) material forming interconnect 112 is subsequently deposited into interconnect layer 110.

[0031] FIG. 3 show s conductive cap material 1 18 being disposed over interconnect 112. More specifically, conductive cap material 118 is selectively deposited, disposed, and / or formed directly over interconnect 112 included in interconnect layer 110. In exemplary embodiments, conductive cap material 118 is selectively deposited only over interconnect 112 and / or is not deposited and / or disposed over an exposed surface 132 of interconnect layer 110. Conductive cap material 118 is disposed, deposited, patterned, and / or formed over interconnect 112 using any suitable material deposition technique and / or process including, but not limited to, self-assembly monolayer (SAM) deposition, lithography, reactive ion etch (RIE). chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), chemical mechanical planarization (CMP), and the like.

[0032] FIG. 4 shows the formation of alignment trench 130 within interconnect layer 110. More specifically, and subsequent to performing a material removal process, alignment trench 130 is formed in interconnect layer 110. As shown in FIG. 4. alignment trench 130 extends from surface 132 only partially into and / or through interconnect layer 110. Additionally, alignment trench 130 is formed adjacent to and / or spaced apart from interconnect 112 / conductive cap material 118 a predetermined distance (D). As discussed herein, the predetermined distance (D) facilitates ensuring features, elements, and / or components (e.g., bottom electrode 122) are formed over and / or aligned with interconnect 112 and conductive cap material 118, respectively, when forming semiconductor device 100.

[0033] FIG. 5 shows various layers being deposited over interconnect layer 110, interconnect 112, and conductive cap material 118, respectively. In the exemplary embodiment, a first bottom electrode layer 138 is deposited directly over conductive cap material 118. That is, first bottom electrode layer 138 is deposited, disposed, and / or formed directly over the entirety of conductive cap material 118, as well as exposed surface 132 (see, FIG. 5) of interconnect layer 110. First bottom electrode layer 138 is formed from any suitable electrically conductive material. In the exemplary embodiment shown in FIG. 5, depositing first bottom electrode layer 138includes depositing first distinct conductive material 124 directly over conductive cap material 118 and interconnect layer 110. respectively. Additionally, first bottom electrode layer 138 is deposited over interconnect layer 110 and conductive cap material 118 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), chemical mechanical planarization (CMP), and the like.

[0034] Additionally as shown in FIG. 5, at least one distinct bottom electrode layer 140 is deposited over first bottom electrode layer 138. More specifically, and subsequent to depositing first bottom electrode layer 138 over conductive cap material 118 and interconnect layer 110, at least one distinct bottom electrode layer 140 is disposed, deposited, and / or formed directly over first bottom electrode layer 138. The depositing of the at least one distinct bottom electrode layer 140 also includes depositing second distinct conductive material 126 directly over the first distinct conductive material 124 forming first bottom electrode layer 138. Similar to first bottom electrode layer 138, the at least one distinct bottom electrode layer 140 is formed from any suitable electrically conductive material (e.g., second distinct conductive material 126) that is distinct from first bottom electrode layer 138 (e.g, first distinct conductive material 124). In the exemplary embodiment shown in FIG. 5, the at least one distinct bottom electrode layer 140 / second distinct conductive material 126 is formed from titanium nitride (TiN), such that the distinct bottom electrode layer 140 includes a layer of titanium nitride (TiN) material deposited directly over the layer of titanium (Ti) forming the first bottom electrode layer 138 / first distinct conductive material 124. In other exemplary embodiments (see, FIG. 11), the at least one distinct bottom electrode layer 140 is formed from and / or formed as a plurality of layers of distinct, conductive materials. As such, depositing the at least one distinct bottom electrode layer 140 can include depositing second distinct conductive material 126 directly over first bottom electrode layer 140 formed from first distinct conductive material 124, and subsequently depositing a layer of a third distinct conductive material directly over second distinct conductive material 126. The at least one distinct bottom electrode layer 140 is deposited over first bottom electrode layer 138 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), chemical mechanical planarization (CMP), and the like.

[0035] A hard mask layer 128 is deposited directly over the at least one distinct bottom electrode layer 140. More specifically, hard mask layer 128 is deposited, disposed, and / or formed directly over the at least one distinct bottom electrode layer 140. Hard mask layer 128 is011-2325W001 formed from any suitable mask material including, but not limited to, silicon nitride (SiN), silicon dioxide (SiCh), aluminum oxide (A12O3), or the like.. Additionally, hard mask layer 128 is deposited over the at least one distinct bottom electrode layer 140 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), chemical mechanical planarization (CMP), and the like.

[0036] Subsequent to depositing the hard mask layer 128 over the at least one distinct bottom electrode layer 140, a lithography stack 142 is deposited directly over hard mask layer 128. In exemplary embodiments, lithography stack 142 includes an organic planarization layer (OPL) 144 deposited directly hard mask layer 128. As shown in FIG. 5, OPL 144 is deposited, disposed, and / or formed directly over hard mask layer 128. OPL 144 is formed from any suitable organic material used in material removal processes, as discussed herein. Additionally, OPL 144 is deposited over hard mask layer 128 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), a chemical mechanical planarization (CMP), and the like.

[0037] Furthermore, and as shown in FIG. 5, lithography stack 142 includes an antireflective coating (ARC) layer 146 deposited over OPL 144. More specifically, ARC layer 146 is deposited, disposed, and / or formed directly over OPL 144. ARC layer 146 is deposited over OPL 144 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical plating (ECP), chemical mechanical planarization (CMP), and the like.

[0038] Additionally, a resist mask 148 included in lithography stack 142 is formed over ARC layer 146. That is, and as shown in FIG. 5, resist mask 148 is formed over a portion of ARC layer 146. Resist mask 148 is substantially aligned with interconnect 112 and conductive cap material 1 18, respectively. In exemplary embodiments, resist mask 148 is aligned with interconnect 112 and conductive cap material 118 using alignment trench 130. More specifically, the various material layers deposited prior to forming and / or positing resist mask 148 over ARC layer 146 form and / or include identifiable or detectable features in each layer as a result of forming alignment trench 130 within interconnect layer 110. For example, hard mask layer 128 and OPL 144 each include an identifiable or detectable “bump” that is substantially aligned with alignment trench 130. The bumps in layers 128, 144 may indicate where alignment trench 130 is formed in interconnect layer 110 and thus identify where interconnect 112 and conductive cap material 118011-2325W001 are formed in interconnect layer 110 based on the known distance (D) (see, FIG. 4). Resist mask 148 is formed from any suitable material capable of facilitating the patterning of the various layers of material, as discussed herein with respect to FIGS. 6-10. Additionally, resist mask 148 is disposed and / or formed over the portion of ARC layer 146 using any suitable technique including, but not limited to, spin coating.

[0039] FIGS. 6-10 show various layers being patterned, etched, and / or removed to form semiconductor device 100 (see, FIG. 10). That is, and subsequent to forming resist mask 148 of lithography stack 142 over ARC layer 146, at least a portion of ARC layer 146, OPL 144, hard mask layer 128, the at least one distinct bottom electrode layer 140, and first bottom electrode layer 138 are etched, patterned, and / or at least partially removed to form bottom electrode 122 and hard mask layer 128 within semiconductor device 100. In exemplary embodiments, at least one patterning, etching, and / or material removal process is performed on ARC layer 146, OPL 144, hard mask layer 128, the at least one distinct bottom electrode layer 140, and first bottom electrode layer 138 to remove at least a portion of the material. The patterning, etching, and / or material removal processes include any suitable processes capable of structuring the material including, but not limited to, lithography, reactive ion etch (RIE), ion milling, wet etching, and the like.

[0040] As shown in FIG. 6, a portion of resist mask 148 and ARC layer 146 of lithography stack 142 are removed. More specifically, an exposed portion 1 0 (see, FIG. 5) of ARC layer 146 uncovered and / or exposed by resist mask 148 is removed to form a remaining pillar portion 152 of ARC layer 146. Pillar portion 152 of ARC layer 146 remains positioned below and / or under the remainder of resist mask 148. Additionally, pillar portion 152 of ARC layer 146 is disposed, formed, and / or positioned between the remainder of resist mask 148 and OPL 144.

[0041] In the exemplary embodiment shown in FIG. 7. a portion of OPL 144 of lithography stack 142 is removed. More specifically, an exposed portion 154 (see, FIG. 6) of OPL 144 uncovered and / or exposed by resist mask 148 and pillar portion 152 of ARC layer 146 is removed to form a remaining pillar portion 156 of OPL 144. Pillar portion 156 of OPL 144 remains positioned below and / or under the remainder of pillar portion 152 of ARC layer 146. Additionally, pillar portion 156 of OPL 144 is disposed, formed, and / or positioned between the remainder of pillar portion 152 of ARC layer 146 and hard mask layer 128. As shown in FIG. 7, the remainder of resist mask 148 of lithography stack 142 is completely removed from pillar portion 152 of ARC layer 146.

[0042] As show n in FIG. 8, a portion of hard mask layer 128 is removed. More specifically, an exposed portion 158 (see, FIG. 7) of hard mask layer 128 uncovered and / or exposed by pillar portion 152 of ARC layer 146 and pillar portion 156 of OPL 144 is removed to form a remaining pillar portion 160 of hard mask layer 128. Pillar portion 160 of hard mask layer 128 remains positioned below and / or under the remainder of pillar portion 156 of OPL 144. Additionally, pillar portion 160 of hard mask layer 128 is disposed, formed, and / or positioned between the remainder of pillar portion 156 of OPL 144 and at least one distinct bottom electrode layer 140. As shown in FIG. 8, the remainder of pillar portion 152 of ARC layer 146 of lithography stack 142 is completely removed from pillar portion 156 of OPL 144.

[0043] In the exemplary embodiment shown in FIG. 9, the at least one distinct bottom electrode layer 140 is partially removed. More specifically, an exposed portion 162 (see, FIG. 8) of the at least one distinct bottom electrode layer 140 uncovered and / or exposed by pillar portion 156 of OPL 144 and pillar portion 160 of hard mask layer 128 is partially removed to form both a pillar portion 164 of the at least one distinct bottom electrode layer 140, and a reduced thickness portion 166 of the at least one distinct bottom electrode layer 140. Pillar portion 164 of the at least one distinct bottom electrode layer 140 remains positioned below and / or under the remainder of pillar portion 160 of hard mask layer 128. Additionally, reduced thickness portion 1 6 of the at least one distinct bottom electrode layer 140 is disposed, formed, and / or positioned adjacent to pillar portion 164 and remains exposed and / or uncovered by pillar portion 160 of hard mask layer 128. As shown in FIG. 9, the remainder of pillar portion 156 of OPL 144 of lithography stack 142 is completely removed from pillar portion 160 of hard mask layer 128.

[0044] As shown in FIG. 10, the reduced thickness portion 166 of the at least one distinct bottom electrode layer 140 is removed. That is, the reduced thickness portion 166 of the at least one distinct bottom electrode layer 140 disposed, positioned, and / or formed adjacent pillar portion 164 is completely removed to maintain pillar portion 164 of distinct bottom electrode layer 140. In exemplar}7embodiments, pillar portion 164 of the at least one distinct bottom electrode layer 140 remains positioned below and / or under the remainder of pillar portion 160 of hard mask layer 128.

[0045] Additionally as shown in FIG. 10, portions of first bottom electrode layer 138 are removed. More specifically, portions of first bottom electrode layer 138 uncovered and / or exposed by remaining pillar portion 160 of hard mask layer 128 and pillar portion 164 of distinct bottom electrode layer 140 are removed to form pillar portion 168 of first bottom electrode layer 138. Pillar portion 168 of first bottom electrode layer 138 remains positioned below and / or under011-2325W001 the remainder of pillar portion 164 of distinct bottom electrode layer 140. Additionally, pillar portion 168 of first bottom electrode layer 138 is disposed, formed, and / or positioned between the remainder of pillar portion 164 of distinct bottom electrode layer 140 and conductive cap material 1 18. In exemplary embodiments shown in FIG. 10, the removal of uncovered and / or exposed portions of first bottom electrode layer 138 also results in exposing a portion of conductive cap material 118 formed adjacent to pillar portion 168 of first bottom electrode layer 138, as well as results in exposing surface 132 of interconnect layer 110.

[0046] As shown in FIG. 10, the etching and / or material removal of the various layers to form the various pillar portions also results in formation of bottom electrode 122 and hard mask layer 128. More specifically, the patterning, etching, and / or material removal of resist mask 148 and layers 138, 140, 128, 144, 146 facilitates hard mask layer 128 being formed from the remainder of pillar portion 160 of hard mask layer 128, and bottom electrode 122 being formed from the remainder of pillar portion 164 of distinct bottom electrode layer 140 and pillar portion 168 of first bottom electrode layer 138. In the exemplary embodiments, pillar portion 168 of first bottom electrode layer 138 forming a portion of bottom electrode 122 is disposed directly over and / or contacts conductive cap material 118.

[0047] FIG. 1 1 shows cross-sectional view of an additional exemplary embodiment of semiconductor device 200 including interconnect 212, conductive cap material 218, and electrode 222 formed therein. In the exemplary7embodiment, and as similarly discussed herein with respect to FIG. 1, semiconductor device 200 shown and discussed herein with respect to FIG. 11 is included within and / or formed in a portion of a larger semiconductor structure. It is understood that similarly numbered and / or named components may function in a substantially similar fashion. Redundant explanation of these components has been omitted for brevity7.

[0048] In the exemplary embodiment shown in FIG. 11, semiconductor device 200 includes a copper (Cu) interconnect 212 formed within interconnect layer 210, and conductive cap material 218 disposed directly over interconnect 212. Similar to semiconductor device 100 shown and discussed herein with respect to FIG. 1, semiconductor device 200 includes bottom electrode 222 disposed directly over conductive cap material 218, and a hard mask layer 228 disposed directly over bottom electrode 22. However, distinct from semiconductor device 100, bottom electrode 222 included in semiconductor device 200 includes additional layers, elements, and / or materials. In the exemplary^ embodiment show i in FIG. 11 , bottom electrode 222 includes first distinct conductive material 224 formed as tantalum nitride (TaN) disposed directly over a portion of conductive cap material 218, second distinct conductive material 226 formed as titanium (Ti)disposed directly over first distinct conductive material 224 (e.g., tantalum nitride (TaN)), and a third distinct conductive material 274 formed as titanium nitride (TiN) disposed directly over second distinct conductive material 226 (e.g.. titanium (Ti)). During processes for forming semiconductor device 200, tantalum nitride (TaN) forming first distinct conductive material 224 acts as a diffusion blocking layer for interconnect 212, as well as forms a portion of bottom electrode 222 within semiconductor device 200. In non-limiting examples, first distinct conductive material 224 formed from tantalum nitride (TaN) includes a thickness greater than approximately 2 nanometers (nm).

[0049] FIG. 12 shows a flowchart illustrating example processes 300 for manufacturing a semiconductor device. More specifically, FIG. 12 shows non-limiting examples of processes for manufacturing semiconductor devices including electrodes formed over conductive cap material and interconnects. The semiconductor device manufactured using the processes shown and discussed herein with respect to FIG. 12 may be substantially similar to semiconductor devices 100, 200 shown and discussed herein with respect to FIGS. 1-11.

[0050] In process 302, a conductive cap material is selectively deposited over an interconnect disposed within an interconnect layer disposed over a substrate. In process 304, an alignment trench is etched in an exposed portion of the interconnect layer.

[0051] In process 306, a first bottom electrode layer is deposited directly over the conductive cap material and the surface of the interconnect layer. Additionally , depositing the first bottom electrode layer includes depositing a first distinct conductive material over the conductive cap material and the interconnect layer, where the first distinct conductive material is formed from a material distinct from the conductive cap material. In a non-limiting example, depositing the first bottom electrode layer includes depositing a layer of titanium (Ti) directly over the conductive cap material and the surface of the interconnect layer. In another non-limiting example, depositing the first bottom electrode layer in process 306 further includes depositing a layer of tantalum nitride (TaN) directly over the conductive cap material and the surface of the interconnect layer.

[0052] In process 308, at least one distinct bottom electrode layer is deposited over the first bottom electrode layer. Depositing the at least one distinct bottom electrode layer can also include depositing a second distinct conductive material over the first distinct conductive material forming the first bottom electrode layer, and / or depositing a third distinct conductive material over the second distinct conductive material forming a portion of the at least one distinct bottom electrode layer. In exemplary’ embodiments, the second distinct conductive material isformed from a material distinct from the first distinct conductive material, and the third distinct conductive material is formed from a material distinct from the second distinct conductive material. Continuing the examples from process 306, where the first bottom electrode layer includes a layer of titanium (Ti), depositing the at least one distinct bottom electrode layer further includes depositing a layer of titanium nitride (TiN) directly over the layer of titanium (Ti). Conversely, where the first bottom electrode layer includes a layer of tantalum nitride (TaN), depositing the at least one distinct bottom electrode layer further includes depositing a layer of titanium (Ti) directly over the layer of tantalum nitride (TaN); and depositing a layer of titanium nitride (TiN) directly over the layer of titanium (Ti).

[0053] In process 310, a hard mask layer is deposited directly over the at least one distinct bottom electrode layer. In process 312, a lithography stack is deposited over the hard mask layer. Depositing the lithography stack in process 312 can include depositing an optical planarization layer (OPL) directly over the hard mask layer, depositing an anti-reflection coating (ARC) layer directly over the OPL. and forming a resist mask over a portion of the ARC layer. The resist mask is formed over the ARC layer and is aligned with the interconnect and / or the conductive cap material.

[0054] In process 314 the lithography stack, the hard mask layer, the at least one distinct bottom electrode layer, and the first bottom electrode layer are etched, patterned, and / or have at least a portion of the material removed. The etching of the lithography stack and the various layers in process 314 includes removing exposed portions of the ARC layer of the lithography stack exposed by the resist mask to form a pillar portion of the ARC layer under the resist mask, and removing exposed portions of the OPL exposed by the resist mask and the pillar portion of the ARC layer to form a pillar portion of the OPL under the pillar portion of the ARC layer. Furthermore, the etching in process 314 includes removing exposed portions of the hard mask layer exposed by the pillar portion of the ARC layer and the pillar portion of the OPL to form a pillar portion of the hard mask layer under the pillar portion of the OPL. Additionally, the etching in process 314 includes partially removing exposed portions of the at least one distinct bottom electrode layer exposed by the pillar portion of OPL and the pillar portion of the hard mask layer to form (1) a pillar portion of the at least one distinct bottom electrode layer disposed under the pillar portion of the hard mask layer, and (2) a reduced thickness portion of the at least one distinct bottom electrode layer disposed adjacent the pillar portion of the at least one distinct bottom electrode layer. Process 314 also includes removing the reduced thickness portion of the at least one distinct bottom electrode to maintain the pillar portion of the at least one distinctbottom electrode layer, and removing portions of the first bottom electrode layer uncovered by the pillar portion of the hard mask layer and the pillar portion of the at least one distinct bottom electrode layer to form a pillar portion of the first bottom electrode layer. Moreover, the etching in process 314 also includes exposing a portion of the conductive cap material selectively deposited over the interconnect. In exemplary' embodiments, the etching of the first bottom layer in process 312 also includes exposing the surface of the interconnect layer.

[0055] In process 316. and as a result of the etching in process 314. a bottom electrode is formed over a portion of the conductive cap material, and in turn, the interconnect.

[0056] The foregoing drawings show some of the processing associated according to several embodiments of this disclosure. In this regard, each drawing or block within a flow' diagram of the drawings represents a process associated with embodiments of the method described. It should also be noted that in some alternative implementations, the acts noted in the drawings or blocks may occur out of the order noted in the figure or, for example, may in fact be executed substantially concurrently or in the reverse order, depending upon the act involved. Also, one of ordinary' skill in the art w ill recognize that additional blocks that describe the processing may be added.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.

[0058] Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary' without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” “approximately” and “substantially,” are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and / or interchanged, such ranges areidentified and include all the sub-ranges contained therein unless context or language indicates otherwise. “Approximately” and / or “substantially” as applied to a particular value of a range applies to both values, and unless otherwise dependent on the precision of the instrument measuring the value, may indicate + / - 10% of the stated value(s).

[0059] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

CLAIMSWhat is claimed is:1 . A semiconductor device, comprising: a substrate; an interconnect layer disposed over the substrate; an interconnect disposed within the interconnect layer; a conductive cap material disposed directly over the interconnect; and a bottom electrode disposed directly over a portion of the conductive cap material, the bottom electrode electrically coupled to the interconnect via the conductive cap material.

2. The semiconductor device of claim 1, wherein the conductive cap material disposed directly over the interconnect is formed from a material selected from the group consisting of: ruthenium (Ru), iridium (Ir), tantalum nitride (TaN) and other suitable conductive materials.

3. The semiconductor device of claim 1, wherein the bottom electrode further includes at least one distinct conductive material positioned over the conductive cap material.

4. The semiconductor device of claim 3, wherein the at least one distinct conductive material positioned over the conductive cap material includes: a first distinct conductive material disposed directly over the conductive cap material, the first distinct conductive material distinct from the conductive cap material; and a second distinct conductive material disposed directly over the first distinct conductive material, the second distinct conductive material distinct from the first distinct conductive material.

5. The semiconductor device of claim 4, wherein the at least one distinct conductive material positioned over the conductive cap material further includes a third distinct conductive material disposed directly over the second distinct conductive material, the third distinct conductive material distinct from the second distinct conductive material.

6. The semiconductor device of claim 3, wherein the at least one distinct conductivematerial positioned over the conductive cap material is formed from a material selected from the group consisting of: tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN). tungsten (W), iridium (Ir), ruthenium (Ru). and other suitable conductive material.

7. The semiconductor device of claim 5, wherein the first distinct conductive material includes a thickness greater than approximately 2 nanometers (nm).

8. The semiconductor device of claim 1 further comprising a hard mask layer disposed directly over the bottom electrode, the hard mask layer formed from a material selected from the group consisting of: silicon nitride (SiN), silicon dioxide (SiCh), aluminum oxide (A12O3), and other suitable hard mask materials.

9. The semiconductor device of claim 1, wherein the conductive cap material includes a thickness between approximately 5 nanometers (nm) and approximately 20 nm.

10. A method of manufacturing a semiconductor device, the method comprising: selectively depositing a conductive cap material directly over an interconnect, the interconnect disposed within an interconnect layer disposed over a substrate; depositing a first bottom electrode layer directly over the conductive cap material and a surface of the interconnect layer; depositing at least one distinct bottom electrode layer over the first bottom electrode layer; depositing a hard mask layer directly over the at least one distinct bottom electrode layer; depositing a lithography stack directly over the hard mask layer; and etching the lithography stack, the hard mask layer, the at least one distinct bottom electrode layer, and the first bottom electrode layer to form a bottom electrode over the conductive cap material.

11. The method of claim 10, wherein the etching of the lithography stack, the hard mask layer, the at least one distinct bottom electrode layer, and the first bottom electrode layer further includes: removing exposed portions of an ARC layer included in the lithography stack exposed by a resist mask of the lithography stack to form a pillar portion of the ARC layer under the011-2325W001 resist mask; removing exposed portions of an optical planarization layer (OPL) of the lithography stack exposed by the resist mask and the pillar portion of the ARC layer to form a pillar portion of the OPL under the pillar portion of the ARC layer; removing exposed portions of the hard mask layer exposed by the pillar portion of the ARC layer and the pillar portion of the OPL to form a pillar portion of the hard mask layer under the pillar portion of the OPL; partially removing exposed portions of the at least one distinct bottom electrode layer exposed by the pillar portion of OPL and the pillar portion of the hard mask layer to form: a pillar portion of the at least one distinct bottom electrode layer disposed under the pillar portion of the hard mask layer; and a reduced thickness portion of the at least one distinct bottom electrode layer disposed adjacent the pillar portion of the at least one distinct bottom electrode layer; removing the reduced thickness portion of the at least one distinct bottom electrode to maintain the pillar portion of the at least one distinct bottom electrode layer; and removing portions of the first bottom electrode layer uncovered by the pillar portion of the hard mask layer and the pillar portion of the at least one distinct bottom electrode layer to form a pillar portion of the first bottom electrode layer.

12. The method of claim 10, wherein the etching of the lithography stack, the hard mask layer, the at least one distinct bottom electrode layer, and the first bottom electrode layer further includes: exposing a portion of the conductive cap material selectively deposited over the interconnect.

13. The method of claim 10, further comprising: etching an alignment trench in an exposed portion of the interconnect layer, the alignment trench formed adjacent the interconnect.

14. The method of claim 10, wherein the depositing of the first bottom electrode layer further includes depositing a first distinct conductive material directly over the conductive cap material, the first distinct conductive material distinct from the conductive cap material.

15. The method of claim 14, wherein the depositing of the at least one distinct bottomelectrode layer further includes depositing a second distinct conductive material directly over the first distinct conductive material, the second distinct conductive material distinct from the first distinct conductive material.

16. The method of claim 15, wherein the depositing of the at least one distinct bottom electrode layer further includes depositing a third distinct conductive material directly over the second distinct conductive material, the third distinct conductive material distinct from the second distinct conductive material.

17. The method of claim 16, wherein the first distinct conductive material, the second distinct conductive material, and the third distinct conductive material is formed from a material selected from the group consisting of: tantalum nitride (TaN). titanium (Ti), titanium nitride (TiN), tungsten (W), iridium (Ir), ruthenium (Ru), and other suitable conductive material.

18. The method of claim 14, wherein the depositing of the first distinct conductive material directly over the conductive cap material further includes forming the first distinct conductive material to include a thickness greater than approximately 2 nanometers (nm).

19. The method of claim 10, wherein selectively depositing the conductive cap material directly over the interconnect further includes forming the conductive cap material to include a thickness between approximately 5 nanometers (nm) and approximately 20 nm.

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