Pressure sensor chip and manufacturing method therefor, and pressure sensor

Abstract

The present application relates to the technical field of sensors. Disclosed in the present application are a pressure sensor chip and a manufacturing method therefor, and a pressure sensor. The pressure sensor chip comprises a support layer, a conductive layer and a first insulating layer; a first sub-support layer of the support layer comprises a first cavity, and a second sub-support layer thereof comprises at least part of a pressure sensitive film; the conductive layer comprises piezoresistive portions; at least a recess of the first insulating layer, the conductive layer and the support layer may enclose a second cavity. As the piezoresistive portions are enclosed inside the second cavity, the piezoresistive portions can be prevented from being exposed outside, thereby avoiding the impact of external media on the piezoresistive portions, and improving the reliability of pressure sensors.

Description

Pressure sensor chip and its fabrication method, pressure sensor Technical Field

[0001] This application relates to the field of sensor technology, and in particular to a pressure sensor chip and its fabrication method, and a pressure sensor. Background Technology

[0002] A pressure sensor is an electronic device that converts pressure signals into electrical signals. A pressure sensor includes a pressure sensor chip and a drive circuit. Piezoresistive pressure sensors are the most widely used due to their simple manufacturing process, low cost, and high reliability. Piezoresistive pressure sensors typically include a piezoresistive component.

[0003] Summary of the Invention

[0004] This application provides a pressure sensor chip, its fabrication method, and a pressure sensor. The technical solution is as follows:

[0005] On one hand, a pressure sensor chip is provided, the pressure sensor chip comprising: a support layer and a conductive layer stacked thereon, the support layer comprising a first sub-support layer and a second sub-support layer, the second sub-support layer being closer to the conductive layer than the first sub-support layer, the first sub-support layer comprising a first cavity; the second sub-support layer comprising at least a portion of a pressure-sensitive diaphragm; the orthographic projection of the first cavity onto a reference plane and the orthographic projection of the pressure-sensitive diaphragm onto the reference plane at least partially overlap; the conductive layer comprising a plurality of piezoresistive portions and a plurality of electrodes; the reference plane being parallel to the surface of the support layer near the conductive layer;

[0006] And, a first insulating layer, the first insulating layer is located on the side of the conductive layer away from the support layer; the side of the first insulating layer near the conductive layer includes a groove, and at least the groove, the conductive layer and the support layer form a second cavity, the orthographic projection of the pressure-sensitive film on the reference plane and the orthographic projection of the varistor on the reference plane are both located within the orthographic projection of the second cavity on the reference plane;

[0007] In this case, the orthographic projection of each varistor on the reference plane and the orthographic projection of the pressure-sensitive film on the reference plane at least partially overlap.

[0008] In some embodiments, each varistor portion includes at least one varistor, which has a convex structure on the side away from the support layer, and the orthographic projection of the first surface of the varistor away from the support layer on the reference plane is located within the orthographic projection of the second surface of the varistor close to the support layer on the reference plane.

[0009] In some embodiments, the material of the conductive layer includes a first host material and a first dopant material doped within the first host material;

[0010] In the direction from the first side to the second side of the varistor, the doping concentration of the first doped material of the conductive layer gradually decreases.

[0011] In some embodiments, the conductive layer has the same doping concentration at all points on any cross-section of the varistor in the direction from the first surface to the second surface, and the cross-section is parallel to the reference plane.

[0012] In some embodiments, the conductive layer includes multiple sub-conductive layers stacked sequentially along a direction close to the support layer; each sub-conductive layer includes a first host material and a first dopant material doped within the first host material, and the doping concentration is the same at all locations in each sub-conductive layer.

[0013] In the multilayer sub-conductive layers, the doping concentration decreases sequentially from the sub-conductive layer furthest from the support layer to the sub-conductive layer closest to the support layer.

[0014] In some embodiments, the support layer further includes a second insulating layer, and the first sub-support layer, the second insulating layer and the second sub-support layer are stacked sequentially along the direction close to the conductive layer;

[0015] The first cavity exposes a first target portion of the first insulating layer, and the pressure-sensitive membrane includes the first target portion and a second target portion of the second sub-support layer.

[0016] In some embodiments, the support layer further includes a second insulating layer, and the first sub-support layer, the second sub-support layer and the second insulating layer are stacked sequentially along the direction close to the conductive layer;

[0017] The first cavity exposes the third target portion of the second sub-support layer, and the pressure-sensitive membrane includes the third target portion and the fourth target portion of the second insulating layer;

[0018] The conductive layer consists of a first host material and a first doped material doped within the first host material; the doping concentration is the same throughout the conductive layer.

[0019] In some embodiments, the conductive layer includes four varistor sections;

[0020] The orthographic projections of the varistor in the first varistor section and the varistor in the second varistor section on the reference plane are symmetrically arranged with respect to the orthographic projection of the first axis on the reference plane. The orthographic projections of the varistor in the first varistor section and the varistor in the second varistor section on the reference plane overlap with the orthographic projection of the second axis on the reference plane. The orthographic projections of the varistor in the first varistor section and the varistor in the second varistor section on the reference plane are symmetrically arranged with respect to the orthographic projection of the second axis on the reference plane.

[0021] The orthographic projections of the varistor in the third and fourth varistor sections on the reference plane are symmetrically arranged with respect to the orthographic projection of the second axis on the reference plane. The orthographic projections of the varistor in the third and fourth varistor sections on the reference plane overlap with the orthographic projection of the first axis on the reference plane. The orthographic projections of the varistor in the third and fourth varistor sections on the reference plane are symmetrically arranged with respect to the orthographic projection of the first axis on the reference plane.

[0022] The orthographic projection of the varistor in each varistor section onto the reference plane and the orthographic projection of the pressure-sensitive film onto the reference plane at least partially overlap, and each varistor section is closer to the edge of the pressure-sensitive film relative to the center of the pressure-sensitive film.

[0023] Wherein, the orthographic projection of the first axis on the reference plane passes through the middle of the orthographic projection of the pressure-sensitive diaphragm on the reference plane, and the first axis extends along the first direction; the orthographic projection of the second axis on the reference plane passes through the middle of the orthographic projection of the pressure-sensitive diaphragm on the reference plane, and the second axis extends along the second direction; both the first and second directions are parallel to the reference plane; the second direction is perpendicular to the first direction.

[0024] In some embodiments, each varistor section includes one or more varistors; when each varistor section includes multiple varistors, each varistor section also includes at least one connecting section, the at least one connecting section being used to connect multiple varistors in series; the orthographic projection of the varistor on the reference plane and the orthographic projection of the connecting section on the reference plane are both strip-shaped.

[0025] The extension direction of the varistor included in any varistor section is the second direction, and the extension direction of the connection portion included in any varistor section is the first direction.

[0026] In some embodiments, the cross-sectional area of ​​any varistor is less than or equal to the cross-sectional area of ​​any connection portion, the cross-section of the varistor is perpendicular to the reference plane and parallel to the first direction, and the cross-section of the connection portion is perpendicular to the reference plane and parallel to the second direction.

[0027] In some embodiments, the conductive layer further includes a first connection lead and a second connection lead corresponding to each varistor portion;

[0028] For each varistor section, the first end of the varistor section is connected to one end of the first connecting lead, the other end of the first connecting lead is connected to an electrode, the second end of the varistor section is connected to one end of the second connecting lead, and the other end of the second connecting lead is connected to another electrode.

[0029] Wherein, the minimum area of ​​the cross-section of any first connecting lead is greater than or equal to the area of ​​the cross-section of any connecting part, and the minimum area of ​​the cross-section of any second connecting lead is greater than or equal to the area of ​​the cross-section of any connecting part; the cross-section of the first connecting lead is perpendicular to the routing direction of the first connecting lead, and the cross-section of the second connecting lead is perpendicular to the routing direction of the second connecting lead.

[0030] In some embodiments, the plurality of electrodes includes: a first input electrode, a second input electrode, a first output electrode, and a second output electrode;

[0031] The first input electrode is connected to the first varistor section and the third varistor section, and the second input electrode is connected to the second varistor section and the fourth varistor section; the first output electrode is connected to the first varistor section and the fourth varistor section, and the second output electrode is connected to the second varistor section and the third varistor section.

[0032] In some embodiments, the first insulating layer further includes a plurality of through holes, each corresponding to a plurality of electrodes, with each through hole exposing a portion of an electrode; the pressure sensor chip further includes a plurality of conductive component portions, each of which includes a conductive post located in the through hole, and the end of each conductive post near the conductive layer is connected to an electrode exposed by the through hole.

[0033] In some embodiments, the conductive post includes a first portion and a second portion connected in phase;

[0034] The first part is attached to the wall of the through hole, and the shape of the orthographic projection of the first part on the reference plane is annular;

[0035] The second part is located at one end of the first part near the conductive layer. The second part is surrounded by the first part and is electrically connected to the electrode.

[0036] In some embodiments, the conductive component further includes a transition portion located at the end of the conductive post away from the electrode, wherein the orthographic projection of the conductive post on the reference plane and the orthographic projection of the transition portion on the reference plane at least partially overlap, and the transition portion and the conductive post are electrically connected.

[0037] In some embodiments, the pressure sensor chip further includes a filling portion that fills a through-hole and is surrounded by conductive posts.

[0038] In some embodiments, the pressure sensor chip further includes a third insulating layer;

[0039] The third insulating layer is located between the second insulating layer and the transition portion. The third insulating layer includes a first via for exposing the conductive post. The transition portion is electrically connected to the conductive post through the first via.

[0040] In some embodiments, the conductive component portion further includes a first signal transmission layer and a transition portion, the first signal transmission layer is connected to the conductive post, and at least a portion of the orthographic projection of the first signal transmission layer on the reference plane is located outside the orthographic projection of the via on the reference plane.

[0041] The adapter is located on the side of the first signal transmission layer away from the second insulating layer. The adapter is electrically connected to the target transmission area of ​​the first signal transmission layer. The orthographic projection of the target transmission area on the reference plane and the orthographic projection of the conductive pillar on the reference plane do not overlap.

[0042] In some embodiments, the pressure sensor chip further includes a third insulating layer;

[0043] The third insulating layer is located between the first signal transmission layer and the adapter. The third insulating layer includes a first via and a second via. The first via exposes the second part of the conductive pillar, and the second via exposes the target transmission area of ​​the first signal transmission layer. The adapter is electrically connected to the target transmission area through the second via.

[0044] In some embodiments, the conductive component portion further includes an overlap portion located on the side of the second portion near the electrode, and the conductive post is electrically connected to the electrode through the overlap portion.

[0045] In some embodiments, the conductive component portion further includes a second signal transmission layer;

[0046] The second signal transmission layer is located on the side of the adapter near the second insulating layer. The second signal transmission layer is connected to the adapter. The orthographic projection of the second signal transmission layer on the reference plane and the orthographic projection of the adapter on the reference plane overlap at least partially. The adapter and the conductive post are electrically connected through the second signal transmission layer.

[0047] In some embodiments, the aperture of the via gradually increases in the direction along the support layer toward the conductive layer.

[0048] In some embodiments, the ratio of the depth of the via to the equivalent diameter of the via ranges from 5:1 to 20:1, where the equivalent diameter is the equivalent diameter of the pattern formed by the intersection of the via with the surface of the first insulating layer away from the conductive layer.

[0049] In some embodiments, the angle between the side surface of the first cavity and the bottom surface of the first cavity ranges from 89° to 91°.

[0050] Secondly, a pressure sensor is provided, the pressure sensor comprising: a pressure sensor chip according to any of the above embodiments;

[0051] In addition, a driving circuit is electrically connected to the electrodes of the pressure sensor chip. The driving circuit is used to provide a first electrical signal to the pressure sensor chip and output a second electrical signal converted by the pressure sensor chip.

[0052] Thirdly, a device integrating a pressure sensor is provided, comprising: a device body, wherein the pressure sensor is located within the device body, and the pressure sensor is the aforementioned pressure sensor.

[0053] Fourthly, a method for fabricating a pressure sensor chip is provided, for fabricating the pressure sensor chip of some of the above embodiments, comprising:

[0054] Form a conductive layer;

[0055] An initial support layer is formed, which is located on one side of the conductive layer;

[0056] A first insulating layer and a conductive layer are connected, with the groove in the first insulating layer facing the conductive layer;

[0057] The initial support layer is processed to obtain a support layer, and the side of the support layer away from the conductive layer includes a first cavity. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1A is a cross-sectional view of a pressure sensor chip provided in some embodiments of this disclosure;

[0060] Figure 1B is a cross-sectional view of a pressure sensor chip provided in some other embodiments of this disclosure;

[0061] Figure 1C is a cross-sectional view of a pressure sensor chip provided in some other embodiments of this disclosure;

[0062] Figure 1D is a cross-sectional view of a pressure sensor chip provided in some other embodiments of this disclosure;

[0063] Figure 1E is a cross-sectional view of a pressure sensor chip provided in some other embodiments of this disclosure;

[0064] Figure 1F is a cross-sectional view of a pressure sensor chip provided in some other embodiments of this disclosure;

[0065] Figure 1G is a cross-sectional view of a pressure sensor chip provided in some other embodiments of this disclosure;

[0066] Figure 1H is a cross-sectional view of a pressure sensor chip provided in some other embodiments of this disclosure;

[0067] Figure 1I is a cross-sectional view of a pressure sensor chip provided in some other embodiments of this disclosure;

[0068] Figure 1J is a cross-sectional view of a pressure sensor chip provided in some other embodiments of this disclosure;

[0069] Figure 1K is a cross-sectional view of a pressure sensor chip provided in some other embodiments of this disclosure;

[0070] Figure 1L is a cross-sectional view of a pressure sensor chip provided in some other embodiments of this disclosure;

[0071] Figure 1M is a cross-sectional view of a pressure sensor chip provided in some other embodiments of this disclosure;

[0072] Figure 1N is a cross-sectional view of a pressure sensor chip provided in some other embodiments of this disclosure;

[0073] Figure 2A is a top view of a pressure sensor chip provided in some embodiments of this disclosure;

[0074] Figure 2B is a top view of a pressure sensor chip provided in some other embodiments of this disclosure;

[0075] Figure 3A is a top view of the conductive layer of a pressure sensor chip provided in some embodiments of this disclosure;

[0076] Figure 3B is a top view of the conductive layer of a pressure sensor chip provided in some other embodiments of this disclosure;

[0077] Figure 3C is a top view of the conductive layer of a pressure sensor chip provided in some other embodiments of this disclosure;

[0078] Figures 4A to 4C are schematic diagrams of the cross-sectional shapes of varistors, and / or doped leads, and / or connections, and / or electrodes provided in some embodiments of this disclosure;

[0079] Figure 5A is a schematic diagram of the cross-sectional position of the connection portion of the pressure sensor chip provided in some embodiments of this disclosure;

[0080] Figure 5B is a schematic diagram of the cross-sectional positions of the electrodes and doped leads of a pressure sensor chip provided in some embodiments of this disclosure;

[0081] Figure 5C is a schematic diagram showing the cross-sectional position of the electrodes of a pressure sensor chip provided in some embodiments of this disclosure;

[0082] Figure 6A is a top view of the conductive layer of a pressure sensor chip provided in some embodiments of this disclosure;

[0083] Figure 6B is a top view of the conductive layer of a pressure sensor chip provided in some other embodiments of this disclosure;

[0084] Figure 6C is a top view of the conductive layer of a pressure sensor chip provided in some other embodiments of this disclosure;

[0085] Figure 7 is a top view of the conductive layer of a pressure sensor chip provided in some other embodiments of this disclosure;

[0086] Figure 8 is a top view of the conductive layer of a pressure sensor chip provided in some other embodiments of this disclosure;

[0087] Figure 9A is a schematic diagram of a Wheatstone bridge;

[0088] Figure 9B is a schematic diagram of another type of Wheatstone bridge;

[0089] Figure 9C is a schematic diagram of another type of Wheatstone bridge;

[0090] Figure 10A is a schematic diagram of the first and second portions of the conductive pillars of a pressure sensor chip provided in some embodiments of this disclosure;

[0091] Figure 10B is a schematic diagram of the first and second portions of the conductive pillars of a pressure sensor chip provided in some other embodiments of this disclosure;

[0092] Figure 11 is a cross-sectional view of a pressure sensor chip provided in some other embodiments of this disclosure;

[0093] Figure 12A is a cross-sectional view of a pressure sensor chip provided in some embodiments of this disclosure;

[0094] Figure 12B is a cross-sectional view of a pressure sensor chip provided in some other embodiments of this disclosure;

[0095] Figure 13 is a cross-sectional view of a pressure sensor chip provided in some embodiments of this disclosure;

[0096] Figure 14 is a flowchart illustrating the fabrication process of a pressure sensor chip provided in some embodiments of this disclosure;

[0097] Figures 15A to 15L are schematic diagrams of the film structure during the fabrication process of the pressure sensor chip provided in some embodiments of this disclosure;

[0098] Figure 16 is a flowchart illustrating the fabrication process of a pressure sensor chip provided in some other embodiments of this disclosure;

[0099] Figures 17A to 17L are schematic diagrams of the film structure during the fabrication process of the pressure sensor chip provided in some other embodiments of this disclosure;

[0100] Figure 18 is a flowchart illustrating the fabrication process of a pressure sensor chip provided in some other embodiments of this disclosure;

[0101] Figures 19A to 19M are schematic diagrams of the membrane structure during the fabrication process of the pressure sensor chip provided in some other embodiments of this disclosure. Detailed Implementation

[0102] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0103] In related technologies, since the pressure-sensitive resistor is directly exposed to the outside, it is easily affected by the external medium, resulting in low reliability of the pressure sensor.

[0104] In a first aspect, embodiments of this disclosure provide a pressure sensor chip, as shown in FIG1A. The pressure sensor chip provided in this embodiment includes a support layer 101 and a conductive layer 102 stacked together. The support layer 101 includes a first sub-support layer 1011 and a second sub-support layer 1012, wherein the second sub-support layer 1012 is closer to the conductive layer 102 than the first sub-support layer 1011. The first sub-support layer 1011 includes a first cavity 105, and the second sub-support layer 1012 includes at least a portion of a pressure-sensitive diaphragm.

[0105] The orthographic projection of the first cavity 105 onto the reference plane and the orthographic projection of the pressure-sensitive membrane 106 onto the reference plane at least partially overlap. The second sub-support layer 1012 including at least a portion of the pressure-sensitive membrane can have two meanings: the second sub-support layer 1012 may include a part of the pressure-sensitive membrane, and another part of the pressure-sensitive membrane may belong to other membrane layers; or, the second sub-support layer 1012 includes all of the pressure-sensitive membrane, that is, the entire pressure-sensitive membrane belongs to the second sub-support layer 1012.

[0106] In embodiments of this disclosure, the conductive layer 102 may include a plurality of piezoresistive portions 103 and a plurality of electrodes 104. The plurality of piezoresistive portions 103 and the plurality of electrodes 104 are connected to form a Wheatstone bridge, and each arm of the Wheatstone bridge includes at least one piezoresistive portion 103. Taking the pressure sensor chip shown in FIG1A and FIG3A as an example, the conductive layer 102 includes four piezoresistive portions 103 and four electrodes 104. Each piezoresistive portion 103 is connected to two electrodes 104, and at least one of the two electrodes 104 connected to different piezoresistive portions 103 is different. The four piezoresistive portions 103 and the four electrodes 104 form a Wheatstone bridge. The reference plane is parallel to the surface of the support layer 101 near the conductive layer 102.

[0107] As shown in Figure 1A, the pressure sensor chip provided in this embodiment further includes a first insulating layer 201, which is located on the side of the conductive layer 102 away from the support layer 101. The side of the first insulating layer 201 closest to the conductive layer 102 includes a groove, and at least the groove, the conductive layer 102, and the support layer 101 form a second cavity 202. The orthographic projection of the pressure-sensitive film 106 on the reference plane and the orthographic projection of the pressure-sensitive resistor portion 103 on the reference plane are both located within the orthographic projection of the second cavity 202 on the reference plane. In other embodiments of this disclosure, other objects may also be used to form the second cavity together with the groove, the conductive layer, and the support layer; this disclosure does not limit this.

[0108] For example, the second cavity 202 can be a sealed cavity.

[0109] For example, the second cavity 202 may be a vacuum cavity or a cavity with a reference pressure.

[0110] The pressure sensor chip provided in this embodiment includes a support layer 101, a conductive layer 102, and a first insulating layer 201. The first sub-support layer 1011 of the support layer 101 includes a first cavity 105, and the second sub-support layer 1012 includes at least a portion of a pressure-sensitive membrane 106. The conductive layer 102 includes a pressure-sensitive resistor portion 103. At least the groove of the first insulating layer 201, the conductive layer 102, and the support layer 101 can form a second cavity 202. Since the pressure-sensitive resistor portion 103 is enclosed inside the second cavity 202, it is prevented from being exposed to the outside, thereby avoiding the influence of external media on the pressure-sensitive resistor portion 103 and improving the reliability of the pressure sensor.

[0111] It should be noted that the pressure sensor chip shown in Figure 1A is only an example of the pressure sensor chip provided in the embodiments of this disclosure, and the pressure sensor chip provided in the embodiments of this disclosure is not limited to this.

[0112] Figures 1B to 1E, 1J, 1K, and 1N are cross-sectional views of pressure sensor chips provided in some embodiments of this disclosure. Figure 2A is a top view of a pressure sensor chip provided in some embodiments of this disclosure (the third insulating layer 206 is not shown in the figure). Figures 1B to 1E, 1J, 1K, and 1N are cross-sectional views of Figure 2A taken along the A-A' plane, which is perpendicular to the reference plane. Figures 1F to 1I, 1L, and 1M are cross-sectional views of pressure sensor chips provided in other embodiments of this disclosure. Figure 2B is a top view of a pressure sensor chip provided in other embodiments of this disclosure (the third insulating layer 206 is not shown in the figure). Figures 1F to 1I, 1L, and 1M are cross-sectional views of Figure 2B taken along the A-A' plane. Figure 3A is a top view of the conductive layer 102 of the pressure sensor chip provided in an embodiment of this disclosure. The conductive layer 102 in Figures 1B to 1N is a cross-sectional view of Figure 3A taken along the A-A' plane.

[0113] In some embodiments, as shown in FIG3A, where the dashed box represents the pressure-sensitive film 106, the orthographic projection of each varistor portion 103 on the reference plane at least partially overlaps with the orthographic projection of the pressure-sensitive film 106 on the reference plane. Each varistor portion 103 includes at least one varistor 107, as shown in FIGS. 1B to 1N, where the varistor 107 has a convex structure on the side away from the support layer 101. FIGS. 4A to 4C are enlarged cross-sectional views of the varistor 107 shown in FIGS. 1B to 1N. FIGS. 4A to 4C show various possible cross-sectional structures of a varistor 107. As shown in FIGS. 4A to 4C, the varistor 107 includes a first surface 1071 away from the support layer 101 and a second surface 1072 close to the support layer 101. The orthographic projection of the first surface 1071 of the varistor 107 away from the support layer 101 on the reference plane lies within the orthographic projection of the second surface 1072 of the varistor 107 close to the support layer 101 on the reference plane.

[0114] It should be noted that the pressure sensor chip shown in Figure 1A is an example of a pressure sensor chip according to some embodiments of this disclosure. In other embodiments of this disclosure, the first insulating layer 201 only includes grooves and does not include through holes 203. In this case, the grooves of the first insulating layer 201, the conductive layer 102, and the support layer 101 form a second cavity 202. At the same time, the first insulating layer 201 is recessed towards the center of the pressure sensor chip, and the first insulating layer 201 only covers a portion of each electrode, while the other portion of each electrode is exposed.

[0115] The pressure sensor chip provided in this embodiment is a piezoresistive pressure sensor chip. When pressure is detected and the pressure is not zero, the pressure-sensitive membrane 106 deforms in the direction from the support layer 101 to the conductive layer 102. Therefore, the second surface 1072 of the piezoresistor near the support layer 101 becomes the pressure-sensitive surface. The sensitivity of the piezoresistive pressure sensor chip involves multiple factors, including changes in the resistance value of the piezoresistor and the influence of temperature. Among these, sensitivity is positively correlated with changes in resistance value. In the pressure sensor chip provided in this embodiment, since the second surface 1072 is the pressure-sensitive surface, the orthogonal projection of the first surface 1071 of the piezoresistor 107 away from the support layer 101 onto the reference plane lies within the orthogonal projection of the second surface 1072 of the piezoresistor 107 near the support layer 101 onto the reference plane. This allows the piezoresistor 107 to have a larger pressure-sensitive area, thereby significantly reducing the stress loss during conduction within the piezoresistor 107 in the direction from the second surface 1072 to the first surface 1071. Furthermore, when pressure causes the pressure-sensitive diaphragm 106 to deform in the direction of the support layer 101 pointing towards the conductive layer 102, the resistance of the pressure-sensitive resistor 107 changes significantly, thereby making the pressure sensor chip more sensitive.

[0116] In some embodiments, the conductive layer 102 comprises a first host material and a first doped material doped within the first host material. In the direction from the first surface 1071 to the second surface 1072 of the varistor 107, the doping concentration of the first doped material in the conductive layer 102 gradually decreases. The doping concentration refers to the doping concentration of the first doped material within the first host material.

[0117] For example, in the direction from the first surface 1071 to the second surface 1072 of the varistor 107, the concentration of the first doped material of the conductive layer 102 is from 10... 20 cm -3 Up to 10 18 cm -3 The concentration of the first doped material in the conductive layer 102 changes continuously and gradually decreases. Specifically, the direction from the first surface 1071 to the second surface 1072 of the varistor 107 is perpendicular to the reference plane. In this embodiment, the concentration of the first doped material in the conductive layer 102 changes from 10... 20 cm -3 Up to 10 18 cm -3 Continuous variation can make the pressure-sensitive electrode and the Wheatstone bridge formed by the electrodes more stable, and make the output of the pressure sensor chip more stable.

[0118] In some embodiments, the doping concentration of the conductive layer 102 is the same at all points on any cross-section of the varistor 107 in the direction from the first surface 1071 to the second surface 1072, and any cross-section of the conductive layer 102 in the direction from the first surface 1071 to the second surface 1072 of the varistor 107 is parallel to the reference plane. The direction from the first surface 1071 to the second surface 1072 of the varistor 107 is perpendicular to the reference plane.

[0119] In some embodiments, the conductive layer includes multiple sub-conductive layers stacked sequentially along a direction close to the support layer. Each sub-conductive layer includes a first host material and a first dopant material doped within the first host material, and the doping concentration is the same throughout each sub-conductive layer. The doping concentration of the multiple sub-conductive layers decreases sequentially from the sub-conductive layer furthest from the support layer to the sub-conductive layer closest to the support layer.

[0120] As shown in Figure 1N, the conductive layer 102 includes a first sub-conductive layer 1021, a second sub-conductive layer 1022, and a third sub-conductive layer 1023, which are sequentially stacked along the direction close to the support layer 101. The portion of the varistor 107 located in the first sub-conductive layer 1021 is the first sub-sub-layer portion 107-1, and the portion of the first input electrode 1042 located in the first sub-sub-layer 1021 is the first sub-sub-layer portion 1042-1. The portion of the varistor 107 located in the second sub-conductive layer 1022 is the second sub-sub-layer portion 107-2, and the portion of the first input electrode 1042 located in the second sub-sub-layer 1022 is the second sub-sub-layer portion 1042-2. The portion of the varistor 107 located in the third sub-conductive layer 1023 is the third sub-sub-layer portion 107-3, and the portion of the first input electrode 1042 located in the third sub-sub-layer 1023 is the third sub-sub-layer portion 1042-3. The first sub-conductive layer 1021, the second sub-conductive layer 1022, and the third sub-conductive layer 1023 each comprise a first host material and a first doped material doped within the first host material. The doping concentration is the same at all points in the first sub-conductive layer 1021, the second sub-conductive layer 1022, and the third sub-conductive layer 1023. The doping concentration of the first sub-conductive layer 1021 is 10. 19 cm -3 Up to 10 20 cm -3 A certain value. The doping concentration of the second sub-conductive layer 1022 is approximately 10. 19 cm -3 Up to 10 18 cm -3 A certain value. The doping concentration of the third sub-conductive layer 1023 is 10. 18 cm -3 Up to 10 19 cm-3 A certain value. That is, the doping concentration can decrease sequentially from the first sub-conductive layer 1021 to the third sub-conductive layer 1023.

[0121] The pressure sensor chip shown in Figure 1N includes three conductive sublayers. In other embodiments of this disclosure, the pressure sensor chip may also include only two conductive sublayers, which is not a limitation of this disclosure. When the pressure sensor chip includes only two conductive sublayers, the conductive layer 102 includes a first conductive layer 1021 and a second conductive layer 1022 sequentially stacked along the direction close to the support layer 101. The first conductive layer 1021 and the second conductive layer 1022 respectively include a first host material and a first dopant material doped within the first host material. The doping concentration is the same at all points in the first conductive layer 1021, and the doping concentration is the same at all points in the second conductive layer 1022. The doping concentration of the first conductive layer 1021 is 10. 20 cm -3 Up to 10 18 cm -3 At a certain value, the doping concentration of the second sub-conductive layer 1022 is 10. 18 cm -3 Up to 10 16 cm -3 A certain value.

[0122] The structure of the conductive layer 102 of the pressure sensor chip shown in Figure 1N differs from that of the pressure sensor chips shown in Figures 1B to 1M. The conductive layer 102 of the pressure sensor chip shown in Figure 1N comprises multiple sub-conductive layers stacked sequentially along a direction close to the support layer 101; each sub-conductive layer includes a first host material and a first dopant material doped within the first host material, with the same doping concentration at all points within each sub-conductive layer. The doping concentration of the sub-conductive layers decreases sequentially from the layer furthest from the support layer 101 to the layer closest to the support layer 101. The material of the conductive layer 102 of the pressure sensor chips shown in Figures 1B to 1M includes a first host material and a first dopant material doped within the first host material. In the direction from the first surface 1071 to the second surface 1072 of the piezoresistive resistor 107, the concentration of the first dopant material in the conductive layer 102 gradually decreases. Furthermore, the conductive layer 102 has the same doping concentration at all points on any cross-section of the piezoresistive 107 in the direction from the first surface 1071 to the second surface 1072, and the cross-section is parallel to the reference plane. FIG. 1N is used as an example. In other embodiments of this disclosure, the conductive layer 102 of the pressure sensor chip shown in any of FIG. 1B to FIG. 1M may include multiple sub-conductive layers stacked sequentially along a direction close to the support layer 101. Each sub-conductive layer includes a first host material and a first dopant material doped within the first host material, and the doping concentration is the same at all points in each sub-conductive layer. The doping concentration of the multiple sub-conductive layers decreases sequentially from the sub-conductive layer furthest from the support layer 101 to the sub-conductive layer closest to the support layer 101.

[0123] In some embodiments, as shown in FIG1D, FIG1E, FIG1H and FIG1I, which are cross-sectional views of pressure sensor chips provided in some embodiments of the present disclosure, the support layer 101 further includes a second insulating layer 1013. The first sub-support layer 1011, the second insulating layer 1013 and the second sub-support layer 1012 are sequentially stacked along the direction close to the conductive layer 102. The first cavity 105 exposes the first target portion 1061 of the second insulating layer 1013 near the surface of the first cavity 105. In this case, the second sub-support layer 1012 may include a portion of the pressure-sensitive membrane 106, for example, the second target portion 1062 of the second sub-support layer 1012 is a portion of the pressure-sensitive membrane 106. Another portion of the pressure-sensitive membrane 106 belongs to the second insulating layer 1013, for example, the first target portion 1061 of the second insulating layer 1013 is another portion of the pressure-sensitive membrane 106. Thus, the pressure-sensitive membrane 106 includes the first target portion 1061 of the second insulating layer 1013 and the second target portion 1062 of the second sub-support layer 1012. The second target portion 1062 is the overlapping portion of the orthographic projection of the second sub-support layer 1012 on the reference plane and the orthographic projection of the first target portion 1061 on the reference plane.

[0124] In some embodiments, for the pressure sensor chip shown in Figures 1B to 1M, the material of the conductive layer 102 includes a first host material and a first dopant material doped within the first host material. Exemplarily, the first host material can be monocrystalline silicon or N-type monocrystalline silicon with a target doping concentration. The first dopant material is a P-type dopant material; exemplaryly, the first dopant material is boron atoms. The target doping concentration is 10. 15 Up to 10 17 cm -3 The first sub-support layer 1011 includes a second host material; or, the first sub-support layer 1011 includes a second host material and a second dopant material doped within the second host material. That is, the first sub-support layer 1011 may or may not be doped with a second dopant material, and this embodiment does not limit this. The second sub-support layer 1012 includes a second host material and a second dopant material doped within the second host material. Exemplarily, the second host material may be monocrystalline silicon. The second dopant material is an N-type dopant material; exemplaryly, the second dopant material is phosphorus atoms.

[0125] For example, the material of the first insulating layer 201 is monocrystalline silicon or glass. When the material of the first insulating layer 201 is monocrystalline silicon, the first insulating layer 202 and the conductive layer 102 are connected by silicon-silicon bonding technology. When the material of the first insulating layer 201 is glass, the first insulating layer and the conductive layer 102 are connected by anodic bonding technology.

[0126] Silicon-silicon bonding technology involves chemically cleaning and activating two silicon wafers, then bonding them at room temperature, followed by high-temperature annealing. This process causes a vigorous physicochemical reaction at the bonding interface, forming strong covalent bonds that increase bonding strength and create a unified whole. In this embodiment, the first insulating layer 202 and the conductive layer 102 can refer to the two silicon wafers in the silicon-silicon bonding technology.

[0127] Anodic bonding is an electric field-assisted bonding technique that can be used to bond glass and other materials. In this embodiment, when the first insulating layer 201 is made of glass, the first insulating layer and the conductive layer 102 are connected by anodic bonding.

[0128] For example, the surface of the first insulating layer 201 near the conductive layer 102 and the surface of the conductive layer 102 near the first insulating layer 201 cooperate with each other, so that after the groove of the first insulating layer 201, the conductive layer 102, and the support layer 101 form the second cavity 201, the second cavity 201 is airtight at the bonding point between the surface of the first insulating layer 201 near the conductive layer 102 and the surface of the conductive layer 102 near the first insulating layer 201, ensuring the airtightness of the second cavity. The cooperation between the surface of the first insulating layer 201 near the conductive layer 102 and the surface of the conductive layer 102 near the first insulating layer 201 can include the following two situations:

[0129] Firstly, the surface of the first insulating layer 201 near the conductive layer 102 and the surface of the conductive layer 102 near the first insulating layer 201 are both planar. These two surfaces can cooperate with each other so that the groove of the first insulating layer 201, the conductive layer 102, and the support layer 101 form a sealed second cavity.

[0130] Secondly, the surfaces of the first insulating layer 201 near the conductive layer 102 and the conductive layer 102 near the first insulating layer 201 are both curved surfaces. The convex (or concave) surfaces on the surfaces of the first insulating layer 201 near the conductive layer 102 and the concave (or convex) surfaces on the surfaces of the conductive layer 102 near the first insulating layer 201 can cooperate with each other, so that the grooves of the first insulating layer 201, the conductive layer 102, and the support layer 101 form a sealed second cavity.

[0131] The sensitivity of a pressure sensor chip refers to the proportional relationship between the change in the sensor's output signal and the change in the measured pressure. Higher sensitivity indicates a more responsive sensor to pressure changes. The piezoresistive coefficient of a piezoresistor refers to the relative change in resistivity of the piezoresistor under unit stress, expressed by the formula:

[0132] K=(Δρ / ρ) / σ Formula (1)

[0133] In the above formula (1), K represents the piezoresistive coefficient, and the unit of K is Pa. -1 Δρ represents the change in resistivity of the varistor, ρ represents the initial resistivity of the varistor, and σ represents the stress, with units of Pa.

[0134] The sensitivity of a pressure sensor chip is directly proportional to its piezoresistive coefficient. That is, the larger the piezoresistive coefficient, the higher the sensitivity of the pressure sensor chip; the smaller the piezoresistive coefficient, the lower the sensitivity of the pressure sensor chip.

[0135] For silicon materials, at very low ambient temperatures, the resistivity decreases as the ambient temperature increases, causing the piezoresistive coefficient to decrease as the ambient temperature increases; at ambient temperatures near room temperature, the resistivity increases as the ambient temperature increases, causing the piezoresistive coefficient to increase as the ambient temperature increases; at very high ambient temperatures, the resistivity decreases as the ambient temperature increases, causing the piezoresistive coefficient to decrease as the ambient temperature increases.

[0136] The relationship between the piezoresistive coefficient and the doping concentration of the varistor is as follows: the higher the doping concentration, the smaller the piezoresistive coefficient; the lower the doping concentration, the larger the piezoresistive coefficient.

[0137] Since the sensitivity of a pressure sensor chip is related to its piezoresistive coefficient, and the piezoresistive coefficient is related to the ambient temperature and the doping concentration of the varistor, the sensitivity of the pressure sensor chip will be affected by the ambient temperature and the doping concentration of the varistor. Alternatively, it can be understood that changes in ambient temperature and the doping concentration of the varistor may cause changes in the sensitivity of the pressure sensor chip.

[0138] The change in sensitivity of the pressure sensor chip caused by changes in ambient temperature can be called the temperature drift of the pressure sensor chip's sensitivity. The temperature coefficient of a varistor refers to the relative rate of change of its resistance when the ambient temperature rises or falls by 1 degree Celsius, expressed by the formula: C=(ΔR / R) / ΔT (Formula (2))

[0139] In Formula 2 above, C represents the temperature coefficient of the varistor, and the unit of C is ppm / ℃. ΔR represents the change in the resistance of the varistor, R represents the initial resistance of the varistor, and ΔT represents the change in ambient temperature per unit area.

[0140] Optionally, the temperature drift of the pressure sensor chip's sensitivity is proportional to the temperature coefficient of the piezoresistor. That is, the smaller the temperature coefficient, the smaller the temperature drift of the pressure sensor chip's sensitivity; the larger the temperature coefficient, the greater the temperature drift of the pressure sensor chip's sensitivity.

[0141] In this disclosure, as shown in Figures 1B to 1I and Figure 1N, the conductive layer 102 is formed from single-crystal silicon or N-type single-crystal silicon with a target doping concentration through P-type doping. Similarly, the varistor 107 is formed from single-crystal silicon or N-type single-crystal silicon with a target doping concentration through P-type doping. The temperature coefficient of the varistor 107 obtained in this manner is inversely proportional to its doping concentration; that is, the higher the doping concentration, the smaller the temperature coefficient; and the lower the doping concentration, the larger the temperature coefficient.

[0142] In the direction from the first surface 1071 to the second surface 1072 of the varistor 107, the concentration of the first doped material in the conductive layer 102 gradually decreases (or decreases sequentially), resulting in a higher doping concentration in the portion of the varistor 107 closer to the first surface 1071. Consequently, the temperature coefficient of this portion of the varistor 107 closer to the first surface 1071 is smaller. Therefore, for a single varistor 107, the higher doping concentration region closer to the first surface 1071 contributes to a smaller overall sensitivity temperature drift, which in turn results in a smaller sensitivity temperature drift for the pressure sensor chip.

[0143] Furthermore, in the direction from the first surface 1071 to the second surface 1072 of the varistor 107, the concentration of the first doped material in the conductive layer 102 gradually decreases (or decreases sequentially), resulting in a lower doping concentration in the portion of the varistor 107 closer to the second surface 1072. This leads to a higher piezoresistive coefficient in this portion of the varistor 107. Since the sensitivity of a pressure sensor chip is proportional to the piezoresistive coefficient, for a single varistor 107, the lower doping concentration region closer to the second surface 1072 contributes to a higher overall sensitivity of the varistor 107, thus enabling the pressure sensor chip to achieve higher sensitivity.

[0144] In summary, under the combined effect of the high and low doping concentration regions of the varistor 107, the pressure sensor chip exhibits small sensitivity temperature drift and high sensitivity.

[0145] Furthermore, in related technologies, it is common to use lightly doped N-type (the doping concentration of light doping is in the range of 10). 15 Up to 10 17 cm -3(The same applies below) A certain area of ​​P-type lightly doped region is fabricated on a silicon substrate to serve as a varistor. The P-type lightly doped region formed by this method is embedded in the N-type lightly doped silicon substrate. The PN junction structure formed by this method has more parasitic parameters and surface defects, resulting in a lower breakdown voltage. Furthermore, after the pressure sensor is powered on, the PN junction has leakage current, and the leakage current increases with the increase of ambient temperature, causing the pressure sensor chip to be unable to operate at relatively high temperatures. This limits the application scenarios of the pressure sensor and causes the measurement stability of the pressure sensor to deteriorate continuously with long-term use. In contrast, the conductive layer 102 of the pressure sensor chip provided in this embodiment is formed by P-type doping of single crystal silicon or N-type single crystal silicon with a target doping concentration, that is, the varistor 107 is formed by P-type doping of single crystal silicon or N-type single crystal silicon with a target doping concentration. In addition, the second sub-support layer 1012 is formed by N-type doping of single crystal silicon. The varistor 107 has a convex structure on the side away from the support layer 101. This allows the PN junction formed by the conductive layer 102 and the second sub-support layer 1012 to have a deeper junction depth and smaller parasitic parameters, and improves the breakdown voltage of the PN junction, enabling the pressure sensor chip to operate at higher temperatures.

[0146] Based on the above design, the support layer 101 provided in this embodiment, which only includes a first sub-support layer 1011 and a second sub-support layer 1012, allows the pressure sensor chip (e.g., the pressure sensor chips shown in Figures 1B, 1C, 1F, and 1G) to operate in a wide temperature range of -40 to 150°C. In contrast, the support layer 101 provided in this embodiment, which includes a first sub-support layer 1011, a second insulating layer 1013, and a second sub-support layer 1012 stacked sequentially, allows the pressure sensor chip to operate at temperatures above 150°C because the presence of the second insulating layer 1013 blocks leakage current between the conductive layer 102 and the first sub-support layer 1011. Furthermore, when the first cavity 105 is formed by wet etching, the second insulating layer 1013 can serve as a wet etching self-stopping layer, meaning that the etching solution hardly etches the second insulating layer 1013, which facilitates control over the size of the first cavity 105 and the thickness of the pressure-sensitive film 106.

[0147] In some embodiments, as shown in Figures 1J to 1M, which are cross-sectional views of another pressure sensor chip provided in this disclosure, the support layer 101 further includes a second insulating layer 1013. The first sub-support layer 1011, the second sub-support layer 1012, and the second insulating layer 1013 are sequentially stacked along a direction close to the conductive layer 102. The first sub-support layer 1011 includes a first cavity 105, and the first cavity 105 exposes the surface of the third target portion 1063 of the second sub-support layer 1012 near the surface of the first cavity 105. In this case, the second sub-support layer 1012 may include a portion of the pressure-sensitive membrane 106, for example, the third target portion 1063 of the second sub-support layer 1012 is a portion of the pressure-sensitive membrane 106. Another portion of the pressure-sensitive membrane 106 belongs to the second insulating layer 1013, for example, the fourth target portion 1064 of the second insulating layer 1013 is another portion of the pressure-sensitive membrane 106. Thus, the pressure-sensitive membrane 106 includes the third target portion 1063 and the fourth target portion 1064 of the second insulating layer 1013. The fourth target portion 1064 is the overlapping portion of the orthographic projection of the second insulating layer 1013 onto the reference plane and the orthographic projection of the third target portion 1063 onto the reference plane. The conductive layer 102 is made of a first host material and a first dopant material doped within the first host material, and the doping concentration is the same throughout the conductive layer 102.

[0148] In some embodiments, as shown in Figures 1J to 1M, the material of the conductive layer 102 includes a first host material and a first dopant material doped within the first host material. Exemplarily, the first host material can be polycrystalline silicon, monocrystalline silicon, or N-type monocrystalline silicon with a target doping concentration, and the first dopant material is a P-type dopant material. Exemplarily, the first dopant material is boron atoms. The target doping concentration is 10. 15 Up to 10 17 cm -3 The first sub-support layer 1011 includes a second host material; or the first sub-support layer 1011 includes a second host material and a second dopant material doped within the second host material. That is, the first sub-support layer 1011 may or may not be doped with a second dopant material, and this embodiment of the application does not limit this. The second sub-support layer 1012 includes a second host material and a second dopant material doped within the second host material. For example, the second host material may be monocrystalline silicon, and the second dopant material may be an N-type dopant material, for example, phosphorus atoms.

[0149] The support layer 101 provided in this embodiment includes a pressure sensor chip (e.g., the pressure sensor chips shown in Figures 1J to 1M) consisting of a first sub-support layer 1011, a second sub-support layer 1012, and a second insulating layer 1013 stacked sequentially. The presence of the second insulating layer 1013 blocks leakage current between the conductive layer 102 and the support layer 101, allowing the pressure sensor to operate at higher temperatures. Simultaneously, it prevents the second doped material of the conductive layer 102 from further diffusing into the support layer 101, increasing the doping concentration of the conductive layer 102 and reducing the impact of temperature on the output characteristics of the pressure sensor. Furthermore, using doped polycrystalline silicon to fabricate the varistor allows the pressure sensor chip to operate at temperatures above 200°C, as polycrystalline silicon has better high-temperature resistance than monocrystalline silicon.

[0150] As described above, Figure 3A is a top view of the conductive layer 102 of a pressure sensor chip provided in some embodiments of this disclosure, and Figures 3B and 3C are top views of the conductive layer 102 of a pressure sensor chip provided in other embodiments of this disclosure. In Figure 3A, the orthographic projection of the pressure-sensing diaphragm 106 onto the reference plane is rectangular, such as a square. In Figure 3B, the orthographic projection of the pressure-sensing diaphragm 106 onto the reference plane is circular. In Figure 3C, the orthographic projection of the pressure-sensing diaphragm 106 onto the reference plane is octagonal, such as a regular octagon. In the pressure sensor chips provided in other embodiments of this disclosure, the orthographic projection of the pressure-sensing diaphragm 106 onto the reference plane has a different shape than that of the orthographic projections of the pressure-sensing diaphragm 106 onto the reference plane in Figures 3A to 3C. For example, the orthographic projection of the pressure-sensing diaphragm 106 onto the reference plane is a polygon, such as a regular polygon, wherein the number of sides of the polygon is a multiple of 4.

[0151] Since the pressure-sensitive membrane 106 is formed by forming the first cavity 105 on the support layer 101, the shape of the orthographic projection of the pressure-sensitive membrane 106 on the reference plane is determined by the shape of the orthographic projection of the first cavity 105 on the reference plane. The shape of the orthographic projection of the first cavity 105 on the reference plane is the same as the shape of the orthographic projection of the pressure-sensitive membrane 106 on the reference plane. However, there may be process errors during the fabrication of the first cavity 105, which may cause deviations in the shape of the orthographic projection of the pressure-sensitive membrane 106 on the reference plane. Therefore, it should be noted that the shape of the orthographic projection of the pressure-sensitive membrane 106 on the reference plane is not a strictly geometric figure; it only needs to approximate that shape, which is also within the scope of protection of this disclosure.

[0152] In some embodiments, as shown in Figures 3A to 3C, the conductive layer 102 includes four varistor sections 103. The four varistor sections 103 are a first varistor section 1031, a second varistor section 1032, a third varistor section 1033, and a fourth varistor section 1034, respectively. The orthographic projections of the varistor 107 in the first varistor section 1031 and the varistor 107 in the second varistor section 1032 onto the reference plane are symmetrically arranged with respect to the orthographic projection of the first axis B-B' onto the reference plane. Both the orthographic projections of the varistor 107 in the first varistor section 1031 and the varistor 107 in the second varistor section 1032 onto the reference plane overlap with the orthographic projection of the second axis C-C' onto the reference plane. The orthographic projections of the varistor 107 in the first varistor section 1031 and the varistor 107 in the second varistor section 1032 onto the reference plane are both symmetrically arranged with respect to the orthographic projection of the second axis C-C' onto the reference plane. In other words, the orthographic projections of the plurality of varistor 107s in the first varistor section 1031 as a whole onto the reference plane, and the orthographic projections of the plurality of varistor 107s in the second varistor section 1032 as a whole onto the reference plane are both symmetrically arranged with respect to the orthographic projection of the second axis C-C' onto the reference plane. Similarly, the orthographic projections of the varistor 107 in the third varistor section 1033 and the varistor 107 in the fourth varistor section 1034 onto the reference plane are symmetrically arranged with respect to the orthographic projection of the second axis C-C' onto the reference plane. The orthographic projections of the varistor 107 in the third varistor section 1033 and the varistor 107 in the fourth varistor section 1034 onto the reference plane both overlap with the orthographic projection of the first axis B-B' onto the reference plane. The orthographic projections of the varistor 107 in the third varistor section 1033 and the varistor 107 in the fourth varistor section 1034 onto the reference plane are symmetrically arranged with respect to the orthographic projection of the first axis B-B' onto the reference plane. In other words, the orthographic projections of the plurality of varistor 107 in the third varistor section 1033 as a whole onto the reference plane and the orthographic projections of the plurality of varistor 107 in the fourth varistor section 1034 as a whole onto the reference plane are symmetrically arranged with respect to the orthographic projection of the first axis B-B' onto the reference plane.

[0153] In some embodiments, as shown in Figures 3A to 3C, the orthographic projection of the varistor 107 in each varistor section 104 onto the reference plane and the orthographic projection of the pressure-sensitive film 106 onto the reference plane at least partially overlap, and each varistor section 104 is closer to the edge of the pressure-sensitive film 106 relative to the center of the pressure-sensitive film 106.

[0154] In some embodiments, as shown in Figures 3A to 3C, the orthographic projection of the first axis B-B' onto the reference plane passes through the middle of the orthographic projection of the pressure-sensitive diaphragm 106 onto the reference plane, and the first axis B-B' extends along a first direction; the orthographic projection of the second axis C-C' onto the reference plane passes through the middle of the orthographic projection of the pressure-sensitive diaphragm 106 onto the reference plane, and the second axis C-C' extends along a second direction; both the first and second directions are parallel to the reference plane. The second direction is perpendicular to the first direction, as shown in Figures 3A to 3C, Figures 6A to 6C, Figure 7, and Figure 8, where the X-X' direction is the first direction and the Y-Y' direction is the second direction.

[0155] Through the above design, the resistance value of each piezoresistive section can be made equal, which meets the design requirements of the Wheatstone bridge. When the pressure-sensitive diaphragm is subjected to pressure, stress concentration areas exist near the edges of each side of the diaphragm, causing each piezoresistive section 104 to be closer to the edge of the pressure-sensitive diaphragm 106 relative to its center. This allows each piezoresistive section 104 to be located as close as possible to the stress concentration areas of the pressure-sensitive diaphragm 106, resulting in greater strain in each piezoresistive section 104 during pressure measurement, i.e., a greater relative rate of change in resistance, thus improving the output voltage and sensitivity of the pressure sensor chip.

[0156] In some embodiments, as shown in Figures 3A to 3C, each varistor portion 103 includes a plurality of varistors 107 and a plurality of connecting portions 108, the connecting portions 108 being used to connect the plurality of varistors 107 in series. The orthographic projection of the varistor 107 onto the reference plane and the orthographic projection of the connecting portion 108 onto the reference plane are both stripes. A strip can refer to a narrow and long shape, with at least two sides being substantially parallel. Two sides being substantially parallel can include two sides being completely parallel, or the included angle between the two sides being less than an included angle threshold. The included angle threshold can be 10 degrees, 20 degrees, or 30 degrees, etc.

[0157] In some embodiments, the extension direction of the varistor 107 included in any varistor section 103 is a second direction, and the extension direction of the connection section 108 included in any varistor section 103 is a first direction.

[0158] In some embodiments, the cross-sectional area of ​​any varistor 107 is less than or equal to the cross-sectional area of ​​any connection portion 108, as shown in Figures 1B to 1N and Figures 4A to 4C. The cross-section of any varistor 107 is perpendicular to the reference plane and parallel to the first direction. Exemplarily, as shown in Figure 5A, the cross-section of the connection portion 108 can be obtained by cutting along the D-D' plane, which is perpendicular to the reference plane and parallel to the second direction. That is, the cross-section of the connection portion 108 is perpendicular to the reference plane and parallel to the second direction. Figures 4A to 4C can also be used to show enlarged views of the cross-section of the connection portion 108.

[0159] In this disclosure, the resistance value of each varistor section is the sum of the resistance values ​​of multiple varistors. By setting the cross-sectional area of ​​any varistor to be less than or equal to the cross-sectional area of ​​any connection section, the area of ​​the orthographic projection of each varistor onto the pressure-sensitive diaphragm can be made smaller. Therefore, multiple varistors can be arranged in the stress concentration area of ​​the pressure-sensitive diaphragm, thereby facilitating the adjustment of the resistance value of the varistor section.

[0160] In some embodiments, as shown in FIG3A to 3C, the conductive layer 102 further includes a first connection lead 1091 and a second connection lead 1092 corresponding to each varistor portion 103.

[0161] In some embodiments, for each varistor portion 103, a first end of the varistor portion 103 is connected to one end of a first connecting lead 1091, and the other end of the first connecting lead 1091 is connected to an electrode 104. A second end of the varistor portion 103 is connected to one end of a second connecting lead 1092, and the other end of the second connecting lead 1092 is connected to another electrode 104. The minimum cross-sectional area of ​​any first connecting lead 1091 is greater than or equal to the cross-sectional area of ​​any connecting portion 108, and the minimum cross-sectional area of ​​any second connecting lead 1092 is greater than or equal to the minimum cross-sectional area of ​​any connecting portion 108. Exemplarily, as shown in FIG5B, the cross-section of the first connecting lead 1091 can be obtained by cutting along the E-E' plane, which is perpendicular to the routing direction of the first connecting lead 1091. That is, the cross-section of the first connecting lead 1091 is perpendicular to the routing direction of the first connecting lead 1091. For example, as shown in FIG5B, the cross-section of the second connecting lead 1092 can be obtained by cutting along the F-F' plane, which is perpendicular to the routing direction of the second connecting lead. That is, the cross-section of the second connecting lead 1092 is perpendicular to the routing direction of the second connecting lead.

[0162] By designing the minimum cross-sectional area of ​​any first connecting lead 1091 to be greater than or equal to the cross-sectional area of ​​any connecting portion 108, and the minimum cross-sectional area of ​​any second connecting lead 1092 to be greater than or equal to the minimum cross-sectional area of ​​any connecting portion 108, the resistance of the first connecting leads 1091 and 1092 can be reduced, resulting in better conductivity and more stable current flow through them. The first connecting leads 1091 and 1092 are used for input and output electrical signals to the Wheatstone bridge. This design allows for more stable operation of the pressure sensor chip and enables multiple pressure-sensitive resistors 107, multiple first connecting leads 1091, and multiple second connecting leads 1092 to be arranged in the same layer.

[0163] In some other embodiments of this disclosure, each varistor section 103 may also include only one varistor 107. In this case, each varistor section 103 does not include a connecting portion 108. For the varistor 107 included in each varistor section 103, the first end of the varistor 107 is connected to one end of the first connecting lead 1091, and the other end of the first connecting lead 1091 is connected to an electrode 104. The second end of the varistor 107 is connected to one end of the second connecting lead 1092, and the other end of the second connecting lead 1092 is connected to another electrode 104. It should be noted that the shape and position of the first doped lead 1091 and the second doped lead 1092 can be adjusted according to actual needs so that the first doped lead 1091, the second doped lead 1092, the varistor 107, and the electrode 104 can be connected while ensuring that the position of the varistor 107 remains substantially unchanged. The orthographic projection of the varistor 107 on the reference plane is a bar shape, and the extension direction of the varistor 107 included in any varistor section 103 is the second direction.

[0164] In some embodiments, as shown in Figures 3A to 3C, the electrode 104 includes a first input electrode 1041, a first ground electrode 1042, a first output electrode 1043, and a second output electrode 1044. The first input electrode 1041 is connected to the first varistor section 1031 and the third varistor section 1033, and the second input electrode 1042 is connected to the second varistor section 1032 and the fourth varistor section 1034. The first output electrode 1043 is connected to the first varistor section 1031 and the fourth varistor section 1034, and the second output electrode 1044 is connected to the second varistor section 1032 and the third varistor section 1033. The orthographic projections of the plurality of electrodes 104 on the reference plane are all "L"-shaped. The plurality of electrodes 104 are arranged around the pressure-sensitive membrane 106, and adjacent electrodes 104 are separated by grooves 110. The orthographic projection of any electrode 104 on the reference plane and the orthographic projection of the pressure-sensitive membrane 106 on the reference plane do not overlap.

[0165] Figures 6A to 6C show a top view of the conductive layer 102 of the pressure sensor chip provided in other embodiments of this disclosure. The electrode 104 includes a first input electrode 1041, a first ground electrode 1042, a first output electrode 1043, and a second output electrode 1044. The first input electrode 1041 is connected to a first piezoresistive section 1031 and a third piezoresistive section 1033. The first ground electrode 1042 is connected to the second piezoresistive section 1032 and a fourth piezoresistive section 1034. The first output electrode 1043 is connected to the first piezoresistive section 1031 and the fourth piezoresistive section 1034. The second output electrode 1044 is connected to the second piezoresistive section 1032 and the third piezoresistive section 1033. The orthographic projections of the plurality of electrodes 104 on the reference plane are all rectangular. The plurality of electrodes 104 are arranged around the pressure-sensitive membrane 106, and the orthographic projections of any electrode 104 on the reference plane and the orthographic projections of the pressure-sensitive membrane 106 on the reference plane do not overlap. In Figure 6A, the orthographic projection of the pressure-sensing diaphragm 106 onto the reference plane is a rectangle, such as a square. In Figure 6B, the orthographic projection of the pressure-sensing diaphragm 106 onto the reference plane is a circle. In Figure 6C, the orthographic projection of the pressure-sensing diaphragm 106 onto the reference plane is an octagon, such as a regular octagon. In some other embodiments of the pressure sensor chip provided in this disclosure, the orthographic projection of the pressure-sensing diaphragm 106 onto the reference plane has a different shape than that of the orthographic projections of the pressure-sensing diaphragm 106 onto the reference plane in Figures 6A to 6C. For example, the orthographic projection of the pressure-sensing diaphragm 106 onto the reference plane is a polygon, such as a regular polygon, wherein the number of sides of the polygon is a multiple of 4.

[0166] FIG7 shows a top view of the conductive layer 102 of the pressure sensor chip provided in other embodiments of this disclosure. The electrode 104 includes a first input electrode 1041, a second input electrode 1045, a first ground electrode 1042, a first output electrode 1043, and a second output electrode 1044. The first input electrode 1041 is connected to a first piezoresistive section 1031, the second input electrode 1045 is connected to a third piezoresistive section 1033, and the second input electrode 1042 is connected to the second piezoresistive section 1032 and the fourth piezoresistive section 1034. The first output electrode 1043 is connected to the first piezoresistive section 1031 and the fourth piezoresistive section 1034, and the second output electrode 1044 is connected to the second piezoresistive section 1032 and the third piezoresistive section 1033. The orthographic projections of the multiple electrodes 104 onto the reference plane are all rectangular. The multiple electrodes 104 are arranged around the pressure-sensitive membrane 106, and the orthographic projections of any electrode 104 and the pressure-sensitive membrane 106 onto the reference plane do not overlap. In Figure 7, the orthographic projection of the pressure-sensitive membrane 106 onto the reference plane is rectangular, preferably square. Similar to Figures 3A to 3C and Figures 6A to 6C, the orthographic projection of the pressure-sensitive membrane 106 onto the reference plane in Figure 7 can also be other shapes, which will not be elaborated further here.

[0167] FIG8 shows a top view of the conductive layer 102 of the pressure sensor chip provided in other embodiments of this disclosure. The electrode 104 includes a first input electrode 1041, a first ground electrode 1042, a second ground electrode 1046, a first output electrode 1043, and a second output electrode 1044. The first input electrode 1041 is connected to the first piezoresistive section 1031 and the third piezoresistive section 1033. The first ground electrode 1042 is connected to the second piezoresistive section 1032. The second ground electrode 1046 is connected to the fourth piezoresistive section 1034. The first output electrode 1043 is connected to the first piezoresistive section 1031 and the fourth piezoresistive section 1034. The second output electrode 1044 is connected to the second piezoresistive section 1032 and the third piezoresistive section 1033. The orthographic projections of the multiple electrodes 104 onto the reference plane are all rectangular. The multiple electrodes 104 are arranged around the pressure-sensitive membrane 106, and the orthographic projections of any electrode 104 and the pressure-sensitive membrane 106 onto the reference plane do not overlap. In Figure 8, the orthographic projection of the pressure-sensitive membrane 106 onto the reference plane is rectangular, for example, it could be a square. Similar to Figures 3A to 3C and Figures 6A to 6C, the orthographic projection of the pressure-sensitive membrane 106 onto the reference plane in Figure 11 can also be other shapes, which will not be elaborated further here.

[0168] In some embodiments, as shown in Figures 5B and 5C, the cross-section of electrode 104 can be obtained by cutting along the G-G' plane, or the H-H' plane, or the I-I' plane, or the J-J' plane. The G-G' and J-J' planes are perpendicular to the reference plane and parallel to the first direction, while the H-H' and I-I' planes are perpendicular to the reference plane and parallel to the second direction. Figures 4A to 4C can also be used to show enlarged views of the cross-section of electrode 104.

[0169] Figures 4A to 4C show the cross-sectional shapes of the varistor 107. It should be noted that the cross-sectional shapes shown in Figures 4A to 4C also apply to the cross-sectional shapes of the connector 108, the first connecting lead 1091, the second connecting lead 1092, and the electrode 104 along the G-G', H-H', I-I', or J-J' planes. In other words, when designing the cross-sections of the connector 108, the first connecting lead 1091, the second connecting lead 1092, and the electrode 104 along the G-G', H-H', I-I', or J-J' planes, the shapes of the cross-sections shown in Figures 4A to 4C can be used as a reference. The cross-sectional shapes shown in Figures 4A to 4C are merely schematic representations of the cross-sectional shape of the varistor 107, or they may also schematically represent the cross-sectional shape of the connector 108, the first connecting lead 1091, the second connecting lead 1092, and the cross-sectional shape of the electrode 104 along the G-G', H-H', I-I', or J-J' planes. Figures 4A to 4C do not represent the relative sizes of the aforementioned cross-sections and do not reflect the proportions of the actual cross-sections of an object.

[0170] Figure 9A is a schematic diagram of a Wheatstone bridge. The Wheatstone bridge formed by the electrode 104 and the varistor section 103 in Figures 3A to 3C and Figures 6A to 6C is equivalent to the Wheatstone bridge shown in Figure 9A. The first input electrode 1041 is connected to the power input terminal VDD, the first ground electrode 1042 is connected to the ground terminal GND, the first output electrode 1043 is connected to the first output terminal OUT1, and the second output electrode 1044 is connected to the second output terminal OUT2.

[0171] Figure 9B is a schematic diagram of another type of Wheatstone bridge. The Wheatstone bridge formed by electrode 104 and varistor 103 in Figure 7 is equivalent to the Wheatstone bridge shown in Figure 9B. The first input electrode 1041 is connected to the first power input terminal VDD1, the second input electrode 1045 is connected to the second power input terminal VDD2, the first ground electrode 1042 is connected to the ground terminal GND, the first output electrode 1043 is connected to the first output terminal OUT1, and the second output electrode 1044 is connected to the second output terminal OUT2. The voltage values ​​at the first power input terminal VDD1 and the second power input terminal VDD2 are the same.

[0172] Figure 9C is a schematic diagram of another type of Wheatstone bridge. The Wheatstone bridge formed by electrode 104 and varistor 103 in Figure 8 is equivalent to the Wheatstone bridge shown in Figure 11B. The first input electrode 1041 is connected to the power input terminal VDD, the first ground electrode 1042 is connected to the first ground terminal GND1, the second ground electrode 1046 is connected to the second ground terminal GND2, the first output electrode 1043 is connected to the first output terminal OUT1, and the second output electrode 1044 is connected to the second output terminal OUT2. The voltage values ​​of the first ground terminal GND1 and the second ground terminal GND2 are the same.

[0173] The Wheatstone bridge shown in Figures 9A to 9C includes resistors R1, R2, R3, and R4. Resistor R1 corresponds to the first varistor section 1031, and its resistance is equivalent to that of the first varistor section 1031. Resistor R2 corresponds to the second varistor section 1032, and its resistance is equivalent to that of the second varistor section 1032. Resistor R3 corresponds to the third varistor section 1033, and its resistance is equivalent to that of the third varistor section 1033. Resistor R4 corresponds to the fourth varistor section 1034, and its resistance is equivalent to that of the fourth varistor section 1034. In the embodiments of this disclosure, the resistance values ​​of the first varistor section 1031, the second varistor section 1032, the third varistor section 1033, and the fourth varistor section 1034 are all equal, which is R. For the Wheatstone bridges shown in Figures 9A to 9C: Vin = VDD - GND Equation (3)

[0174] In formulas (3) and (4) above, VDD represents the voltage value at the power input terminal, and GND represents the voltage value at the ground terminal or the first ground terminal or the second ground terminal. OUT1 represents the voltage value at the first output terminal, and OUT2 represents the voltage value at the second output terminal. Vin represents the difference between the voltage value at the power input terminal and the voltage value at the ground terminal or the first ground terminal or the second ground terminal. Vout represents the difference between the voltage value at the first output terminal and the voltage value at the second output terminal. R1, R2, R3, and R4 represent the resistance values ​​of resistors R1, R2, R3, and R4 in the Wheatstone bridge, respectively.

[0175] When the bridge is balanced, R1 = R2 = R3 = R4 = R, Vout = 0. When the pressure sensor chip is subjected to pressure, the pressure-sensitive diaphragm 106 deforms in the direction of the support layer 101 pointing towards the conductive layer 102. The resistance of the first piezoresistive section 1031 and the second piezoresistive section 1032 increases by ΔR, while the resistance of the third piezoresistive section 1033 and the fourth piezoresistive section 1034 decreases by ΔR. That is, R1 and R2 increase by ΔR, and R3 and R4 decrease by ΔR in the above equation, then:

[0176] In the above formula (5), ΔR / R is the relative rate of change of resistance, which is the ratio between the change in resistance and the initial resistance. Thus, through the Wheatstone bridge, the magnitude of the pressure is positively correlated with the relative rate of change of resistance, that is, the output voltage of the bridge is positively correlated with the relative rate of change of resistance, thereby realizing the measurement of pressure.

[0177] In some embodiments, as shown in Figures 1F to 1I, 1L and 1M, the first insulating layer 201 further includes a plurality of through holes 203, each corresponding to a plurality of electrodes 104, with each through hole 203 exposing a portion of an electrode 104. The pressure sensor chip also includes a plurality of conductive component portions 204, each including a conductive post 2041 located in the through hole 203, with one end of each conductive post 2041 near the conductive layer 102 connected to an electrode 104 exposed by the through hole 203.

[0178] For example, the conductive post 2041 includes a seed layer and a body layer. The seed layer is located on the sidewall of the via 203 and the electrode 104 is exposed on the surface of the via 203. The body layer is located on the side of the seed layer near the center of the via 203 and surrounds the body layer.

[0179] For example, the seed layer is copper, or titanium and copper, and the body layer is copper.

[0180] In some embodiments, FIG10A shows a cross-sectional view of the conductive post 2041, which is taken along plane A-A' in FIG2A or FIG2B. As shown in FIG10A, the conductive post 2041 has a first portion 2042 and a second portion 2043 connected to each other. The first portion 2042 and the second portion 2043 are separated by lines K-K' and L-L', as shown in FIG1B to FIG1N and FIG10A. The first portion 2042 is attached to the wall of the through hole 203, and the orthographic projection of the first portion 2042 on the reference plane is annular. The second portion 2043 is located at one end of the first portion 2042 near the conductive layer 102. The second portion 2043 is surrounded by the first portion, and the second portion 2043 is electrically connected to the electrode 104. The first portion 2042 includes a seed layer and a main layer, and the second portion 2043 includes a seed layer and a main layer.

[0181] For example, the shape of the orthographic projection of the first part onto the reference plane can be a circular ring, an elliptical ring, a rectangular ring, or a polygonal ring, etc.

[0182] In some embodiments, as shown in Figures 1F to 1I, 1L and 1M, the conductive component portion 204 further includes a transition portion 2044. The transition portion 2044 is located at the end of the conductive post 2041 away from the conductive layer 102. The orthographic projection of the conductive post 2041 on the reference plane and the orthographic projection of the transition portion 2044 on the reference plane at least partially overlap. The transition portion 2044 and the conductive post 2041 are electrically connected.

[0183] For example, the adapter 2044 is a solder ball.

[0184] In some embodiments, as shown in Figures 1F to 1I, 1L and 1M, the pressure sensor chip further includes a filling portion 205. The filling portion 205 fills the through-hole 203 and can be surrounded by conductive pillars 2041. The filling portion 205 can be made of an organic material, such as polyimide, or a mixture thereof, which may include epoxy resin, silicone filler, phenolic resin, solvent, etc. The filling portion 205 serves to provide support for the adapter portion 2044.

[0185] In related technologies, the interior of a through-hole is completely filled with conductive pillars to achieve electrical connection between the electrode and the adapter. However, the conductive pillars are usually made of metal (such as copper), while the first insulating layer is usually made of silicon or glass. Due to the difference in thermal expansion coefficients between the metal and the silicon or glass, when the pressure sensor chip is heated or cooled down, the metal and the silicon or glass are pulled or squeezed, leading to delamination or the metal breaking through the silicon or glass. This results in quality problems with the pressure sensor chip, and the electrical connection between the electrode 104 and the adapter 2044 becomes unstable or fails. In this disclosure, the design of the conductive pillars 2041 surrounding the filling portion 205 provides elasticity due to the material properties of the filling portion 205. This allows the filling portion 205 to both support the adapter 2044 and allow the conductive pillars 2041 to expand in the direction of the filling portion 205 when heated, thus preventing the expansion of the conductive pillars 2041 from breaking through the first insulating layer 201.

[0186] In some embodiments, as shown in Figures 1F to 1I, 1L and 1M, the pressure sensor chip further includes a third insulating layer 206. The third insulating layer 206 is located between the first insulating layer 201 and the transition portion 2044, and includes a first via 2061. The first via 2061 exposes the conductive post 2041, and the transition portion 2044 is electrically connected to the conductive post 2041 through the first via 2061. The third insulating layer 206 serves to define the position of the transition portion 2044.

[0187] In some embodiments, as shown in Figures 1B to 1E, 1J, 1K, and 1N, the first insulating layer 201 further includes a plurality of through holes 203, each corresponding to a plurality of electrodes 104, with each through hole 203 exposing a portion of an electrode 104. The pressure sensor chip also includes a plurality of conductive component portions 204, each including a conductive post 2041 located in the through hole 203, with one end of each conductive post 2041 near the conductive layer 102 connected to an electrode 104 exposed by the through hole 203.

[0188] For example, the conductive post 2041 includes a seed layer and a body layer. The seed layer is located on the sidewall of the via 203 and the electrode 104 is exposed on the surface of the via 203. The body layer is located on the side of the seed layer near the center of the via 203 and surrounds the body layer.

[0189] For example, the seed layer is copper, or titanium and copper, and the body layer is copper.

[0190] In some embodiments, FIG10A shows a cross-sectional view of the conductive post 2041, which is taken along plane A-A' in FIG2A or FIG2B. As shown in FIG10A, the conductive post 2041 includes a first portion 2042 and a second portion 2043 connected to each other. The first portion 2042 and the second portion 2043 are separated by lines K-K' and L-L', as shown in FIG1B to FIG1N and FIG10A. The first portion 2042 is attached to the wall of the through hole 203, and the orthographic projection of the first portion 2042 on the reference plane is annular. The second portion 2043 is located at one end of the first portion 2042 near the conductive layer 102. The second portion 2043 is surrounded by the first portion, and the second portion 2043 is electrically connected to the electrode 104. The first portion 2042 includes a seed layer and a main layer, and the second portion 2043 includes a seed layer and a main layer.

[0191] For example, the shape of the orthographic projection of the first part onto the reference plane can be a circular ring, an elliptical ring, a rectangular ring, or a polygonal ring, etc.

[0192] In some embodiments, as shown in Figures 1B to 1E, 1J, 1K, and 1N, the conductive component portion 204 includes a first signal transmission layer 2045 and a transition portion 2044. The first signal transmission layer 2045 is connected to the conductive post 2041. At least a portion of the orthographic projection of the first signal transmission layer 2045 onto the reference plane is located outside the orthographic projection of the through-hole 203 onto the reference plane. The transition portion 2044 is located on the side of the first signal transmission layer 2045 away from the first insulating layer 201. The transition portion 2044 is electrically connected to the target transmission area 2046 of the first signal transmission layer 2045. The orthographic projection of the target transmission area 2046 onto the reference plane and the orthographic projection of the conductive post 2041 onto the reference plane do not overlap.

[0193] In some embodiments, the orthographic projection of any electrode 104 on the reference plane and the orthographic projection of the pressure-sensitive diaphragm 106 on the reference plane do not overlap. With this design, the presence of the electrode 106 can be avoided from affecting the deformation of the pressure-sensitive diaphragm 106 when subjected to pressure, thereby improving the accuracy of the pressure sensor chip measurement.

[0194] For example, the conductive pillar 2041 and the first signal transmission layer 2045 are integral components, meaning they can be formed in a single process. The first signal transmission layer 2045 also includes a seed layer and a main layer, with the main layer located on the side of the seed layer away from the first insulating layer 201. The materials of the seed layer and the main layer of the first signal transmission layer 2045 are the same as those of the seed layer and the main layer of the conductive pillar 2041, respectively, and will not be described again here.

[0195] In related technologies, the interior of a through-hole is completely filled with conductive pillars to achieve electrical connection between the electrode and the adapter. However, the conductive pillars are usually made of metal (such as copper), while the first insulating layer is usually made of silicon or glass. Due to the difference in thermal expansion coefficients between the metal and the silicon or glass, when the pressure sensor chip is heated or cooled down, the metal and the silicon or glass are pulled or squeezed, leading to delamination or the metal breaking through the silicon or glass. This results in quality problems with the pressure sensor chip, and the electrical connection between the electrode and the adapter becomes unstable or fails. In this disclosure, by providing conductive pillars 2041 and a first signal transmission layer 2045, and by attaching the first portion 2042 of the conductive pillars 2041 to the wall of the through-hole 203, free space is left in the through-hole 203. This allows the conductive pillars 2041 to expand towards this free space when heated, thus preventing the expansion of the conductive pillars 2041 from breaking through the first insulating layer 201.

[0196] In some embodiments, as shown in Figures 1B to 1E, 1J, 1K, and 1N, the pressure sensor chip further includes a third insulating layer 206. The third insulating layer 206 includes a first insulating portion 2063, which is located between the first signal insulating layer 2045 and the transition portion 2044. The third insulating layer 206 includes a first via 2061 and a second via 2062. The first via 2061 exposes a second portion 2043 of the conductive post 2041. The second via 2062 exposes a target transmission region 2046 of the first signal transmission layer 2045, and the transition portion 2044 is electrically connected to the target transmission region 2046 through the second via 2062.

[0197] In some embodiments, as shown in Figures 1B to 1E, 1J, 1K, and 1N, the third insulating layer 206 further includes a second insulating portion 2064. A portion of the second insulating portion 2064 is located on the side of the first signal transmission layer 2045 away from the first insulating layer 201, and another portion of the second insulating portion 2064 is located on the side of the first insulating layer 201 away from the conductive layer 102. Exemplarily, the material of the third insulating layer 206 is solder resist.

[0198] In this embodiment of the disclosure, the design of the third insulating layer 206 limits the position of the adapter 2044. At the same time, the third insulating layer 206 covers the first signal transmission layer 2045, avoiding the influence of the external environment on the first signal transmission layer 2045, which can make the working state of the pressure sensor more stable.

[0199] In some embodiments, as shown in FIG11, the conductive component 204 further includes an overlap portion 2047. Referring to FIG11 and FIG10B, in FIG10B, the conductive post 2041 includes a first portion 2042 and a second portion 2043 connected to each other. The first portion 2042 and the second portion 2043 are separated by K-K' line and L-L' line. The overlap portion 2047 is located on the side of the second portion 2043 of the conductive post 2041 closer to the electrode 104. The conductive post 2041 is electrically connected to the electrode 104 through the overlap portion 2047.

[0200] It should be noted that FIG11 uses the pressure sensor chip shown in FIG1B as an example to illustrate the case where the conductive component portion 204 includes the overlapping portion 2047. In some other embodiments of this disclosure, the conductive component portion 204 of the pressure sensor chip shown in FIG1C to FIG1N may also include the overlapping portion 2047, and the position of the overlapping portion 2047 is shown in FIG11.

[0201] For example, the material of the overlap portion 2047 is copper. In this embodiment of the present disclosure, through the above-described design of the overlap portion 2047, after the conductive layer 102 is subjected to high-temperature annealing during the preparation process, the overlap portion 2047 and the electrode 104 can form an ohmic contact, thereby ensuring that after the conductive pillar 2041 is subsequently formed, the overlap portion 2047, the conductive pillar 2041, and the transition portion 2044 constitute an electrical path, improving the stability of the input and output electrical signals of the Wheatstone bridge.

[0202] In some implementations, as shown in Figures 12A and 12B, the conductive component 204 further includes a second signal transmission layer 2048. The second signal transmission layer 2048 is located on the side of the adapter 2044 near the first insulating layer 201. The second signal transmission layer 2048 is connected to the adapter 2044. The orthographic projection of the second signal transmission layer 2048 on the reference plane and the orthographic projection of the adapter 2044 on the reference plane at least partially overlap. The adapter 2044 and the conductive post 2041 are electrically connected through the second signal transmission layer 2048.

[0203] It should be noted that FIG12A uses the pressure sensor chip shown in FIG1B as an example to illustrate the case where the conductive component portion 204 includes the second signal transmission layer 2048, and FIG12B uses the pressure sensor chip shown in FIG1F as an example to illustrate the case where the conductive component portion 204 includes the second signal transmission layer 2048. In some other embodiments of this disclosure, the conductive component portion 204 of the pressure sensor chips shown in FIGS. 1C to 1E, 1J, 1K, and 1N may also include the second signal transmission layer 2048, and the position of the second signal transmission layer 2048 is shown in FIG12A. In some other embodiments of this disclosure, the conductive component portion 204 of the pressure sensor chips shown in FIGS. 1F to 1I, 1L, and 1M may also include the second signal transmission layer 2048, and the position of the second signal transmission layer 2048 is shown in FIG12B.

[0204] It should be noted that the conductive component portion 204 of any of the pressure sensor chips shown in Figures 1B to 1N may simultaneously include the overlapping portion 2047 and the second signal transmission layer 2048, as shown in Figure 13, or may only include either the overlapping portion 2047 or the second signal transmission layer 2048. This disclosure does not limit this.

[0205] For example, the second signal transmission layer 2048 is a nickel-palladium-gold protective layer. The second signal transmission layer 2048 can serve as a bonding layer for interconnecting the adapter 2044 with the conductive post 2041 or the first signal transmission layer 2045, ensuring an electrical connection between the conductive post 2041 or the first signal transmission layer 2045 and the adapter 2044. Since the adapter 2044 is made of solder balls, the second signal transmission layer 2048 prevents the diffusion of solder ball material atoms into the first signal transmission layer 2045, thus preventing the formation of brittle metal compounds in the first signal transmission layer 2045 and avoiding corrosion, which would significantly reduce the reliability of the interconnect system.

[0206] In some embodiments, as shown in any of Figures 1B to 1N, the orthographic projection of the through-hole 203 onto another reference plane is trapezoidal. This other reference plane is perpendicular to the reference plane in the above embodiments. The aperture of the through-hole 203 gradually increases in the direction along the support layer 101 towards the conductive layer 102. The angle between the orthographic projection of the waist of the trapezoid onto the reference plane and the waist of the trapezoid is θ, and θ ranges from 40° to 60°.

[0207] In some embodiments, the orthographic projection of the through-hole 203 onto the reference plane is a circular ring, an elliptical ring, a rectangular ring, or a polygonal ring, etc. The ratio of the depth of the through-hole 203 to its equivalent diameter ranges from 5:1 to 20:1. The equivalent diameter of the through-hole 203 is the equivalent diameter of the pattern formed by the intersection of the through-hole 203 and the surface of the first insulating layer 201 away from the conductive layer 102.

[0208] In this embodiment, a robust connection needs to be formed between the conductive pillar 2041 and the first signal transmission layer 2045 to ensure a stable electrical connection. The conductive pillar 2041 and the first signal transmission layer 2045 are typically formed using physical vapor deposition (PVD) and electroless plating. In this embodiment, by setting θ to a range of 40° to 60°, a robust connection can be formed between the formed conductive pillar 2041 and the first signal transmission layer 2045. Furthermore, by using the aforementioned θ range of 40° to 60° and the design of the ratio of the depth to the equivalent diameter of the via 203 to a range of 5:1 to 20:1, the area occupied by the via 203 on the pressure sensor chip can be minimized, thereby minimizing the area of ​​the pressure sensor chip itself and reducing its size and volume. The area of ​​the pressure sensor chip refers to the area of ​​the orthogonal projection of the pressure sensor chip onto the reference plane, and the area of ​​the pressure sensor chip occupied by the through hole 203 refers to the ratio of the area of ​​the orthogonal projection of the through hole 203 onto the reference plane to the area of ​​the orthogonal projection of the pressure sensor chip onto the reference plane.

[0209] In some embodiments, as shown in Figures 1C, 1E, 1F, 1H, 1K, and 1M, the included angle between the side surface and the bottom surface of the first cavity 105 is . The range is 89° to 91°. The portion of the surface of the second sub-support layer 1012 or the second insulating layer 1013 on the side away from the conductive layer 102 exposed to the first cavity 105 constitutes the bottom surface of the first cavity 105. Exemplarily, the orthographic projection of the first cavity 105 onto the reference plane is a polygon, such as a rectangle or a circle. When the orthographic projection of the first cavity 105 onto the reference plane is a polygon, the first cavity is a prism or frustum, and the included angle between the side surface and the bottom surface of the first cavity 105... This is equivalent to the angle between the lateral surface of a prism or frustum and the bottom surface of the first cavity 105. When the orthographic projection of the first cavity 105 onto the reference plane is a circle, then the first cavity is a cylinder or frustum, and the angle between the lateral surface of the first cavity 105 and the bottom surface of the first cavity 105 is... It is equivalent to the angle or supplementary angle between the orthographic projection of the generatrix of the cylinder or frustum onto the plane containing the bottom surface of the first cavity 105 and the generatrix of the cylinder or frustum.

[0210] In this embodiment, the pressure sensor chips shown in Figures 1B, 1D, 1G, 1I, 1J, 1L, and 1N are referred to as first-type pressure sensor chips. The first cavity 105 of the first-type pressure sensor chip is formed by wet etching, and the angle between the side surface and the bottom surface of the first cavity 105 ranges from 120° to 130°. The first-type pressure sensor chip has the largest area. The pressure sensor chips shown in Figures 1C, 1E, and 1K are referred to as second-type pressure sensor chips. The first cavity 105 of the second-type pressure sensor chip is formed by dry etching, and the angle between the side surface and the bottom surface of the first cavity 105 ranges from 89° to 91°. The area of ​​the first cavity 105 of the second-type pressure sensor is smaller. Meanwhile, compared to the first type of pressure sensor chip, the conductive component portion 204 and the through hole 203 of the second type of pressure sensor chip can be positioned closer to the center of the first insulating layer 201. Therefore, the area of ​​the second type of pressure sensor chip is 10% to 15% smaller than that of the first type of pressure sensor chip. The pressure sensor chips shown in Figures 1F, 1H, and 1M are referred to as third type pressure sensor chips. The first cavity 105 of the third type of pressure sensor chip is formed by dry etching, and the angle between the side surface and the bottom surface of the first cavity 105 ranges from 89° to 91°. The area of ​​the first cavity 105 of the third type of pressure sensor is even smaller. Furthermore, compared to the first type of pressure sensor chip, the conductive component portion 204 and the through hole 203 of the third type of pressure sensor chip can be positioned closer to the center of the first insulating layer 201. Therefore, the area of ​​the third type of pressure sensor chip is approximately 50% smaller than that of the first type of pressure sensor chip.

[0211] It should be noted that the area of ​​any of the above components is the area of ​​the orthographic projection of that component onto the reference plane.

[0212] Secondly, embodiments of this disclosure provide a pressure sensor, including a pressure sensor chip provided in the embodiments of the first aspect of this disclosure, and a driving circuit, wherein the driving circuit is electrically connected to the electrodes 104 of the pressure sensor chip. The driving circuit is used to provide a first electrical signal to the pressure sensor chip and output a second electrical signal converted by the pressure sensor chip.

[0213] For example, the drive circuit can be electrically connected to the first input electrode 1041, the first ground electrode 1042, the first output electrode 1043, and the second output electrode 1044. The first input electrode 1041 is connected to the power input terminal VDD, the first ground electrode 1042 is connected to the ground terminal GND, the first output electrode 1043 is connected to the first output terminal OUT1, and the second output electrode 1044 is connected to the second output terminal OUT2. As described above:

[0214] In the above formula (6), Vin is the first electrical signal provided by the driving circuit to the pressure sensor chip, and Vout is the second electrical signal output by the driving circuit after being converted by the pressure sensor chip.

[0215] Since the pressure sensor can have essentially the same technical effect as the pressure sensor chip described in the previous embodiments, for the sake of brevity, the technical effect of the pressure sensor will not be described again here.

[0216] Thirdly, embodiments of this disclosure provide an apparatus integrating a pressure sensor, the apparatus including an apparatus body and a pressure sensor located within the apparatus body, the pressure sensor being the pressure sensor provided in the embodiments of the second aspect of this disclosure described above.

[0217] For example, if the device is a car, then the main body of the device is the car's outer shell.

[0218] For example, if the device is an air conditioning system, then the main body of the device is the outer casing of the air conditioning system.

[0219] Since the device integrating the pressure sensor can have essentially the same technical effect as the pressure sensor chip described in the previous embodiments, for the sake of brevity, the technical effect of the device integrating the pressure sensor will not be described again here.

[0220] Fourthly, this disclosure provides a method for fabricating a pressure sensor chip, used to fabricate the pressure sensor chip described in the first aspect of this disclosure.

[0221] As shown in Figure 14, the fabrication method of the pressure sensor chip in some embodiments of this disclosure may include the following steps S100-S500:

[0222] Step S100: A first substrate is provided, the first substrate comprising a first sublayer and a second sublayer stacked sequentially.

[0223] Step S200: The second sublayer is doped and etched to form a conductive layer.

[0224] Step S300: The first sub-layer is etched to form a support layer. The side of the support layer away from the conductive layer includes a first cavity, and the unetched portion of the support layer near the conductive layer is the pressure-sensitive film included in the support layer.

[0225] Step S400: A second substrate is provided, the second substrate including opposing first and second surfaces, and a groove is formed on the first surface of the second substrate to form a first insulating layer.

[0226] Step S500: Connect the first insulating layer and the conductive layer, with the groove of the first insulating layer facing the conductive layer.

[0227] Figures 15A-15L are schematic diagrams of the membrane structure during the fabrication process of pressure sensor chips according to some embodiments of this disclosure.

[0228] By way of example, in the embodiments of this disclosure, with reference to Figures 15A-15L, the detailed description of each step in the fabrication method of the pressure sensor chip is as follows:

[0229] In step S100, a first substrate is provided, the first substrate comprising a first sublayer and a second sublayer stacked sequentially.

[0230] Specifically, as shown in Figure 15A, a first substrate is provided, which includes a first sublayer 301 and a second sublayer 302 stacked sequentially, wherein the first substrate is an N-type lightly doped silicon substrate.

[0231] In step S200, the second sublayer is doped and etched to form a conductive layer.

[0232] Specifically, as shown in Figure 15B, an oxide layer 303 is formed on two opposite surfaces of the first substrate using high-temperature oxidation technology, serving as a protective layer for subsequent ion implantation processes. Next, ion implantation is performed on the third sublayer 303, i.e., doping of the third sublayer 303, for example, p-type doping. After doping, the oxide layer 303 is removed. Next, as shown in Figure 15C, a photoresist layer 304 is formed using photolithography, and a conductive layer 102 is formed by dry etching or wet etching. The conductive layer 102 includes multiple varistors 107 and multiple electrodes 104. Next, the conductive layer 102 is annealed, causing the doping concentration of the conductive layer 102 to gradually decrease from the surface of the conductive layer 102 furthest from the first sublayer 301 to the surface closer to the first sublayer 301.

[0233] For example, as shown in FIG15D, the fabrication method of the pressure sensor chip further includes forming an overlap portion 2047 on the side of the electrode 104 away from the first sub-layer 301. Specifically, a metal layer of a predetermined thickness can be formed on the surface of the side of the electrode 104 away from the first sub-layer 301, and then the overlap portion 2047 can be formed by photolithography and etching processes. The etching process can be a wet etching process or a metal lift-off technology. After forming the overlap portion 2047, high-temperature annealing is performed, which can make the overlap portion 2047 and the electrode 104 form an ohmic contact, thereby forming a good electrical connection between the two.

[0234] It should be noted that in some other embodiments of this disclosure, the overlapping portion 2047 may not be prepared.

[0235] For example, as shown in FIG15D, the fabrication method of the pressure sensor chip further includes providing a protective layer 305 in the gap between the piezoresistive resistor 107 and the electrode 104, and on the side of the electrode 104 away from the first sub-layer 301. The protective layer 305 may be, for example, an organic material, to protect the piezoresistive resistor 107 and the electrode 104 of the pressure sensor chip during the subsequent etching process of the first cavity 105. As shown in FIG15E, the fabrication method of the pressure sensor chip further includes forming a patterned mask layer 306 on the surface of the first sub-layer 301 away from the conductive layer 102. The mask layer 306 serves as a mask layer during the etching of the first sub-layer 301 to form the first cavity 105, and the mask layer 307 may be, for example, silicon nitride.

[0236] In step S300, the first sub-layer is etched to form a support layer. The side of the support layer away from the conductive layer includes a first cavity, and the unetched portion of the support layer near the conductive layer is the pressure-sensitive film included in the support layer.

[0237] Specifically, as shown in Figure 15F, the first sub-layer 301 is etched to form a support layer 101. The side of the support layer 101 away from the conductive layer 102 includes a first cavity 105, and the unetched portion of the support layer 101 near the conductive layer 102 is the pressure-sensitive film 106 included in the support layer 101, as shown in the dashed box in Figure 15F.

[0238] In step S400, a second substrate is provided, the second substrate including opposing first and second surfaces, and a groove is formed on the first surface of the second substrate to form a first insulating layer.

[0239] Specifically, as shown in FIG15G, a second substrate is provided, the second substrate including opposing first surfaces 401 and second surfaces 402. As shown in FIG15I, a groove is formed in the first surface 401 of the second substrate to form a first insulating layer 201.

[0240] For example, as shown in FIG15I, forming the first insulating layer 201 further includes forming a plurality of through holes 203 penetrating the second substrate.

[0241] For example, the second substrate is a glass sheet. As shown in FIG15H, before forming grooves and vias on the second substrate, the locations on the second substrate where grooves and vias need to be formed are laser-induced modified, and then the glass sheet is etched using HF solution to form grooves and vias.

[0242] In some embodiments, step S400 may be performed before or after any of steps S100, S200 and S300, and this disclosure does not limit this.

[0243] In step S500, the first insulating layer and the conductive layer are connected, with the groove of the first insulating layer facing the conductive layer.

[0244] Specifically, as shown in Figure 15J, the first insulating layer 201 is disposed on the side of the conductive layer 102 away from the support layer 101, and the groove, the conductive layer 102, and the support layer 101 form a second cavity 202. When the first insulating layer 201 is glass, the first insulating layer 201 and the conductive layer 202 are connected by anodic bonding, and the second cavity 202 is a sealed cavity.

[0245] For example, as shown in FIG15K, the fabrication method of the pressure sensor chip further includes forming conductive pillars 2041 and a first signal transmission layer 2045. Forming the conductive pillars 2041 includes forming a seed layer using physical vapor deposition (PVD), the seed layer being, for example, titanium / copper. A body layer is formed using electroplating or chemical plating, the body layer being, for example, copper. The seed layer is located on the sidewall of the via 203, the surface of the electrode 104 exposed in the via 203, and the surface of the overlap portion 2047 away from the electrode 104. The body layer is located on the side of the seed layer near the center of the via 203, and the seed layer surrounds the body layer. Forming the first signal transmission layer 2045 includes forming a seed layer using physical vapor deposition (PVD), the seed layer being, for example, titanium / copper. A body layer is formed using electroplating or chemical plating, the body layer being, for example, copper. The body layer is located on the side of the seed layer away from the first insulating layer 201. For example, the seed layer of the conductive pillar 2041 and the seed layer of the first signal transmission layer 2045 can be formed in a single process, and the main layer of the conductive pillar 2041 and the main layer of the first signal transmission layer 2045 can be formed in a single process.

[0246] For example, as shown in FIG15L, the fabrication method of the pressure sensor chip further includes forming a third insulating layer 206. Specifically, the third insulating layer 206 is formed on a portion of the surface of the first insulating layer 201 away from the conductive layer 102, and on the side of the first signal transmission layer 2045 away from the first insulating layer 201. The third insulating layer 206 includes a first via 2061 and a second via 2062. The first via 2061 exposes the conductive post 2041, and the second via 2062 exposes the target transmission area 2046 of the first signal transmission layer 2045. The portion outlined by the dashed box in FIG15L is the target transmission area 2046 of the first signal transmission layer 2045.

[0247] For example, as shown in FIG15L, the method for fabricating a pressure sensor chip further includes forming a second signal transmission layer 2048. The second signal transmission layer 2048 is located on the side of the adapter 2044 near the first insulating layer 201, and is connected to the adapter 2044. The adapter 2044 and the conductive post 2041 are electrically connected through the second signal transmission layer 2048. For example, the second signal transmission layer 2048 is a nickel-palladium-gold protective layer, which can be prepared using chemical plating technology on the surface of the first signal transmission layer 2045 away from the second insulating layer and on the surface of the third insulating layer 206 away from the second insulating layer.

[0248] For example, as shown in FIG15L, the method for fabricating a pressure sensor chip further includes forming a transition portion 2044. The transition portion 2044 is located on the side of the first signal transmission layer 2045 away from the first insulating layer 201, and the transition portion 2044 is electrically connected to the target transmission area 2046 of the first signal transmission layer 2045. For example, the transition portion 2044 is a solder ball, which can be formed by processes such as applying flux, placing solder balls, reflowing, and cleaning.

[0249] It should be noted that in some other embodiments of this disclosure, the second signal transmission layer 2048 may not be prepared. In this case, the adapter 2044 is located on the side of the first signal transmission layer 2045 away from the first insulating layer 201, and the adapter 2044 and the target transmission area 2046 of the first signal transmission layer 2045 are in contact connection.

[0250] As shown in Figure 16, the fabrication method of the pressure sensor chip in some other embodiments of this disclosure may include the following steps S100-S500:

[0251] Step S100: A first substrate is provided, the first substrate comprising a first sublayer, a second insulating layer, a second sublayer and a third sublayer stacked sequentially.

[0252] In step S200, the third sublayer is doped and etched to form a conductive layer, and the first sublayer, the second insulating layer, and the second sublayer form an initial support layer.

[0253] Step S300: A second substrate is provided, the second substrate including opposing first and second surfaces, and a groove is formed on the first surface of the second substrate to form a first insulating layer.

[0254] Step S400: Connect the first insulating layer and the conductive layer, with the groove of the first insulating layer facing the conductive layer.

[0255] Step S500: The initial support layer is processed to obtain a support layer, and the side of the support layer away from the conductive layer includes a first cavity.

[0256] The process of processing the initial support layer to obtain the support layer can refer to etching the first sub-layer to form a first cavity, thereby forming a first sub-support layer. Furthermore, the second sub-layer can form a second sub-support layer. The first sub-support layer, the second insulating layer, and the second sub-support layer constitute the support layer, and the portions of the second insulating layer and the second sub-support layer exposed in the first cavity constitute a pressure-sensitive membrane.

[0257] Figures 17A-17L are schematic diagrams of the membrane structure during the fabrication process of pressure sensor chips according to other embodiments of this disclosure.

[0258] By way of example, in the embodiments of this disclosure, with reference to Figures 17A-17L, the detailed description of each step in the fabrication method of the pressure sensor chip is as follows:

[0259] In step S100, a first substrate is provided, the first substrate comprising a first sublayer, a second insulating layer, a second sublayer and a third sublayer stacked sequentially.

[0260] Specifically, as shown in Figure 17A, a first substrate is provided, which includes a first sublayer 301, a second insulating layer 1013, a second sublayer 302 and a third sublayer 303 stacked sequentially, wherein the first sublayer 301, the second sublayer 302 and the third sublayer 303 are lightly doped N-type silicon substrates.

[0261] In step S200, the third sublayer is doped and etched to form a conductive layer, and the first sublayer, the second insulating layer, and the second sublayer form an initial support layer.

[0262] Specifically, as shown in Figure 17B, an oxide layer 304 is formed on two opposite surfaces of the first substrate using high-temperature oxidation technology, serving as a protective layer for subsequent ion implantation processes. Next, ion implantation is performed on the third sublayer 303, i.e., doping of the third sublayer 303, for example, P-type doping. After doping is complete, the oxide layer 304 is removed. Next, as shown in Figure 17C, a photoresist layer 305 is formed using photolithography, and a conductive layer 102 is formed by dry etching or wet etching. The conductive layer 102 includes multiple varistors 107 and multiple electrodes 104. Next, the conductive layer 102 is annealed, causing the doping concentration of the conductive layer 102 to gradually decrease from the side of the conductive layer 102 furthest from the first sublayer 301 to the side closer to the first sublayer 301.

[0263] For example, as shown in FIG17D, the fabrication method of the pressure sensor chip further includes forming an overlap portion 2047 on the side of the electrode 104 away from the first sub-layer 301. Specifically, a metal layer of a predetermined thickness can be formed on the surface of the side of the electrode 104 away from the first sub-layer 301, and then the overlap portion 2047 can be formed by photolithography and etching processes. The etching process can be a wet etching process or a metal lift-off technology. After forming the overlap portion 2047, high-temperature annealing is performed, which can make the overlap portion 2047 and the electrode 104 form an ohmic contact, thereby forming a good electrical connection between the two.

[0264] It should be noted that in some other embodiments of this disclosure, the preparation of the overlapping portion 2047 may be omitted.

[0265] In step S300, a second substrate is provided, the second substrate including opposing first and second surfaces, and a groove is formed on the first surface of the second substrate to form a first insulating layer.

[0266] Specifically, as shown in FIG17E, a second substrate is provided, the second substrate including a first surface 401 and a second surface 402 opposite to each other. As shown in FIG17G, a groove is formed on the first surface 401 of the second substrate to form a plurality of through holes 203 through the second substrate to form a first insulating layer 201.

[0267] For example, as shown in FIG17G, forming the first insulating layer 201 further includes forming a plurality of through holes 203 through the second substrate.

[0268] For example, the second substrate is a glass sheet. As shown in FIG17F, before forming grooves and vias on the second substrate, the locations on the second substrate where grooves and vias need to be formed are laser-induced modified, and then the glass sheet is etched using HF solution to form grooves and vias.

[0269] In step S400, the first insulating layer and the conductive layer are connected, with the groove of the first insulating layer facing the conductive layer.

[0270] Specifically, as shown in Figure 17H, the first insulating layer 201 is disposed on the side of the conductive layer 102 away from the second sub-layer 102, and the groove, the conductive layer 102, and the second sub-layer 302 form a second cavity 202. When the first insulating layer 201 is glass, the first insulating layer 201 and the conductive layer 202 are connected by anodic bonding, and the second cavity 202 is a sealed cavity.

[0271] In step S500, the initial support layer is processed to obtain a support layer, and the side of the support layer away from the conductive layer includes a first cavity.

[0272] Specifically, as shown in FIG17H, before etching the first sub-layer 301 to form the first cavity 105, the fabrication method of the pressure sensor chip further includes thinning the first sub-layer 301 using a grinding thinning technique until the first sub-layer 301 reaches the target thickness. Next, as shown in FIG17I, a patterned mask layer 306 is formed on the surface of the first sub-layer 301 away from the conductive layer 102. The mask layer 306 serves as a mask layer when etching the first sub-layer 301 to form the first cavity. The mask layer 306 may be, for example, silicon nitride.

[0273] Specifically, as shown in Figure 17J, processing the initial support layer to obtain the support layer can refer to etching the first sub-layer 301 to form the first cavity 105, so that the first sub-layer 301 forms the first sub-support layer 1011 of the pressure sensor chip, and the second sub-layer 302 forms the second sub-support layer 1012. The first sub-support layer 1011, the second insulating layer 1012, and the second sub-support layer 1012 constitute the support layer 101, as shown in the part enclosed by the dashed box in Figure 17J. The part of the second insulating layer 1013 and the second sub-support layer 1012 exposed in the first cavity is the pressure-sensitive film 106.

[0274] It should be noted that, because the first sublayer needs to be thinned in this embodiment, if the first sublayer of the first substrate used in this embodiment has the same thickness as the first sublayer of the first substrate used in the embodiments shown in FIG14 and FIG15A to FIG15L, then the thickness of the first sub-support layer 1011 in this embodiment is less than the thickness of the first sub-support layer in the embodiments shown in FIG14 and FIG15A to FIG15L.

[0275] For example, as shown in FIG17K, the fabrication method of the pressure sensor chip further includes forming conductive pillars 2041 and a first signal transmission layer 2045. Forming the conductive pillars 2041 includes forming a seed layer using physical vapor deposition (PVD), the seed layer being, for example, titanium / copper. A body layer is formed using electroplating or chemical plating, the body layer being, for example, copper. The seed layer is located on the sidewall of the via 203, the surface of the electrode 104 exposed in the via 203, and the surface of the overlap portion 2047 away from the electrode 104. The body layer is located on the side of the seed layer near the center of the via 203, and the seed layer surrounds the body layer. Forming the first signal transmission layer 2045 includes forming a seed layer using physical vapor deposition (PVD), the seed layer being, for example, titanium / copper. A body layer is formed using electroplating or chemical plating, the body layer being, for example, copper. The body layer is located on the side of the seed layer away from the first insulating layer 201. For example, the seed layer of the conductive pillar 2041 and the seed layer of the first signal transmission layer 2045 can be formed in a single process, and the main layer of the conductive pillar 2041 and the main layer of the first signal transmission layer 2045 can be formed in a single process.

[0276] For example, as shown in FIG17L, the fabrication method of the pressure sensor chip further includes forming a third insulating layer 206. Specifically, the third insulating layer 206 is formed on a portion of the surface of the first insulating layer 201 away from the conductive layer 102, and on the side of the first signal transmission layer 2045 away from the first insulating layer 201. The third insulating layer 206 includes a first via 2061 and a second via 2062. The first via 2061 exposes the conductive post 2041, and the second via 2062 exposes the target transmission area 2046 of the first signal transmission layer 2045. The portion outlined by the dashed box in FIG17L is the target transmission area 2046 of the first signal transmission layer 2045.

[0277] For example, as shown in FIG17L, the method for fabricating a pressure sensor chip further includes forming a second signal transmission layer 2048. The second signal transmission layer 2048 is located on the side of the adapter 2044 near the first insulating layer 201, and the second signal transmission layer 2048 is connected to the adapter 2044. The adapter 2044 and the conductive post 2041 are electrically connected through the second signal transmission layer 2048. For example, the second signal transmission layer 2048 is a nickel-palladium-gold protective layer, which can be fabricated using chemical plating technology on the surface of the first signal transmission layer 2045 away from the second insulating layer 201 and on the surface of the third insulating layer 206 away from the second insulating layer 201.

[0278] For example, as shown in FIG17L, the method for fabricating a pressure sensor chip further includes forming a transition portion 2044. The transition portion 2044 is located on the side of the first signal transmission layer 2045 away from the first insulating layer 201, and the transition portion 2044 is electrically connected to the target transmission area 2046 of the first signal transmission layer 2045. For example, the transition portion 2044 is a solder ball, which can be formed by processes such as applying flux, placing solder balls, reflowing, and cleaning.

[0279] It should be noted that in some other embodiments of this disclosure, the second signal transmission layer 2048 may not be prepared. In this case, the adapter 2044 is located on the side of the first signal transmission layer 2045 away from the first insulating layer 201, and the adapter 2044 and the target transmission area 2046 of the first signal transmission layer 2045 are in contact connection.

[0280] As shown in Figure 18, the fabrication method of the pressure sensor chip in some embodiments of this disclosure may include the following steps S100-S500:

[0281] Step S100: A first substrate is provided, the first substrate comprising a first sublayer and a second sublayer stacked sequentially.

[0282] In step S200, a second insulating layer is formed on the side of the second sublayer away from the first sublayer, and a third sublayer is formed on the side of the second insulating layer away from the second sublayer. The third sublayer is etched to form a conductive layer, and the first sublayer, the second sublayer, and the third insulating layer form an initial support layer.

[0283] Step S300: A second substrate is provided, the second substrate including opposing first and second surfaces, and a groove is formed on the first surface of the second substrate to form a first insulating layer.

[0284] Step S400: Connect the first insulating layer and the conductive layer, with the groove of the first insulating layer facing the conductive layer.

[0285] Step S500: The initial support layer is processed to obtain a support layer, and the side of the support layer away from the conductive layer includes a first cavity.

[0286] The process of processing the initial support layer to obtain the support layer can refer to etching the first sub-layer to form a first cavity, thereby forming a first sub-support layer. Furthermore, the second sub-layer can form a second sub-support layer. The first sub-support layer, the second sub-support layer, and the second insulating layer constitute the support layer, and the portions of the second sub-support layer and the second insulating layer exposed in the first cavity constitute a pressure-sensitive membrane.

[0287] Figures 19A-19M are schematic diagrams of the membrane structure during the fabrication process of pressure sensor chips according to some embodiments of this disclosure.

[0288] By way of example, in the embodiments of this disclosure, with reference to Figures 19A-19M, the detailed description of each step in the fabrication method of the pressure sensor chip is as follows:

[0289] In step S100, a first substrate is provided, the first substrate comprising a first sublayer and a second sublayer stacked sequentially.

[0290] Specifically, as shown in FIG19A, a first substrate is provided, the first substrate including a first sublayer 301 and a second sublayer 302 stacked sequentially, wherein the first substrate is an N-type lightly doped silicon substrate.

[0291] In step S200, a second insulating layer is formed on the side of the second sub-layer away from the first sub-layer, and a third sub-layer is formed on the side of the second insulating layer away from the second sub-layer. The third sub-layer is etched to form a conductive layer, and the first sub-layer, the second sub-layer, and the third insulating layer form an initial support layer.

[0292] Specifically, as shown in Figure 19B, a second insulating layer 1013 is formed on the surface of the second sub-layer 302 away from the first sub-layer 301 using a high-temperature oxidation technique. Next, as shown in Figure 19C, a P-type doped polysilicon layer is formed on the side of the second insulating layer 1013 away from the second sub-layer 302. This P-type doped polysilicon layer can be formed, for example, through epitaxial growth or by growing a nanoscale polysilicon thin film at low temperature. Next, as shown in Figure 19D, a photoresist layer 304 is formed using photolithography, and a conductive layer 102 is formed using dry etching or wet etching. The conductive layer 102 includes multiple varistors 107 and multiple electrodes 104.

[0293] For example, as shown in FIG19E, the fabrication method of the pressure sensor chip further includes forming an overlap portion 2047 on the side of the electrode 104 away from the first layer 301. Specifically, a metal layer of a predetermined thickness can be formed on the surface of the electrode 104 away from the first sub-layer 301, and then the overlap portion 2047 can be formed by photolithography and etching processes. The etching process can be a wet etching process or a metal lift-off technology. After forming the overlap portion 2047, high-temperature annealing is performed, which can make the overlap portion 2047 and the electrode 104 form an ohmic contact, so that a good electrical connection is formed between the two.

[0294] It should be noted that in some other embodiments of this disclosure, the preparation of the overlapping portion 2047 may be omitted.

[0295] In step S300, a second substrate is provided, the second substrate including opposing first and second surfaces, and a groove is formed on the first surface of the second substrate to form a first insulating layer.

[0296] Specifically, as shown in FIG19F, a second substrate is provided, the second substrate including opposing first surfaces 401 and second surfaces 402. As shown in FIG19H, a groove is formed on the first surface 401 of the second substrate to form a plurality of through holes 203 through the second substrate to form a first insulating layer 201.

[0297] For example, as shown in FIG19H, forming the first insulating layer 201 further includes forming a plurality of through holes 203 penetrating the second substrate.

[0298] For example, the second substrate is a glass sheet. As shown in FIG19G, before forming grooves and vias on the second substrate, the locations on the second substrate where grooves and vias need to be formed are laser-induced modified, and then the glass sheet is etched using HF solution to form grooves and vias.

[0299] In step S400, the first insulating layer and the conductive layer are connected, with the groove of the first insulating layer facing the conductive layer.

[0300] Specifically, as shown in Figure 19I, the first insulating layer 201 is disposed on the side of the conductive layer 102 away from the second sub-layer 302, and the groove, the conductive layer 102, and the second insulating layer 1013 form a second cavity 202. When the first insulating layer 201 is glass, the first insulating layer 201 and the conductive layer 202 are connected by anodic bonding, and the second cavity 202 is a sealed cavity.

[0301] In step S500, the initial support layer is processed to obtain a support layer, and the side of the support layer away from the conductive layer includes a first cavity.

[0302] Specifically, as shown in Figure 19J, before etching the first sub-layer 301 to form the first cavity, the fabrication method of the pressure sensor chip further includes thinning the first sub-layer 301 using a grinding thinning technique until the first sub-layer 301 reaches the target thickness. Next, a patterned mask layer 305 is formed on the surface of the first sub-layer 301 away from the conductive layer 102. The mask layer 305 serves as a mask layer during the etching of the first sub-layer 301 to form the first cavity. The mask layer 305 can be, for example, silicon nitride.

[0303] Specifically, as shown in Figure 19K, processing the initial support layer to obtain the support layer can refer to etching the first sub-layer 301 to form the first cavity 105, so that the first sub-layer 301 forms the first sub-support layer 1011 of the pressure sensor chip, and the second sub-layer 302 forms the second sub-support layer 1012. The first sub-support layer 1011, the second sub-support layer 1012, and the second insulating layer 1013 constitute the support layer 101, as shown in the part enclosed by the dashed box in Figure 19K. The portion of the second sub-support layer 1012 and the second insulating layer 1013 exposed to the first cavity 105 is the pressure-sensitive film 106.

[0304] For example, as shown in FIG19L, the fabrication method of the pressure sensor chip further includes forming conductive pillars 2041 and a first signal transmission layer 2045. Forming the conductive pillars 2041 includes forming a seed layer using physical vapor deposition (PVD), the seed layer being, for example, titanium / copper. A body layer is formed using electroplating or chemical plating, the body layer being, for example, copper. The seed layer is located on the sidewall of the via 203, the surface of the electrode 104 exposed in the via 203, and the surface of the overlap portion 2047 away from the electrode 104. The body layer is located on the side of the seed layer near the center of the via 203, and the seed layer surrounds the body layer. Forming the first signal transmission layer 2045 includes forming a seed layer using physical vapor deposition (PVD), the seed layer being, for example, titanium / copper. A body layer is formed using electroplating or chemical plating, the body layer being, for example, copper. The body layer is located on the side of the seed layer away from the first insulating layer 201. For example, the seed layer of the conductive pillar 2041 and the seed layer of the first signal transmission layer 2045 can be formed in a single process, and the main layer of the conductive pillar 2041 and the main layer of the first signal transmission layer 2045 can be formed in a single process.

[0305] For example, as shown in FIG19M, the fabrication method of the pressure sensor chip further includes forming a third insulating layer 206. Specifically, the third insulating layer 206 is formed on a portion of the surface of the first insulating layer 201 away from the conductive layer 102, and on the side of the first signal transmission layer 2045 away from the first insulating layer 201. The third insulating layer 206 includes a first via 2061 and a second via 2062. The first via 2061 exposes the conductive post 2041, and the second via 2062 exposes the target transmission area 2046 of the first signal transmission layer 2045. The portion outlined by the dashed box in FIG19M is the target transmission area 2046 of the first signal transmission layer 2045.

[0306] For example, as shown in FIG19M, the method for fabricating a pressure sensor chip further includes forming a second signal transmission layer 2048. The second signal transmission layer 2048 is located on the side of the adapter 2044 near the first insulating layer 201, and is connected to the adapter 2044. The adapter 2044 and the conductive post 2041 are electrically connected through the second signal transmission layer 2048. For example, the second signal transmission layer 2048 is a nickel-palladium-gold protective layer, which can be prepared using chemical plating technology on the surface of the first signal transmission layer 2045 away from the second insulating layer and on the surface of the third insulating layer 206 away from the second insulating layer.

[0307] For example, as shown in FIG19M, the method for fabricating a pressure sensor chip further includes forming a transition portion 2044. The transition portion 2044 is located on the side of the first signal transmission layer 2045 away from the first insulating layer 201, and the transition portion 2044 is electrically connected to the target transmission area 2046 of the first signal transmission layer 2045. For example, the transition portion 2044 is a solder ball, which can be formed by processes such as applying flux, placing solder balls, reflowing, and cleaning.

[0308] It should be noted that in some other embodiments of this disclosure, the second signal transmission layer 2048 may not be prepared. In this case, the adapter 2044 is located on the side of the first signal transmission layer 2045 away from the first insulating layer 201, and the adapter 2044 and the target transmission area 2046 of the first signal transmission layer 2045 are in contact connection.

[0309] Since the fabrication method of the pressure sensor chip can achieve essentially the same technical effect as the pressure sensor chip described in the previous embodiments, for the sake of brevity, the technical effect of the fabrication method of the pressure sensor chip will not be repeated here.

[0310] The terminology used in the embodiments section of this application is for explaining the embodiments of this application only and is not intended to limit this application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0311] The Description of Embodiments section of this application describes several embodiments; however, this description is exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0312] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0313] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0314] In the accompanying drawings, the dimensions and relative dimensions of the elements may be enlarged for clarity and / or descriptive purposes. Thus, the dimensions and relative dimensions of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this application is not limited to the shapes or values ​​shown in the drawings.

[0315] The ordinal numbers "first," "second," and "third" used in this specification are for the purpose of avoiding confusion among the constituent elements, not for limiting the quantity. The term "multiple" in this application refers to two or more quantities.

[0316] The thickness range of the film layer in this specification is A to B, which means that the thickness is between A and B, including the two endpoints of A and B.

[0317] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the described constituent elements. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0318] In this specification, unless otherwise expressly specified and limited, the terms "connected" or "linked" should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a mechanical connection or an electrical connection; it can refer to a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of the above terms in this application according to the specific circumstances.

[0319] In this specification, unless otherwise stated, the term "electrical connection" may mean that two components or elements are directly electrically connected, for example, component or element A is in direct contact with component or element B, and an electrical signal can be transmitted between them; it may also mean that two components or elements are electrically connected through a conductive medium, such as a conductive wire, for example, component or element A is electrically connected to component or element B through a conductive wire to transmit an electrical signal between the two components or elements; it may also mean that two components or elements are electrically connected through at least one electronic component, for example, component or element A is electrically connected to component or element B through at least one thin-film transistor to transmit an electrical signal between the two components or elements.

[0320] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0321] It should be noted that in this paper, "the same layer" refers to a layer structure formed by using the same film deposition process to create a film layer for forming a specific pattern, and then using the same photomask to pattern this film layer in a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or parts located in the "same layer" are made of the same material and formed by the same single patterning process. These specific patterns may also be at different heights or have different thicknesses.

[0322] In this application, "thickness" and "height" refer to the vertical distance between the surface of the film layer away from the substrate and the surface of the film layer closer to the substrate.

[0323] In this application, "about" means a value that is not strictly limited and allows for process and measurement errors.

[0324] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A pressure sensor chip, characterized in that, The pressure sensor chip includes: A support layer and a conductive layer are stacked together. The support layer includes a first sub-support layer and a second sub-support layer, the second sub-support layer being closer to the conductive layer than the first sub-support layer. The first sub-support layer includes a first cavity. The second sub-support layer includes at least a portion of a pressure-sensitive membrane. The orthographic projection of the first cavity onto a reference plane and the orthographic projection of the pressure-sensitive membrane onto the reference plane at least partially overlap. The conductive layer includes a plurality of piezoresistive portions and a plurality of electrodes. The reference plane is parallel to the surface of the support layer adjacent to the conductive layer. And, a first insulating layer, the first insulating layer being located on the side of the conductive layer away from the support layer; the side of the first insulating layer near the conductive layer includes a groove, at least the groove, the conductive layer and the support layer together form a second cavity, the orthographic projection of the pressure-sensitive film on the reference plane and the orthographic projection of the piezoresistive portion on the reference plane are both located within the orthographic projection of the second cavity on the reference plane; The orthographic projection of each of the varistor portions onto the reference plane and the orthographic projection of the pressure-sensitive membrane onto the reference plane at least partially overlap.

2. The pressure sensor chip according to claim 1, characterized in that, Each of the varistor portions includes at least one varistor, which has a convex structure on the side away from the support layer. The orthographic projection of the first surface of the varistor away from the support layer on the reference plane is located within the orthographic projection of the second surface of the varistor close to the support layer on the reference plane.

3. The pressure sensor chip according to claim 1 or 2, characterized in that, The material of the conductive layer includes a first host material and a first dopant material doped within the first host material; In the direction from the first surface to the second surface of the varistor, the doping concentration of the first doped material of the conductive layer gradually decreases.

4. The pressure sensor chip according to claim 3, characterized in that, The conductive layer has the same doping concentration at all points on any cross-section of the varistor in the direction from the first surface to the second surface, and the cross-section is parallel to the reference plane.

5. The pressure sensor chip according to claim 1 or 2, characterized in that, The conductive layer includes multiple sub-conductive layers stacked sequentially; each sub-conductive layer includes a first host material and a first dopant material doped within the first host material, and the doping concentration is the same at all points in each sub-conductive layer; In the multilayer sub-conductive layers, the doping concentration decreases sequentially from the sub-conductive layer furthest from the support layer to the sub-conductive layer closest to the support layer.

6. The pressure sensor chip according to any one of claims 1 to 5, characterized in that, The support layer further includes a second insulating layer, and the first sub-support layer, the second insulating layer, and the second sub-support layer are stacked sequentially along the direction close to the conductive layer; The first cavity exposes a first target portion of the first insulating layer, and the pressure-sensitive membrane includes the first target portion and a second target portion of the second sub-support layer.

7. The pressure sensor chip according to claim 1 or 2, characterized in that, The support layer further includes a second insulating layer, and the first sub-support layer, the second sub-support layer and the second insulating layer are stacked sequentially along the direction close to the conductive layer; The first cavity exposes a third target portion of the second sub-support layer, and the pressure-sensitive membrane includes the third target portion and a fourth target portion of the second insulating layer; The conductive layer is made of a first host material and a first dopant material doped within the first host material; the doping concentration is the same throughout the conductive layer.

8. The pressure sensor chip according to any one of claims 1 to 7, characterized in that, The conductive layer includes four of the varistor sections; The orthographic projections of the varistor in the first varistor section and the second varistor section on the reference plane are symmetrically arranged with respect to the orthographic projection of the first axis on the reference plane. The orthographic projections of the first and second varistor components overlap with the orthographic projections of the second axis on the reference plane. The orthographic projections of the varistor in the first varistor component and the varistor in the second varistor component on the reference plane are symmetrically arranged relative to the orthographic projection of the second axis on the reference plane. The orthographic projections of the varistor in the third varistor section and the varistor in the fourth varistor section on the reference plane are symmetrically arranged with respect to the orthographic projection of the second axis on the reference plane. The orthographic projections of the varistor in the third varistor section and the varistor in the fourth varistor section on the reference plane overlap with the orthographic projection of the first axis on the reference plane. The orthographic projections of the varistor in the third varistor section and the varistor in the fourth varistor section on the reference plane are symmetrically arranged with respect to the orthographic projection of the first axis on the reference plane. The orthographic projection of the varistor in each of the varistor portions onto the reference plane and the orthographic projection of the pressure-sensitive film onto the reference plane at least partially overlap, and each of the varistor portions is closer to the edge of the pressure-sensitive film relative to the center of the pressure-sensitive film; Wherein, the orthographic projection of the first axis on the reference plane passes through the middle of the orthographic projection of the pressure-sensitive diaphragm on the reference plane, and the first axis extends along the first direction; The orthographic projection of the second axis onto the reference plane passes through the middle of the orthographic projection of the pressure-sensitive diaphragm onto the reference plane, and the second axis extends along the second direction; both the first direction and the second direction are parallel to the reference plane; the second direction is perpendicular to the first direction.

9. The pressure sensor chip according to claim 8, characterized in that, Each of the varistor portions includes one or more of the varistors; when each of the varistor portions includes multiple varistors, each of the varistor portions further includes at least one connecting portion, the at least one connecting portion being used to connect the multiple varistors in series; the orthographic projection of the varistor on the reference plane and the orthographic projection of the connecting portion on the reference plane are both strip-shaped; The extension direction of the varistor included in any of the varistor portions is the second direction, and the extension direction of the connection portion included in any of the varistor portions is the first direction.

10. The pressure sensor chip according to claim 9, characterized in that, The cross-sectional area of ​​any of the varistors is less than or equal to the cross-sectional area of ​​any of the connecting portions. The cross-section of the varistor is perpendicular to the reference plane and parallel to the first direction, and the cross-section of the connecting portion is perpendicular to the reference plane and parallel to the second direction.

11. The pressure sensor chip according to claim 9, characterized in that, The conductive layer further includes a first connection lead and a second connection lead corresponding to each of the varistor portions; The first end of the varistor is connected to one end of the first connecting lead, and the other end of the first connecting lead is connected to one of the electrodes. The second end of the varistor is connected to one end of the second connecting lead, and the other end of the second connecting lead is connected to the other electrode. Wherein, the minimum area of ​​the cross-section of any of the first connecting leads is greater than or equal to the area of ​​the cross-section of any of the connecting portions, and the minimum area of ​​the cross-section of any of the second connecting leads is greater than or equal to the area of ​​the cross-section of any of the connecting portions; the cross-section of the first connecting lead is perpendicular to the routing direction of the first connecting lead, and the cross-section of the second connecting lead is perpendicular to the routing direction of the second connecting lead.

12. The pressure sensor chip according to any one of claims 8 to 11, characterized in that, The plurality of electrodes includes: a first input electrode, a second input electrode, a first output electrode, and a second output electrode; The first input electrode is connected to the first varistor and the third varistor, and the second input electrode is connected to the second varistor and the fourth varistor; the first output electrode is connected to the first varistor and the fourth varistor, and the second output electrode is connected to the second varistor and the third varistor.

13. The pressure sensor chip according to any one of claims 1 to 12, characterized in that, The first insulating layer further includes a plurality of through holes, each corresponding to one of the plurality of electrodes, with each through hole exposing a portion of one of the electrodes; the pressure sensor chip further includes a plurality of conductive component portions, each of which includes a conductive post located in one of the through holes, and one end of each conductive post near the conductive layer being connected to one of the electrodes exposed by the through hole. catch.

14. The pressure sensor chip according to claim 13, characterized in that, The conductive post includes a first part and a second part that are connected in phase; The first part is attached to the wall of the through hole, and the shape of the orthographic projection of the first part on the reference plane is annular; The second portion is located at one end of the first portion near the conductive layer, the second portion is surrounded by the first portion, and the second portion is electrically connected to the electrode.

15. The pressure sensor chip according to claim 14, characterized in that, The conductive component further includes a transition section located at the end of the conductive post away from the electrode. The orthographic projection of the conductive post on the reference plane and the orthographic projection of the transition section on the reference plane at least partially overlap. The transition section and the conductive post are electrically connected.

16. The pressure sensor chip according to claim 15, characterized in that, The pressure sensor chip also includes a filling portion that fills the through hole and is surrounded by the conductive post.

17. The pressure sensor chip according to claim 16, characterized in that, The pressure sensor chip also includes a third insulating layer; The third insulating layer is located between the second insulating layer and the transition portion. The third insulating layer includes a first via for exposing the conductive post. The transition portion is electrically connected to the conductive post through the first via.

18. The pressure sensor chip according to claim 14, characterized in that, The conductive component further includes a first signal transmission layer and a transition section. The first signal transmission layer is connected to the conductive post, and at least a portion of the orthographic projection of the first signal transmission layer on the reference plane is located outside the orthographic projection of the through hole on the reference plane. The adapter is located on the side of the first signal transmission layer away from the second insulating layer. The adapter is electrically connected to the target transmission area of ​​the first signal transmission layer. The orthographic projection on the reference plane and the orthographic projection of the conductive post on the reference plane do not overlap.

19. The pressure sensor chip according to claim 18, characterized in that, The pressure sensor chip also includes a third insulating layer; The third insulating layer is located between the first signal transmission layer and the adapter. The third insulating layer includes a first via and a second via. The first via exposes a second portion of the conductive post, and the second via exposes the target transmission area of ​​the first signal transmission layer. The adapter is electrically connected to the target transmission area through the second via.

20. The pressure sensor chip according to any one of claims 15 to 19, characterized in that, The conductive component also includes an overlap portion located on the side of the second part closer to the electrode, and the conductive post is electrically connected to the electrode through the overlap portion.

21. The pressure sensor chip according to any one of claims 15 to 19, characterized in that, The conductive component also includes a second signal transmission layer; The second signal transmission layer is located on the side of the adapter near the second insulating layer. The second signal transmission layer is connected to the adapter. The orthographic projection of the second signal transmission layer on the reference plane and the orthographic projection of the adapter on the reference plane at least partially overlap. The adapter and the conductive post are electrically connected through the second signal transmission layer.

22. A pressure sensor, characterized in that, The pressure sensor includes: The pressure sensor chip as described in any one of claims 1 to 21; And a driving circuit, which is electrically connected to the electrodes of the pressure sensor chip.

23. A method for fabricating a pressure sensor chip, characterized in that, The preparation method is used to prepare the pressure sensor chip according to any one of claims 1 to 21; the method includes: Form a conductive layer; An initial support layer is formed, the initial support layer being located on one side of the conductive layer; A first insulating layer is formed, the first insulating layer including grooves; The first insulating layer and the conductive layer are connected, with the groove of the first insulating layer facing the conductive layer; The initial support layer is processed to obtain a support layer, and the side of the support layer away from the conductive layer includes a first cavity.

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