Silicon carbide semiconductor device

Abstract

This silicon carbide semiconductor device has: a silicon carbide substrate that has a first main surface; a gate insulating film; and a gate electrode. The silicon carbide substrate has a drift region that has a first conductivity type, a body region that is provided on the drift region and has a second conductivity type differing from the first conductivity type, and a source region that is provided on the body region so as to be separated from the drift region and has the first conductivity type. A gate trench is provided in the first main surface, said gate trench extending along a first axis and comprising a first side surface that passes through the source region and the body region to arrive at the drift region, and a bottom surface that is continuous with the side surface. The gate insulating film is in contact with the first side surface and the bottom surface. The gate electrode has a first section that is inside the gate trench, and a second section that is connected to the first section and is outside the gate trench. The gate electrode is provided on the gate insulating film so as to sandwich the gate insulating film between the silicon carbide substrate and the gate electrode. In a cross-sectional view perpendicular to the first axis, a first angle that is formed by a first imaginary straight line including the first main surface and a second imaginary straight line including a section of the first side surface where the same passes through the body region is smaller than a second angle that is formed by the first imaginary straight line and a tangent at a boundary between the first section and the second section on a second side surface of the gate electrode.

Description

Silicon carbide semiconductor equipment

[0001] This disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority under Japanese application No. 2024-186455, filed on 23 October 2024, and incorporates all the provisions contained in the said Japanese application.

[0003] A semiconductor device is disclosed having a gate trench formed on a substrate and a gate insulating film in contact with the inner surface of the gate trench.

[0004] International Publication No. 2023 / 166657

[0005] The silicon carbide semiconductor device of the present disclosure comprises a silicon carbide substrate having a first main surface, a gate insulating film, and a gate electrode, wherein the silicon carbide substrate has a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the drift region and having the first conductivity type, the first main surface has a first side surface penetrating the source region and the body region and reaching the drift region, and a bottom surface connected to the first side surface, and a gate trench extending along a first axis is provided, and the gate The gate insulating film is in contact with the first side surface and the bottom surface, and the gate electrode has a first portion inside the gate trench and a second portion connected to the first portion and outside the gate trench, and the gate electrode is provided on the gate insulating film such that it is sandwiched between the silicon carbide substrate and the gate insulating film, and in a cross-sectional view perpendicular to the first axis, the first angle formed by a first virtual line including the first main surface and a second virtual line including the portion of the first side surface that penetrates the body region is smaller than the second angle formed by the tangent at the boundary between the first portion and the second portion of the second side surface of the gate electrode and the first virtual line.

[0006] Figure 1 is a diagram showing the configuration of the interlayer insulating film and the first main surface in the silicon carbide semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the first embodiment. Figure 3 is a cross-sectional view (part 1) showing the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 4 is a cross-sectional view (part 2) showing the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 5 is a cross-sectional view (part 3) showing the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 6 is a cross-sectional view (part 4) showing the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 7 is a cross-sectional view (part 5) showing the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 8 is a cross-sectional view (part 6) showing the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 9 is a cross-sectional view (part 7) showing the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 10 is a cross-sectional view (part 8) showing the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 11 is a cross-sectional view (part 9) showing the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 12 is a cross-sectional view (10) showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. Figure 13 is a cross-sectional view (11) showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. Figure 14 is a cross-sectional view (12) showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. Figure 15 is a cross-sectional view (13) showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. Figure 16 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the second embodiment. Figure 17 is a cross-sectional view (1) showing a method for manufacturing a silicon carbide semiconductor device according to the second embodiment. Figure 18 is a cross-sectional view (2) showing a method for manufacturing a silicon carbide semiconductor device according to the second embodiment. Figure 19 is a cross-sectional view (3) showing a method for manufacturing a silicon carbide semiconductor device according to the second embodiment. Figure 20 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to a modified example of the first embodiment.

[0007] [Issues this disclosure aims to address] In recent years, there has been a growing demand for improved long-term reliability.

[0008] This disclosure aims to provide a silicon carbide semiconductor device that can improve long-term reliability.

[0009] [Effects of this disclosure] This disclosure can improve long-term reliability.

[0010] The implementation methods are described below.

[0011] [Description of Embodiments of the Disclosure] Embodiments of the Disclosure are first listed and described. In the following description, the same or corresponding elements are denoted by the same reference numeral, and the same description is not repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [], collective orientations by <>, individual planes by (), and collective planes by {}. Also, while negative crystallographic exponents are usually indicated by placing a "-" (bar) above the number, in this disclosure a negative sign is placed before the number. Also, in the following description, the XYZ Cartesian coordinate system is used, but this coordinate system is defined for illustrative purposes and is not limited to the orientation of the silicon carbide semiconductor device. Also, the XY plane view is called a plan view, and from any point, the +Z direction may be called up, upper side, or up, and the -Z direction may be called down, lower side, or down.

[0012] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure comprises a silicon carbide substrate having a first main surface, a gate insulating film, and a gate electrode, wherein the silicon carbide substrate has a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the drift region and having the first conductivity type, the first main surface has a first side surface that penetrates the source region and the body region and reaches the drift region, and a bottom surface connected to the first side surface, and a gate trench extending along a first axis is provided, The gate insulating film is in contact with the first side surface and the bottom surface, and the gate electrode has a first portion inside the gate trench and a second portion connected to the first portion and outside the gate trench, and the gate electrode is provided on the gate insulating film such that it is sandwiched between the silicon carbide substrate and the gate insulating film, and in a cross-sectional view perpendicular to the first axis, the first angle formed by a first virtual line including the first main surface and a second virtual line including the portion of the first side surface that penetrates the body region is smaller than the second angle formed by the tangent at the boundary between the first portion and the second portion of the second side surface of the gate electrode and the first virtual line.

[0013] In a silicon carbide substrate, the electric field tends to concentrate near the boundary between the first main surface and the first side surface. In a gate electrode, the electric field tends to concentrate near the boundary between the second side surface and the top surface. In a cross-sectional view perpendicular to the first axis, the first angle formed by the first and second virtual lines is smaller than the second angle formed by the tangent line and the first virtual line. Therefore, the distance between the area where the electric field tends to concentrate in the silicon carbide substrate and the area where the electric field tends to concentrate in the gate electrode can be increased. Consequently, dielectric breakdown of the gate insulating film becomes less likely, and long-term reliability can be improved.

[0014] [2] In [1], the silicon carbide substrate may have a second main surface opposite to the first main surface, and the second side surface may have a curved portion that curves such that the inclination angle with respect to the first main surface approaches 90° as it moves away from the second main surface. In this case, the areas where electric fields tend to concentrate are separated, dielectric breakdown of the gate insulating film is made less likely, and long-term reliability can be further improved.

[0015] [3] In [1] or [2], the maximum width of the gate electrode in the cross-sectional view may be smaller than the maximum width of the gate trench. In this case as well, locations where electric fields tend to concentrate are separated, making dielectric breakdown of the gate insulating film less likely and further improving long-term reliability.

[0016] [4] In any of [1] to [3], the distance between the point on the second portion furthest from the first virtual line and the first virtual line in the cross-sectional view may be 0.1 μm or more. In this case as well, locations where electric fields tend to concentrate are separated, making dielectric breakdown of the gate insulating film less likely and further improving long-term reliability.

[0017] [5] In any of [1] to [4], an insulating film covering the gate electrode is provided, and the insulating film may have a curved surface that is convex when viewed from the gate electrode. In this case, it is easier to form a source pad in the contact hole of the insulating film.

[0018] [6] In any of [1] to [5], the intersection point of the first virtual line and the first side surface, as seen from the gate electrode, may be farther away from the intersection point of the first virtual line and the second virtual line. In this case as well, by separating the points where electric fields tend to concentrate, dielectric breakdown of the gate insulating film is made less likely, and long-term reliability can be further improved.

[0019] [7] In any of [1] to [6], the first side surface may include a {0-33-8} plane. Including a {0-33-8} plane in the first side surface allows for good mobility on the first side surface of the gate trench and reduces channel resistance.

[0020] [Embodiments of the Disclosure] (First Embodiment) The first embodiment will be described below. The first embodiment relates to a so-called vertical MOS (metal oxide semiconductor) type field-effect transistor (FET) using silicon carbide. This MOS type FET is an example of a silicon carbide semiconductor device. Figure 1 is a diagram showing the configuration of the interlayer insulating film and the first main surface in the silicon carbide semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the first embodiment. Figure 2 corresponds to a cross-sectional view along the line II-II in Figure 1.

[0021] As shown in Figures 1 and 2, the silicon carbide semiconductor device 100 according to the first embodiment includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, a source electrode 60, a drain electrode 70, an interlayer insulating film 85, and a barrier metal film 86.

[0022] The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is in the +Z direction when viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The first main surface 1 is on the silicon carbide epitaxial layer 40, and the second main surface 2 is on the silicon carbide single crystal substrate 50. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are formed of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type conductivity type (first conductivity type).

[0023] The first main surface 1 is the {0001} surface or a surface inclined by an off-angle of 8° or less in the off-direction. Preferably, the first main surface 1 is the (000-1) surface or a surface inclined by an off-angle of 8° or less in the off-direction. The off-direction may be, for example, the <11-20> direction or the <1-100> direction. The off-angle may be, for example, 1° or more or 2° or more. The off-angle may be 6° or less or 4° or less. The first main surface 1 may be the (0001) surface or a surface inclined by an off-angle of 8° or less in the off-direction.

[0024] The silicon carbide epitaxial layer 40 has a drift region 11, a body region 12, a source region 13, an electric field relaxation region 14, and a contact region 18.

[0025] The drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has an n-type conductivity. The drift region 11 is provided on a silicon carbide single crystal substrate 50.

[0026] The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type conductivity. The body region 12 is located on top of the drift region 11. The lower end surface of the body region 12 and the upper end surface of the drift region 11 are in contact with each other.

[0027] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has an n-type conductivity. The source region 13 is located on top of the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. A portion of the first main surface 1 is located in the source region 13.

[0028] A plurality of gate trenches 5 are provided on the first main surface 1, defined by a side surface 3 and a bottom surface 4. Each gate trench 5 has a side surface 3 and a bottom surface 4. The gate trenches 5 extend, for example, along the Y-axis. In addition, a plurality of gate trenches 5 are provided along the X-axis at regular intervals (first pitch P1). The side surface 3 penetrates the source region 13, the body region 12, and a part of the drift region 11, reaching the drift region 11. The bottom surface 4 is connected to the side surface 3. The bottom surface 4 is located in the drift region 11. For example, the bottom surface 4 is parallel to the first main surface 1 and the second main surface 2. In a cross-sectional view perpendicular to the Y-axis, the angle θ3 of the side surface 3 with respect to the virtual plane 30 including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ3 may also be, for example, 50° or more and 65° or less. The angle θ3 may also be, for example, 50° or more and 60° or less. The side surface 3 preferably has a {0-33-8} surface. The {0-33-8} plane is a crystal plane that provides excellent mobility. The Y-axis is an example of the first axis. Side surface 3 is an example of the first side surface.

[0029] The contact region 18 contains p-type impurities such as aluminum and has a p-type conductivity. The contact region 18 penetrates the source region 13 and is in contact with the body region 12. A portion of the first main surface 1 is located in the contact region 18. In a plan view perpendicular to the first main surface 1, the contact region 18 is located between adjacent gate trenches 5 along the X-axis. Between two adjacent gate trenches 5 along the X-axis, the contact region 18 and the source region 13 may be alternately provided along the Y-axis. Between two adjacent gate trenches 5 along the X-axis, the contact region 18 may be provided intermittently along the Y-axis.

[0030] Multiple gate trenches 5 may be arranged at regular intervals along the Y-axis. If multiple gate trenches 5 are arranged at regular intervals along the Y-axis, a portion of the contact area 18 may be located between adjacent gate trenches 5 along the Y-axis. Multiple gate trenches 5 may be arranged in an array.

[0031] The field relaxation region 14 contains p-type impurities such as aluminum and has a p-type conductivity. The field relaxation region 14 is located between adjacent gate trenches 5 along the X-axis in a plan view perpendicular to the first main surface 1. The field relaxation region 14 is separated from the gate trenches 5. The body region 12 is exposed to the side surface 3 of the gate trenches 5. The field relaxation region 14 is further away from the gate trenches 5 than the body region 12 along the X-axis. The field relaxation region 14 is located between the body region 12 and the second main surface 2 and is in contact with the body region 12. The field relaxation region 14 may overlap the contact region 18 in a plan view perpendicular to the first main surface 1. The field relaxation region 14 may be in contact with the body region 12 and the contact region 18. The field relaxation region 14 may extend along the Y-axis. Multiple field relaxation regions 14 are arranged at regular intervals along the X-axis. Multiple field relaxation regions 14 may be arranged in a stripe pattern. The lower end surface of the electric field relaxation region 14 is closer to the second main surface 2 than to the bottom surface 4. The contact region 18, the body region 12, and the electric field relaxation region 14 are electrically connected to each other.

[0032] The drift region 11 is exposed on the side surface 3 and is in contact with the body region 12 and the electric field relaxation region 14. The drift region 11 may also be in contact with the silicon carbide single crystal substrate 50. The drift region 11 may include a current diffusion region in which the effective concentration of n-type impurities is particularly high.

[0033] Along the Z-axis, a silicon carbide single crystal substrate 50 and a drift region 11 are located between the bottom surface 4 and the second main surface 2, and the conductivity type of the silicon carbide substrate 10 between the bottom surface 4 and the second main surface 2 is n-type.

[0034] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 contains, for example, silicon dioxide. The gate insulating film 81 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is in contact with the drift region 11 at the bottom surface 4. The gate insulating film 81 is in contact with the source region 13, the body region 12 and the drift region 11 at the side surface 3.

[0035] The gate electrode 82 is provided on the gate insulating film 81, sandwiching the gate insulating film 81 between it and the silicon carbide substrate 10. The gate electrode 82 includes, for example, polycrystalline silicon containing conductive impurities. The gate electrode 82 has a first portion 82A inside the gate trench 5 and a second portion 82B outside the gate trench 5. The second portion 82B is connected to the first portion 82A. The first portion 82A faces the side surface 3 and the bottom surface 4. The gate electrode 82 has a side surface 87 and a top surface 88. The top surface 88 is connected to the side surface 87. The gate electrode 82 extends along the Y axis. In a plan view perpendicular to the first main surface 1, the gate electrode 82 may overlap with a plurality of gate trenches 5. Side surface 87 is an example of a second side surface.

[0036] In a cross-sectional view perpendicular to the Y-axis, the first angle θ1 is smaller than the second angle θ2. The first angle θ1 is the angle between the first virtual line L1, which includes the first main surface 1, and the second virtual line L2, which includes the portion that penetrates the body region 12 of the side surface 3 of the gate trench 5. The second angle θ2 is the angle between the tangent line TL at the boundary 82C between the first portion 82A and the second portion 82B of the side surface 87 of the gate electrode 82, and the first virtual line L1.

[0037] The interlayer insulating film 85 covers the gate electrode 82. The interlayer insulating film 85 has insulating films 83 and 84. The insulating film 83 contacts the side surface 87 of the gate electrode 82 and the upper surface of the gate insulating film 81. An opening 83A reaching the upper surface 88 of the gate electrode 82 is formed in the insulating film 83. The inner wall surface of the opening 83A is a curved surface that curves so that the inclination angle with respect to the first main surface 1 approaches 90° as it moves away from the second main surface 2. The second portion 82B of the gate electrode 82 is inside the opening 83A. For example, the side surface 87 of the gate electrode 82 has a curved surface portion 87A that curves so that the inclination angle with respect to the first main surface 1 approaches 90° as it moves away from the second main surface 2. The curved surface portion 87A contacts the inner wall surface of the opening 83A. The insulating film 84 is on the gate electrode 82 and the insulating film 83 and contacts the upper surface 88 of the gate electrode 82. The insulating films 83 and 84 are, for example, oxide films. The insulating films 83 and 84 contain, for example, silicon dioxide. The insulating films 83 and 84 are, for example, non-doped silicate glass (NSG) films. The interlayer insulating film 85 electrically insulates the gate electrode 82 and the source electrode 60 from each other.

[0038] Contact holes 90 are formed in the interlayer insulating film 85 at regular intervals along the X-axis. The contact holes 90 are arranged such that the gate trench 5 is positioned between adjacent contact holes 90 along the X-axis. The contact holes 90 extend along the Y-axis. The contact holes 90 have a first hole 91 reaching the source region 13 and the contact region 18, and a second hole 92 connected to the first hole 91. The first hole 91 is between the first main surface 1 and the second hole 92. The width of the first hole 91 is constant along the Z-axis, and the width of the second hole 92 increases as it moves away from the first main surface 1. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 85.

[0039] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 includes a contact electrode 61 in contact with the source region 13 and the contact region 18, and a source pad 62 in contact with the contact electrode 61. The contact electrode 61 contains, for example, nickel silicide (NiSi). The contact electrode 61 may contain titanium (Ti), aluminum, and silicon. The contact electrode 61 is ohmicly joined to the source region 13 and the contact region 18.

[0040] The barrier metal film 86 covers the surface of the interlayer insulating film 85. The barrier metal film 86 is in contact with the interlayer insulating film 85 and the contact electrode 61. The barrier metal film 86 contains, for example, titanium nitride (TiN).

[0041] The source pad 62 covers the surface of the barrier metal film 86 and the upper surface of the contact electrode 61. The source pad 62 is in contact with the barrier metal film 86 and the contact electrode 61. The barrier metal film 86 is between the source pad 62 and the interlayer insulating film 85. The source pad 62 contains, for example, aluminum.

[0042] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 on the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 contains, for example, nickel silicide. The drain electrode 70 may contain titanium, aluminum, and silicon. The drain electrode 70 is ohmicly joined to the silicon carbide single crystal substrate 50.

[0043] A buffer layer containing an n-type impurity such as nitrogen and having an n-type conductivity type may be provided between the silicon carbide single crystal substrate 50 and the drift region 11. Also, a passivation film covering a part of the source electrode 60 may be provided.

[0044] The effective concentration of the p-type impurity in the contact region 18 may be higher than the effective concentration of the p-type impurity in the body region 12. For example, the effective concentration of the p-type impurity in the contact region 18 is 1×10 １８ cm －３ or more and 1×10 ２０ cm－３ is as follows, and the effective concentration of p-type impurities in the body region 12 is 5 × 10 １７ cm －３ or more and 1 × 10 １８ cm －３ or less.

[0045] The effective concentration of n-type impurities in the source region 13 may be higher than the effective concentration of p-type impurities in the body region 12. The effective concentration of n-type impurities in the source region 13 is, for example, 1 × 10 １９ cm －３ or so. The effective concentration of n-type impurities in the drift region 11 is, for example, 1 × 10 １６ cm －３ or more and 5 × 10 １７ cm －３ or less.

[0046] In the present disclosure, the effective concentration of impurities of the first conductivity type is the concentration obtained by subtracting the concentration of impurities of the second conductivity type from the concentration of impurities of the first conductivity type, and the effective concentration of impurities of the second conductivity type is the concentration obtained by subtracting the concentration of impurities of the first conductivity type from the concentration of impurities of the second conductivity type. The effective concentration can be measured using, for example, a scanning capacitance microscope (SCM). Also, the effective concentration of impurities contained in each region is the average value of the effective concentration of impurities contained in the region.

[0047] The drift region 11 has an n-type conductivity type, and the body region 12 and the electric field relaxation region 14 have a p-type conductivity type. Therefore, the boundary between the drift region 11 and the body region 12 and the boundary between the drift region 11 and the electric field relaxation region 14 are clear.

[0048] In the silicon carbide substrate 10 of the silicon carbide semiconductor device 100, the electric field tends to concentrate near the boundary between the first main surface 1 and the side surface 3 of the gate trench 5. In the gate electrode 82, the electric field tends to concentrate near the boundary between the side surface 87 and the top surface 88. In this embodiment, as described above, in a cross-sectional view perpendicular to the Y-axis, which is an example of the first axis, the first angle θ1 formed by the first virtual line L1 and the second virtual line L2 is smaller than the second angle θ2 formed by the tangent line TL at the boundary 82C of the side surface 87 of the gate electrode 82 and the first virtual line L1. Therefore, the distance between the area where the electric field tends to concentrate in the silicon carbide substrate 10 and the area where the electric field tends to concentrate in the gate electrode 82 can be increased. Consequently, dielectric breakdown of the gate insulating film 81 becomes less likely, and long-term reliability can be improved.

[0049] In particular, if the side surface 87 of the gate electrode 82 bends so that the inclination angle with respect to the first main surface 1 approaches 90° as it moves away from the second main surface 2, it separates areas where electric fields tend to concentrate, making dielectric breakdown of the gate insulating film 81 less likely and further improving long-term reliability.

[0050] In a cross-sectional view perpendicular to the Y-axis, if the maximum width W1 of the gate electrode 82 is smaller than the maximum width W2 of the gate trench 5, the points where electric fields tend to concentrate are separated, making dielectric breakdown of the gate insulating film 81 less likely and further improving long-term reliability.

[0051] In a cross-sectional view perpendicular to the Y-axis, if the distance D1 between the point 31 furthest from the first virtual line L1 in the second part 82B and the first virtual line L1 is 0.1 μm or more, the points where electric fields tend to concentrate are separated, making dielectric breakdown of the gate insulating film 81 less likely and further improving long-term reliability. Long-term reliability can be further improved if the distance D1 is 0.2 μm or more, and even more so if it is 0.3 μm or more.

[0052] Next, a method for manufacturing the silicon carbide semiconductor device 100 will be described. Figures 3 to 15 are cross-sectional views showing a method for manufacturing the silicon carbide semiconductor device 100 according to the first embodiment.

[0053] First, prepare the silicon carbide substrate 10 as shown in Figure 3.

[0054] Next, as shown in Figure 4, an insulating film 201 is formed on the first main surface 1. The insulating film 201 is, for example, an NSG film.

[0055] Next, as shown in Figure 5, an opening 201A is formed in the insulating film 201. The opening 201A can be formed, for example, by dry etching of the insulating film 201 using a photoresist mask.

[0056] Next, as shown in Figure 6, a gate trench 5 is formed on the first main surface 1. In forming the gate trench 5, for example, reactive ion etching (RIE) is performed through the opening 201A, followed by thermal etching through the opening 201A.

[0057] Next, as shown in Figure 7, an insulating film 202 is formed that is in contact with the side surface 3 and bottom surface 4 of the gate trench 5, while leaving the insulating film 201 intact. The insulating film 202 is formed, for example, by a thermal oxidation method.

[0058] Next, annealing is performed at a temperature at which the insulating films 201 and 202 soften, for example, a temperature between 1300°C and 1400°C. As a result, as shown in Figure 8, the insulating films 201 and 202 flow and become one, resulting in a gate insulating film 81 that contacts the side surface 3 and bottom surface 4 of the gate trench 5, and an insulating film 83 that contacts the gate insulating film 81.

[0059] Next, as shown in Figure 9, a polycrystalline silicon film 210 containing conductive impurities is formed on the gate insulating film 81 and the insulating film 83.

[0060] Next, the polycrystalline silicon film 210 is etched back. As a result, as shown in Figure 10, the gate electrode 82 is obtained from the polycrystalline silicon film 210. The etch-back of the polycrystalline silicon film 210 is performed, for example, until the point 31 furthest from the first virtual line L1 of the second portion 82B is closer to the first main surface 1 than to the upper surface of the insulating film 83.

[0061] Next, as shown in Figure 11, an insulating film 84 is formed on the gate electrode 82 and the insulating film 83. The insulating film 84 is, for example, an NSG film. An interlayer insulating film 85 is obtained from the insulating films 83 and 84.

[0062] Next, as shown in Figure 12, a mask 110 is formed on the interlayer insulating film 85. The mask 110 is, for example, a photoresist mask. The mask 110 has openings 111 in the region that forms the first holes 91 of the contact holes 90 in a plan view perpendicular to the first main surface 1.

[0063] Next, as shown in Figure 13, contact holes 90 are formed by etching the interlayer insulating film 85 through the opening 111. In forming the contact holes 90, for example, a second hole 92 is formed by wet etching, and then a first hole 91 is formed by dry etching.

[0064] Next, as shown in Figure 14, the mask 110 is removed to form the contact electrode 61.

[0065] Next, as shown in Figure 15, a barrier metal film 86 is formed to create a source pad 62.

[0066] Next, the drain electrode 70 is formed (see Figure 2). In this way, the silicon carbide semiconductor device 100 according to the first embodiment can be manufactured.

[0067] (Second Embodiment) The second embodiment will now be described. The second embodiment differs from the first embodiment mainly in the configuration of the interlayer insulating film. Figure 16 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the second embodiment.

[0068] In the silicon carbide semiconductor device 200 according to the second embodiment, the shape of the interlayer insulating film 85 differs from that of the first embodiment. That is, the interlayer insulating film 85 has a curved surface 84A that is convex when viewed from the gate electrode 82. The curved surface 84A may be included in the inner wall surface of the second hole 92 of the contact hole 90. For example, the insulating film 83 is an NSG film, and the insulating film 84 is a borophosphosilicate glass (BPSG) film or a phosphosilicate glass (PSG) film.

[0069] The other components of the silicon carbide semiconductor device 200 are the same as those of the silicon carbide semiconductor device 100.

[0070] Next, a method for manufacturing the silicon carbide semiconductor device 200 will be described. Figures 17 to 19 are cross-sectional views showing a method for manufacturing the silicon carbide semiconductor device 200 according to the second embodiment.

[0071] First, as shown in Figure 17, the process up to the formation of the gate electrode 82 (see Figure 10) is carried out, just as in the first embodiment. Next, an insulating film 84 is formed on the gate electrode 82 and the insulating film 83. The insulating film 84 is, for example, a BPSG film or a PSG film. An interlayer insulating film 85 is obtained from the insulating films 83 and 84.

[0072] Next, as shown in Figure 18, a mask 110 is formed on the interlayer insulating film 85. The mask 110 has an opening 111 in the region where the first hole 91 of the contact hole 90 is formed in a plan view perpendicular to the first main surface 1. Next, the interlayer insulating film 85 is dry-etched through the opening 111 to form the first hole 91 so as to penetrate the insulating films 84 and 83.

[0073] Next, as shown in Figure 19, the mask 110 is removed, and annealing is performed at a temperature at which the gate insulating film 81 and insulating film 83 do not soften, but the insulating film 84 softens, for example, a temperature of 800°C to 1000°C. As a result, the insulating film 84 flows, and a curved surface 84A is formed on the insulating film 84.

[0074] Subsequently, the same process as in the first embodiment is carried out, starting with the formation of the contact electrode 61 (see Figure 14). In this way, the silicon carbide semiconductor device 200 according to the second embodiment can be manufactured.

[0075] The silicon carbide semiconductor device 200 can achieve the same effects as the silicon carbide semiconductor device 100. Furthermore, in the silicon carbide semiconductor device 200, the interlayer insulating film 85 has a curved surface 84A that bends convexly when viewed from the gate electrode 82, making it easier to form the source pad 62 within the contact hole 90. In other words, pores are less likely to form within the contact hole 90 when forming the source pad 62. Therefore, connection reliability can be improved. Moreover, since the insulating film 84 is a BPSG film or a PSG film, the insulating film 84 exhibits a gettering effect on impurities, which can reduce the diffusion of impurities from the source pad 62 to the gate electrode 82.

[0076] (Modification of the First Embodiment) A modification of the first embodiment will now be described. The modification of the first embodiment differs from the first embodiment mainly in the configuration of the gate trench and the gate insulating film. Figure 20 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the modification of the first embodiment.

[0077] In the silicon carbide semiconductor device 100A according to a modification of the first embodiment, there is a region in the side surface 3 of the gate trench 5 that penetrates the source region 13, where the inclination angle of the side surface 3 with respect to the first main surface 1 is smaller than the inclination angle of the portion that penetrates the body region 12. For example, in the vicinity of the first main surface 1, the inclination angle becomes smaller as it approaches the first main surface 1. Furthermore, on the first virtual line L1, as seen from the gate electrode 82, the intersection point 32 of the first virtual line L1 and the side surface 3 of the gate trench 5 is further away than the intersection point 33 of the first virtual line L1 and the second virtual line L2.

[0078] The other components of the silicon carbide semiconductor device 100A are the same as those of the silicon carbide semiconductor device 100.

[0079] The silicon carbide semiconductor device 100A can achieve the same effects as the silicon carbide semiconductor device 100. Furthermore, in the silicon carbide semiconductor device 100A, on the first virtual line L1, the intersection point 32 is further away from the gate electrode 82 than the intersection point 33, making it easier to increase the distance between the area where the electric field of the silicon carbide substrate 10 tends to concentrate and the area where the electric field of the gate electrode 82 tends to concentrate. Consequently, dielectric breakdown of the gate insulating film 81 becomes less likely, and long-term reliability can be further improved.

[0080] In the silicon carbide semiconductor device 200 according to the second embodiment, long-term reliability can be further improved if, on the first virtual line L1, the intersection point 32 is farther away from the gate electrode 82 than the intersection point 33.

[0081] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims.

[0082] 1 First main surface 2 Second main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 11 Drift region 12 Body region 13 Source region 14 Field relaxation region 18 Contact region 30 Virtual plane 31 Point 32, 33 Intersection 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source pad 70 Drain electrode 81 Gate insulating film 82 Gate electrode 82A First part 82B Second part 82C Boundary 83, 84 Insulating film 83A Aperture 84A Curved surface 85 Interlayer insulating film 86 Barrier metal film 87 Side surface 87A Curved surface portion 88 Top surface 90 Contact hole 91 First hole 92 Second hole 100, 100A, 200 Silicon carbide semiconductor device 110 Mask 111 Aperture 201, 202 Insulating film 201A Aperture 210 Polycrystalline silicon film D1 Distance L1 First virtual line L2 Second virtual line P1 First pitch TL Tangent W1 Maximum value W2 Maximum value θ1 First angle θ2 Second angle θ3 Angle

Claims

1. A silicon carbide substrate having a first main surface, a gate insulating film, and a gate electrode, wherein the silicon carbide substrate has a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the drift region and having the first conductivity type, the first main surface has a first side surface that penetrates the source region and the body region and reaches the drift region, and a bottom surface connected to the first side surface, and a gate trench extending along a first axis, the gate insulating film is in contact with the first side surface and the bottom surface, the gate electrode has a first portion inside the gate trench, and a second portion connected to the first portion and outside the gate trench, the gate electrode is provided on the gate insulating film so as to sandwich the gate insulating film between itself and the silicon carbide substrate, and in a cross-sectional view perpendicular to the first axis, A silicon carbide semiconductor device wherein the first angle formed by a first virtual line including the first main surface and a second virtual line including the portion of the first side surface that penetrates the body region is smaller than the second angle formed by the tangent at the boundary between the first and second portions of the second side surface of the gate electrode and the first virtual line.

2. The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide substrate has a second main surface opposite to the first main surface, and the second side surface has a curved portion that bends such that the angle of inclination with respect to the first main surface approaches 90° as it moves away from the second main surface.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein, in the cross-sectional view, the maximum width of the gate electrode is smaller than the maximum width of the gate trench.

4. In the cross-sectional view, the distance between the point furthest from the first virtual line in the second portion and the first virtual line is 0.1 μm or more, the silicon carbide semiconductor device according to any one of claims 1 to 3.

5. A silicon carbide semiconductor device according to any one of claims 1 to 4, comprising an insulating film covering the gate electrode, wherein the insulating film has a curved surface that is convex when viewed from the gate electrode.

6. The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein, on the first virtual line, with respect to the gate electrode, the intersection point of the first virtual line and the first side surface is farther away than the intersection point of the first virtual line and the second virtual line.

7. The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein the first side surface includes a {0-33-8} plane.

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