Artificial synapse device having bidirectional current, and manufacturing method thereof and operating method thereof

Abstract

An artificial synapse device is provided. The artificial synapse device comprises: a substrate; a gate electrode disposed on the substrate; an insulating layer disposed on the substrate to cover the gate electrode; a weight control layer disposed on the insulating layer and capable of trapping or de-trapping charges by a voltage applied to the gate electrode; a semiconductor layer disposed on the weight control layer and including a two-dimensional semiconductor material; a source electrode disposed to be in contact with one side of the semiconductor layer and including a metal having a relatively low work function; and a drain electrode disposed to be in contact with the other side of the semiconductor layer and including a metal having a relatively high work function, wherein both a current flowing from the source electrode toward the drain electrode and a current flowing from the drain electrode toward the source electrode can be generated.

Description

Artificial synapse device having bidirectional current and method of manufacturing and operation thereof

[0001] The present invention relates to an artificial synapse device having both bidirectional (positive and negative) currents, and a method for manufacturing and operating the same.

[0002] With the rapid advancement of AI and large-scale language models, and the resulting surge in the need to process various forms of unstructured data, the required computing system resources are increasing exponentially. As the need for energy-efficient, high-speed computing architectures emerges to overcome the limitations of serial computing based on the existing Von Neumann architecture, brain-inspired parallel computing technology is gaining attention. Parallel computing generally utilizes hardware neural network structures characterized by extensive parallel connections between artificial synapses. Artificial synapses can adjust and store the internal conductivity of components related to the neural network's weights using electrical and optical signals, thereby enabling the learning and inference functions of the hardware neural network.

[0003] In the early stages of hardware neural network implementation, the conductivity value (G) of artificial synapses was used as the weights (W) of the hardware neural network (W = G). However, due to the asymmetry of the set / reset switching of the memory elements constituting the artificial synapses, it was difficult to symmetrically control conductivity. Subsequently, a model was introduced that controls conductivity using two artificial synapses as a pair, and the weights of the hardware neural network came to have positive / negative signs (W = G + - G ->0 or <0). The ease of the weight transfer process in this model improved the recognition rate of hardware neural networks and became the foundation for various component-based artificial synapse models. However, for the circuit implementation of this model, a subtraction operation on the output of an artificial synapse pair is required for each weight, and the number of necessary components doubles. An increase in the number of components implies an increase in circuit wiring for input / output signal transmission and weight update signal transmission. Furthermore, the expansion of hardware neural networks due to the continuous increase in the complexity of unstructured data is further intensifying the complexity of wiring. Under these circumstances, the advantages of the high-performance and low-power characteristics of existing parallel computing technology are inevitably being gradually offset.

[0004] Accordingly, the present invention enables the expression of both positive and negative weights in a single device without the need for a subtractor and additional wiring, which were required when using a pair of artificial synapses for positive / negative weight adjustment in existing hardware neural networks, by using a bidirectional postsynaptic current (I PSC + And I PSC - We aim to provide an artificial synapse device through which ) flows.

[0005] The technical problem that the present invention aims to solve is to provide an artificial synapse device, a method for manufacturing the same, and a method for operating the same.

[0006] Another technical problem that the present invention aims to solve is to provide an artificial synapse device capable of generating both negative and positive currents within a single device without a separate subtractor and additional wiring, as well as a method for manufacturing and operating the same.

[0007] Another technical problem that the present invention aims to solve is to provide an artificial synapse device that can be easily applied to parallel computing, as well as a method for manufacturing and operating the same.

[0008] The technical problems that the present invention aims to solve are not limited to those described above.

[0009] To solve the technical problems described above, the present invention provides an artificial synapse device.

[0010] According to one embodiment, the artificial synapse element comprises a substrate, a gate electrode disposed on the substrate, an insulating layer disposed on the substrate to cover the gate electrode, a weighting control layer disposed on the insulating layer and capable of trapping or detrapping a charge by a voltage applied to the gate electrode, a semiconductor layer disposed on the weighting control layer and comprising a two-dimensional semiconductor material, a source electrode disposed to be in contact with one side of the semiconductor layer and comprising a metal having a relatively low work function, and a drain electrode disposed to be in contact with the other side of the semiconductor layer and comprising a metal having a relatively high work function, wherein both a current flowing from the source electrode toward the drain electrode and a current flowing from the drain electrode toward the source electrode can be generated.

[0011] According to one embodiment, a potential difference is generated within the semiconductor layer due to a difference in work function between the source electrode and the drain electrode, and a current flowing from the source electrode toward the drain electrode and a current flowing from the drain electrode toward the source electrode can both be generated by the potential difference generated within the semiconductor layer.

[0012] According to one embodiment, when light is irradiated onto the semiconductor layer and a first voltage is applied to the drain electrode, a current flowing from the source electrode toward the drain electrode may be generated.

[0013] According to one embodiment, when a second voltage greater than 0 V is applied to the gate electrode for a period longer than a reference time, the current flowing from the source electrode toward the drain electrode may be switched to flow from the drain electrode toward the source electrode.

[0014] According to one embodiment, the two-dimensional semiconductor material may include any one of a transition metal dichalcogenide, graphene, and black phosphorus.

[0015] According to one embodiment, the source electrode may comprise titanium (Ti) and the drain electrode may comprise platinum (Pt).

[0016] According to one embodiment, the weight control layer may include hexagonal boron nitride (h-BN).

[0017] According to one embodiment, the source electrode may be used as a pre-synaptic terminal and the drain electrode may be used as a post-synaptic terminal.

[0018]

[0019] To solve the technical problems described above, the present invention provides a method for manufacturing an artificial synapse device.

[0020] According to one embodiment, the method for manufacturing the artificial synapse device comprises the steps of preparing a substrate, forming a gate electrode on the substrate, forming an insulating layer on the substrate to cover the gate electrode, forming a weight control layer containing a two-dimensional insulating material on the insulating layer, forming a semiconductor layer containing a two-dimensional semiconductor material on the weight control layer, and forming a source electrode to contact one side of the semiconductor layer and forming a drain electrode to contact the other side, wherein one region of the upper surface of the semiconductor layer is formed to be exposed to the outside without overlapping with the source electrode and the drain electrode.

[0021] According to one embodiment, the step of forming the weight control layer may include providing a two-dimensional insulating material on the insulating layer, and treating the two-dimensional insulating material provided on the insulating layer with oxygen plasma (O2 plasma).

[0022]

[0023] To solve the technical problems described above, the present invention provides a method for manufacturing an artificial synapse device.

[0024] According to one embodiment, a method of operating an artificial synapse device comprises a gate electrode, an insulating layer disposed on the gate electrode, a weight control layer disposed on the insulating layer, a semiconductor layer disposed on the weight control layer, a source electrode disposed to contact one side of the semiconductor layer, and a drain electrode disposed to contact the other side of the semiconductor layer, wherein a potential difference is generated within the semiconductor layer due to a work function difference between the source electrode and the drain electrode, wherein the method of operating the artificial synapse device comprises the steps of: irradiating light onto the semiconductor layer to generate electron-hole pairs within the semiconductor layer; applying a first voltage to the drain electrode to generate a current flowing from the source electrode toward the drain electrode; applying a second voltage greater than 0 V to the gate electrode to depress the current flowing from the source electrode toward the drain electrode; applying the second voltage to the gate electrode for a period greater than or equal to a reference time to convert the current flowing from the source electrode toward the drain electrode toward the current flowing from the drain electrode toward the source electrode; and applying 0 to the gate electrode It may include a step of applying a third voltage of less than V to depress the current flowing from the drain electrode toward the source electrode.

[0025] According to one embodiment, the method further includes the step of applying the third voltage to the gate electrode for a period of time longer than a reference time after the step of applying the third voltage to the gate electrode to switch the current flowing from the drain electrode to the source electrode to flow from the source electrode to the drain electrode, and may include the step of applying the second voltage to the gate electrode for a period of time longer than a reference time after the step of applying the third voltage to the gate electrode, the step of applying the second voltage to the gate electrode for a period of time longer than a reference time, the step of applying the third voltage to the gate electrode, and the step of applying the third voltage to the gate electrode for a period of time longer than a reference time, which are performed sequentially and repeatedly.

[0026] According to one embodiment, the current flowing from the drain electrode toward the source electrode is potentialized in the step of applying the second voltage to the gate electrode for a period longer than a reference time, and the current flowing from the source electrode toward the drain electrode is potentialized in the step of applying the third voltage to the gate electrode for a period longer than a reference time.

[0027] According to one embodiment, in the step of applying the second voltage to the gate electrode, electrons are trapped in the weight control layer, and in the step of applying the third voltage to the gate electrode, electrons are detrapped in the weight control layer.

[0028] An artificial synapse device according to an embodiment of the present invention may comprise a substrate, a gate electrode disposed on the substrate, an insulating layer disposed on the substrate to cover the gate electrode, a weighting control layer disposed on the insulating layer and capable of trapping or de-trapping a charge by a voltage applied to the gate electrode, a semiconductor layer disposed on the weighting control layer and comprising a two-dimensional semiconductor material, a source electrode disposed to be in contact with one side of the semiconductor layer and comprising a metal having a relatively low work function, and a drain electrode disposed to be in contact with the other side of the semiconductor layer and comprising a metal having a relatively high work function.

[0029] Accordingly, since an internal potential difference can be generated within the semiconductor layer, the artificial synapse device can generate both a current flowing from the source electrode toward the drain electrode (negative direction current) and a current flowing from the drain electrode toward the source electrode (positive direction current). As a result, the artificial synapse device can express both positive and negative weights within a single device without a separate subtractor or additional wiring.

[0030] FIG. 1 is a flowchart illustrating a method for manufacturing an artificial synapse device according to an embodiment of the present invention.

[0031] FIG. 2 is a perspective view illustrating step S200 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention.

[0032] FIG. 3 is a plan view illustrating step S200 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention.

[0033] FIG. 4 is a perspective view illustrating step S300 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention.

[0034] FIG. 5 is a plan view illustrating step S300 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention.

[0035] FIG. 6 is a perspective view illustrating step S400 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention.

[0036] FIG. 7 is a plan view illustrating step S400 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention.

[0037] FIG. 8 is a perspective view illustrating step S500 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention.

[0038] FIG. 9 is a plan view illustrating step S500 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention.

[0039] FIG. 10 is a perspective view illustrating step S600 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention.

[0040] FIG. 11 is a plan view illustrating step S600 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention.

[0041] FIG. 12 is a schematic diagram of an artificial synapse device according to an embodiment of the present invention, and FIG. 13 is a diagram for explaining the state between the semiconductor layer, the source electrode, and the drain electrode of an artificial synapse device according to an embodiment of the present invention.

[0042] FIG. 14 is a flowchart illustrating the operation process of an artificial synapse device according to an embodiment of the present invention.

[0043] FIG. 15 is a diagram illustrating the change in energy bandgap that occurs during the operation process of an artificial synapse device according to an embodiment of the present invention.

[0044] FIG. 16 is a diagram for specifically explaining the change in energy bandgap occurring at step S20 during the operation of an artificial synapse device according to an embodiment of the present invention.

[0045] FIG. 17 is a diagram for specifically explaining the change in energy bandgap that occurs at step S30 during the operation of an artificial synapse device according to an embodiment of the present invention.

[0046] FIG. 18 is a diagram for specifically explaining the change in energy bandgap occurring at step S40 during the operation of an artificial synapse device according to an embodiment of the present invention.

[0047] FIG. 19 is a diagram for specifically explaining the change in energy bandgap that occurs at step S50 during the operation of an artificial synapse device according to an embodiment of the present invention.

[0048] FIG. 20 is a diagram for specifically explaining the change in energy bandgap that occurs at step S60 during the operation of an artificial synapse device according to an embodiment of the present invention.

[0049] FIG. 21 is a diagram illustrating a change in current that occurs during the operation of an artificial synapse device according to an embodiment of the present invention.

[0050] FIG. 22 is a diagram illustrating the long-term potentiation and degradation characteristics of an artificial synapse device according to an embodiment of the present invention.

[0051] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed content is thorough and complete and to ensure that the concept of the present invention is sufficiently conveyed to those skilled in the art.

[0052] In this specification, when a component is described as being on another component, it means that it may be formed directly on the other component or that a third component may be interposed between them. Additionally, in the drawings, the thicknesses of the films and regions are exaggerated for the effective description of the technical content.

[0053] Additionally, although terms such as first, second, third, etc., have been used to describe various components in the various embodiments of this specification, these components should not be limited by such terms. These terms are used merely to distinguish one component from another. Accordingly, what is referred to as the first component in one embodiment may be referred to as the second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiment. Furthermore, in this specification, "and / or" is used to mean including at least one of the components listed before and after it.

[0054] In the specification, singular expressions include plural expressions unless the context clearly indicates otherwise. Furthermore, terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, components, or combinations thereof described in the specification, and should not be understood as excluding the existence or addition of one or more other features, numbers, steps, components, or combinations thereof. Additionally, in this specification, "connection" is used to include both indirectly connecting multiple components and directly connecting them.

[0055] Furthermore, in describing the present invention below, if it is determined that a detailed description of related known functions or configurations could unnecessarily obscure the essence of the invention, such detailed description will be omitted.

[0056]

[0057] FIG. 1 is a flowchart illustrating a method for manufacturing an artificial synapse device according to an embodiment of the present invention; FIG. 2 is a perspective view illustrating step S200 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention; FIG. 3 is a plan view illustrating step S200 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention; FIG. 4 is a perspective view illustrating step S300 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention; FIG. 5 is a plan view illustrating step S300 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention; FIG. 6 is a perspective view illustrating step S400 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention; FIG. 7 is a plan view illustrating step S400 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention; FIG. 8 is a perspective view illustrating step S500 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention; and FIG. 9 is an embodiment of the present invention Figure 10 is a plan view for explaining step S500 of a method for manufacturing an artificial synapse device according to an example, Figure 10 is a perspective view for explaining step S600 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention, and Figure 11 is a plan view for explaining step S600 of a method for manufacturing an artificial synapse device according to an embodiment of the present invention.

[0058] Referring to FIGS. 1 to 3, a substrate (100) may be prepared (S100). According to one embodiment, the substrate (100) may include any one of a silicon (Si) substrate, a germanium (Ge) substrate, and a glass substrate. Additionally, an insulating layer comprising any one of silicon oxide (SiO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2) may be formed on the upper surface of the substrate (100). Furthermore, various substrates that can be used in a semiconductor process may be used as the substrate (100). That is, the type of the substrate (100) is not limited.

[0059] A gate electrode (200) may be formed on the substrate (100) (S200). According to one embodiment, the gate electrode (200) may include a metal with high conductivity. According to one embodiment, the gate electrode (200) may be formed by any one of thermal evaporation, electron beam evaporation, sputtering, or atomic layer deposition.

[0060] Referring to FIGS. 1, 4, and 5, an insulating layer (300) may be formed on the substrate (100) to cover the gate electrode (200) (S300). According to one embodiment, the insulating layer (300) may include either a two-dimensional insulating material or a three-dimensional insulating material. For example, the two-dimensional insulating material may include hexagonal boron nitride (h-BN). For example, the three-dimensional insulating material may include any one of silicon oxide (SiO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2).

[0061] Referring to FIGS. 1, 6, and 7, a weight control layer (400) may be formed on the insulating layer (300) (S400). The weight control layer (400) is a layer capable of trapping or de-trapping charges by a voltage applied to the gate electrode (200), and according to one embodiment, may include a two-dimensional insulating material. For example, the weight control layer (400) may include hexagonal boron nitride (h-BN). Additionally, according to one embodiment, the step of forming the weight control layer (400) may include providing a two-dimensional insulating material (e.g., h-BN) on the insulating layer (300), and treating the two-dimensional insulating material (e.g., h-BN) provided on the insulating layer (300) with oxygen plasma (O2plasma). That is, hexagonal boron nitride (h-BN) treated with oxygen plasma (O2 plasma) can be used as the weight control layer (400).

[0062] Referring to FIGS. 1, 8, and 9, a semiconductor layer (500) may be formed on the weight control layer (400) (S500). According to one embodiment, the semiconductor layer (500) may include a two-dimensional semiconductor material. For example, the two-dimensional semiconductor material may be a material capable of operating as a p-type, n-type, or bipolar material, and may include any one of a transition metal dichalcogenide, graphene, and black phosphorus. More specifically, the transition metal dichalcogenide material that can be used as the semiconductor layer (500) may be tungsten diselenide (WSe2). According to one embodiment, the semiconductor layer (500) may be formed by a method of exfoliating and transferring a bulk-grown material or by chemical vapor deposition, etc.

[0063] Referring to FIGS. 1, 10, and 11, a source electrode (S) may be formed to contact one side of the semiconductor layer (500), and a drain electrode (D) may be formed to contact the other side. According to one embodiment, the source electrode (S) may be formed on the substrate (100) to contact all of the semiconductor layer (500), the weighting control layer (400), and the insulating layer (300), but may not be formed to contact the gate electrode (200). Alternatively, the drain electrode (D) may be formed on the substrate (100) to contact all of the other side of the semiconductor layer (500), the other side of the weighting control layer (400), and the other side of the insulating layer (300), but may not be formed to contact the gate electrode (200). According to one embodiment, one side of the semiconductor layer (500), weight control layer (400), and insulating layer (300) and the other side of the semiconductor layer (500), weight control layer (400), and insulating layer (400) may mean sides facing each other.

[0064] According to one embodiment, the source electrode (S) and the drain electrode (D) may be formed by any one of thermal evaporation, electron beam evaporation, sputtering, and atomic layer deposition.

[0065] Additionally, according to one embodiment, a region of the upper surface of the semiconductor layer (500) may be formed so as not to overlap with the source electrode (S) and the drain electrode (D). Accordingly, a region of the upper surface of the semiconductor layer (500) may be formed to be exposed to the outside. As a result, external light may be irradiated onto the semiconductor layer (500) through the exposed region of the upper surface of the semiconductor layer (500).

[0066] The source electrode (S) and the drain electrode (D) may comprise metals having different work functions. According to one embodiment, the source electrode (S) may comprise a metal having a relatively low work function. For example, the source electrode (S) may comprise titanium (Ti). In contrast, the drain electrode (D) may comprise a metal having a relatively high work function. For example, the drain electrode (D) may comprise platinum (Pt).

[0067] An internal potential difference may be generated within the semiconductor layer (500) due to the difference in work function between the source electrode (S) and the drain electrode (D). As a result, since the artificial synapse device can generate both a current flowing from the source electrode (S) toward the drain electrode (D) and a current flowing from the drain electrode (D) toward the source electrode (S), both positive and negative weights can be expressed within a single device. Below, a method of operation of the artificial synapse device is described, in which both a current flowing from the source electrode (S) toward the drain electrode (D) and a current flowing from the drain electrode (D) toward the source electrode (S) can be generated.

[0068] FIG. 12 is a schematic diagram of an artificial synapse device according to an embodiment of the present invention, FIG. 13 is a diagram explaining the state between the semiconductor layer, the source electrode, and the drain electrode of an artificial synapse device according to an embodiment of the present invention, FIG. 14 is a flowchart explaining the operation process of an artificial synapse device according to an embodiment of the present invention, FIG. 15 is a diagram explaining the change in energy bandgap occurring during the operation process of an artificial synapse device according to an embodiment of the present invention, FIG. 16 is a diagram specifically explaining the change in energy bandgap occurring at step S20 during the operation overload of an artificial synapse device according to an embodiment of the present invention, FIG. 17 is a diagram specifically explaining the change in energy bandgap occurring at step S30 during the operation overload of an artificial synapse device according to an embodiment of the present invention, FIG. 18 is a diagram specifically explaining the change in energy bandgap occurring at step S40 during the operation overload of an artificial synapse device according to an embodiment of the present invention, and FIG. 19 is a diagram of an artificial synapse device according to an embodiment of the present invention FIG. 20 is a drawing for specifically explaining the change in energy bandgap occurring at step S50 during operation overload of an artificial synapse device according to an embodiment of the present invention, FIG. 21 is a drawing for explaining the change in current occurring during the operation process of an artificial synapse device according to an embodiment of the present invention, and FIG. 22 is a drawing for explaining the long-term potentiation and degradation characteristics of an artificial synapse device according to an embodiment of the present invention.

[0069] Referring to FIG. 12, bidirectional current flow operation is described through an artificial synapse device in which the gate electrode (200) is used as a weight control terminal, the source electrode (S) is used as a pre-synaptic terminal, and the drain electrode (D) is used as a post-synaptic terminal.

[0070] In explaining the current flow of the artificial synapse device above, the current flowing from the source electrode (S) toward the drain electrode (D) is a negative direction current (I PSC - Defined as ), and the current flowing from the drain electrode (D) toward the source electrode (D) is a positive direction current (I PSC + It is defined as ).

[0071] Additionally, an artificial synapse device is described in which hexagonal boron nitride (h-BN) is used as the insulating layer (300), tungsten diselenide (WSe2) is used as the semiconductor layer (500), titanium (Ti) is used as the source electrode (S), and platinum (Pt) is used as the drain electrode (D).

[0072] Referring to FIG. 13 (a) and (b), FIG. 13 (a) shows a state before the source electrode (S) and the drain electrode (D) are formed on the semiconductor layer (500), and FIG. 13 (b) shows a state after the source electrode (S) and the drain electrode (D) are formed on the semiconductor layer (500).

[0073] As can be seen in Figures 13 (a) and (b), due to the difference in work function between the source electrode (S) and the drain electrode (D), it can be seen that an internal potential difference is generated in the region where the semiconductor layer (WSe2, 500), the source electrode (Ti, S), and the drain electrode (Pt, D) are joined in the equilibrium state.

[0074] Referring to FIGS. 14 and 21, light can be irradiated onto the semiconductor layer (500) to generate electron hole pairs (EHP) within the semiconductor layer (500) (S10). More specifically, as light is irradiated onto the semiconductor layer (500), electron hole pairs can be generated across the entire channel within the semiconductor layer (500). According to one embodiment, the photo-excited carriers shown in FIG. 15 refer to carriers generated as light is irradiated onto the semiconductor layer (500), and the injected carriers refer to carriers generated as voltage is applied to the gate electrode (200).

[0075] Referring to FIGS. 14 to 16 and FIG. 21, a first voltage (V) is applied to the drain electrode (D). read By applying ), a current flowing from the source electrode (S) toward the drain electrode (D) can be generated (S20). That is, the first voltage (V) at the drain electrode (D) read By applying ) negative direction current (① I PSC - It can generate ). More specifically, the first voltage (V read ) can be greater than 0 V and less than the reference voltage. Accordingly, the first voltage (V) at the drain electrode (D) read When ) is applied, the first voltage (V readSince the current generated by the internal potential difference of the semiconductor layer (500) (negative direction current) is dominant over the current generated by the application (positive direction current), a negative direction current can be generated.

[0076] Referring to FIGS. 14, 15, 17, and 21, a second voltage (+V) greater than 0 V is applied to the gate electrode (200). write By applying ), the current flowing from the source electrode (S) toward the drain electrode (D) can be depressed (S30). That is, the second voltage (+V) is applied to the gate electrode (200). write By applying ) to lower the negative direction current (② I PSC - It can cause depression. According to one embodiment, the second voltage (+V write ) can be applied in the form of a pulse. More specifically, the second voltage (+V) to the gate electrode (200). write When ) is applied, electrons can be trapped within the weight control layer (400). Accordingly, the energy band (E band) of the semiconductor layer (500) is bent upward, so the current due to the internal potential difference can be reduced. As a result, the negative current can be depressed.

[0077] Referring to FIGS. 14, 15, 18, and 21, the second voltage (+V) applied to the gate electrode (200) write By applying ) for a period longer than a reference time, the current flowing from the source electrode (S) toward the drain electrode (D) can be switched to flow from the drain electrode (D) toward the source electrode (S). That is, the second voltage (+V) on the gate electrode (200) write By accumulating ) to convert negative current into positive current (② I PSC - -> ③ IPSC + ) can be switched. More specifically, a second voltage (+V) applied to the gate electrode (200) can be switched. write When ) accumulates, the energy band (E band) of the semiconductor layer (500) bends further upward, and as a result, the magnitude of the positive direction current may increase, so the negative direction current may be converted into a positive direction current. In addition, the second voltage (+V write As the accumulated time of ) increases, the positive direction current rises (③ I PSC + potentiation can be

[0078] Referring to FIGS. 14, 15, 19, and 21, a third voltage (-V) of less than 0 V is applied to the gate electrode (200). write By applying ), the current flowing from the drain electrode (D) toward the source electrode (S) can be depressed (S50). That is, the third voltage (-V) is applied to the gate electrode (200). write By applying ), the positive direction current decreases (④ I PSC + It can cause depression. According to one embodiment, the third voltage (-V write ) can be applied in the form of a pulse. More specifically, the third voltage (-V) to the gate electrode (200). write When ) is applied, electrons within the weight control layer (400) can be de-trapped. Accordingly, the energy band (E band) of the semiconductor layer (500) is bent downward, so the current due to the internal potential difference can be increased. As a result, the positive current can be depressed.

[0079] Referring to FIGS. 14, 15, 20, and 21, the third voltage (-V) applied to the gate electrode (200)write By applying ) for a period longer than a reference time, the current flowing from the drain electrode (D) toward the source electrode (S) can be switched to flow from the source electrode (S) toward the drain electrode (D). That is, the third voltage (-V) on the gate electrode (200) write By accumulating ) to convert the positive current into a negative current (④ I PSC + -> ⑤ I PSC - ) can be switched. More specifically, a third voltage (-V) applied to the gate electrode (200) can be switched. write When ) accumulates, the energy band (E band) of the semiconductor layer (500) bends further downward, and as a result, the magnitude of the negative direction current may increase, so the positive direction current may be converted into a negative direction current. In addition, the third voltage (-V write As the accumulated time of ) increases, the negative direction current rises (⑤ I PSC - potentiation can be

[0080] According to one embodiment, after steps S20 to S60 are performed sequentially (① I PSC - -> ② I PSC - depression -> ③ I PSC + potentiation -> ④ I PSC + depression -> ⑤ I PSC - potentiation) The above steps S30 through S60 may be performed sequentially and repeatedly (② I PSC - depression -> ③ I PSC + potentiation -> ④ I PSC +depression -> ⑤ I PSC - potentiation).

[0081] Consequently, the artificial synapse device according to the above embodiment can be operated to generate both negative and positive currents. Additionally, referring to FIG. 22, it can be seen that the artificial synapse device exhibits long-term potentialization and depression characteristics under lighting conditions. As a result, it can be seen that the artificial synapse device according to the above embodiment can be easily applied to parallel computing.

[0082]

[0083] Although the present invention has been described in detail using preferred embodiments, the scope of the invention is not limited to specific embodiments and should be interpreted by the appended claims. Furthermore, those skilled in the art will understand that many modifications and variations are possible without departing from the scope of the invention.

[0084] The present invention can be used in the semiconductor industry.

Claims

1. Substrate; A gate electrode disposed on the above substrate; An insulating layer disposed on the substrate to cover the gate electrode; A weighted control layer disposed on the insulating layer and capable of trapping or detrapping a charge by a voltage applied to the gate electrode; A semiconductor layer disposed on the above-mentioned weight control layer and comprising a two-dimensional semiconductor material; A source electrode disposed to be in contact with one side of the semiconductor layer and comprising a metal having a relatively low work function; and A drain electrode comprising a metal having a relatively high work function, disposed to be in contact with the other side of the semiconductor layer, wherein An artificial synapse device capable of generating both a current flowing from the source electrode toward the drain electrode and a current flowing from the drain electrode toward the source electrode.

2. In Paragraph 1, A potential difference is generated within the semiconductor layer due to the difference in work function between the source electrode and the drain electrode, and An artificial synapse device capable of generating both a current flowing from the source electrode toward the drain electrode and a current flowing from the drain electrode toward the source electrode by means of a potential difference generated within the semiconductor layer.

3. In Paragraph 1, When light is irradiated onto the semiconductor layer and a first voltage is applied to the drain electrode, An artificial synapse device comprising generating a current flowing from the source electrode toward the drain electrode.

4. In Paragraph 3, If a second voltage exceeding 0 V is applied to the gate electrode for a period longer than a reference time, An artificial synapse device comprising a current flowing from the source electrode toward the drain electrode that is switched to flow from the drain electrode toward the source electrode.

5. In Paragraph 1, The above two-dimensional semiconductor material is an artificial synapse device comprising any one of transition metal dichalcogenide, graphene, and black phosphorus.

6. In Paragraph 1, An artificial synapse device in which the source electrode comprises titanium (Ti) and the drain electrode comprises platinum (Pt).

7. In Paragraph 1, The above weight control layer is an artificial synapse device comprising hexagonal boron nitride (h-BN).

8. In Paragraph 1, An artificial synapse device comprising the source electrode being used as a pre-synaptic terminal and the drain electrode being used as a postsynaptic terminal.

9. Step of preparing the substrate; A step of forming a gate electrode on the substrate; A step of forming an insulating layer on the substrate to cover the gate electrode; A step of forming a weight control layer comprising a two-dimensional insulating material on the insulating layer; A step of forming a semiconductor layer comprising a two-dimensional semiconductor material on the weight control layer; and The method includes the step of forming a source electrode to contact one side of the semiconductor layer and forming a drain electrode to contact the other side, wherein A method for manufacturing an artificial synapse device comprising forming a region of the upper surface of the semiconductor layer such that it is exposed to the outside without overlapping with the source electrode and the drain electrode.

10. In Paragraph 9, The step of forming the above-mentioned weight control layer is, A step of providing a two-dimensional insulating material on the insulating layer; and A method for manufacturing an artificial synapse device comprising the step of treating the two-dimensional insulating material provided on the insulating layer with oxygen plasma (O2 plasma).

11. A method of operation of an artificial synapse device comprising a gate electrode, an insulating layer disposed on the gate electrode, a weight control layer disposed on the insulating layer, a semiconductor layer disposed on the weight control layer, a source electrode disposed to be in contact with one side of the semiconductor layer, and a drain electrode disposed to be in contact with the other side of the semiconductor layer, wherein a potential difference is generated within the semiconductor layer by a difference in work function between the source electrode and the drain electrode, A step of generating electron-hole pairs within the semiconductor layer by irradiating light onto the semiconductor layer; A step of applying a first voltage to the drain electrode to generate a current flowing from the source electrode toward the drain electrode; A step of applying a second voltage exceeding 0 V to the gate electrode to depress the current flowing from the source electrode toward the drain electrode; A step of applying the second voltage to the gate electrode for a period longer than a reference time to convert the current flowing from the source electrode toward the drain electrode toward flowing from the drain electrode toward the source electrode; and A method of operating an artificial synapse device comprising the step of applying a third voltage of less than 0 V to the gate electrode to depress the current flowing from the drain electrode toward the source electrode.

12. In Paragraph 11, After the step of applying the third voltage to the gate electrode, the method further includes the step of applying the third voltage to the gate electrode for a period longer than a reference time to convert the current flowing from the drain electrode toward the source electrode toward the direction of the source electrode. A method of operating an artificial synapse device comprising the steps of applying the third voltage to the gate electrode for a period of time greater than or equal to a reference time, applying the second voltage to the gate electrode, applying the second voltage to the gate electrode for a period of time greater than or equal to a reference time, applying the third voltage to the gate electrode, and applying the third voltage to the gate electrode for a period of time greater than or equal to a reference time, wherein these steps are performed sequentially and repeatedly.

13. In Paragraph 12, In the step of applying the second voltage to the gate electrode for a period longer than a reference time, the current flowing from the drain electrode toward the source electrode is potentialized, and A method of operating an artificial synapse device comprising applying the third voltage to the gate electrode for a period of time longer than a reference time, wherein the current flowing from the source electrode toward the drain electrode is potentialized.

14. In Paragraph 11, In the step of applying the second voltage to the gate electrode, electrons are trapped within the weight control layer, and A method of operating an artificial synapse device comprising de-trapping electrons within the weight control layer in the step of applying the third voltage to the gate electrode.

15. Weight control terminal; A weight control layer disposed on the above weight control terminal; A semiconductor layer disposed on the above-mentioned weight control layer and comprising a two-dimensional semiconductor material; A presynaptic terminal disposed to be in contact with one side of the semiconductor layer and having a relatively small work function; and A postsynaptic terminal having a relatively large work function and arranged to be in contact with the other side of the semiconductor layer, wherein A current flowing from the presynaptic terminal to the postsynaptic terminal is generated by light irradiated onto the semiconductor layer and a voltage applied to the postsynaptic terminal, and An artificial synapse device comprising a pulse voltage applied to the weight control terminal, wherein a current flowing from the postsynaptic terminal to the presynaptic terminal is generated.

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