Die-to-wafer stacking

Abstract

Improved die-to-wafer stacking techniques are disclosed. In particular, during assembly of a three-dimensional integrated circuit (3DIC), a wafer may include insulation between multiple dice provided by a spun polymer. This spun polymer replaces a more traditional silicon oxide insulator created by deposition techniques. Replacement of the silicon oxide insulator makes mass production of the wafer economically feasible, which in turn allows creation of 3DIC at commercially practical volumes. The use of a 3DIC minimizes lateral surface area of a circuit package, allowing for more real estate to be used by a battery within a mobile computing device. Further, the use of a 3DIC may allow for shorter interconnects between circuit elements, which may, in turn, allow for faster communication between the circuit elements.

Description

DIE-TO-WAFER STACKINGPRIORITY APPLICATION

[0001] The present application is related to U.S. Provisional Patent Application Serial No. 63 / 711,312, filed on October 24, 2024, and entitled “DIE-TO-WAFER STACKING,” the contents of which are incorporated herein by reference in their entirety.BACKGROUNDI. Field of the Disclosure

[0002] The technology of the disclosure relates generally to three-dimensional integrated circuits (3DIC) and, more particularly, to methods for supporting die-to-wafer stacking.IL Background

[0003] Computing devices abound in modern society, and more particularly, mobile communication devices have become increasingly common. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, thus enabling enhanced user experiences. With the advent of the myriad functions available to such devices, there has been increased pressure to find increased processing power coupled with long operating times. This combination has resulted in the expansion of the battery within the mobile device coupled with pressures to increase the size of the processing circuitry. Given commercial pressure to reduce the overall size of the mobile device, these pressures are at odds with one another. Finding ways to satisfy these pressures provides room for innovation.SUMMARY

[0004] Aspects disclosed in the detailed description include improved die-to-wafer stacking techniques. In particular, during assembly of a three-dimensional integrated circuit (3DIC), a wafer may include insulation between multiple dice provided by a spun polymer. This spun polymer replaces a more traditional silicon oxide insulator created by deposition techniques. Replacement of the silicon oxide insulator makes mass production of the wafer economically feasible, which in turn allows creation of 3DIC atcommercially practical volumes. The use of a 3D1C minimizes lateral surface area of a circuit package, allowing for more real estate to be used by a battery within a mobile computing device. Further, the use of a 3DIC may allow for shorter interconnects between circuit elements, which may, in turn, allow for faster communication between the circuit elements.

[0005] In this regard, in one aspect, a 3DIC is disclosed. The 3DIC includes a first layer comprising a device wafer comprising a first circuit, a second layer comprising a die sandwiched between two polymer side walls, the die comprising a second circuit, the first circuit electrically coupled to the second circuit through vias that extend from the first layer to the second layer and an additional via extending from the first layer through the second layer to an external contact without passing through the die.

[0006] In another aspect, a mobile communication device is disclosed. The mobile communication device includes a wireless transceiver including a 3DIC comprising a first layer comprising a device wafer comprising a first circuit, a second layer comprising a die sandwiched between two polymer sidewalls, the die comprising a second circuit, the first circuit electrically coupled to the second circuit through vias that extend from the first layer to the second layer; and an additional via extending from the first layer through the second layer to an external contact without passing through the die.

[0007] In another aspect, a method of making a 3DIC is disclosed. The method includes placing a plurality of dice on a carrier substrate to form an intermediate product, spin coating the intermediate product with a polymer in spaces between the plurality of dice such that the polymer separates and insulates the dice from one another and attaching the dice to a device wafer.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional elevational view of a three-dimensional integrated circuit (3DIC) formed according to aspects of the present disclosure;

[0009] Figure 2 is a flowchart of a process for making the 3DIC of Figure 1 ;

[0010] Figures 3A-3O are cross-sectional elevational views of intermediate products formed during the process of Figure 2; and

[0011] Figure 4 is a block diagram of a mobile computing device, which may include a 3DIC according to the present disclosure.DETAILED DESCRIPTION

[0012] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0013] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element without departing from the scope of the present disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0014] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, no intervening elements are present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, no intervening elements are present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, no intervening elements are present.

[0015] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0016] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a," “an,” and “the” are intended to include the plural forms as well unless the context clearly indicates otherwise. It will be further understood that the terms “comprises," “comprising," “includes,” and / or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0017] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0018] In keeping with the above admonition about definitions, the present disclosure uses transceiver in a broad manner. Current industry literature uses “transceiver” in two ways. The first way uses transceiver broadly to refer to a plurality of circuits that send and receive signals. Exemplary circuits may include a baseband processor, an up / down conversion circuit, filters, amplifiers, couplers, and the like coupled to one or more antennas. A second way, used by some authors in the industry literature, refers to a circuit positioned between a baseband processor and a power amplifier circuit as a transceiver. This intermediate circuit may include the up / down conversion circuits, mixers, oscillators, filters, and the like but generally does not include the power amplifiers. As used herein, the term transceiver is used in the first sense. Where relevant to distinguish between the two definitions, the terms “transceiver chain” and “transceiver circuit” are used respectively.

[0019] Additionally, to the extent that the term “approximately” is used in the claims, it is herein defined to be within five percent (5%).

[0020] Aspects disclosed in the detailed description include improved die-to-wafer stacking techniques. In particular, during assembly of a three-dimensional integrated circuit (3DIC), a wafer may include insulation between multiple dice provided by a spun polymer. This spun polymer replaces a more traditional silicon oxide insulator created by deposition techniques. Replacement of the silicon oxide insulator makes mass production of the wafer economically feasible, which in turn allows creation of 3DIC atcommercially practical volumes. The use of a 3D1C minimizes lateral surface area of a circuit package, allowing for more real estate to be used by a battery within a mobile computing device. Further, the use of a 3DIC may allow for shorter interconnects between circuit elements, which may, in turn, allow for faster communication between the circuit elements.

[0021] In this regard, Figure 1 provides a cross-sectional elevational view of a 3DIC 100 according to aspects of the present disclosure. In particular, the 3DIC may have a first layer 102 coupled to a second layer 104 in a front-to-back configuration. The first layer 102 may include a substrate 106 with internal metallization layers 108 and circuitry 110. The internal metallization layers 108 may couple circuitry 110 to vias 112. Additional vias 114 couple the first layer to external contacts 116. The circuitry 110 may be memory elements, power amplifiers, a power management circuit, an application processor, a baseband processor, or the like.

[0022] The second layer 104 may include a die 120 with circuitry 122 therein. A polymer 124 is positioned on either side of the die 120. The vias 114 pass through the polymer 124. Vias 126 couple to the circuitry 122 and to an interconnect metallization layer 128. The vias 112 also couple to the interconnect metallization layer 128 and allow electrical and / or communicative coupling between the circuitry 110 and the circuitry 122. An additional metallization layer 130 may couple the circuitry 122 to the external contacts 116 and / or assist in lateral coupling of vias 114 to the external contacts 116.

[0023] While the above discussion makes no assumptions about the specific function of the circuitry 110 or the circuitry 122, it should be appreciated that the 3DIC 100 may be a front-end module (FEM) for a transceiver, an entire transceiver, a power management structure with associated switching elements, or other structure, as needed or desired.

[0024] In traditional 3DIC structures, the polymer 124 is not a polymer but is another insulator such as a silicon oxide, which is formed through a vacuum deposition process. Such vacuum deposition processes are extremely time-consuming and expensive. While such processes may be appropriate for high-end graphics processors or the like, for the large quantities contemplated for mobile communication devices, such processes are commercially impractical. However, the flexibility provided by the size of a 3DIC increasingly requires such options to be available for mobile devices.

[0025] The difference between a traditional 3DIC and the 3DIC 100 is further highlighted by the process 200 set forth in Figure 2. Figures 3A-3O show intermediateproducts 300A-3000 formed during the process 200, and accordingly, the following discussion intermingles discussion of the process 200 with reference to Figures 3A-3O.

[0026] In this regard, the process 200 begins by forming a device wafer 300A (block 202, see Figure 3A). The device wafer 300A may include multiple sets of circuitry 122(1)- 122(N) embedded in a substrate 302. The device wafer 300A may be formed through any traditional technique and may be based on complementary metal oxide semiconductor (CMOS) technology. In an exemplary aspect, the device wafer 300A may be approximately 775 micrometers (pm) thick (in the z-axis). The circuitry 122(1)- 122(N) are conceptually separate dice, with each die having a width (in the x-axis) between approximately one and twenty millimeters (1-20 mm) and a pitch ranging from approximately one to ten millimeters (1-10 mm)(see also Figure 3C and discussion of same below).

[0027] The process 200 continues by grinding and thinning the wafer 300A (block 204, see Figure 3B) to form intermediate product 300B. The intermediate product 300B may be approximately 150 micrometers thick (in the z-axis), which is thick enough that the circuitry 122(1)-122(N) is still well within the height of the intermediate product 300B. The intermediate product 300B is then diced (block 206, see Figure 3C) into dice 300C(l)-300C(N). Dice 300C(l)-300C(N) are also collectively and generically referred to as dice 300C.

[0028] The process 200 continues by reconstructing the wafer by attaching the dice 300C(l)-300C(N) to a carrier 304 (block 208, see Figure 3D) to form intermediate product 300D. In an exemplary aspect, the carrier 304 is a silicon substrate and is attached in such a manner that facilitates easy removal. For example, an inorganic layer (not shown) may be used that enables the bonding and debonding as desired.

[0029] The process 200 continues applying a polymer 306 through a spin coating step (block 210, see Figure 3E) to form intermediate product 300E. The polymer 306 may be photo-imageable and is optimized for uniform coating across the intermediate product 300D. The polymer 306 may be baked at certain temperatures for a predefined time (e.g., at 500 °C for 1 hour) to achieve robust stability. The polymer 306 acts as an insulator.

[0030] In traditional processes, the insulator was formed from a material such as silicon oxide through a vacuum deposition process. This vacuum deposition process is slow and expensive. The topography of the intermediate product 300D makes the deposition process even more costly as layers are built up over the dice 300C(l)-300C(N) to heights that are unnecessary, as the gaps between the dice 300C(l)-300C(N) are filled.Replacing the vacuum deposition process with the spin coating greatly reduces the time and cost requirements.

[0031] The process 300 continues by grinding and planarizing the polymer 306 (block 212, see Figure 3F) to form an intermediate product 300F with a planar top surface 308 that exposes the dice 300C(l)-300C(N). In an exemplary aspect, the height of the dice 300C(l)-300C(N) after block 212 is approximately 29 micrometers, although this value is exemplary. Other heights up to approximately 150 micrometers are possible. Planarizing can be done through a conventional chemical mechanical polish (CMP).

[0032] The process 300 continues by adding a photoresist coating 310 (block 214, see Figure 3G) to form intermediate product 300G. The photoresist coating 310 is patterned for backside contact formation and is subjected to an appropriate lithographic process (block 216, see Figure 3H) to form via apertures 312.

[0033] The via apertures 312 may then be plasma etched to form trenches 314 (block 218, see Figure 31) in the dice 3OOC(1)-3OOC(N) to form intermediate product 3001. The trenches 314 are then filled with metal, and the top surface is planarized (block 220, see Figure 3 J) to form the intermediate product 300J. Planarizing may be CMP and removes the photoresist coating 310, re-exposing the dice 300C(l)-300C(N). The metal may be added through an electrodeposition process and may be a metal such as copper. Relevantly, the metal-filled trenches 314 act as vias 126 and provide electrical connections to the circuitry 122.

[0034] The process 200 continues by passivation contact via formation (block 222, see Figure 3K) to form intermediate product 300K. That is, a metallization layer 316 is added with contacts and interior metal layers that provide conductive paths from the trenches 314 to vias 318 (which are part of the vias 112).

[0035] The process 200 continues by hybrid bonding to a device wafer 320 (block 224, see Figure 3L) to form intermediate product 300L. The device wafer 320 includes a metallization layer 322 that has vias 324 that align with the vias 318 to provide electrical connections from the dice 3OOC(1)-3OOC(N) to circuits 326 in the device wafer 320.

[0036] The process 200 continues by removal of the carrier 304 (block 226, see Figure 3M1), such as by infrared release techniques to form intermediate product 300M. Figure 3M2 is a close-up of one portion 300M’ of the intermediate product 300M with a single die 300C(X). Also more readily visible are metallization layers 330 in the wafer 320.

[0037] The process 200 continues by forming vias 332 (block 228, see Figure 3N) through the polymer 306 and the metallization layer 322 to couple to the metallizationlayers 330 to form intermediate product 300N. The vias 332 may be formed through an etch and metal deposition process. A redistribution layer (RDL) 334 and passivation process is performed (block 230, see Figure 30) to form intermediate product 3000.

[0038] The process 200 concludes with pillar and bump formation (block 232) and a dice and singulate step (block 234) to give the 3DIC 100 of Figure 1.

[0039] The 3DIC, according to aspects disclosed herein, may be a chip or system on a chip provided in or integrated into any processor-based device. Examples, without limitation, include a set-top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

[0040] Figure 4 is a schematic diagram of an exemplary communication device 400 wherein any of the circuits supporting the function of the communication device 400 may be the 3DIC 100. Herein, the communication device 400 can be any type of communication device, such as those listed above as well as access points, base stations (e.g., eNB or gNB), and any other type of wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultra-wideband (UWB), and near field communications.

[0041] More particularly, the communication device 400 will generally include a control system 402, a baseband processor 404, transmit circuitry 406, receive circuitry 408, antenna switching circuitry 410, multiple antennas 412, and user interface circuitry 414. As noted, these may be instantiated in a 3DIC 100. In a non-limiting example, the control system 402 can be a field-programmable gate array (FPGA) or an applicationspecific integrated circuit (ASIC), as an example. In this regard, the control system 402 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 408 receives radio frequency signals via the antennas 412 and through the antenna switching circuitry 410 from one or more base stations. A low noise amplifier and a filter of the receive circuitry 408cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0042] The baseband processor 404 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations. The baseband processor 404 is generally implemented in one or more digital signal processors (DSPs) and ASICs.

[0043] For transmission, the baseband processor 404 receives digitized data, which may represent voice, data, or control information, from the control system 402, which it encodes for transmission. The encoded data is output to the transmit circuitry 406, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 412 through the antenna switching circuitry 410 to the antennas 412. The multiple antennas 412 and the replicated transmit and receive circuitries 406, 408 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0044] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications, as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents,electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0045] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

AMENDED CLAIMS received by the International Bureau on 15 April 2026 (15.04.2026)

1. (Currently Amended) A three-dimensional integrated circuit (3DIC) comprising: a first layer comprising a device wafer comprising a first circuit, wherein the first layer comprises first vias; an interconnect metallization layer, the first vias coupled to the interconnect metallization layer; a second layer comprising a die sandwiched between two polymer side walls, the die comprising a second circuit, the second layer further comprising second vias, the second vias coupled to the first vias through the interconnect metallization layer such that the first circuit is electrically coupled to the second circuit through > vias that extend from the first layer to the second layer; and an additional via extending from the first layer through the second layer to an external contact without passing through the die.

2. (Original) The 3DIC of claim 1, wherein the first layer is adjacent to the second layer.

3. (Original) The 3DIC of claim 1, wherein the second layer comprises a redistribution layer (RDL), wherein the additional via is coupled to the external contact through the RDL.

4. (Original) The 3DIC of claim 1, wherein the first layer comprises internal metallization layers coupling the first circuit to the additional via.

5. (Original) The 3DIC of claim 1, wherein the additional via comprises a copper pillar.

6. (Original) The 3DIC of claim 1, further comprising a second external contact and wherein the second circuit is electrically coupled to the second external contact without passing through the first layer.

7. (Currently Amended) The 3DIC of claim 1, wherein the polymer sidewalls are not a silicon oxide insulator are spin-coated.

8. (Original) The 3DIC of claim 1, wherein the polymer sidewalls act as an electrical insulator.

9. (Original) The 3DIC of claim 1, wherein the first circuit comprises a power switch or a power amplifier.

10. (Original) The 3DIC of claim 1, wherein the second circuit comprises a complementary metal oxide semiconductor (CMOS) circuit.

11. (Currently Amended) A mobile communication device comprising:a wireless transceiver comprising: the 3DIC of claim 1 a three-dimensional integrated circuit (3DIC) comprising: a first layer comprising a device wafer comprising a first circuit; a second layer comprising a die sandwiched between two polymer side walls, the die comprising a second circuit, the first circuit electrically coupled to the second circuit through vias that extend from the first layer to the second layer; and an additional via extending from the first layer through the second layer to an external contact without passing through the die.

12. (Original) The mobile communication device of claim 11, wherein the3DIC comprises a front-end module.

13. (Original) A method of making a three-dimensional integrated circuit(3DIC), comprising: placing a plurality of dice on a carrier substrate to form an intermediate product; spin coating the intermediate product with a polymer in spaces between the plurality of dice such that the polymer separates and insulates the plurality of dice from one another; and attaching the plurality of dice to a device wafer.

14. (Original) The method of claim 13, further comprising forming the plurality of dice using complementary metal oxide semiconductor (CMOS) techniques.

15. (Original) The method of claim 13, further comprising grinding and planarizing the polymer after spin coating.

16. (Original) The method of claim 15, further comprising adding a photoresist layer to a surface of the polymer after planarizing.

17. (Original) The method of claim 16, further comprising using a lithographic process to start trenches defined by the photoresist layer through the polymer.

18. (Original) The method of claim 17, further comprising etching trenches in the plurality of dice.

19. (Original) The method of claim 13, wherein attaching the plurality of dice to the device wafer comprises hybrid bonding.

20. (Original) The method of claim 13, further comprising forming vias from the device wafer to an external contact.Claim 1 is amended.Claim 7 is amended.Claim 11 is amended.The remaining claims are unchanged.The amendment to claim 1 is supported by paragraphs 0021-22 and Figure 1.The amendment to claim 7 is responsive to the clarity rejection and is supported by paragraph 0024.The amendment to claim 11 is responsive to the conciseness rejection, and the scope of the claim has not changed.

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