Display panel and display device

Abstract

A display panel and a display device. The display panel comprises a base substrate, and a gate driving circuit and a gating control line which are arranged on the base substrate, wherein the gate driving circuit comprises a plurality of cascaded shift registers, and each shift register comprises a gating unit. The gating unit comprises: a first gating control transistor (T23), a second gating control transistor (T22) and a gating control node (N11), wherein the gating control node (N11) is used for controlling whether a gate driving signal output end of the shift register to which the gating control node (N11) belongs outputs an active level; a first electrode of the first gating control transistor (T23) is coupled to the gating control line, a second electrode of the first gating control transistor (T23) is coupled to a first electrode of the second gating control transistor (T22), and a second electrode of the second gating control transistor (T22) is coupled to the gating control node (N11); and the length of a channel portion of the second gating control transistor (T22) is greater than the length of a channel portion of the first gating control transistor (T23).

Description

Display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In recent years, with the rapid development of the display industry, displays using organic light-emitting diode (OLED) technology have been increasingly used in various industries, such as mobile phones, smartwatches, automotive displays, laptops, and televisions. However, as industries with high refresh rate requirements continue to develop, displays capable of achieving high or even ultra-high refresh rates are becoming increasingly needed. This overall increase in refresh rate leads to increased power consumption and reduced standby time, resulting in a poor user experience. To address this, Hybrid Refresh Display (HRD) technology has been introduced, which saves power while still allowing for high refresh rates.

[0003] Summary of the Invention

[0004] The purpose of this disclosure is to provide a display panel and a display device.

[0005] To achieve the above objectives, this disclosure provides the following technical solution:

[0006] A first aspect of this disclosure provides a display panel, including a substrate, and a gate driving circuit and a gating control line disposed on the substrate. The gate driving circuit includes a plurality of cascaded shift registers, each shift register including a gating unit. The gating unit includes a first gating control transistor, a second gating control transistor, and a gating control node. The gating control node is used to control whether the gate driving signal output terminal of its respective shift register outputs an effective level. A first terminal of the first gating control transistor is coupled to the gating control line, a second terminal of the first gating control transistor is coupled to the first terminal of the second gating control transistor, and a second terminal of the second gating control transistor is coupled to the gating control node. The length of the channel portion of the second gating control transistor is greater than the length of the channel portion of the first gating control transistor.

[0007] Optionally, the shift register further includes a first cascaded control transistor, the gate of which is coupled to a first cascaded control node, a first terminal of which is coupled to a first-level signal line, and a second terminal of which is coupled to a cascaded signal output terminal; the gating unit further includes a first node control transistor, a second node control transistor, and a fifth capacitor, the first terminal of which is coupled to a second-level signal line, the second terminal of which is coupled to the first terminal of the second node control transistor, and the second terminal of the second node control transistor is coupled to a first output control node; the gating control node is used to control the first output control node. The potential of the point, the first output control node is used to control whether the gate drive signal output terminal of its corresponding shift register outputs an effective level; the first plate of the fifth capacitor is coupled to the gating control node, and the second plate of the fifth capacitor is coupled to the first output control node; the first part of the orthographic projection of the fifth capacitor on the substrate is located between the orthographic projection of the first node control transistor on the substrate and the orthographic projection of the first cascaded control transistor on the substrate; the second part of the orthographic projection of the fifth capacitor on the substrate is located between the orthographic projection of the second node control transistor on the substrate and the orthographic projection of the first cascaded control transistor on the substrate.

[0008] Optionally, the gating unit further includes a second output transistor and a sixth capacitor; the gate of the second output transistor is coupled to a second output control node, the first terminal of the second output transistor is coupled to a first level signal line, and the second terminal of the second output transistor is coupled to a gate drive signal output terminal; the first plate of the sixth capacitor is coupled to the gate of the second output transistor, and the second plate of the sixth capacitor is coupled to the gate drive signal output terminal; at least a portion of the orthographic projection of the fifth capacitor on the substrate is located between the orthographic projection of the sixth capacitor on the substrate and the orthographic projection of the first cascaded control transistor on the substrate.

[0009] Optionally, the shift register further includes a second cascaded control transistor and a second capacitor; the gate of the second cascaded control transistor is coupled to a second cascaded control node, the first electrode of the second cascaded control transistor is coupled to a second level signal line, and the second electrode of the second cascaded control transistor is coupled to the cascaded signal output terminal; the first plate of the second capacitor is coupled to the gate of the second cascaded control transistor, and the second plate of the second capacitor is coupled to the second level signal line; there is a first distance between the orthographic projection of the gate of the first cascaded control transistor on the substrate and the display area of ​​the display panel, and a second distance between the orthographic projection of the second plate of the second capacitor on the substrate and the display area, wherein the first distance is greater than the second distance; the orthographic projection of the fifth capacitor on the substrate is located on the side of the orthographic projection of the gate of the first cascaded control transistor on the substrate closer to the display area.

[0010] Optionally, the gating unit further includes: a third gating control transistor, the gate of which is coupled to a cascaded signal output terminal, the first terminal of which is coupled to the second terminal of the second gating control transistor, and the second terminal of which is coupled to the gating control node.

[0011] Optionally, at least a portion of the orthographic projection of the third gating control transistor on the substrate is located between the orthographic projection of the second gating control transistor on the substrate and the orthographic projection of the fifth capacitor on the substrate.

[0012] Optionally, the channel portions of the first and second gate control transistors are arranged along a first direction; the channel portion of the third gate control transistor is offset from the channel portion of the second gate control transistor along the first direction.

[0013] Optionally, the shift register further includes a third node control transistor, the gate of which is coupled to the gating control node, the first terminal of which is coupled to the second cascaded control node, and the second terminal of which is coupled to the first output control node; at least a portion of the orthographic projection of the third gating control transistor on the substrate is located between the orthographic projection of the first cascaded control transistor on the substrate and the orthographic projection of the third node control transistor on the substrate.

[0014] Optionally, the gate of the second cascaded control transistor is coupled to the first terminal of the third node control transistor through a first connection portion; the first portion of the orthographic projection of the first connection portion on the substrate is located between the orthographic projection of the gate of the second gate control transistor on the substrate and the orthographic projection of the gate of the third gate control transistor on the substrate.

[0015] Optionally, the second portion of the orthographic projection of the first connection portion on the substrate is located between the orthographic projection of the gate of the second gate control transistor on the substrate and the orthographic projection of the gate of the third node control transistor on the substrate.

[0016] Optionally, the gating unit includes a second connection portion, which is coupled to the first plate of the fifth capacitor, the second electrode of the third gating control transistor, and the gate of the third node control transistor.

[0017] Optionally, the second connection portion includes a first sub-part and a second sub-part coupled together; the first sub-part includes at least a portion extending along a second direction, and the first sub-part is coupled to the first plate of the fifth capacitor and the second electrode of the third gate control transistor respectively; the second sub-part includes at least a portion extending along a third direction, and the second sub-part is coupled to the gate of the third node control transistor, the third direction intersecting the second direction.

[0018] Optionally, the gating unit includes a third connection portion, which includes a third sub-part, a fourth sub-part, and a fifth sub-part coupled in sequence; the third sub-part is coupled to the second plate of the fifth capacitor; the first end of the fifth sub-part coupled to the fourth sub-part is coupled to the second electrode of the third node control transistor; and the second end of the fifth sub-part away from the fourth sub-part is coupled to the first output control node; the fourth sub-part includes at least a portion extending in a third direction.

[0019] Optionally, the first gating control transistor adopts a dual-gate transistor structure; and / or, the second gating control transistor adopts a dual-gate transistor structure; and / or, the third gating control transistor adopts a dual-gate transistor structure.

[0020] Optionally, the length of the channel portion of the second gating control transistor is x1 times the length of the channel portion of the first gating control transistor, where x1 satisfies: 1.5 ≤ x1 ≤ 2.5; and / or, the length of the channel portion of the third gating control transistor is x2 times the length of the channel portion of the first gating control transistor, where x2 satisfies: 1.5 ≤ x2 ≤ 3.

[0021] Optionally, the orthographic projection of the channel portion in the second and / or the third gate control transistor onto the substrate adopts one of a zigzag structure, an L-shaped structure, and an S-shaped structure.

[0022] Optionally, the width W1 of the channel portion of the first gating control transistor satisfies: 3μm≤W1≤4μm, and the length L1 of the channel portion of the first gating control transistor satisfies: 5μm<L1≤10μm; and / or, the width W2 of the channel portion of the second gating control transistor satisfies: 3μm≤W2≤4μm, and the length L2 of the channel portion of the second gating control transistor satisfies: 5μm<L2≤13μm.

[0023] Optionally, the selection unit further includes a voltage-stabilizing capacitor, the first plate of which is coupled to the first terminal of the second selection control transistor, and the second plate of which is coupled to the second level signal line.

[0024] Optionally, the display panel includes an active layer, a first gate metal layer, and a second gate metal layer sequentially stacked on the substrate along a direction away from the substrate; the first electrode of the voltage regulator capacitor is disposed in the same layer and with the same material as the active layer, and the second electrode of the voltage regulator capacitor is disposed in the same layer and with the same material as the second gate metal layer.

[0025] Optionally, the first plate of the voltage regulator capacitor, the second plate of the first selection control transistor, and the first plate of the second selection control transistor are formed into an integral structure; the selection unit further includes a first output transistor and a fourth capacitor, the gate of the first output transistor is coupled to a first output control node, the first plate of the first output transistor is coupled to a second level signal line, and the second plate of the first output transistor is coupled to a gate drive signal output terminal; the first plate of the fourth capacitor is coupled to the first output control node, and the second plate of the fourth capacitor is coupled to the second level signal line; the second plate of the voltage regulator capacitor and the second plate of the fourth capacitor are formed into an integral structure.

[0026] Optionally, the orthographic projections of the first gating control transistor, the orthographic projections of the voltage-stabilizing capacitor, and the orthographic projections of the second gating control transistor on the substrate are arranged sequentially along a first direction; the first plate of the voltage-stabilizing capacitor extends along a second direction, the second plate of the voltage-stabilizing capacitor extends along the second direction, and the second direction intersects with the first direction.

[0027] Based on the above-described display panel technical solution, a second aspect of this disclosure provides a display device including the display panel provided in the above embodiments. Attached Figure Description

[0028] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0029] Figure 1 is a circuit diagram of the pixel driving circuit provided in an embodiment of this disclosure;

[0030] Figure 2 is a first circuit schematic diagram of the shift register provided in an embodiment of this disclosure;

[0031] Figure 3 is a schematic diagram of the second circuit of the shift register provided in an embodiment of this disclosure;

[0032] Figure 4 is a schematic diagram of the first layout of the active layer corresponding to Figure 2;

[0033] Figure 5 is a schematic diagram of the first layout of the first gate metal layer corresponding to Figure 2;

[0034] Figure 6 is a composite diagram of Figures 4 and 5;

[0035] Figure 7 is a schematic diagram of the first layout of the second gate metal layer corresponding to Figure 2;

[0036] Figure 8 is a stacked diagram based on Figure 6 with the addition of Figure 7;

[0037] Figure 9 is a schematic diagram of the first layout of the first source / drain metal layer corresponding to Figure 2;

[0038] Figure 10 is a schematic diagram of the first layout of the first source / drain metal layer corresponding to Figure 2;

[0039] Figure 11 is a stacked diagram based on Figure 8 with the addition of Figure 9;

[0040] Figure 12 is a schematic diagram of the first layout of the second source / drain metal layer corresponding to Figure 2;

[0041] Figure 13 is a stacked diagram based on Figure 11 with Figure 12 added;

[0042] Figure 14 is a schematic diagram of the second layout of the active layer corresponding to Figure 2;

[0043] Figure 15 is a schematic diagram of the second layout of the first gate metal layer corresponding to Figure 2;

[0044] Figure 16 is a composite diagram of Figures 14 and 15;

[0045] Figure 17 is a schematic diagram of the second layout of the second gate metal layer corresponding to Figure 2;

[0046] Figure 18 is a stacked diagram based on Figure 16 with the addition of Figure 17;

[0047] Figure 19 is a stacked diagram based on Figure 18 with Figure 9 added;

[0048] Figure 20 is a stacked diagram based on Figure 19 with the addition of Figure 12;

[0049] Figure 21 is a schematic diagram of the third layout of the active layer corresponding to Figure 2;

[0050] Figure 22 is a schematic diagram of the third layout of the first gate metal layer corresponding to Figure 2;

[0051] Figure 23 is a composite diagram of Figures 21 and 22;

[0052] Figure 24 is a stacked diagram based on Figure 23 with the addition of Figure 17;

[0053] Figure 25 is a stacked diagram based on Figure 24 with the addition of Figure 9;

[0054] Figure 26 is a stacked diagram based on Figure 25 with the addition of Figure 12;

[0055] Figure 27 is a schematic diagram of the first layout of the active layer corresponding to Figure 3;

[0056] Figure 28 is a schematic diagram of the first layout of the first gate metal layer corresponding to Figure 3;

[0057] Figure 29 is a stacked diagram of Figures 27 and 28;

[0058] Figure 30 is a schematic diagram of the first layout of the second gate metal layer corresponding to Figure 3;

[0059] Figure 31 is a stacked diagram based on Figure 29 with Figure 30 added;

[0060] Figure 32 is a schematic diagram of the first layout of the first source / drain metal layer corresponding to Figure 3;

[0061] Figure 33 is a schematic diagram of the first layout of the first source / drain metal layer corresponding to Figure 3;

[0062] Figure 34 is a stacked diagram based on Figure 31 with Figure 32 added;

[0063] Figure 35 is a stacked diagram based on Figure 34 with the addition of Figure 12;

[0064] Figure 36 is a schematic diagram of the second layout of the active layer corresponding to Figure 3;

[0065] Figure 37 is a schematic diagram of the second layout of the first gate metal layer corresponding to Figure 3;

[0066] Figure 38 is a stacked diagram of Figures 36 and 37;

[0067] Figure 39 is a stacked diagram of Figure 30 added to Figure 38;

[0068] Figure 40 is a stacked diagram based on Figure 39 with the addition of Figure 32;

[0069] Figure 41 is a stacked diagram based on Figure 40 with the addition of Figure 12. Detailed Implementation

[0070] To further illustrate the display panel and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0071] Display products using HRD technology differ from traditional global refresh displays. Partial refresh technology only updates the parts of the screen that need to change, thus reducing power consumption and latency and improving the smoothness of the displayed image. However, with the production of displays using HRD technology, a series of display defects unique to HRD technology have also emerged. For example, during partitioned refresh, there are noticeable bright lines at the boundary between a high refresh rate display area and a low refresh rate display area.

[0072] Research revealed that the location of the bright line is random; it appears at some boundary points and not at others, and it is present on some display products and absent on others. Furthermore, the bright line appears in different locations on different display products, exhibiting a high degree of randomness. Therefore, eliminating this bright line has become an urgent technical problem to be solved.

[0073] Please refer to Figures 2 to 41. This disclosure provides a display panel, including a substrate, and a gate driving circuit and a gating control line disposed on the substrate. The gate driving circuit includes a plurality of cascaded shift registers, and the shift registers include gating units.

[0074] The gating unit includes: a first gating control transistor T23, a second gating control transistor T22, and a gating control node N11. The gating control node N11 is used to control whether the gate drive signal output terminal of its corresponding shift register outputs an effective level. The first terminal of the first gating control transistor T23 is coupled to the gating control line, the second terminal of the first gating control transistor T23 is coupled to the first terminal of the second gating control transistor T22, and the second terminal of the second gating control transistor T22 is coupled to the gating control node N11.

[0075] The length of the channel portion of the second gating control transistor T22 is greater than the length of the channel portion of the first gating control transistor T23.

[0076] It should be noted that, as shown in Figures 4, 14, 21, 27 and 36, the part circled by the small dashed box within the large dashed box is the channel part, which is the channel part of the corresponding transistor.

[0077] For example, the display panel includes, but is not limited to, a Low Temperature Polycrystalline Oxide Active-matrix Organic Light-Emitting Diode (LTPO AMOLED) display panel. The display panel can achieve adaptive refresh, that is, control any position within the display area of ​​the display panel to achieve different refresh rates in real time, thereby reducing the overall power consumption of the screen. For example, the display area can be divided into an upper display area, a middle display area, and a lower display area, with the upper and lower display areas having a refresh rate of 1Hz, and the middle display area having a refresh rate of 120Hz, but this is not limited to these examples.

[0078] For example, the display panel includes a display area and a peripheral area surrounding the display area, the peripheral area including a left bezel area and a right bezel area, the display area being located between the left bezel area and the right bezel area. The gate driving circuit may be arranged in the left bezel area and / or the right bezel area, but is not limited thereto.

[0079] For example, the gate driving circuit includes multiple cascaded shift registers, as shown in FIG1. ​​The shift registers include a compensation shift register Gate_N GOA, and the gate driving signal output terminal of the compensation shift register Gate_N GOA is coupled to the gate of the compensation transistor T32 in the corresponding sub-pixel driving circuit.

[0080] For example, the sub-pixel driving circuit adopts an 8T1C (i.e., 8 transistors and 1 capacitor) circuit structure, but is not limited to this. For instance, as shown in Figure 1, the sub-pixel driving circuit includes the following specific structure:

[0081] The first reset transistor T31 is driven by a driving transistor T33 and a first reset transistor T31. The gate of the first reset transistor T31 is coupled to the gate drive signal output terminal of the corresponding first reset shift register Reset_P GOA. The first terminal of the first reset transistor T31 is coupled to the first initialization signal line Vinit1. The second terminal of the first reset transistor T31 is coupled to the second terminal of the driving transistor T33.

[0082] The compensation transistor T32 has its gate coupled to the gate drive signal output terminal of the corresponding compensation shift register Gate_N GOA. The first terminal of the compensation transistor T32 is coupled to the second terminal of the driving transistor T33, and the second terminal of the compensation transistor T32 is coupled to the gate of the driving transistor T33.

[0083] A write control transistor T34 is provided, the gate of which is coupled to the gate drive signal output terminal of the corresponding write control shift register Gate_P GOA, the first terminal of which is coupled to the corresponding data line DA, and the second terminal of which is coupled to the first terminal of the drive transistor T33.

[0084] A power control transistor T35 is provided, wherein the gate of the power control transistor T35 is coupled to the gate drive signal output terminal of the corresponding light emission control shift register EM GOA, the first terminal of the power control transistor T35 is coupled to the corresponding power signal input terminal VDD, and the second terminal of the power control transistor T35 is coupled to the first terminal of the driving transistor T33.

[0085] The light-emitting control transistor T36 has its gate coupled to the gate drive signal output terminal of the corresponding light-emitting control shift register EM GOA. The first terminal of the light-emitting control transistor T36 is coupled to the second terminal of the driving transistor T33. The second terminal of the light-emitting control transistor T36 is coupled to the anode of the light-emitting element.

[0086] The second reset transistor T37 has its gate coupled to the gate drive signal output terminal of the corresponding second reset shift register Reset_H GOA, its first terminal coupled to the corresponding second initialization signal line Vinit2, and its second terminal coupled to the anode of the light-emitting element. The cathode of the light-emitting element is connected to the VSS signal.

[0087] The third reset transistor T38 has its gate coupled to the gate drive signal output terminal of the corresponding second reset shift register Reset_H GOA, its first terminal coupled to the corresponding third initialization signal line Vinit3, and its second terminal coupled to the first terminal of the drive transistor T33.

[0088] The storage capacitor Cst has its first plate coupled to the gate of the driving transistor T33, and its second plate coupled to the power signal input terminal VDD.

[0089] For example, the compensation transistor T32 includes an N-type transistor, and the high level output of the compensation shift register Gate_N GOA is used to turn on the compensation transistor T32.

[0090] For example, the shift register includes a gating unit, which controls whether the gate drive signal output terminal outputs an effective level, which is used to turn on the transistor in the sub-pixel drive circuit coupled to the gate drive signal output terminal.

[0091] For example, the gating unit includes: a first gating control transistor T23, a second gating control transistor T22, and a gating control node N11; the first gating control transistor T23 and the second gating control transistor T22 are connected in series and between the gating control line and the gating control node N11, for controlling whether to conduct the electrical connection between the gating control line and the gating control node N11; the gating control node N11 further controls whether the gate drive signal output terminal of its corresponding shift register outputs an effective level;

[0092] For example, when the signal transmitted by the strobe control line is low, the shift register currently in the scanning state is controlled to perform a high refresh rate scan; when the signal transmitted by the strobe control line is high, the shift register currently in the scanning state is controlled to perform a low refresh rate scan.

[0093] Research has revealed that when the signal transmitted by the gating control line switches from a low level to a high level, that is, when moving from a display area refreshed by a high refresh rate to a display area refreshed by a low refresh rate, the transistor coupled to the gating control node N11 is prone to leakage, causing the potential of the gating control node N11 to be unstable, which in turn leads to display abnormalities and the appearance of bright lines.

[0094] As can be seen from the specific structure of the display panel described above, in the display panel provided in this embodiment, by connecting the first selection control transistor T23 and the second selection control transistor T22 in series between the selection control line and the selection control node N11, the first selection control transistor T23 and the second selection control transistor T22 can control whether the electrical connection between the selection control line and the selection control node N11 is turned on, thereby controlling the potential of the selection control node N11. Simultaneously, the length of the channel portion of the second selection control transistor T22 is set to be greater than the length of the channel portion of the first selection control transistor T23, so that the second selection control transistor T22 coupled to the selection control node N11 has a longer channel portion. This results in better stability for the second selection control transistor T22, improves the leakage current problem of the second selection control transistor T22, and ensures the stability of the selection control node N11. Therefore, the display panel provided in this embodiment improves the leakage problem of the gating unit in the shift register, thereby solving the problem of bright lines generated at the random boundary position of high frequency to low frequency switching in the display area. When the display area of ​​the display panel is divided into multiple display areas with different refresh rates, good display effect can be guaranteed.

[0095] It should be noted that the transistor includes an active pattern, and the overlapping portion between the orthographic projection of the active pattern on the substrate and the orthographic projection of the gate of the transistor on the substrate is the channel portion of the transistor. The length and width of the channel portion can determine the properties of the transistor.

[0096] As shown in Figures 27 to 35, in some embodiments, the shift register further includes a first cascaded control transistor T10, the gate of the first cascaded control transistor T10 is coupled to the first cascaded control node N7, the first terminal of the first cascaded control transistor T10 is coupled to the first level signal line, and the second terminal of the first cascaded control transistor T10 is coupled to the cascaded signal output terminal.

[0097] The gating unit further includes a first node control transistor T24, a second node control transistor T26, and a fifth capacitor C5. The first terminal of the first node control transistor T24 is coupled to a second level signal line, and the second terminal of the first node control transistor T24 is coupled to the first terminal of the second node control transistor T26. The second terminal of the second node control transistor T26 is coupled to a first output control node N12. The gating control node N11 is used to control the potential of the first output control node N12, and the first output control node N12 is used to control whether the gate drive signal output terminal of its corresponding shift register outputs an effective level. The first plate of the fifth capacitor C5 is coupled to the gating control node N11, and the second plate of the fifth capacitor C5 is coupled to the first output control node N12.

[0098] The first portion of the orthographic projection of the fifth capacitor C5 onto the substrate is located between the orthographic projection of the first node control transistor T24 onto the substrate and the orthographic projection of the first cascaded control transistor T10 onto the substrate.

[0099] The second portion of the orthographic projection of the fifth capacitor C5 onto the substrate is located between the orthographic projection of the second node control transistor T26 onto the substrate and the orthographic projection of the first cascaded control transistor T10 onto the substrate.

[0100] For example, the first cascade control node N7 is used to control whether the first cascade control transistor T10 is turned on, thereby controlling whether the electrical connection between the first level signal line and the cascade signal output terminal is turned on.

[0101] For example, the active pattern of the first cascaded control transistor T10 extends along a first direction, and the gate of the first cascaded control transistor T10 includes a plurality of gate patterns spaced apart along the first direction. The first ends of the plurality of gate patterns are coupled to each other, and the orthographic projection of each gate pattern on the substrate overlaps at least partially with the orthographic projection of the active pattern on the substrate.

[0102] For example, the first node control transistor T24 and the second node control transistor T26 are connected in series between the second level signal line and the first output control node N12 to control whether the electrical connection between the second level signal line and the first output control node N12 is turned on.

[0103] For example, the first electrode of the fifth capacitor C5 is disposed in the same layer and made of the same material as the first gate metal layer in the display panel, and the second electrode of the fifth capacitor C5 is disposed in the same layer and made of the same material as the second gate metal layer in the display panel. The fifth capacitor C5 is used to stabilize the potential of the gating control node N11.

[0104] The above-described configuration of the fifth capacitor C5's orthogonal projection on the substrate includes the first portion and the second portion, allowing the fifth capacitor C5 to utilize the layout space between the first node control transistor T24 and the first cascaded control transistor T10, as well as the layout space between the second node control transistor T26 and the first cascaded control transistor T10. This enables the fifth capacitor C5 to have a larger layout area, thereby better ensuring the potential stability of the gating control node N11.

[0105] As shown in Figures 27 to 35, in some embodiments, the gating unit further includes a second output transistor T20 and a sixth capacitor C6; the gate of the second output transistor T20 is coupled to the second output control node N13, the first terminal of the second output transistor T20 is coupled to the first level signal line, and the second terminal of the second output transistor T20 is coupled to the gate drive signal output terminal; the first plate of the sixth capacitor C6 is coupled to the gate of the second output transistor T20, and the second plate of the sixth capacitor C6 is coupled to the gate drive signal output terminal;

[0106] At least a portion of the orthographic projection of the fifth capacitor C5 onto the substrate is located between the orthographic projection of the sixth capacitor C6 onto the substrate and the orthographic projection of the first cascaded control transistor T10 onto the substrate.

[0107] For example, the first level signal line is used to transmit a low-level signal, but is not limited to this.

[0108] For example, the second output control node N13 is used to control whether the second output transistor T20 is turned on, thereby controlling whether the electrical connection between the first level signal line and the gate drive signal output terminal is realized.

[0109] For example, the first electrode plate of the sixth capacitor C6, the gate of the second output transistor T20, and the gate of the first node control transistor T24 are formed into an integral structure, and the second electrode plate of the sixth capacitor C6 is disposed in the same layer and with the same material as the second gate metal layer in the display panel.

[0110] The above configuration allows the fifth capacitor C5 to utilize the layout space between the sixth capacitor C6 and the first cascaded control transistor T10, enabling the fifth capacitor C5 to have a larger layout area, thereby better ensuring the potential stability of the gating control node N11.

[0111] As shown in Figures 27 to 35, in some embodiments, the shift register further includes a second cascaded control transistor T9 and a second capacitor C2; the gate of the second cascaded control transistor T9 is coupled to the second cascaded control node N4, the first terminal of the second cascaded control transistor T9 is coupled to the second level signal line, and the second terminal of the second cascaded control transistor T9 is coupled to the cascaded signal output terminal; the first plate of the second capacitor C2 is coupled to the gate of the second cascaded control transistor T9, and the second plate of the second capacitor C2 is coupled to the second level signal line;

[0112] The gate of the first cascaded control transistor T10 has a first distance between its orthogonal projection on the substrate and the display area of ​​the display panel, and the second capacitor C2 has a second distance between its orthogonal projection on the substrate and the display area, wherein the first distance is greater than the second distance.

[0113] The orthogonal projection of the fifth capacitor C5 on the substrate is located on the side of the orthogonal projection of the gate of the first cascaded control transistor T10 on the substrate toward the display area.

[0114] For example, the second cascade control node N4 is used to control whether the second cascade control transistor T9 is turned on, and thus control whether the electrical connection between the second level signal line and the cascade signal output terminal is turned on.

[0115] For example, both the first distance and the second distance refer to the shortest distance, but are not limited to this.

[0116] For example, by narrowing the size of the first cascaded control transistor T10 along the second direction, a larger layout space can be freed up on the side of the first cascaded control transistor T10 facing the display area.

[0117] The above-mentioned setting of the first distance being greater than the second distance leaves a larger layout space on the side of the first cascaded control transistor T10 facing the display area. By setting the orthogonal projection of the fifth capacitor C5 on the substrate to be located on the side of the orthogonal projection of the gate of the first cascaded control transistor T10 on the substrate facing the display area, the larger layout space is utilized to arrange the fifth capacitor C5, so that the fifth capacitor C5 can achieve a larger area, thereby better ensuring the potential stability of the gating control node N11.

[0118] The above arrangement moves the fifth capacitor C5 to a position below the overall layout area occupied by a single shift register, making better use of the limited layout space and achieving a larger capacitor area. Compared with the original layout, the area of ​​the fifth capacitor C5 can be increased by at least 100%.

[0119] As shown in Figures 27 to 41, in some embodiments, the gating unit further includes: a third gating control transistor T27, the gate of the third gating control transistor T27 being coupled to the cascaded signal output terminal, the first terminal of the third gating control transistor T27 being coupled to the second terminal of the second gating control transistor T22, and the second terminal of the third gating control transistor T27 being coupled to the gating control node N11.

[0120] For example, the active patterns of the third gating control transistor T27, the second gating control transistor T22, and the first gating control transistor T23 are sequentially coupled to form an integral structure.

[0121] The gate of the third gating control transistor T27 is coupled to the cascade signal output terminal of the shift register at this stage, and is controlled by the cascade signal output terminal of the shift register at this stage. The gate of the second gating control transistor T22 is coupled to the cascade signal output terminal of the adjacent previous stage shift register, and is controlled by the cascade signal output terminal of the adjacent previous stage shift register. This design does not affect the effective transmission of the signal provided by the gating control line.

[0122] The above-mentioned gating unit also includes the third gating control transistor T27, which further effectively prevents the problem of unstable potential of gating control node N11 caused by leakage of the first gating control transistor T23.

[0123] As shown in Figures 27 to 35, in some embodiments, at least a portion of the orthographic projection of the third gating control transistor T27 onto the substrate is located between the orthographic projection of the second gating control transistor T22 onto the substrate and the orthographic projection of the fifth capacitor C5 onto the substrate.

[0124] After arranging the fifth capacitor C5 according to the above embodiment, usable layout space can be freed up between the fifth capacitor C5 and the second gating control transistor T22. Therefore, arranging the third gating control transistor T27 here does not require additional layout space for the entire shift register.

[0125] As shown in Figures 27 to 35, in some embodiments, the channel portions of the first selection control transistor T23 and the second selection control transistor T22 are arranged along a first direction; the channel portion of the third selection control transistor T27 is offset from the channel portion of the second selection control transistor T22 along the first direction.

[0126] For example, the distance between the channel portion of the first gating control transistor T23 and the display area is equal to the distance between the channel portion of the second gating control transistor T22 and the display area; the distance between the channel portion of the second gating control transistor T22 and the display area is less than the distance between the channel portion of the third gating control transistor T27 and the display area.

[0127] The above configuration allows the third gating control transistor T27 to avoid other functional structures located between it and the display area, which, while ensuring operational stability, helps reduce the layout difficulty of the shift register within the limited layout space.

[0128] As shown in Figures 27 to 35, in some embodiments, the shift register further includes a third node control transistor T21, the gate of which is coupled to the gating control node N11, the first terminal of which is coupled to the second cascaded control node N4, and the second terminal of which is coupled to the first output control node N12.

[0129] At least a portion of the orthographic projection of the third gating control transistor T27 onto the substrate is located between the orthographic projection of the first cascade control transistor T10 onto the substrate and the orthographic projection of the third node control transistor T21 onto the substrate.

[0130] For example, the gating control node N11 can control whether the third node control transistor T21 is turned on, thereby controlling whether the electrical connection between the second cascaded control node N4 and the first output control node N12 is turned on.

[0131] For example, the third node control transistor T21 adopts a dual-gate transistor structure, and the third node control transistor T21 includes two channel portions arranged along a first direction.

[0132] The above arrangement makes the third node control transistor T21, the third gating control transistor T27 and the fifth capacitor C5 adjacent to each other, which helps to reduce the connection difficulty between the gate of the third node control transistor T21, the second electrode of the third gating control transistor T27 and the first plate of the fifth capacitor C5.

[0133] As shown in Figures 27 to 35, in some embodiments, the gate of the second cascaded control transistor T9 is coupled to the first pole of the third node control transistor T21 through the first connection portion 31; the first portion of the orthographic projection of the first connection portion 31 on the substrate is located between the orthographic projection of the gate of the second gate control transistor T22 on the substrate and the orthographic projection of the gate of the third gate control transistor T27 on the substrate.

[0134] For example, the first connection portion 31 is coupled to the gate of the second cascaded control transistor T9 through the first 107 via 107, and the first connection portion 31 is coupled to the first terminal of the third node control transistor T21 through the first 100 via 100.

[0135] For example, the first connection portion 31 is disposed in the same layer and with the same material as the first source / drain metal layer in the display panel, but is not limited thereto.

[0136] For example, the second portion of the orthographic projection of the first connection portion 31 on the substrate is located between the orthographic projection of the gate of the second gate control transistor T22 on the substrate and the orthographic projection of the gate of the third node control transistor T21 on the substrate.

[0137] By adopting the above structure and arranging the first connection portion 31 in the above manner, it is possible not only to connect the gate of the second cascaded control transistor T9 with the first pole of the third node control transistor T21, but also to effectively utilize the limited layout space, reduce the overlap area between the first connection portion 31 and other conductive structures, and ensure the stability of the signal transmitted by the first connection portion 31.

[0138] As shown in Figures 27 to 35, in some embodiments, the gating unit includes a second connection portion 32, which is coupled to the first plate of the fifth capacitor C5, the second electrode of the third gating control transistor T27, and the gate of the third node control transistor T21.

[0139] For example, the second connection portion 32 is coupled to the first plate of the fifth capacitor C5 through the first 101 via a101, the second connection portion 32 is coupled to the second electrode of the third gate control transistor T27 through the first 102 via a102, and the second connection portion 32 is coupled to the gate of the third node control transistor T21 through the first 103 via a103.

[0140] For example, the second connection portion 32 is disposed in the same layer and material as the first source / drain metal layer in the display panel, but is not limited thereto.

[0141] For example, the second connection portion 32 can serve as the gating control node N11, but is not limited to this.

[0142] For example, the second connection portion 32 includes a first sub-portion 321 and a second sub-portion 322 coupled together; the first sub-portion 321 includes at least a portion extending along a second direction, and the first sub-portion 321 is coupled to the first plate of the fifth capacitor C5 and the second plate of the third gate control transistor T27 respectively; the second sub-portion 322 includes at least a portion extending along a third third direction, and the second sub-portion 322 is coupled to the gate of the third node control transistor T21, the third third direction intersecting the second direction.

[0143] For example, the first direction intersects the second direction, and the third direction intersects both the first and second directions. For instance, the first direction includes a longitudinal direction, and the second direction includes a transverse direction, but is not limited to these.

[0144] By adopting the above structure and arranging the second connection part 32 in the above manner, it is possible not only to connect the first plate of the fifth capacitor C5, the second electrode of the third gate control transistor T27, and the gate of the third node control transistor T21 together, but also to effectively utilize the limited layout space, reduce the overlap area between the second connection part 32 and other conductive structures, and ensure the stability of the signal transmitted by the second connection part 32.

[0145] As shown in Figures 27 to 35, in some embodiments, the gating unit includes a third connection portion 33, which includes a third sub-part 331, a fourth sub-part 332, and a fifth sub-part 333 coupled in sequence; the third sub-part 331 is coupled to the second plate of the fifth capacitor C5; the first end of the fifth sub-part 333 coupled to the fourth sub-part 332 is coupled to the second electrode of the third node control transistor T21; the second end of the fifth sub-part 333 away from the fourth sub-part 332 is coupled to the first output control node N12; the fourth sub-part 332 includes at least a portion extending in a third direction.

[0146] For example, the third connection part 33 is coupled to the second plate of the fifth capacitor C5 through the first 105 via a105, the third connection part 33 is coupled to the second electrode of the third node control transistor T21 through the first 106 via a106, and the third connection part 33 is coupled to the first output control node N12 through the first 104 via a104.

[0147] For example, the third connection portion 33 is disposed in the same layer and with the same material as the first source / drain metal layer in the display panel, but is not limited thereto.

[0148] For example, the third sub-part 331 adopts an inverted L-shaped structure that is flipped along the first direction, and the fifth sub-part 333 adopts an inverted L-shaped structure that is flipped along the second direction.

[0149] For example, the fourth sub-part 332 is at least partially parallel to the second sub-part 322, but is not limited thereto.

[0150] By adopting the above structure and arranging the third connection part 33 in the above manner, it is possible not only to connect the second plate of the fifth capacitor C5, the second electrode of the third node control transistor T21, and the first output control node N12 together, but also to effectively utilize the limited layout space, reduce the overlap area between the third connection part 33 and other conductive structures, and ensure the stability of the signal transmitted by the second connection part 32.

[0151] As shown in Figures 6, 16 and 38, in some embodiments, the first gating control transistor T23 adopts a single-gate transistor structure; and / or, the second gating control transistor T22 adopts a single-gate transistor structure; and / or, the third gating control transistor T27 adopts a single-gate transistor structure.

[0152] As shown in Figures 23 and 29, in some embodiments, the first gating control transistor T23 adopts a dual-gate transistor structure; and / or, the second gating control transistor T22 adopts a dual-gate transistor structure; and / or, the third gating control transistor T27 adopts a dual-gate transistor structure.

[0153] For example, the gate in the dual-gate transistor structure adopts a U-shaped structure with the opening of the U-shaped structure facing the display area. The dual-gate transistor structure includes two channel portions arranged along a first direction, but is not limited thereto.

[0154] The above-described configuration of the first selection control transistor T23 using a dual-gate transistor structure improves its leakage current and enhances its stability. Similarly, the above-described configuration of the second selection control transistor T22 using a dual-gate transistor structure improves its leakage current and enhances its stability. Finally, the above-described configuration of the third selection control transistor T27 using a dual-gate transistor structure improves its leakage current and enhances its stability.

[0155] The above configuration better ensures the stability of the gating control node N11, improves the leakage problem of the gating unit in the shift register, and thus solves the problem of bright lines caused by the random boundary position of high frequency to low frequency in the display area.

[0156] As shown in Figures 6, 16, 23, 29, and 38, in some embodiments, the length of the channel portion of the second gating control transistor T22 is x1 times the length of the channel portion of the first gating control transistor T23, where x1 satisfies: 1.5 ≤ x1 ≤ 2.5; and / or, the length of the channel portion of the third gating control transistor T27 is x2 times the length of the channel portion of the first gating control transistor T23, where x2 satisfies: 1.5 ≤ x2 ≤ 3.

[0157] For example, x1 can take the values ​​1.5, 1.6, 1.7, 1.8, 1.9, 2.0, 2.1, 2.2, 2.3, 2.4, and 2.5, but is not limited to these.

[0158] For example, x2 can take the following values: 1.5, 1.6, 1.7, 1.8, 1.9, 2.0, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3.0, but is not limited to these.

[0159] The above configuration enables the second gating control transistor T22 and the third gating control transistor T27 to have better stability, effectively preventing leakage of the second gating control transistor T22 and the third gating control transistor T27, thereby better ensuring the potential stability of the gating control node N11, and thus solving the problem of bright lines generated at the random boundary position of high frequency to low frequency switching in the display area.

[0160] In some embodiments, the orthographic projection of the channel portion in the second gating control transistor T22 and / or the third gating control transistor T27 onto the substrate adopts one of a zigzag structure, an L-shaped structure, and an S-shaped structure.

[0161] The above configuration can effectively extend the length of the channel portion of the second selection control transistor T22 and / or the third selection control transistor T27, thereby better improving the leakage current phenomenon of the second selection control transistor T22 and / or the third selection control transistor T27 and enhancing the potential stability of the selection control node N11.

[0162] In some embodiments, the width W1 of the channel portion of the first gating control transistor T23 satisfies: 3μm≤W1≤4μm, and the length L1 of the channel portion of the first gating control transistor T23 satisfies: 5μm<L1≤10μm.

[0163] For example, the width W1 of the channel portion of the first gating control transistor T23 can take values ​​of 3μm, 3.1μm, 3.2μm, 3.3μm, 3.4μm, 3.5μm, 3.6μm, 3.7μm, 3.8μm, 3.9μm, and 4μm, but is not limited to these values.

[0164] For example, the length L1 of the channel portion of the first gating control transistor T23 can take values ​​of 5.1μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, 9.5μm, and 10μm, but is not limited to these.

[0165] The above configuration increases the length of the channel portion of the first control transistor to 2 to 3 times its original length.

[0166] The above configuration allows the channel portion of the first gating control transistor T23 to have a longer length, thereby better improving the leakage current phenomenon of the first gating control transistor T23 and enhancing the potential stability of the gating control node N11.

[0167] In some embodiments, the width W2 of the channel portion of the second gating control transistor T22 satisfies: 3μm≤W2≤4μm, and the length L2 of the channel portion of the second gating control transistor T22 satisfies: 5μm<L2≤13μm.

[0168] For example, the width W2 of the channel portion of the second gating control transistor T22 can take values ​​of 3μm, 3.1μm, 3.2μm, 3.3μm, 3.4μm, 3.5μm, 3.6μm, 3.7μm, 3.8μm, 3.9μm, and 4μm, but is not limited to these.

[0169] For example, the length L2 of the channel portion of the second gating control transistor T22 can take values ​​of: 5.1μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, 9.5μm, 10μm, 10.5μm, 11μm, 11.5μm, 12μm, 12.5μm, 13μm, but is not limited to these.

[0170] The above configuration increases the length of the channel portion of the second control transistor to 2 to 3 times its original length.

[0171] The above configuration allows the channel portion of the second selection control transistor T22 to have a longer length, thereby better improving the leakage current phenomenon of the second selection control transistor T22 and enhancing the potential stability of the selection control node N11.

[0172] As shown in Figures 4 to 13, in some embodiments, the selection unit further includes a voltage regulator capacitor C8, the first plate C81 of the voltage regulator capacitor C8 is coupled to the first terminal of the second selection control transistor T22, and the second plate C82 of the voltage regulator capacitor C8 is coupled to the second level signal line.

[0173] For example, the second level signal transmitted by the second level signal line is a high-level power signal, but it is not limited to this.

[0174] The above configuration allows the voltage-stabilizing capacitor C8 to act as a coupling capacitor between the first terminal of the second gating control transistor T22 and the second level signal line, thus stabilizing the potential of the first terminal of the second gating control transistor T22. Therefore, when the signal transmitted by the gating control line transitions from low to high, even if the first gating control transistor T23 leaks, the voltage-stabilizing capacitor C8 can still provide some voltage stabilization for the first terminal of the second gating control transistor T22, further preventing leakage and protecting it, and further stabilizing the potential of the gating control node N11.

[0175] As shown in Figures 4 to 13, in some embodiments, the display panel includes an active layer, a first gate metal layer and a second gate metal layer sequentially stacked on the substrate along a direction away from the substrate; the first electrode C81 of the voltage regulator capacitor C8 is disposed in the same layer and with the same material as the active layer, and the second electrode C82 of the voltage regulator capacitor C8 is disposed in the same layer and with the same material as the second gate metal layer.

[0176] For example, the display panel includes an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, an anode layer, a light-emitting material layer, a cathode layer, and an encapsulation layer, etc., sequentially stacked along a direction away from the substrate. It is worth noting that the display panel may further include a passivation layer, which is located between the first source / drain metal layer and the first planarization layer.

[0177] The above-mentioned configuration of the first electrode C81 of the voltage regulator capacitor C8 being made of the same material and layer as the active layer, and the second electrode C82 of the voltage regulator capacitor C8 being made of the same material and layer as the second gate metal layer, allows the first electrode C81 and the active layer of the voltage regulator capacitor C8 to be formed simultaneously in the same patterning process, and the second electrode C82 and the second gate metal layer of the voltage regulator capacitor C8 to be formed simultaneously in the same patterning process. This avoids the need for additional patterning processes to manufacture the voltage regulator capacitor C8, effectively simplifying the manufacturing process of the display panel and reducing manufacturing costs.

[0178] As shown in Figures 4 to 13, in some embodiments, the first plate C81 of the voltage regulator capacitor C8, the second electrode of the first gate control transistor T23, and the first electrode of the second gate control transistor T22 are formed into an integral structure.

[0179] The selection unit further includes a first output transistor T19 and a fourth capacitor C4. The gate of the first output transistor T19 is coupled to the first output control node N12, the first terminal of the first output transistor T19 is coupled to the second level signal line, and the second terminal of the first output transistor T19 is coupled to the gate drive signal output terminal. The first plate of the fourth capacitor C4 is coupled to the first output control node N12, and the second plate of the fourth capacitor C4 is coupled to the second level signal line. The second plate C82 of the voltage regulator capacitor C8 and the second plate of the fourth capacitor C4 are formed as an integral structure.

[0180] For example, the first output transistor T19 is used to control whether to conduct the electrical connection between the second level signal line and the gate drive signal output terminal under the control of the first output control node N12, thereby controlling whether the gate drive signal output terminal outputs a high-level signal.

[0181] The first plate C81 of the voltage regulator capacitor C8 is integrated with the second terminal of the first gate control transistor T23 and the first terminal of the second gate control transistor T22, so that the first plate C81 of the voltage regulator capacitor C8 is directly coupled with the second terminal of the first gate control transistor T23 and the first terminal of the second gate control transistor T22. No additional adapter structure is needed, which helps to simplify the layout structure of the shift register and reduce the layout difficulty of the shift register.

[0182] The second plate C82 of the voltage regulator capacitor C8 and the second plate of the fourth capacitor C4 are integrated into one structure, so that the second plate C82 of the voltage regulator capacitor C8 can receive the second level signal transmitted by the second level signal line through the second plate of the adjacent fourth capacitor C4, without having to set up an additional structure to realize the electrical connection between the second plate C82 of the voltage regulator capacitor C8 and the second level signal line. This helps to simplify the layout structure of the shift register and reduce the layout difficulty of the shift register.

[0183] As shown in Figures 4 to 13, in some embodiments, the orthographic projection of the first gating control transistor T23 on the substrate, the orthographic projection of the voltage regulator capacitor C8 on the substrate, and the orthographic projection of the second gating control transistor T22 on the substrate are arranged sequentially along a first direction.

[0184] The first plate C81 of the voltage regulator capacitor C8 extends along the second direction, and the second plate C82 of the voltage regulator capacitor C8 extends along the second direction, which intersects with the first direction.

[0185] For example, the orthographic projection of the channel portion of the first gate control transistor T23 on the substrate, the orthographic projection of the voltage regulator capacitor C8 on the substrate, and the orthographic projection of the channel portion of the second gate control transistor T22 on the substrate are arranged sequentially along a first direction.

[0186] The above configuration can maximize the use of the original layout space along the second direction between the first selection control transistor T23 and the second selection control transistor T22 while minimizing the use of the layout space along the first direction between the first selection control transistor T23 and the second selection control transistor T22. This helps to reduce the width of the layout space occupied by the shift register as a whole along the first direction.

[0187] More specifically, as shown in Figure 2, the shift register provided in the above embodiment adopts the following structure:

[0188] The shift register specifically includes:

[0189] The first transistor T1 has its gate coupled to the first clock signal line CK, its first terminal coupled to the frame start signal line STV, and its second terminal coupled to the first node N1.

[0190] The second transistor T2 has its gate coupled to the first node N1, its first terminal coupled to the first clock signal line CK, and its second terminal coupled to the second node N2.

[0191] The third transistor T3 has its gate coupled to the first clock signal line CK, its first terminal coupled to the second first level signal line VGL2, and its second terminal coupled to the second node N2.

[0192] The fourth transistor T4 has its gate coupled to the ninth node N9, its first terminal coupled to the second clock signal line CB, and its second terminal coupled to the fifth node N5.

[0193] The fifth transistor T5 has its gate coupled to the second node N2, its first terminal coupled to the first second-level signal line VGH-N1, and its second terminal coupled to the fifth node N5.

[0194] The sixth transistor T6 has its gate coupled to the sixth node N6, its first terminal coupled to the second clock signal line CB, and its second terminal coupled to the third node N3.

[0195] The seventh transistor T7 has its gate coupled to the second clock signal line CB, its first terminal coupled to the third node N3, and its second terminal coupled to the second cascaded control node N4.

[0196] The eighth transistor T8 has its gate coupled to the first node N1, its first terminal coupled to the first second-level signal line VGH-N1, and its second terminal coupled to the second cascaded control node N4.

[0197] The second cascaded control transistor T9 has its gate coupled to the second cascaded control node N4, its first terminal coupled to the first second-level signal line VGH-N1, and its second terminal coupled to the cascaded signal output terminal Scan(n).

[0198] The first cascaded control transistor T10 has its gate coupled to the first cascaded control node N7, its first terminal coupled to the second first level signal line VGL2, and its second terminal coupled to the cascaded signal output terminal Scan(n).

[0199] The eleventh transistor T11 has its gate coupled to the second first-level signal line VGL2, its first terminal coupled to the second node N2, and its second terminal coupled to the sixth node N6.

[0200] The twelfth transistor T12 has its gate coupled to the second first level signal line VGL2, its first terminal coupled to the first node N1, and its second terminal coupled to the first cascaded control node N7.

[0201] The thirteenth transistor T13 has its gate coupled to the initialization control line NCX, its first terminal coupled to the first second-level signal line VGH-N1, and its second terminal coupled to the first node N1.

[0202] The fourteenth transistor T14 has its gate coupled to the first clock signal line CK, its first terminal coupled to the frame start signal line STV, and its second terminal coupled to the eighth node N8.

[0203] The fifteenth transistor T15 has its gate coupled to the second first-level signal line VGL2, its first terminal coupled to the eighth node N8, and its second terminal coupled to the ninth node N9.

[0204] The sixteenth transistor T16 has its gate coupled to the ninth node N9, its first terminal coupled to the first cascaded control node N7, and its second terminal coupled to the ninth node N9.

[0205] The seventeenth transistor T17 has its gate coupled to the ninth node N9, its first terminal coupled to the ninth node N9, and its second terminal coupled to the second output control node N13.

[0206] The eighteenth transistor T18 has its gate coupled to the gating control node N11, its first terminal coupled to the first node N1, and its second terminal coupled to the second output control node N13.

[0207] The first output transistor T19 has its gate coupled to the first output control node N12, its first terminal coupled to the second second-level signal line VGH-N2 or the third second-level signal line VGH-N3, and its second terminal coupled to the gate drive signal output terminal Nout(n).

[0208] The second output transistor T20 has its gate coupled to the thirteenth transistor N13, its first terminal coupled to the third first-level signal line VGL3, and its second terminal coupled to the gate drive signal output terminal Nout(n).

[0209] The third node control transistor T21 is a dual-gate transistor. The gate of the third node control transistor T21 is coupled to the gating control node N11, the first terminal of the third node control transistor T21 is coupled to the second cascaded control node N4, and the second terminal of the third node control transistor T21 is coupled to the first output control node N12.

[0210] The second gating control transistor T22 has its gate coupled to Scan(n-1), the cascaded signal output terminal of the adjacent previous stage shift register, its first terminal coupled to the tenth node N10, and its second terminal coupled to the gating control node N11.

[0211] The first gating control transistor T23 has its gate coupled to the third node N3(n-2) of the adjacent two-stage shift register, its first terminal coupled to the gating signal line MS, and its second terminal coupled to the tenth node N10.

[0212] The first node control transistor T24 has its gate coupled to the second output control node N13, its first terminal coupled to the first second level signal line VGH-N1, and its second terminal coupled to the fourteenth node N14.

[0213] The gate of the 25th transistor T25 is coupled to the fifth node N5(n-1) of the adjacent previous stage shift register, the first terminal of the 25th transistor T25 is coupled to the second first level signal line VGL2, and the second terminal of the 25th transistor T25 is coupled to the gating control node N11.

[0214] The second node control transistor T26 has its gate coupled to the gate drive signal output terminal Nout(n), its first terminal coupled to the fourteenth node N14, and its second terminal coupled to the first output control node N12.

[0215] The first capacitor C1 has its first plate coupled to the sixth node N6, and its second plate coupled to the third node N3.

[0216] The second capacitor C2 has its first plate coupled to the second cascaded control node N4, and its second plate coupled to the first second-level signal line VGH-N1.

[0217] The third capacitor C3 has its first plate coupled to the fifth node N5 and its second plate coupled to the ninth node N9.

[0218] The fourth capacitor C4 has its first plate coupled to the first output control node N12, and its second plate coupled to either the second second-level signal line VGH-N2 or the third second-level signal line VGH-N3.

[0219] The fifth capacitor C5 has its first plate coupled to the gating control node N11 and its second plate coupled to the first output control node N12.

[0220] The sixth capacitor C6 has its first plate coupled to the second output control node N13, and its second plate coupled to the gate drive signal output terminal Nout(n).

[0221] The seventh capacitor C7 has its first plate coupled to the cascaded signal output terminal Scan(n) of the current stage shift register, and its second plate connected to the third first level signal line VGL3.

[0222] As shown in Figure 3, the shift register also includes a third gating control transistor T27. The gate of the third gating control transistor T27 is coupled to the cascade signal output terminal Scan(n) of the current stage shift register. The first terminal of the third gating control transistor T27 is coupled to the fifteenth node, and the second terminal of the third gating control transistor T27 is coupled to the gating control node N11.

[0223] As shown in Figure 4, Figure 4 also illustrates the first active pattern 41 included in the first transistor T1, the second active pattern 42 included in the second transistor T2, the third active pattern 43 included in the third transistor T3, the fourth active pattern 44 included in the fourth transistor T4, the fifth active pattern 45 included in the fifth transistor T5, the sixth active pattern 46 included in the sixth transistor T6, the seventh active pattern 47 included in the seventh transistor T7, the eighth active pattern 48 included in the eighth transistor T8, the ninth active pattern 49 included in the second cascaded control transistor T9, the tenth active pattern 410 included in the first cascaded control transistor T10, the eleventh active pattern 411 included in the eleventh transistor T11, the twelfth active pattern 412 included in the twelfth transistor T12, the thirteenth active pattern 413 included in the thirteenth transistor T13, and the fourteenth active pattern 413 included in the fourteenth transistor T14. 14. The fifteenth transistor T15 includes the fifteenth active pattern 415, the sixteenth transistor T16 includes the sixteenth active pattern 416, the seventeenth transistor T17 includes the seventeenth active pattern 417, the eighteenth transistor T18 includes the eighteenth active pattern 418, the first output transistor T19 includes the nineteenth active pattern 419, the second output transistor T20 includes the twentieth active pattern 420, the third node control transistor T21 includes the twenty-first active pattern 421, the second gating control transistor T22 includes the twenty-second active pattern 422, the first gating control transistor T23 includes the twenty-third active pattern 423, the first node control transistor T24 includes the twenty-fourth active pattern 424, the twenty-fifth transistor T25 includes the twenty-fifth active pattern 425, and the second node control transistor T26 includes the twenty-sixth active pattern 426.

[0224] Figure 27 illustrates the twenty-seventh active pattern 427 included in the third gating control transistor T27.

[0225] As shown in Figure 5, the gates of the transistors included in Figure 2 are also illustrated. Specifically, the gate 22g of the second selection control transistor T22 and the gate 23g of the first selection control transistor T23 are marked. The first plate C11 of the first capacitor C1, the first plate C21 of the second capacitor C2, the first plate C31 of the third capacitor C3, the first plate C41 of the fourth capacitor C4, the first plate C51 of the fifth capacitor C5, the first plate C61 of the sixth capacitor C6, and the first plate C71 of the seventh capacitor C7 are also illustrated.

[0226] As shown in Figure 8, the gates of the transistors included in Figure 3 are also illustrated in Figure 8. Specifically, the gate 9g of the second cascade control transistor T9, the gate 10g of the first cascade control transistor T10, the gate 19g of the first output transistor T19, the gate 20g of the second output transistor T20, the gate 21g of the third node control transistor T21, the gate 22g of the second gating control transistor T22, the gate 23g of the first gating control transistor T23, the gate 24g of the first node control transistor T24, the gate 26g of the second node control transistor T26, and the gate 27g of the third gating control transistor T27 are marked.

[0227] As shown in Figure 7, the second plate C12 of the first capacitor C1, the second plate C22 of the second capacitor C2, the second plate C32 of the third capacitor C3, the second plate C42 of the fourth capacitor C4, the second plate C52 of the fifth capacitor C5, the second plate C62 of the sixth capacitor C6, and the second plate C72 of the seventh capacitor C7 are also shown in Figure 7.

[0228] As shown in Figures 2 and 4-13, the connection relationship between each conductive connection and each via is explained in detail below.

[0229] The first conductive connection portion 51 is coupled to the first terminal of the fourteenth transistor T14 through the first via a1, and the first conductive connection portion 51 is coupled to the first terminal of the first transistor T1 through the second via a2. The first conductive connection portion 51 in the current stage shift register is coupled to the fifteenth conductive connection portion 515 in the adjacent previous stage shift register.

[0230] The second conductive connection portion 52 is coupled to the gate of the twenty-fifth transistor T25 through the twenty-tenth via a20. The second conductive connection portion 52 is also coupled to the tenth conductive connection portion 510 in the adjacent previous stage shift register.

[0231] The third conductive connection portion 53 is coupled to the second terminal of the first transistor T1 through the third via a3, and the third conductive connection portion 53 is coupled to the gate of the second transistor T2 through the fourth via a4.

[0232] The fourth conductive connection portion 54 is coupled to the second terminal of the fourteenth transistor T14 through the fifth via a5, and the fourth conductive connection portion 54 is coupled to the first terminal of the fifteenth transistor T15 through the sixth via a6.

[0233] The fifth conductive connection portion 55 is coupled to the second terminal of the third transistor T3 through the seventh via a7, the fifth conductive connection portion 55 is coupled to the second terminal of the second transistor T2 through the eighth via a8, and the fifth conductive connection portion 55 is coupled to the gate of the fifth transistor T5 through the ninth via a9.

[0234] The sixth conductive connection portion 56 is coupled to the first terminal of the third transistor T3 through the tenth via a10, the sixth conductive connection portion 56 is coupled to the gate of the fifteenth transistor T15 and the gate of the eleventh transistor T11 through the eleventh via a11, the sixth conductive connection portion 56 is coupled to the gate of the twelfth transistor T12 through the twelfth via a12, and the sixth conductive connection portion 56 is coupled to the second first level signal line VGL2 through the eighty-third via a83.

[0235] The seventh conductive connection portion 57 is coupled to the second terminal of the eleventh transistor T11 through the fourteenth via a14, and the seventh conductive connection portion 57 is coupled to the gate of the sixth transistor T6 through the fifteenth via a15.

[0236] The eighth conductive connection part 58 is coupled to the second plate C32 of the third capacitor C3 through the twenty-third through hole a23, and the eighth conductive connection part 58 is coupled to the second electrode of the fifth transistor T5 through the twenty-fourth through hole a24.

[0237] The ninth conductive connection portion 59 is coupled to the second electrode of the fifteenth transistor T15 through the sixteenth via a16, and the ninth conductive connection portion 59 is coupled to the first electrode C31 of the third capacitor C3 through the seventeenth via a17. The first electrode C31 of the third capacitor C3 and the gate of the fourth transistor T4 are formed as an integral structure.

[0238] The tenth conductive connection part 510 is coupled to the second plate C32 of the third capacitor C3 through the eighteenth through hole a18, and the tenth conductive connection part 510 is coupled to the second electrode of the fourth transistor T4 through the nineteenth through hole a19.

[0239] The eleventh conductive connection part 511 is coupled to the first terminal of the fourth transistor T4 through the twenty-first via a21, and the eleventh conductive connection part 511 is coupled to the second clock signal line CB through the eighty-sixth via a86.

[0240] The twelfth conductive connection part 512 is coupled to the first pole of the twenty-fifth transistor T25 through the twenty-second via a22, and the twelfth conductive connection part 512 is coupled to the second first level signal line VGL2 through the eighty-seventh via a87.

[0241] The thirteenth conductive connection portion 513 is coupled to the gate of the sixteenth transistor T16 and the gate of the seventeenth transistor T17 through the twenty-fifth via a25. The gates of the sixteenth transistor T16 and the seventeenth transistor T17 are formed as an integral structure with the first plate C31 of the third capacitor C3. The thirteenth conductive connection portion 513 is coupled to the second electrode of the sixteenth transistor T16 through the twenty-sixth via a26.

[0242] The fourteenth conductive connection portion 514 is coupled to the second terminal of the twenty-fifth transistor T25 through the twenty-seventh via a27, and the fourteenth conductive connection portion 514 is coupled to the gate of the eighteenth transistor T18 through the twenty-eighth via a28.

[0243] The fifteenth conductive connection part 515 is coupled to the first plate C71 of the seventh capacitor C7 through the thirty-ninth through hole a39, and the fifteenth conductive connection part 515 is integrated with the twenty-first conductive connection part 521 through the thirty-ninth through hole a39.

[0244] The sixteenth conductive connection part 516 is coupled to the first pole of the fifth transistor T5 through the thirteenth via a13, and the sixteenth conductive connection part 516 is coupled to the first second level signal line VGH-N1 through the eighty-fifth via a85.

[0245] The seventeenth conductive connection portion 517 is coupled to the first terminal of the sixteenth transistor T16 through the thirty-fifth via a35, and the seventeenth conductive connection portion 517 is coupled to the gate of the first cascaded control transistor T10 through the thirty-sixth via a36.

[0246] The eighteenth conductive connection portion 518 is coupled to the second terminal of the seventeenth transistor T17 through the thirty-second via a32, the eighteenth conductive connection portion 518 is coupled to the second terminal of the eighteenth transistor T18 through the thirty-third via a33, and the eighteenth conductive connection portion 518 is coupled to the forty-sixth conductive connection portion 546 through the thirty-fourth via a34.

[0247] The nineteenth conductive connection portion 519 is coupled to the gate of the eighth transistor T8 through the twenty-ninth via a29, the nineteenth conductive connection portion 519 is coupled to the first terminal of the twelfth transistor T12 through the thirtieth via a30, and the nineteenth conductive connection portion 519 is coupled to the first terminal of the eighteenth transistor T18 through the thirty-first via a31.

[0248] The twentieth conductive connection portion 520 is coupled to the gate of the thirteenth transistor T13 through the fifty-fifth via a55, and the twentieth conductive connection portion 520 is coupled to the initialization control line NCX through the eighty-fourth via a84.

[0249] The 21st conductive connection portion 521 is coupled to the second electrode of the first cascaded control transistor T10 through the 70th through-hole a70.

[0250] The 22nd conductive connection portion 522 is coupled to the first pole of the first cascaded control transistor T10 through the 71st via a71, and the 22nd conductive connection portion 522 is coupled to the second first level signal line VGL2 through the 88th via a88 and the 89th via a89.

[0251] The 23rd conductive connection portion 523 is coupled to the 46th conductive connection portion 546 through the 37th via a37, and the 23rd conductive connection portion 523 is coupled to the gate of the 24th transistor through the 38th via a38.

[0252] The 24th conductive connection part 524 is coupled to the second end of the seventh capacitor C7 through the 73rd via a73, and the 98th via a98 of the 24th conductive connection part 524 is coupled to the third first level signal line VGL3.

[0253] The 25th conductive connection portion 525 is coupled to the first terminal of the first node control transistor T24 through the 72nd via a72. The 25th conductive connection portion 525 is coupled to the first second level signal line VGH-N1 through the 91st via a91.

[0254] The 26th conductive connection portion 526 is coupled to the first terminal of the second transistor T2 through the 41st via a41, the 26th conductive connection portion 526 is coupled to the gate of the first transistor T1 through the 42nd via a42, and the 26th conductive connection portion 526 is coupled to the first clock signal line CK through the 80th via a80.

[0255] The 27th conductive connection portion 527 is coupled to the gate of the 7th transistor T7 through the 47th via a47, and the 27th conductive connection portion 527 is coupled to the second clock signal line CB through the 79th via a79.

[0256] The 28th conductive connection portion 528 is coupled to the second electrode of the sixth transistor T6 through the 43rd via a43, the 28th conductive connection portion 528 is coupled to the second plate of the third capacitor C3 through the 44th via a44, the 28th conductive connection portion 528 is coupled to the first electrode of the seventh transistor T7 through the 45th via a45, and the 28th conductive connection portion 528 is coupled to the 47th conductive connection portion 547 through the 46th via a46.

[0257] The 29th conductive connection portion 529 is coupled to the first terminal of the sixth transistor T6 through the 51st via a51, and the 29th conductive connection portion 529 is coupled to the gate of the seventh transistor T7 through the 52nd via a52.

[0258] The thirtieth conductive connection portion 530 is coupled to the second electrode of the eighth transistor T8 through the forty-seventh via a47, the thirtieth conductive connection portion 530 is coupled to the gate of the second cascaded control transistor T9 through the forty-ninth via a49, the thirtieth conductive connection portion 530 is coupled to the second electrode of the seventh transistor T7 through the forty-eighth via a48, and the thirtieth conductive connection portion 530 is coupled to the first plate of the second capacitor C2 through the fiftieth via a50.

[0259] The thirty-first conductive connection part 531 is coupled to the first terminal of the eighth transistor T8 and the first terminal of the thirteenth transistor T13 through the fifty-third via a53. The thirty-first conductive connection part 531 is coupled to the first terminal of the second cascaded control transistor T9 through the fifty-fourth via a54. The thirty-first conductive connection part 531 is coupled to the first second level signal line VGH-N1 through the eighty-second via a82.

[0260] The thirty-second conductive connection 532 is coupled to the gate of the second selection control transistor T22 through the fifty-ninth via a59, and the thirty-second conductive connection 532 is coupled to the fifteenth conductive connection 515 in the adjacent previous stage shift register.

[0261] The thirty-third conductive connection part 533 is coupled to the second plate of the second capacitor C2 through the fifty-sixth via a56, and the thirty-third conductive connection part 533 is coupled to the first second level signal line VGH-N1 through the eighty-first via a81.

[0262] The thirty-fourth conductive connection 534 is coupled to the forty-seventh conductive connection 547 through the fifty-seventh through-hole a57, and the thirty-fourth conductive connection 534 is coupled to the forty-eighth conductive connection 548 through the ninetieth through-hole a90.

[0263] The thirty-fifth conductive connection 535 is coupled to the gate of the first selection control transistor T23 through the fifty-eighth via a58, and the thirty-fifth conductive connection 535 is coupled to the forty-fifth conductive connection 545 through the ninety-second via a92. The forty-fifth conductive connection 545 is coupled to the forty-eighth conductive connection 548 in the adjacent upper two-stage shift register.

[0264] The thirty-sixth conductive connection portion 536 is coupled to the first pole of the first selection control transistor T23 through the sixtieth via a60, and the thirty-sixth conductive connection portion 536 is coupled to the selection signal line MS through the ninety-third via a93.

[0265] The thirty-seventh conductive connection portion 537 is coupled to the second terminal of the second gate control transistor T22 through the sixty-first via a61, and the thirty-seventh conductive connection portion 537 is coupled to the gate of the third node control transistor T21 through the sixty-second via a62.

[0266] The thirty-eighth conductive connection portion 538 is coupled to the first terminal of the third node control transistor T21 through the sixty-fourth via a64, and the thirty-eighth conductive connection portion 538 is coupled to the gate of the second cascaded control transistor T9 through the sixty-fifth via a65.

[0267] The thirty-ninth conductive connection portion 539 is coupled to the gate of the first output transistor T19 through the sixty-sixth via a66. The gate of the first output transistor T19 is coupled to the first plate C41 of the fourth capacitor C4. The thirty-ninth conductive connection portion 539 is coupled to the second plate of the third node control transistor T21 through the sixty-seventh via a67. The thirty-ninth conductive connection portion 539 is coupled to the second plate of the fifth capacitor C5 through the sixty-eighth via a68 and the sixty-ninth via a69.

[0268] The fortieth conductive connection portion 540 is coupled to the second terminal of the first output transistor T19 through the seventy-fifth via a75.

[0269] The forty-first conductive connection portion 541 is coupled to the second terminal of the second output transistor T20 through the seventy-sixth via a76. The forty-first conductive connection portion 541 is coupled to the gate of the second node control transistor T26 through the seventy-fourth via a74.

[0270] The forty-second conductive connection portion 542 is coupled to the first terminal of the first output transistor T19 through the seventy-seventh via a77, and is coupled to the second plate C42 of the fourth capacitor C4 through the sixty-third via a63. The forty-second conductive connection portion 542 is coupled to the third second-level signal line VGH-N3 through the ninety-fourth via a94 and the ninety-fifth via a95.

[0271] The forty-third conductive connection portion 543 is coupled to the first terminal of the second output transistor T20 through the seventy-eighth via a78. The forty-third conductive connection portion 543 is also coupled to the third first-level signal line VGL3 through the ninety-sixth via a96 and the ninety-seventh via a97.

[0272] This disclosure also provides a display device, including the display panel provided in the above embodiments.

[0273] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0274] In the display panel provided by the above embodiments, by connecting the first and second gating control transistors in series between the gating control line and the gating control node, the first and second gating control transistors can control whether to conduct the electrical connection between the gating control line and the gating control node, thereby controlling the potential of the gating control node. Simultaneously, the length of the channel portion of the second gating control transistor is set to be greater than the length of the channel portion of the first gating control transistor, resulting in a longer channel portion for the second gating control transistor coupled to the gating control node. This improves the stability of the second gating control transistor, reduces leakage current, and ensures the stability of the gating control node. Therefore, the display panel provided by the above embodiments improves the leakage current problem of the gating unit in the shift register, thereby solving the problem of bright lines generated at random boundary positions where high frequencies are switched to low frequencies in the display area. When the display area of ​​the display panel is divided into multiple display areas with different refresh rates, a good display effect can be guaranteed.

[0275] Therefore, the display device provided in this embodiment of the present disclosure, when including the above-described display panel, also has the above-described beneficial effects, which will not be repeated here.

[0276] It should be noted that "the structure extends in a certain direction" means that the structure includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends in a certain direction, and the length of the main part extending in a certain direction is greater than the length of the secondary part extending in other directions.

[0277] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0278] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0279] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0280] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0281] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0282] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0283] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising a substrate, and a gate driving circuit and a gating control line disposed on the substrate, wherein the gate driving circuit includes a plurality of cascaded shift registers, and the shift registers include gating units; The gating unit includes: A first gating control transistor, a second gating control transistor, and a gating control node, wherein the gating control node is used to control whether the gate drive signal output terminal of its corresponding shift register outputs an effective level; the first terminal of the first gating control transistor is coupled to the gating control line, the second terminal of the first gating control transistor is coupled to the first terminal of the second gating control transistor, and the second terminal of the second gating control transistor is coupled to the gating control node; The length of the channel portion of the second gating control transistor is greater than the length of the channel portion of the first gating control transistor.

2. The display panel according to claim 1, wherein, The shift register further includes a first cascaded control transistor, the gate of which is coupled to a first cascaded control node, the first terminal of which is coupled to a first level signal line, and the second terminal of which is coupled to a cascaded signal output terminal. The gating unit further includes a first node control transistor, a second node control transistor, and a fifth capacitor. The first terminal of the first node control transistor is coupled to a second level signal line, the second terminal of the first node control transistor is coupled to the first terminal of the second node control transistor, and the second terminal of the second node control transistor is coupled to a first output control node. The gating control node is used to control the potential of the first output control node, and the first output control node is used to control whether the gate drive signal output terminal of its corresponding shift register outputs an effective level. The first plate of the fifth capacitor is coupled to the gating control node, and the second plate of the fifth capacitor is coupled to the first output control node. The first portion of the orthogonal projection of the fifth capacitor onto the substrate is located between the orthogonal projection of the first node control transistor onto the substrate and the orthogonal projection of the first cascaded control transistor onto the substrate. The second portion of the orthogonal projection of the fifth capacitor onto the substrate is located at the orthogonal projection of the second node control transistor onto the substrate and the first cascaded control transistor onto the substrate. Between the orthographic projections on the substrate.

3. The display panel according to claim 2, wherein, The selection unit further includes a second output transistor and a sixth capacitor; the gate of the second output transistor is coupled to a second output control node, the first terminal of the second output transistor is coupled to a first level signal line, and the second terminal of the second output transistor is coupled to a gate drive signal output terminal; the first plate of the sixth capacitor is coupled to the gate of the second output transistor, and the second plate of the sixth capacitor is coupled to the gate drive signal output terminal. At least a portion of the orthographic projection of the fifth capacitor onto the substrate is located between the orthographic projection of the sixth capacitor onto the substrate and the orthographic projection of the first cascaded control transistor onto the substrate.

4. The display panel according to claim 2, wherein, The shift register further includes a second cascaded control transistor and a second capacitor; the gate of the second cascaded control transistor is coupled to a second cascaded control node, the first terminal of the second cascaded control transistor is coupled to a second level signal line, and the second terminal of the second cascaded control transistor is coupled to the cascaded signal output terminal; the first plate of the second capacitor is coupled to the gate of the second cascaded control transistor, and the second plate of the second capacitor is coupled to the second level signal line. The gate of the first cascaded control transistor has a first distance between its orthographic projection on the substrate and the display area of ​​the display panel, and the second plate of the second capacitor has a second distance between its orthographic projection on the substrate and the display area, wherein the first distance is greater than the second distance. The orthogonal projection of the fifth capacitor on the substrate is located on the side of the orthogonal projection of the gate of the first cascaded control transistor on the substrate that is closer to the display area.

5. The display panel according to claim 4, wherein, The gating unit further includes: a third gating control transistor, the gate of which is coupled to a cascaded signal output terminal, the first terminal of which is coupled to the second terminal of the second gating control transistor, and the second terminal of which is coupled to the gating control node.

6. The display panel according to claim 5, wherein, At least a portion of the orthographic projection of the third gating control transistor on the substrate is located between the orthographic projection of the second gating control transistor on the substrate and the orthographic projection of the fifth capacitor on the substrate.

7. The display panel according to claim 5, wherein, The channel portions of the first and second selection control transistors are arranged along a first direction; the channel portion of the third selection control transistor is offset from the channel portion of the second selection control transistor along the first direction.

8. The display panel according to claim 5, wherein, The shift register further includes a third node control transistor, the gate of which is coupled to the gating control node, the first terminal of which is coupled to the second cascaded control node, and the second terminal of which is coupled to the first output control node. At least a portion of the orthographic projection of the third gating control transistor on the substrate is located between the orthographic projection of the first cascade control transistor on the substrate and the orthographic projection of the third node control transistor on the substrate.

9. The display panel according to claim 8, wherein, The gate of the second cascaded control transistor is coupled to the first terminal of the third node control transistor through a first connection portion; the first portion of the orthographic projection of the first connection portion on the substrate is located between the orthographic projection of the gate of the second gate control transistor on the substrate and the orthographic projection of the gate of the third gate control transistor on the substrate.

10. The display panel according to claim 9, wherein, The second portion of the orthographic projection of the first connection portion onto the substrate is located between the orthographic projection of the gate of the second gate control transistor onto the substrate and the orthographic projection of the gate of the third node control transistor onto the substrate.

11. The display panel according to claim 8, wherein, The gating unit includes a second connection portion, which is coupled to the first plate of the fifth capacitor, the second electrode of the third gating control transistor, and the gate of the third node control transistor.

12. The display panel according to claim 11, wherein, The second connection portion includes a first sub-part and a second sub-part coupled together; the first sub-part includes at least a portion extending along a second direction, and the first sub-part is coupled to the first plate of the fifth capacitor and the second electrode of the third gate control transistor respectively; the second sub-part includes at least a portion extending along a third direction, and the second sub-part is coupled to the gate of the third node control transistor, the third direction intersecting the second direction.

13. The display panel according to claim 8, wherein, The gating unit includes a third connection portion, which includes a third sub-part, a fourth sub-part, and a fifth sub-part coupled in sequence; the third sub-part is coupled to the second plate of the fifth capacitor, the first end of the fifth sub-part coupled to the fourth sub-part is coupled to the second electrode of the third node control transistor, and the second end of the fifth sub-part away from the fourth sub-part is coupled to the first output control node; the fourth sub-part includes at least a portion extending in a third direction.

14. The display panel according to claim 5, wherein, The first gating control transistor adopts a dual-gate transistor structure; and / or, the second gating control transistor adopts a dual-gate transistor structure; and / or, the third gating control transistor adopts a dual-gate transistor structure.

15. The display panel according to claim 5, wherein, The length of the channel portion of the second gate control transistor is x1 times the length of the channel portion of the first gate control transistor, where x1 satisfies: 1.5 ≤ x1 ≤ 2.5; and / or, the length of the channel portion of the third gate control transistor is x2 times the length of the channel portion of the first gate control transistor, where x2 satisfies: 1.5 ≤ x2 ≤ 3.

16. The display panel according to claim 5, wherein, The orthographic projection of the channel portion of the second and / or third gate control transistor onto the substrate adopts one of the following structures: a zigzag structure, an L-shaped structure, and an S-shaped structure.

17. The display panel according to any one of claims 1 to 16, wherein, The width W1 of the channel portion of the first gating control transistor satisfies: 3μm ≤ W1 ≤ 4μm, and the length L1 of the channel portion of the first gating control transistor satisfies: 5μm < L1 ≤ 10μm; and / or, The width W2 of the channel portion of the second gating control transistor satisfies: 3μm≤W2≤4μm, and the length L2 of the channel portion of the second gating control transistor satisfies: 5μm<L2≤13μm.

18. The display panel according to any one of claims 1 to 16, wherein, The selection unit further includes a voltage regulator capacitor, the first plate of which is coupled to the first terminal of the second selection control transistor, and the second plate of which is coupled to the second level signal line.

19. The display panel according to claim 18, wherein, The display panel includes an active layer, a first gate metal layer, and a second gate metal layer sequentially stacked on the substrate along a direction away from the substrate; the first electrode of the voltage regulator capacitor is disposed in the same layer and with the same material as the active layer, and the second electrode of the voltage regulator capacitor is disposed in the same layer and with the same material as the second gate metal layer.

20. The display panel according to claim 18, wherein, The first plate of the voltage regulator capacitor, the second plate of the first gate control transistor, and the first plate of the second gate control transistor are formed into an integral structure. The selection unit further includes a first output transistor and a fourth capacitor. The gate of the first output transistor is coupled to a first output control node, the first terminal of the first output transistor is coupled to a second level signal line, and the second terminal of the first output transistor is coupled to a gate drive signal output terminal. The first plate of the fourth capacitor is coupled to the first output control node, and the second plate of the fourth capacitor is coupled to the second level signal line. The second plate of the voltage regulator capacitor and the second plate of the fourth capacitor are formed as an integral structure.

21. The display panel according to claim 20, wherein, The orthographic projections of the first gating control transistor on the substrate, the orthographic projections of the voltage regulator capacitor on the substrate, and the orthographic projections of the second gating control transistor on the substrate are arranged sequentially along a first direction; The first plate of the voltage regulator extends along the second direction, and the second plate of the voltage regulator extends along the second direction, which intersects with the first direction.

22. A display device comprising a display panel as claimed in any one of claims 1 to 21.

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