Display panel and manufacturing method therefor, and display device

Abstract

The present disclosure provides a display panel and a manufacturing method therefor, and a display device. The display panel comprises a base substrate and at least one gate driving circuit provided on the base substrate; the gate driving circuit comprises a plurality of cascaded shift registers; each shift register comprises a transistor structure; the display panel further comprises a first voltage signal input end and a first conductive light-shielding layer; the first voltage signal input end is used for independently inputting a first voltage signal; the first conductive light-shielding layer is coupled to the first voltage signal input end; and the orthographic projection of the first conductive light-shielding layer on the base substrate overlaps the orthographic projection of an active layer of at least part of the transistor structure in the shift register on the base substrate.

Description

Display panel and its manufacturing method, display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] With the continuous development of display technology, the application fields of display products are becoming increasingly wide, and correspondingly, the requirements for display quality are becoming increasingly stringent. To ensure the yield rate of display products, electrostatic discharge (ESD) testing is conducted. This ESD test is a method for evaluating the performance and stability of display products in an electrostatic field environment. This test is typically used to ensure that display products are not damaged or have their display quality affected by electrostatic discharge (ESD) events or high ESD environments.

[0003] Summary of the Invention

[0004] The purpose of this disclosure is to provide a display panel, a method for manufacturing the same, and a display device.

[0005] To achieve the above objectives, this disclosure provides the following technical solution:

[0006] A first aspect of this disclosure provides a display panel, comprising: a substrate and at least one gate driving circuit disposed on the substrate, the gate driving circuit including a plurality of cascaded shift registers, the shift registers including transistor structures; the display panel further comprising:

[0007] A first voltage signal input terminal, wherein the first voltage signal input terminal is used to independently input a first voltage signal; and...

[0008] A first conductive light-shielding layer is coupled to the first voltage signal input terminal. The orthographic projection of the first conductive light-shielding layer on the substrate overlaps with the orthographic projection of the active layer of at least a portion of the transistor structure in the shift register on the substrate.

[0009] Optionally, the display panel includes a display area and a peripheral area surrounding the display area; the display panel further includes:

[0010] A first power signal input terminal is located in the surrounding area and is used to input a first power signal; the first power signal input terminal is independent of the first voltage signal input terminal.

[0011] A first power signal transmission layer extends from the display area to the surrounding area, and the first power signal transmission layer is coupled to the first power signal input terminal.

[0012] Optionally, the display panel further includes:

[0013] Multiple sub-pixels, the sub-pixels being located in the display area, each sub-pixel including a sub-pixel driving circuit, the sub-pixel driving circuit including a driving transistor;

[0014] A second conductive light-shielding layer is independent of the first conductive light-shielding layer. At least a portion of the second conductive light-shielding layer is located in the display area. The orthographic projection of the second conductive light-shielding layer on the substrate overlaps with the orthographic projection of the active layer of the driving transistor on the substrate. In the display area, the second conductive light-shielding layer is coupled to the first power signal transmission layer.

[0015] Optionally, the orthographic projection of the active layer of the transistor structure onto the substrate is located inside the orthographic projection of the first conductive light-shielding layer onto the substrate; the minimum distance d0 between the boundary of the orthographic projection of the active layer of the transistor structure onto the substrate and the boundary of the orthographic projection of the first conductive light-shielding layer onto the substrate satisfies: d0≥1.2μm.

[0016] Optionally, the first voltage signal input terminal includes: a first terminal and an input line coupled together, the first terminal being used to provide the first voltage signal; the first conductive light-shielding layer is coupled to the input line via a transmission line.

[0017] Optionally, the display panel includes at least two transmission lines, at least two gate driving circuits, and at least two first conductive light-shielding layers; the orthographic projection of at least a portion of the active layer of the transistor structure in each gate driving circuit onto the substrate is located inside the orthographic projection of the corresponding first conductive light-shielding layer onto the substrate; each first conductive light-shielding layer is coupled to the input line through a corresponding transmission line.

[0018] Optionally, the transmission line and the input line are disposed on different layers, and the transmission line and the input line are coupled through at least three vias penetrating the insulating layer, the insulating layer being located between the transmission line and the input line.

[0019] Optionally, the input line includes at least two input layers stacked sequentially along a direction away from the substrate; the at least two input layers are connected in parallel.

[0020] Optionally, the display panel includes a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer sequentially stacked along a direction away from the substrate; the input layer is disposed in the same layer and with the same material as one of the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer.

[0021] Optionally, the display panel further includes a third source / drain metal layer, which is located on the side of the second source / drain metal layer facing away from the substrate; and includes an input layer that is disposed in the same layer and with the same material as the third source / drain metal layer.

[0022] Optionally, the display panel further includes a compensation line, which is coupled to one end of the transmission line near the input line, and the compensation line is arranged around the display area of ​​the display panel.

[0023] Optionally, the first conductive light-shielding layer includes a plurality of first conductive light-shielding patterns arranged along a first direction, and the plurality of shift registers are arranged along the first direction; at least a portion of the active layer of the transistor structure in the shift registers is orthographically projected onto the substrate, and is located inside the orthographically projected onto the substrate of the corresponding first conductive light-shielding pattern.

[0024] Adjacent first conductive light-shielding patterns are coupled together by at least one conductive connection.

[0025] Optionally, adjacent first conductive light-shielding patterns are coupled together through a first conductive connection portion and / or a second conductive connection portion;

[0026] The first conductive connection portion is coupled to the edge of each of the two adjacent first conductive light-shielding patterns that is away from the display area.

[0027] The second conductive connection portion is coupled to the edge of each of the two adjacent first conductive light-shielding patterns that is close to the display area.

[0028] Optionally, the shift register includes an output transistor and a plurality of other functional transistors besides the output transistor;

[0029] The first conductive light-shielding pattern includes a first portion and / or a second portion, wherein the second portion is located between the first portion and the display area of ​​the display panel;

[0030] At least a portion of the other functional transistors include an active layer whose orthogonal projection on the substrate is located inside the orthogonal projection of the first portion on the substrate; and / or, the output transistor includes an active layer whose orthogonal projection on the substrate is located inside the orthogonal projection of the second portion on the substrate.

[0031] In the first conductive connection portion, the first portion of each of the two adjacent first conductive light-shielding patterns is coupled to the edge of the first conductive light-shielding pattern that is away from the display area.

[0032] The second conductive connection portion is coupled to the edge of the second portion of each of the two adjacent first conductive light-shielding patterns that is close to the display area.

[0033] Optionally, the orthographic projection of the active layer of all the other functional transistors on the substrate is located inside the orthographic projection of the first portion on the substrate.

[0034] Optionally, within the layout area of ​​the shift register, the first portion and the second portion are independent of each other; the first portion closest to the input line is coupled to the input line via a first transmission line; the second portion closest to the input line is coupled to the input line via a second transmission line.

[0035] Optionally, within the layout area of ​​the shift register, the first part and the second part are formed as a single structure, and this single structure closest to the input line is coupled to the first voltage signal input terminal via a common transmission line.

[0036] Optionally, the display panel includes a first gate driving circuit, the shift register includes a first shift register, the first shift register includes a first output node and a second output node, the output transistor includes a first output transistor and a second output transistor, and the other functional transistors include node control transistors;

[0037] The gate of the node control transistor is coupled to the first output node, the first terminal of the node control transistor is coupled to the first clock signal input terminal, and the second terminal of the node control transistor is coupled to the second output node; the first output node is coupled to the gate of the first output transistor, and the second output node is coupled to the gate of the second output transistor.

[0038] The orthographic projection of the active layer of the node control transistor on the substrate is located inside the orthographic projection of the first portion on the substrate.

[0039] Optionally, the orthographic projection of the active layer of the first output transistor on the substrate is located inside the orthographic projection of the second portion on the substrate; and / or, the orthographic projection of the active layer of the second output transistor on the substrate is located inside the orthographic projection of the second portion on the substrate.

[0040] Optionally, the channel length L of the node control transistor satisfies: 4μm≤L≤8μm.

[0041] Optionally, the channel width W of the first output transistor satisfies: 100μm≤W≤200μm.

[0042] Optionally, the display panel includes a second gate driving circuit, the second gate driving circuit including a second shift register; the first gate driving circuit is located between the second gate driving circuit and the display area of ​​the display panel;

[0043] The display panel includes two first conductive light-shielding layers, the first gate driving circuit corresponds to the first first conductive light-shielding layer, and the second gate driving circuit corresponds to the second first conductive light-shielding layer;

[0044] In the second first conductive light-shielding layer, the adjacent first conductive light-shielding patterns, and the first conductive connection portion and the second conductive connection portion connecting the adjacent first conductive light-shielding patterns together form a first hollow area.

[0045] In the second first conductive light-shielding layer, the first conductive light-shielding pattern includes a first portion having a second hollow area; the area of ​​the first hollow area is larger than the area of ​​the second hollow area.

[0046] Optionally, the plurality of first conductive light-shielding patterns included in the first first conductive light-shielding layer are divided into multiple groups of conductive light-shielding patterns, each group of conductive light-shielding patterns includes two adjacent first conductive light-shielding patterns; the two first conductive light-shielding patterns in each group of conductive light-shielding patterns are coupled to the same first conductive light-shielding pattern in the second first conductive light-shielding layer.

[0047] Optionally, the first conductive light-shielding pattern in each group of conductive light-shielding patterns is coupled to the corresponding first conductive light-shielding pattern in the second first conductive light-shielding layer through the third conductive connection part;

[0048] The first conductive light-shielding layer has a third hollow area between adjacent first conductive light-shielding patterns, which extends to the adjacent third conductive connection portions; the area of ​​the third hollow area is greater than or equal to 1.2 times the area of ​​the second hollow area.

[0049] Optionally, the spacing between adjacent third conductive connections along the first direction is less than the maximum length of the first conductive light-shielding pattern in the second first conductive light-shielding layer along the first direction.

[0050] Optionally, the spacing between adjacent third conductive connections along the first direction is greater than or equal to the spacing between two adjacent clock signal lines coupled to the gate drive circuit.

[0051] Optionally, the first conductive light-shielding layer is coupled to the first voltage signal input terminal via a first common transmission line, and the second conductive light-shielding layer is coupled to the first voltage signal input terminal via a second common transmission line.

[0052] A fourth cutout area is formed between the first common transmission line and the second common transmission line, and the area of ​​the fourth cutout area is larger than that of the third cutout area.

[0053] Optionally, there is a first distance d1 between the orthographic projection of the end of the input line coupled to the transmission line on the substrate and the orthographic projection of the second conductive light-shielding layer on the substrate.

[0054] The first conductive light-shielding layer has a second distance d2 between its boundary near the display area and the second conductive light-shielding layer;

[0055] The boundary of the second first conductive light-shielding layer away from the display area has a third distance d3 between it and the second conductive light-shielding layer; satisfying: d2<d1≤d3.

[0056] Optional, d2≥20μm.

[0057] Optionally, there is a fourth distance d4 between the orthographic projection of the input line and the transmission line coupled to the substrate and the orthographic projection of the second first conductive light-shielding layer on the substrate, where d4 ≥ d2.

[0058] Optionally, the second conductive light-shielding layer includes an inner perimeter portion, an outer perimeter portion, and a plurality of connecting portions, wherein the inner perimeter portion is coupled to the outer perimeter portion through the plurality of connecting portions; the inner perimeter portion is located in the display area, the outer perimeter portion and the plurality of connecting portions are located in the peripheral area, and at least a portion of the outer perimeter portion extends along the boundary of the display area;

[0059] The orthographic projection of the inner perimeter portion on the substrate overlaps with the orthographic projection of the active layer of the driving transistor on the substrate.

[0060] The orthographic projection of the connecting portion on the substrate at least partially overlaps with the orthographic projection of the fan-out line in the display panel on the substrate; the orthographic projection of the connecting portion on the substrate at least partially overlaps with the orthographic projection of the gating unit in the display panel on the substrate.

[0061] The line width of the connecting portion is smaller than the line width of the outer portion.

[0062] Optionally, a fifth hollow area is formed between adjacent connecting portions, and the area of ​​the fifth hollow area is larger than the area of ​​the third hollow area.

[0063] Optionally, the display panel further includes a second power bus and a cathode layer, wherein the second power bus is coupled to the cathode layer;

[0064] The orthographic projection of the first conductive light-shielding layer on the substrate is located between the orthographic projection of the second power bus on the substrate and the display area of ​​the display panel.

[0065] Optionally, the minimum spacing between the orthographic projection of the first conductive light-shielding layer on the substrate and the orthographic projection of the second power bus on the substrate is greater than or equal to 25 μm.

[0066] Based on the above-described display panel technical solution, a second aspect of this disclosure provides a display device including the above-described display panel.

[0067] Based on the above-described display panel technical solution, a third aspect of this disclosure provides a method for manufacturing a display panel, the method comprising: fabricating a first conductive light-shielding layer on a substrate; fabricating at least one gate driving circuit on the substrate, the gate driving circuit including a plurality of cascaded shift registers, the shift registers including transistor structures; fabricating a first voltage signal input terminal, the first voltage signal input terminal being used to independently input a first voltage signal; the first conductive light-shielding layer being coupled to the first voltage signal input terminal, the orthographic projection of the first conductive light-shielding layer on the substrate overlapping the orthographic projection of the active layer of at least a portion of the transistor structures in the shift registers on the substrate. Attached Figure Description

[0068] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0069] Figure 1 is a schematic diagram of the circuit principle of the sub-pixel driving circuit provided in an embodiment of this disclosure;

[0070] Figure 2 is a schematic diagram of the circuit principle of the first shift register provided in an embodiment of this disclosure;

[0071] Figure 3 is the timing diagram of the first shift register;

[0072] Figure 4 is a schematic diagram of the first shift register malfunctioning in stage B;

[0073] Figure 5 is a schematic diagram of independent control of the first conductive light-shielding layer and the first power signal transmission layer provided in an embodiment of this disclosure;

[0074] Figure 6 is a schematic diagram showing that the first conductive light-shielding layer and the first power signal transmission layer provided in the embodiment of this disclosure are controlled by the first power signal input terminal;

[0075] Figure 7 shows that two first conductive light-shielding layers in an embodiment of this disclosure share a first voltage signal input terminal;

[0076] Figure 8 shows that the three first conductive light-shielding layers provided in the embodiment of this disclosure share a first voltage signal input terminal;

[0077] Figure 9 is a schematic diagram of the layout of the active layer and two first conductive light-shielding layers in the first shift register and the second shift register provided in the embodiments of this disclosure;

[0078] Figure 10 is a schematic diagram of the boundary distance between the active layer and the first conductive light-shielding layer of the transistor structure provided in the embodiment of this disclosure.

[0079] Figure 11 is a schematic diagram of the layout of the active layer, the first gate metal layer, and the two first conductive light-shielding layers in the first shift register and the second shift register provided in the embodiments of this disclosure;

[0080] Figure 12 is a schematic diagram of the layout of multiple film layers and two first conductive light-shielding layers of the first shift register and the second shift register provided in the embodiments of this disclosure;

[0081] Figure 13a is a schematic diagram of the layout of the first conductive light-shielding layer and the second conductive light-shielding layer in the peripheral area of ​​the display panel provided in the embodiment of this disclosure.

[0082] Figure 13b is an enlarged view of the left side of Figure 13a;

[0083] Figure 14 is a schematic diagram of the layout of the peripheral area of ​​the display panel provided in an embodiment of this disclosure;

[0084] Figure 15 is a schematic diagram of the layout of the second conductive light-shielding layer, the gating unit, and the fan-out line provided in an embodiment of this disclosure.

[0085] Figure 16 is a schematic diagram of the layout of the peripheral area of ​​the display panel provided in an embodiment of this disclosure. Detailed Implementation

[0086] To further illustrate the display panel, its manufacturing method, and the display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0087] In related technologies, when conducting electrostatic field tests on display products, it was found that display products are prone to defects such as abnormal display and screen flickering. Therefore, how to improve these defects has become an urgent technical problem to be solved.

[0088] Please refer to Figures 3, 9, and 11. This disclosure provides a display panel, including: a substrate and at least one gate driving circuit disposed on the substrate, the gate driving circuit including a plurality of cascaded shift registers, each shift register including a transistor structure; the display panel further includes:

[0089] First voltage signal input terminal 10, the first voltage signal input terminal 10 is used to independently input a first voltage signal; and

[0090] A first conductive light-shielding layer 21 (e.g., a first first conductive light-shielding layer 21-1 and a second first conductive light-shielding layer 21-2) is coupled to the first voltage signal input terminal 10. The orthographic projection of the first conductive light-shielding layer 21 on the substrate overlaps with the orthographic projection of the active layer 30 of at least a portion of the transistor structure in the shift register on the substrate.

[0091] For example, the display panel includes a display area AA and a peripheral area 20 surrounding the display area AA, for example, the peripheral area 20 surrounds the display area AA, but is not limited thereto. The gate driving circuit may be arranged in the peripheral area 20, but is not limited thereto.

[0092] For example, the display area AA includes multiple sub-pixels, and each sub-pixel includes a sub-pixel driving circuit and a light-emitting element coupled together. The specific structure of the sub-pixel driving circuit varies. For example, the sub-pixel driving circuit adopts an 8T1C (i.e., 8 transistors and 1 capacitor) circuit structure, but is not limited to this.

[0093] For example, the gate driving circuits can be of various types, and correspondingly, the specific types of shift registers they include can be varied, as shown in Figure 1. Examples include: a first reset shift register Reset_P GOA, a compensation shift register Gate_N GOA, a write control shift register Gate_P GOA, an emissivity control shift register EM GOA, a second reset shift register Reset_H GOA, etc., but not limited to these. For instance, the compensation shift register Gate_N GOA, the write control shift register Gate_P GOA, and the emissivity control shift register EM GOA are located in the left border area of ​​the display panel; the first reset shift register Reset_P GOA, the second reset shift register Reset_H GOA, and the write control shift register Gate_P GOA are located in the right border area of ​​the display panel, but not limited to these.

[0094] Figure 1 illustrates the connection relationship between the sub-pixel driving circuit using an 8T1C circuit structure and various shift registers. A detailed explanation follows:

[0095] The first reset transistor T31 is driven by a driving transistor T33 and a first reset transistor T31. The gate of the first reset transistor T31 is coupled to the gate drive signal output terminal of the corresponding first reset shift register Reset_P GOA. The first terminal of the first reset transistor T31 is coupled to the first initialization signal line Vinit1. The second terminal of the first reset transistor T31 is coupled to the second terminal of the driving transistor T33.

[0096] The compensation transistor T32 has its gate coupled to the gate drive signal output terminal of the corresponding compensation shift register Gate_N GOA. The first terminal of the compensation transistor T32 is coupled to the second terminal of the driving transistor T33, and the second terminal of the compensation transistor T32 is coupled to the gate of the driving transistor T33.

[0097] A write control transistor T34 is provided, the gate of which is coupled to the gate drive signal output terminal of the corresponding write control shift register Gate_P GOA, the first terminal of which is coupled to the corresponding data line DA, and the second terminal of which is coupled to the first terminal of the drive transistor T33.

[0098] A power control transistor T35 is provided, wherein the gate of the power control transistor T35 is coupled to the gate drive signal output terminal of the corresponding light emission control shift register EM GOA, the first terminal of the power control transistor T35 is coupled to the corresponding power signal input terminal VDD, and the second terminal of the power control transistor T35 is coupled to the first terminal of the driving transistor T33.

[0099] The light-emitting control transistor T36 has its gate coupled to the gate drive signal output terminal of the corresponding light-emitting control shift register EM GOA. The first terminal of the light-emitting control transistor T36 is coupled to the second terminal of the driving transistor T33. The second terminal of the light-emitting control transistor T36 is coupled to the anode of the light-emitting element.

[0100] The second reset transistor T37 has its gate coupled to the gate drive signal output terminal of the corresponding second reset shift register Reset_H GOA, its first terminal coupled to the corresponding second initialization signal line Vinit2, and its second terminal coupled to the anode of the light-emitting element. The cathode of the light-emitting element is connected to the VSS signal.

[0101] The third reset transistor T38 has its gate coupled to the gate drive signal output terminal of the corresponding second reset shift register Reset_H GOA, its first terminal coupled to the corresponding third initialization signal line Vinit3, and its second terminal coupled to the first terminal of the drive transistor T33.

[0102] The storage capacitor Cst has its first plate coupled to the gate of the driving transistor T33, and its second plate coupled to the power signal input terminal VDD.

[0103] For example, different types of shift registers may have the same or different specific circuit structures. All types of shift registers include transistor structures, and may also include capacitor structures. When the shift register is in actual operation, if the transistor structure experiences a threshold voltage Vth offset, it will cause leakage current in the transistor structure, which in turn will cause abnormal display and screen flickering phenomena on the display panel during electrostatic field testing.

[0104] For example, the first voltage signal input terminal 10 can be directly or indirectly coupled to a pin of a driver chip, with the driver chip providing the first voltage signal, but it is not limited to this. The voltage value of the first voltage signal input to the first voltage signal input terminal 10 can be adjusted independently; for example, the voltage value of the first voltage signal can be adjusted between 0V and 7V, including the endpoint value.

[0105] For example, at least a portion of the active layer 30 of the transistor structure in the shift register is projected onto the substrate, and its orthographic projection is located inside the orthographic projection of the first conductive light-shielding layer 21 onto the substrate.

[0106] As can be seen from the specific structure of the display panel described above, the display panel provided in this embodiment of the present disclosure is provided with a first voltage signal input terminal 10 capable of independently inputting a first voltage signal, and the first conductive light-shielding layer 21 is coupled to the first voltage signal input terminal 10, so that the first conductive light-shielding layer 21 has the same stable potential as the first voltage signal, and can control the first conductive light-shielding layer 21 to be connected to a constant positive voltage; at the same time, the orth projection of the first conductive light-shielding layer 21 on the substrate overlaps with the orth projection of the active layer of at least part of the transistor structure in the shift register on the substrate, so that the first conductive light-shielding layer 21 can reduce the positive bias of Vth of the transistor structure in the shift register under electrostatic field, ensuring the conduction characteristics of the transistor structure while minimizing the risk of leakage current; therefore, the display panel provided in this embodiment of the present disclosure can effectively improve the abnormal display and screen flickering phenomena during electrostatic field testing. The electrostatic field test benefit of the display panel provided in this embodiment of the present disclosure is above 4KV.

[0107] Furthermore, the display panel provided in this embodiment includes a first voltage signal input terminal 10 capable of independently inputting a first voltage signal, and the first conductive light-shielding layer 21 is coupled to the first voltage signal input terminal 10. This allows the first conductive light-shielding layer 21 to be independently powered by the first voltage signal input terminal 10. Consequently, the power supply voltage received by the first conductive light-shielding layer 21 is adjustable, better matching the characteristics of transistor structures under different process conditions, reducing the difficulty of signal debugging under different process conditions, and satisfying electrical adjustment requirements under different process conditions. Additionally, the above arrangement helps reduce excessive loading of the signal transmitted by the first conductive light-shielding layer 21, avoiding the problem of discrepancies between the actual voltage and the ideal input voltage, and preventing defects such as high-brightness horizontal lines on the display panel.

[0108] As shown in Figure 5, in some embodiments, the display panel includes a display area AA and a peripheral area 20 located around the display area AA; the display panel further includes:

[0109] A first power signal input terminal 11 is located in the peripheral area 20 and is used to input a first power signal. The first power signal input terminal 11 is independent of the first voltage signal input terminal 10.

[0110] A first power signal transmission layer 12 extends from the display area AA to the peripheral area 20, and the first power signal transmission layer 12 is coupled to the first power signal input terminal 11.

[0111] For example, the first power signal input terminal 11 includes the aforementioned power signal input terminal VDD, but is not limited thereto.

[0112] For example, the first power signal input terminal 11 and the first voltage signal input terminal 10 can be controlled independently and do not affect each other.

[0113] As shown in Figure 6, the first power signal transmission layer 12 and the first conductive light-shielding layer 21 are both connected to the same first power signal input terminal 11. This method cannot achieve independent control of the first power signal transmission layer 12 and the first conductive light-shielding layer 21 in receiving signals.

[0114] In the display panel provided in the above embodiment, the first power signal input terminal 11 and the first voltage signal input terminal 10 are independent of each other, so that the first conductive light-shielding layer 21 can be independently powered by the first voltage signal input terminal 10. This makes the power supply voltage received by the first conductive light-shielding layer 21 adjustable, better matching the characteristics of transistor structures under different process conditions, reducing the difficulty of signal debugging under different process conditions, and meeting the electrical adjustment requirements under different process conditions. Furthermore, the above arrangement helps reduce the excessive loading of the signal transmitted by the first conductive light-shielding layer 21, avoiding the problem of the actual voltage not matching the ideal input voltage, and preventing defects such as high-brightness horizontal lines on the display panel.

[0115] As shown in Figures 13a, 13b, and 15, in some embodiments, the display panel further includes:

[0116] Multiple sub-pixels, the sub-pixels being located in the display area AA, each sub-pixel including a sub-pixel driving circuit, the sub-pixel driving circuit including a driving transistor;

[0117] The second conductive light-shielding layer 22 is independent of the first conductive light-shielding layer 21. At least a portion of the second conductive light-shielding layer 22 is located in the display area AA. The orthographic projection of the second conductive light-shielding layer 22 on the substrate overlaps with the orthographic projection of the active layer of the driving transistor on the substrate. In the display area AA, the second conductive light-shielding layer 22 is coupled to the first power signal transmission layer 12.

[0118] For example, both the first conductive light-shielding layer 21 and the second conductive light-shielding layer 22 are made of conductive materials. For instance, both the first conductive light-shielding layer 21 and the second conductive light-shielding layer 22 are made of conductive metal materials, and the first conductive light-shielding layer 21 and the second conductive light-shielding layer 22 are made of the same material in the same layer.

[0119] The first conductive light-shielding layer 21 is used to adjust the threshold voltage offset of the transistor structure in the shift register, and the second conductive light-shielding layer 22 is used to maintain the characteristic stability of the driving transistor. The above configuration makes the first conductive light-shielding layer 21 and the second conductive light-shielding layer 22 independent of each other and can be controlled independently.

[0120] By coupling the second conductive light-shielding layer 22 to the first power signal transmission layer 12, it is not necessary to set up a separate signal input terminal for the second conductive light-shielding layer 22 to provide signals, which helps to simplify the circuit structure of the display panel.

[0121] As shown in Figure 10, in some embodiments, the orthographic projection of the active layer 30 of the transistor structure TFT on the substrate is located inside the orthographic projection of the first conductive light-shielding layer 21 on the substrate; the minimum distance d0 between the boundary of the orthographic projection of the active layer 30 of the transistor structure TFT on the substrate and the boundary of the orthographic projection of the first conductive light-shielding layer 21 on the substrate satisfies: d0 ≥ 1.2 μm. Optionally, d0 ≤ 5 μm.

[0122] For example, d0 can take specific values ​​of 1.2μm, 1.3μm, 1.4μm, 1.5μm, 1.6μm, 1.7μm, and 1.8μm, but is not limited to these.

[0123] The above setting d0 satisfies d0≥1.2μm, better taking into account the influence of process overlay offset, and can reserve sufficient process margin to ensure that the orthographic projection of the active layer 30 of the transistor structure TFT on the substrate can be located inside the orthographic projection of the first conductive light-shielding layer 21 on the substrate. This better optimizes the film crystallinity of the active layer 30 in the transistor structure TFT and ensures that the transistor structure has good performance characteristics.

[0124] As shown in Figure 16, in some embodiments, the first voltage signal input terminal 10 includes: a first terminal 101 and an input line 102 coupled together, the first terminal 101 being used to provide the first voltage signal; the first conductive light-shielding layer 21 is coupled to the input line 102 through a transmission line (such as a first common transmission line 51 and a second common transmission line 52).

[0125] For example, the first terminal 101 is coupled to the driver chip and receives the first voltage signal provided by the driver chip.

[0126] The first conductive light-shielding layer 21 is coupled to the input line 102 via the transmission line, which allows for flexible layout of the transmission line and the input line 102, reducing the layout difficulty of the surrounding area 20.

[0127] As shown in Figures 14 and 16, in some embodiments, the transmission line and the input line 102 are disposed on different layers, and the transmission line and the input line 102 are coupled through at least three vias penetrating the insulating layer, the insulating layer being located between the transmission line and the input line 102.

[0128] It should be noted that X1 in Figure 14 indicates the Via connection area.

[0129] The above setup helps to mitigate ESD risks during the process of via drilling, ensures the stability of the connection between the transmission line and the input terminal, avoids blind vias caused by ESD, and reduces the risk of signal breakage.

[0130] As shown in FIG16, in some embodiments, at least a portion of the input line 102 comprises at least two input layers stacked sequentially in a direction away from the substrate; the at least two input layers are connected in parallel.

[0131] For example, the at least two input layers are coupled at one end via a via and at the other end via a via, thereby achieving parallel connection.

[0132] It should be noted that the input line 102 marked in Figure 16 extends from the via Via to the first terminal 101. The figure shows that the input line 102 includes multiple segments with different fillers, and at least one segment can be configured to include at least two input layers.

[0133] The above configuration improves the stability of the input signal on the input line 102 and reduces the loading on the input line 102. Furthermore, this configuration reduces the resistance of the input line 102 to below 5Ω, ensuring a stable voltage input to the shift register during electrostatic discharge (ESD) testing, guaranteeing stable and unbiased shift register characteristics, and further enhancing the anti-static capability of the display panel.

[0134] In some embodiments, the display panel includes a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer sequentially stacked along a direction away from the substrate; the input layer is disposed in the same layer and with the same material as one of the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer.

[0135] For example, the display panel includes, sequentially stacked along a direction away from the substrate, a conductive light-shielding layer, a barrier layer, a buffer layer, an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, an anode layer, a pixel defining layer, a light-emitting functional layer, a cathode layer, a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The display substrate may also include a passivation layer, but is not limited to this.

[0136] The above configuration allows each input layer to be formed in the same patterning process as its corresponding film layer made of the same material, thereby simplifying the manufacturing process of the display panel and reducing manufacturing costs.

[0137] In some embodiments, the display panel further includes a third source / drain metal layer located on the side of the second source / drain metal layer facing away from the substrate; and includes an input layer that is disposed in the same layer and with the same material as the third source / drain metal layer.

[0138] For example, the display panel further includes a third source / drain metal layer located between the second planarization layer and the anode layer, and a third planarization layer located between the third source / drain metal layer and the anode layer.

[0139] The above configuration allows each input layer to be formed in the same patterning process as its corresponding film layer made of the same material, thereby simplifying the manufacturing process of the display panel and reducing manufacturing costs.

[0140] As shown in Figures 14 and 16, in some embodiments, the display panel further includes a compensation line 60, which is coupled to one end of the transmission line (such as the first common transmission line 51 and the second common transmission line 52) near the input line 102, and the compensation line 60 is arranged around the display area AA of the display panel.

[0141] For example, the compensation line 60 is disposed in the same layer and material as the transmission line, and the compensation line 60 is closer to the edge of the display panel than the transmission line.

[0142] For example, the display panel further includes a second power bus 80 and a cathode layer, the second power bus 80 being coupled to the cathode layer and used to provide a cathode signal to the cathode layer. The orthographic projection of the second power bus 80 on the substrate is located between the orthographic projection of the compensation line 60 on the substrate and the orthographic projection of the first conductive light-shielding layer 21 on the substrate, but is not limited thereto.

[0143] The display panel described above also includes a compensation line 60, which helps to further reduce the loading of the first conductive light-shielding layer 21.

[0144] As shown in Figures 9, 13a, and 13b, in some embodiments, the first conductive light-shielding layer 21 includes a plurality of first conductive light-shielding patterns 210 arranged along a first direction, and the plurality of shift registers are arranged along the first direction; at least a portion of the active layer 30 of the transistor structure in the shift registers is orthographically projected onto the substrate, and is located inside the orthographically projected image of the corresponding first conductive light-shielding pattern 210 onto the substrate; adjacent first conductive light-shielding patterns 210 are coupled together by at least one conductive connection (e.g., a first conductive connection 211, a second conductive connection 212).

[0145] For example, the plurality of first conductive light-shielding patterns 210 correspond one-to-one with a plurality of shift registers cascaded in a gate driving circuit.

[0146] For example, the first conductive light-shielding pattern 210 and the conductive connection portion are formed as an integral structure.

[0147] For example, adjacent first conductive light-shielding patterns 210 are coupled through a first conductive connection portion 211 and / or a second conductive connection portion 212; the first conductive connection portion 211 is coupled to the edge of each of the two adjacent first conductive light-shielding patterns 210 that is away from the display area AA; the second conductive connection portion 212 is coupled to the edge of each of the two adjacent first conductive light-shielding patterns 210 that is close to the display area AA.

[0148] The above-described configuration not only ensures that the position of the first conductive light-shielding pattern 210 matches the transistor structure, guaranteeing that the orthographic projection of at least a portion of the active layer of the transistor structure in the shift register onto the substrate is located within the orthographic projection of the first conductive light-shielding layer 21 onto the substrate, but also reduces the layout difficulty of the first conductive light-shielding layer 21 and its loading. Furthermore, this configuration also helps reduce the risk of ESD damage to the edges of the first conductive light-shielding layer 21 during the fabrication process.

[0149] As shown in Figures 9 and 11, in some embodiments, the shift register includes: an output transistor (such as the fourth transistor T4, the fifth transistor T5, the ninth transistor T9 and the tenth transistor T10) and a plurality of other functional transistors (such as TFT0, and the first transistor T1, the node control transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8) in addition to the output transistor.

[0150] The first conductive light-shielding pattern 210 includes a first portion 210a and / or a second portion 210b, the second portion 210b being located between the first portion 210a and the display area AA of the display panel; at least a portion of the active layer of the other functional transistors has its orthographic projection on the substrate located inside the orthographic projection of the first portion 210a on the substrate; and / or, the orthographic projection of the active layer of the output transistor on the substrate is located inside the orthographic projection of the second portion 210b on the substrate;

[0151] The first conductive connection portion 211 is coupled to the edge of each of the two adjacent first conductive light-shielding patterns 210, where the first portion 210a is away from the display area AA; the second conductive connection portion 212 is coupled to the edge of each of the two adjacent first conductive light-shielding patterns 210, where the second portion 210b is close to the display area AA.

[0152] For example, the first part 210a is used to regulate the characteristic offset of the other functional transistors, and the second part 210b is used to regulate the characteristic offset of the output transistor.

[0153] The aforementioned arrangement, where each conductive connection is coupled to the edge of the first conductive light-shielding pattern 210, ensures connection performance while facilitating the formation of a larger-area grid structure between the first conductive light-shielding layer 21 and the conductive connections. This further reduces the loading of the first conductive light-shielding layer 21. Furthermore, this arrangement also helps reduce the risk of ESD damage to the edges of the first conductive light-shielding layer 21 during manufacturing.

[0154] As shown in Figures 9 and 11, in some embodiments, the orthographic projection of the active layer of all the other functional transistors on the substrate is located inside the orthographic projection of the first portion 210a on the substrate.

[0155] The above configuration enables the first part 210a to control the characteristic offset of all the other functional transistors, which can better improve various defects generated by the display panel in the electrostatic field.

[0156] In some embodiments, within the layout area of ​​the shift register, the first portion 210a and the second portion 210b are independent of each other; the first portion 210a, which is closest to the input line 102, is coupled to the input line 102 via a first transmission line; the second portion 210b, which is closest to the input line 102, is coupled to the input line 102 via a second transmission line.

[0157] For example, the layout area of ​​the shift register can be a region capable of accommodating the entire shift register. For example, this region can be a rectangular region, but is not limited to this. Specifically, as shown in Figures 11 and 12, the area enclosed by the dashed box in the figures is the layout area of ​​the shift register.

[0158] The above configuration allows the first part 210a and the second part 210b to be independently connected to the input line 102 through their respective transmission lines. This method is beneficial for the first conductive light-shielding layer 21 as a whole, the conductive connection part and the transmission line to form a grid structure that can spread out a larger area, which is beneficial for further reducing the loading of the first conductive light-shielding layer 21.

[0159] As shown in Figures 7 to 9, Figures 13a and 13b, in some embodiments, the first portion 210a and the second portion 210b are formed as a single structure within the layout area of ​​the shift register, and the single structure closest to the input line 102 is coupled to the first voltage signal input terminal 10 via a common transmission line.

[0160] The above setup helps to simplify the layout complexity of the display panel and reduce the difficulty of layout.

[0161] As shown in Figures 7 to 9, 13a and 13b, in some embodiments, the display panel includes at least two transmission lines, at least two gate driving circuits, and at least two first conductive light-shielding layers 21; the orthographic projection of at least a portion of the active layer of the transistor structure in each gate driving circuit onto the substrate is located inside the orthographic projection of the corresponding first conductive light-shielding layer 21 onto the substrate; each first conductive light-shielding layer 21 is coupled to the input line 102 through a corresponding transmission line.

[0162] For example, the at least two transmission lines correspond one-to-one with the at least two gate driving circuits, and the at least two gate driving circuits correspond one-to-one with the at least two first conductive light-shielding layers 21, but are not limited thereto.

[0163] For example, as shown in Figures 7 and 8, the second first conductive light-shielding layer 21-2 corresponding to the light emission control shift register EM GOA is coupled to the input line 102 through the second common transmission line 52, the first first conductive light-shielding layer 21-1 corresponding to the write control shift register Gate_P GOA is coupled to the input line 102 through the first common transmission line 51, and the third first conductive light-shielding layer 21-3 corresponding to the compensation shift register Gate_N GOA is coupled to the input line 102 through the third common transmission line 53.

[0164] The above configuration allows the first conductive light-shielding layer 21 corresponding to each gate driving circuit to be independently connected to the input line 102 through its respective transmission line. This not only helps each first conductive light-shielding layer 21 to be involved in the first voltage signal, but also ensures that the loading of each first conductive light-shielding layer 21 is the same.

[0165] As shown in Figures 2, 9, and 11, in some embodiments, the display panel includes a first gate driving circuit, the shift register includes a first shift register (e.g., write control shift register Gate_P GOA), the first shift register includes a first output node N1 and a second output node N2, the output transistor includes a first output transistor (e.g., a fourth transistor T4) and a second output transistor (a fifth transistor T5), and the other functional transistors include a node control transistor T2;

[0166] The gate of the node control transistor T2 is coupled to the first output node N1, the first terminal of the node control transistor T2 is coupled to the first clock signal input terminal (which is coupled to the first clock signal line CK), and the second terminal of the node control transistor T2 is coupled to the second output node N2; the first output node N1 is coupled to the gate of the first output transistor, and the second output node N2 is coupled to the gate of the second output transistor.

[0167] The orthographic projection of the active layer of the node control transistor T2 onto the substrate is located inside the orthographic projection of the first portion 210a onto the substrate.

[0168] It should be noted that Figure 4 also illustrates the first level signal line VGL, the second level signal line VGH, the first capacitor C1, the second capacitor C2, the gate drive signal output terminal OUT, and the frame start signal input terminal STV.

[0169] It is worth noting that the shift register included in the first gate drive circuit is not limited to the first shift register described above, but may also include shift registers with other structures.

[0170] For example, the first gate drive circuit includes, but is not limited to, writing to the control shift register Gate_PGOA.

[0171] More specifically, as shown in Figures 3 and 4, the study found that in stage B, the threshold voltage of node control transistor T2 is prone to forward bias, causing leakage in node control transistor T2. Due to the high-level signal input at the second level signal input terminal, the potential of the second output node N2 increases, thereby turning off the sixth transistor. This causes the first output node N1 to be in a floating state, and the signal transmitted by the second clock signal line CB switches from high level to low level. Due to the presence of coupling capacitor Cgd, the potential of the first output node N1 decreases, the threshold voltage of node control transistor T2 is forward biased, and it is in an open state. The second output node N2 is at a high level, the second output transistor is turned off, and the gate drive signal output terminal is in a floating state. Under the action of the second capacitor C2, the potential of the gate drive signal output terminal decreases, resulting in multi-pulse output of the gate drive signal output terminal.

[0172] It is evident that the factors leading to the anomaly include: the forward bias of the threshold voltage of the node control transistor T2, the leakage current of the node control transistor T2, and the coupling effect of the coupling capacitor Cgd.

[0173] The above-described configuration places the orthographic projection of the active layer of the node control transistor T2 onto the substrate inside the orthographic projection of the first portion 210a onto the substrate. This allows the first conductive light-shielding layer 21 to reduce the positive bias of the node control transistor T2 under an electrostatic field, ensuring the conduction characteristics of the node control transistor T2 while minimizing the risk of leakage. Therefore, the display panel provided in the above embodiment can effectively improve the abnormal display and screen flickering phenomena that occur during electrostatic field testing.

[0174] As shown in Figures 2, 9 and 11, in some embodiments, the orthographic projection of the active layer of the first output transistor on the substrate is located inside the orthographic projection of the second portion 210b on the substrate; and / or, the orthographic projection of the active layer of the second output transistor on the substrate is located inside the orthographic projection of the second portion 210b on the substrate.

[0175] The above configuration allows the first conductive light-shielding layer 21 to reduce the positive bias of the first and second output transistors under an electrostatic field, ensuring the conduction characteristics of the first and second output transistors while minimizing the risk of leakage. Therefore, the display panel provided in the above embodiment can effectively improve the abnormal display and screen flickering phenomena that occur during electrostatic field testing.

[0176] In some embodiments, the channel length L of the node control transistor T2 satisfies: 4μm≤L≤8μm.

[0177] For example, the channel length L of the node control transistor T2 can take values ​​such as 4μm, 5μm, 6μm, 7μm, 8μm, etc., but is not limited to these.

[0178] Setting the channel length L of the node control transistor T2 within the above range can reduce the leakage risk of the node control transistor T2 while ensuring its conduction characteristics.

[0179] In some embodiments, the channel width W of the first output transistor satisfies: 100μm≤W≤200μm.

[0180] For example, the channel width W of the first output transistor can take values ​​of 100μm, 120μm, 140μm, 160μm, 180μm, 190μm, 200μm, but is not limited to these.

[0181] Setting the channel width W of the first output transistor within the aforementioned range can reduce the coupling amount of the coupling capacitor Cgd while ensuring the conduction characteristics of the first output transistor, thereby improving the display panel's display abnormalities under electrostatic field.

[0182] As shown in Figures 2, 9, 11, 13a, and 13b, in some embodiments, the display panel includes a second gate driving circuit, which includes a second shift register (e.g., a light emission control shift register EMOA); the first gate driving circuit is located between the second gate driving circuit and the display area AA of the display panel.

[0183] The display panel includes two first conductive light-shielding layers 21, the first gate driving circuit corresponds to the first first conductive light-shielding layer 21-1, and the second gate driving circuit corresponds to the second first conductive light-shielding layer 21-2;

[0184] In the second first conductive light-shielding layer 21-2, the adjacent first conductive light-shielding patterns 210, and the first conductive connection portion 211 and the second conductive connection portion 212 connecting the adjacent first conductive light-shielding patterns 210 together form the first hollow area 71.

[0185] In the second first conductive light-shielding layer 21-2, the first conductive light-shielding pattern 210 includes a first portion 210a with a second hollow area 72; the area of ​​the first hollow area 71 is larger than the area of ​​the second hollow area 72.

[0186] For example, the second gate drive circuit includes, but is not limited to, an emission control shift register EM GOA.

[0187] For example, the orthographic projection of at least a portion of the transistor structure included in the first shift register of the first gate driving circuit on the substrate is located inside the orthographic projection of the first first conductive light-shielding layer 21-1 on the substrate, and the orthographic projection of at least a portion of the transistor structure included in the second shift register of the second gate driving circuit on the substrate is located inside the orthographic projection of the second first conductive light-shielding layer 21-2 on the substrate.

[0188] For example, the first conductive light-shielding layer 21-1 is located between the second conductive light-shielding layer 21-2 and the display area AA.

[0189] For example, both the first cutout area 71 and the second cutout area 72 are closed areas.

[0190] As shown in Figures 9, 11, 13a, and 13b, in some embodiments, the plurality of first conductive light-shielding patterns 210 included in the first first conductive light-shielding layer 21-1 are divided into multiple groups of conductive light-shielding patterns, each group of conductive light-shielding patterns includes two adjacent first conductive light-shielding patterns 210; the two first conductive light-shielding patterns 210 in each group of conductive light-shielding patterns are coupled to the same first conductive light-shielding pattern 210 corresponding to the second first conductive light-shielding layer 21-2.

[0191] For example, the first conductive light-shielding pattern 210 in each group of conductive light-shielding patterns is coupled to the corresponding first conductive light-shielding pattern 210 in the second first conductive light-shielding layer 21-2 through the third conductive connection portion 213; there is a third hollow area 73 between adjacent first conductive light-shielding patterns 210 in the first first conductive light-shielding layer 21-1, and the third hollow area 73 extends to the adjacent third conductive connection portions 213; the area of ​​the third hollow area 73 is greater than or equal to 1.2 times the area of ​​the second hollow area 72.

[0192] For example, the spacing d5 between adjacent third conductive connections 213 along the first direction is less than the maximum length d6 of the first conductive light-shielding pattern 210 in the second first conductive light-shielding layer 21-2 along the first direction. This design helps to ensure that the first conductive light-shielding pattern 210 in the second first conductive light-shielding layer 21-2 sufficiently overlaps the active layer length of the corresponding shift register's output transistor, thus reducing loading.

[0193] For example, the spacing d5 of adjacent third conductive connection portions 213 along the first direction is greater than or equal to the spacing between two adjacent clock signal lines coupled to the gate drive circuit (as shown in Figure 12, adjacent CB and CK).

[0194] As shown in Figures 9 and 12, by way of example, the orthographic projection of the third conductive connection portion 213 on the substrate overlaps at least partially with the orthographic projection of the clock signal line on the substrate.

[0195] As shown in Figures 13a, 13b, 14, and 16, in some embodiments, the first first conductive light-shielding layer 21-1 is coupled to the first voltage signal input terminal 10 via a first common transmission line 51, and the second first conductive light-shielding layer 21-2 is coupled to the first voltage signal input terminal 10 via a second common transmission line 52; a fourth cutout region 74 is formed between the first common transmission line 51 and the second common transmission line 52, and the area of ​​the fourth cutout region 74 is larger than that of the third cutout region 73. This design results in a smaller spacing between the first gate driving circuit and the second gate driving circuit, which helps save layout space.

[0196] Setting the first cutout area 71, the second cutout area 72, the third cutout area 73, and the fourth cutout area 74 to satisfy the above relationship can not only ensure that the first conductive light-shielding layer 21 can adjust the characteristics of the transistors in the shift register, but also make reasonable use of the limited layout space, so that the shift registers belonging to the same gate driving circuit and different gate driving circuits have appropriate spacing. This not only ensures the stability of the circuit operation, but also helps to reduce the layout difficulty of the display panel.

[0197] As shown in Figures 13a, 13b, 14, and 16, in some embodiments, the orthographic projection of the input line 102 coupled to the transmission line on the substrate and the orthographic projection of the second conductive light-shielding layer 22 on the substrate have a first distance d1; the boundary of the first conductive light-shielding layer 21-1 near the display area AA has a second distance d2; the boundary of the second conductive light-shielding layer 21-2 away from the display area AA has a third distance d3; satisfying: d2 < d1 ≤ d3.

[0198] For example, d2 ≥ 20 μm. Specifically, d2 can take values ​​such as 20 μm, 21 μm, 22 μm, 23 μm, 24 μm, 25 μm, etc., but is not limited to these. Furthermore, d2 ≤ 40 μm, but is not limited to these.

[0199] For example, there is a fourth distance d4 between the orthographic projection of the end of the input line 102 coupled to the transmission line on the substrate and the orthographic projection of the second first conductive light-shielding layer 21-2 on the substrate, where d4 ≥ d2.

[0200] By setting d1, d2, d3, and d4 in the above manner, it is possible to ensure that the first conductive light-shielding layer 21 can adjust the characteristics of the transistors in the shift register, and to reasonably plan the limited layout space. This ensures that there is a suitable distance between the input line 102 and the second conductive light-shielding layer 22, between the first first conductive light-shielding layer 21-1 and the second conductive light-shielding layer 22, between the second first conductive light-shielding layer 21-2 and the second conductive light-shielding layer 22, and between the input line 102 and the first first conductive light-shielding layer 21-1. This not only ensures the stability of the circuit operation and prevents electrostatic discharge damage and avoids ESD risks, but also helps to reduce the layout difficulty of the display panel.

[0201] As shown in Figure 15, in some embodiments, the second conductive light-shielding layer 22 includes an inner perimeter portion 221, an outer perimeter portion 222, and a plurality of connecting portions 223. The inner perimeter portion 221 is coupled to the outer perimeter portion 222 through the plurality of connecting portions 223. The inner perimeter portion 221 is located in the display area AA, and the outer perimeter portion 222 and the plurality of connecting portions 223 are located in the peripheral area 20. At least a portion of the outer perimeter portion 222 extends along the boundary of the display area AA.

[0202] The orthographic projection of the inner perimeter portion 221 on the substrate overlaps with the orthographic projection of the active layer of the driving transistor on the substrate.

[0203] The orthographic projection of the connecting portion 223 on the substrate overlaps at least partially with the orthographic projection of the fan-out line in the display panel (the Fanout shown in Figure 15 is a densely packed area of ​​fan-out lines) on the substrate; the orthographic projection of the connecting portion 223 on the substrate overlaps at least partially with the orthographic projection of the gating unit MUX in the display panel on the substrate.

[0204] The line width of the connecting portion 223 is smaller than the line width of the peripheral portion 222.

[0205] For example, the orthographic projection of the active layer of the driving transistor on the substrate is located inside the orthographic projection of the inner circumference portion 221 on the substrate.

[0206] For example, the plurality of connecting portions 223 are arranged along a second direction, each connecting portion 223 including at least a portion extending along a third direction, the second direction intersecting the third direction, for example: the second direction includes a longitudinal direction, the third direction includes a transverse direction; each connecting portion 223 is coupled to the inner portion 221 and the outer portion 222 respectively.

[0207] For example, a fifth cutout area 75 is formed between adjacent connecting portions 223, and the area of ​​the fifth cutout area 75 is larger than the area of ​​the third cutout area 73.

[0208] The line width of the connection portion 223 is set to be smaller than that of the outer portion 222, which effectively reduces the overlap area between the connection portion 223, the fanout line, and the gating unit MUX, thereby effectively reducing the ESD risk.

[0209] As shown in Figures 14 and 16, in some embodiments, the display panel further includes a second power bus 80 and a cathode layer, wherein the second power bus 80 is coupled to the cathode layer;

[0210] The orthographic projection of the first conductive light-shielding layer 21 on the substrate is located between the orthographic projection of the second power bus 80 on the substrate and the display area AA of the display panel.

[0211] For example, the second power bus 80 is located in the peripheral region 20, and the cathode layer can extend from the display area AA of the display panel to the peripheral region 20 to achieve an electrical connection with the second power bus 80.

[0212] For example, the second power bus 80 and the cathode layer are used to transmit negative voltage signals.

[0213] For example, the minimum distance between the orthographic projection of the first conductive light-shielding layer 21 on the substrate and the orthographic projection of the second power bus 80 on the substrate is greater than or equal to 25 μm.

[0214] The above arrangement ensures a greater distance between the first conductive light-shielding layer 21 and the second power bus 80, thereby avoiding electrochemical corrosion caused by a large voltage difference between the first conductive light-shielding layer 21 (which transmits positive voltage signals) and the second power bus 80 (which transmits negative voltage signals).

[0215] This disclosure also provides a display device, including the display panel provided in the above embodiments.

[0216] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, vehicle-mounted device, large folding product, large-size Ramless IC+DDL product, tablet computer, etc. The display device also includes flexible circuit board, printed circuit board and backplane, etc.

[0217] For example, the display panel includes a liquid crystal display panel, an organic light-emitting diode display panel, etc., but is not limited to these.

[0218] In the display panel provided in the above embodiments, a first voltage signal input terminal 10 capable of independently inputting a first voltage signal is provided, and the first conductive light-shielding layer 21 is coupled to the first voltage signal input terminal 10, so that the first conductive light-shielding layer 21 has the same stable potential as the first voltage signal, and can control the first conductive light-shielding layer 21 to be connected to a constant positive voltage; at the same time, the orth projection of the first conductive light-shielding layer 21 on the substrate overlaps with the orth projection of the active layer of at least part of the transistor structure in the shift register on the substrate, so that the first conductive light-shielding layer 21 can reduce the positive bias of Vth of the transistor structure in the shift register under electrostatic field, ensuring the conduction characteristics of the transistor structure while minimizing the risk of leakage current; therefore, the display panel provided in the above embodiments can effectively improve the abnormal display and screen flickering phenomena during electrostatic field testing.

[0219] Furthermore, the display panel provided in the above embodiment is equipped with a first voltage signal input terminal 10 capable of independently inputting a first voltage signal, and the first conductive light-shielding layer 21 is coupled to the first voltage signal input terminal 10. This allows the first conductive light-shielding layer 21 to be independently powered by the first voltage signal input terminal 10. In this way, the power supply voltage received by the first conductive light-shielding layer 21 is adjustable, which can better match the characteristics of transistor structures under different process conditions, reduce the difficulty of signal debugging under different process conditions, and meet the electrical adjustment requirements under different process conditions. In addition, the above arrangement helps to reduce the excessive loading of the signal transmitted by the first conductive light-shielding layer 21, avoiding the problem of the actual voltage not matching the ideal input voltage, and preventing defects such as high-brightness horizontal lines on the display panel.

[0220] The display device provided in this embodiment of the present disclosure, when including the above-described display panel, also has the above-described beneficial effects, which will not be repeated here.

[0221] This disclosure also provides a method for manufacturing a display panel, used to manufacture the display panel provided in the above embodiments, the method comprising:

[0222] A first conductive light-shielding layer is fabricated on a substrate.

[0223] At least one gate driving circuit is fabricated on a substrate, the gate driving circuit including a plurality of cascaded shift registers, the shift registers including transistor structures;

[0224] A first voltage signal input terminal is fabricated, which is used to independently input a first voltage signal;

[0225] The first conductive light-shielding layer is coupled to the first voltage signal input terminal. The orthographic projection of the first conductive light-shielding layer on the substrate overlaps with the orthographic projection of the active layer of at least a portion of the transistor structure in the shift register on the substrate.

[0226] In the display panel manufactured using the method provided in this embodiment, a first voltage signal input terminal 10 capable of independently inputting a first voltage signal is provided, and a first conductive light-shielding layer 21 is coupled to the first voltage signal input terminal 10, so that the first conductive light-shielding layer 21 has the same stable potential as the first voltage signal, enabling control of the first conductive light-shielding layer 21 to be connected to a constant positive voltage; simultaneously, the orth projection of the first conductive light-shielding layer 21 on the substrate overlaps with the orth projection of the active layer of at least a portion of the transistor structure in the shift register on the substrate, thereby enabling the first conductive light-shielding layer 21 to reduce the positive bias of Vth of the transistor structure in the shift register under an electrostatic field, ensuring the conduction characteristics of the transistor structure while minimizing the risk of leakage current; therefore, the display panel provided in the above embodiment can effectively improve the abnormal display and screen flickering phenomena that occur during electrostatic field testing.

[0227] Furthermore, in the display panel manufactured using the method provided in this embodiment, a first voltage signal input terminal 10 capable of independently inputting a first voltage signal is provided, and the first conductive light-shielding layer 21 is coupled to the first voltage signal input terminal 10, allowing the first conductive light-shielding layer 21 to be independently powered by the first voltage signal input terminal 10. This makes the power supply voltage received by the first conductive light-shielding layer 21 adjustable, better matching the characteristics of transistor structures under different process conditions, reducing the difficulty of signal debugging under different process conditions, and satisfying electrical adjustment requirements under different process conditions. In addition, the above-mentioned configuration helps reduce excessive loading of the signal transmitted by the first conductive light-shielding layer 21, avoiding the problem of discrepancies between the actual voltage and the ideal input voltage, and preventing defects such as high-brightness horizontal lines on the display panel.

[0228] It should be noted that the signal line extending in a certain direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends in a certain direction, and the length of the main part extending in a certain direction is greater than the length of the secondary part extending in other directions.

[0229] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0230] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0231] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0232] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0233] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0234] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0235] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising: A substrate and at least one gate drive circuit disposed on the substrate, the gate drive circuit comprising a plurality of shift registers cascaded, the shift registers comprising transistor structures; the display panel further comprising: a first voltage signal input end for independently inputting a first voltage signal; and a first conductive light shielding layer coupled with the first voltage signal input end, a projection of the first conductive light shielding layer on the substrate overlaps with a projection of at least part of the active layers of the transistor structures in the shift registers on the substrate.

2. The display panel of claim 1, wherein, The display panel comprises a display area and a peripheral area located at the periphery of the display area; the display panel further comprises: a first power signal input end located in the peripheral area, the first power signal input end is used for inputting a first power signal; the first power signal input end and the first voltage signal input end are independent of each other; a first power signal transmission layer extending from the display area to the peripheral area, the first power signal transmission layer is coupled with the first power signal input end.

3. The display panel of claim 2, wherein, The display panel further comprises: a plurality of sub-pixels located in the display area, the sub-pixels comprise sub-pixel drive circuits, the sub-pixel drive circuits comprise drive transistors; a second conductive light shielding layer independent of the first conductive light shielding layer, at least part of the second conductive light shielding layer is located in the display area, a projection of the second conductive light shielding layer on the substrate overlaps with a projection of the active layers of the drive transistors on the substrate; in the display area, the second conductive light shielding layer is coupled with the first power signal transmission layer.

4. The display panel of claim 1, wherein, The projection of the active layer of the transistor structure on the substrate is located inside the projection of the first conductive light shielding layer on the substrate; the minimum distance d0 between the boundary of the projection of the active layer of the transistor structure on the substrate and the boundary of the projection of the first conductive light shielding layer on the substrate satisfies: d0≥1.2μm.

5. The display panel of claim 3, wherein, The first voltage signal input end comprises a first terminal and an input line coupled with each other, the first terminal is used to provide the first voltage signal; the first conductive light shielding layer is coupled with the input line through a transmission line.

6. The display panel of claim 5, wherein, The display panel comprises at least two transmission lines, at least two gate drive circuits, and at least two first conductive light shielding layers; The projection of the active layer of at least part of the transistor structures in each gate drive circuit on the substrate is located inside the projection of the corresponding first conductive light shielding layer on the substrate; Each first conductive light shielding layer is coupled with the input line through a corresponding transmission line.

7. The display panel of claim 5, wherein, The transmission line and the input line are disposed in different layers, and are coupled through at least three vias penetrating an insulating layer between the transmission line and the input line.

8. The display panel of claim 7, wherein, At least part of the input line comprises at least two input layers arranged in sequence in a direction away from the substrate substrate; the at least two input layers are in parallel.

9. The display panel of claim 8, wherein, The display panel comprises a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer arranged in sequence in a direction away from the substrate substrate; one of the input layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer is arranged in the same layer and the same material.

10. The display panel of claim 9, wherein, The display panel further comprises a third source-drain metal layer, which is located on a side of the second source-drain metal layer away from the substrate substrate; one of the input layer and the third source-drain metal layer is arranged in the same layer and the same material.

11. The display panel of claim 5, wherein, The display panel further comprises a compensation line, which is coupled to one end of the transmission line close to the input line, and the compensation line is arranged around the display area of the display panel.

12. The display panel of claim 5, wherein, The first conductive light shielding layer comprises a plurality of first conductive light shielding patterns arranged in a first direction, and the plurality of shift registers are arranged in the first direction; the active layer of at least part of the transistor structures in the shift register has a projection on the substrate substrate, which is located inside the projection of the corresponding first conductive light shielding pattern on the substrate substrate; Adjacent first conductive light shielding patterns are coupled by at least one conductive connection. Adjacent first conductive light shielding patterns are coupled by a first conductive connection and / or a second conductive connection.

13. The display panel of claim 12, wherein, The first conductive connection is coupled to the edge of each of the two adjacent first conductive light shielding patterns away from the display area. The second conductive connection is coupled to the edge of each of the two adjacent first conductive light shielding patterns close to the display area. The shift register comprises an output transistor and a plurality of other functional transistors other than the output transistor.

14. The display panel of claim 13, wherein, The first conductive light shielding pattern comprises a first part and / or a second part, and the second part is located between the first part and the display area of the display panel. The projection of the active layer of at least part of the other functional transistors on the substrate substrate is located inside the projection of the first part on the substrate substrate; and / or, the projection of the active layer of the output transistor on the substrate substrate is located inside the projection of the second part on the substrate substrate. The first conductive connection is coupled to the edge of each of the two adjacent first conductIVE light shielding patterns away from the display area. The second conductive connection is coupled to the edge close to the display area of each of the two adjacent first conductive light shielding patterns. The projection of the active layer of all the other functional transistors on the substrate substrate is located inside the projection of the first part of the substrate substrate.

15. The display panel of claim 14, wherein, ​ 16. The display panel of claim 14, wherein, In the layout region of the shift register, the first part and the second part are independent of each other; the first part closest to the input line is coupled to the input line through a first transmission line; and the second part closest to the input line is coupled to the input line through a second transmission line.

17. The display panel of claim 14, wherein, In the layout region of the shift register, the first part and the second part are formed as an integrated structure, and the integrated structure closest to the input line is coupled to the first voltage signal input end through a common transmission line.

18. The display panel according to any one of claims 14 to 17, wherein, The display panel includes a first gate drive circuit, and the shift register includes a first shift register, the first shift register including: a first output node and a second output node, the output transistor including a first output transistor and a second output transistor, and the other functional transistor including a node control transistor; The gate of the node control transistor is coupled to the first output node, the first pole of the node control transistor is coupled to a first clock signal input end, and the second pole of the node control transistor is coupled to the second output node; the first output node is coupled to the gate of the first output transistor, and the second output node is coupled to the gate of the second output transistor; The active layer of the node control transistor has a projection on the substrate, which is located inside the projection of the first part on the substrate.

19. The display panel of claim 18, wherein, The active layer of the first output transistor has a projection on the substrate, which is located inside the projection of the second part on the substrate. The active layer of the second output transistor has a projection on the substrate, which is located inside the projection of the second part on the substrate.

20. The display panel of claim 18, wherein, The channel length L of the node control transistor satisfies: 4 μm≤L≤8 μm.

21. The display panel of claim 18, wherein, The channel width W of the first output transistor satisfies: 100 μm≤W≤200 μm.

22. The display panel of claim 18, wherein, The display panel includes a second gate drive circuit, and the second gate drive circuit includes a second shift register; the first gate drive circuit is located between the second gate drive circuit and a display area of the display panel; The display panel includes two first conductive light shielding layers, the first gate drive circuit corresponds to a first first conductive light shielding layer, and the second gate drive circuit corresponds to a second first conductive light shielding layer; In the second first conductive light shielding layer, adjacent first conductive light shielding patterns, and first and second conductive connection parts connecting the adjacent first conductive light shielding patterns together jointly form a first hollow area; In the second first conductive light shielding layer, the first conductive light shielding pattern includes a first part has a second hollow area; the area of the first hollow area is greater than the area of the second hollow area.

23. The display panel of claim 22, wherein, The first first conductive light-shielding layer includes a plurality of first conductive light-shielding patterns, and the plurality of first conductive light-shielding patterns are divided into a plurality of groups of conductive light-shielding pattern groups, each group of conductive light-shielding pattern groups including two adjacent first conductive light-shielding patterns; the two first conductive light-shielding patterns in each group of conductive light-shielding pattern groups are coupled to a same first conductive light-shielding pattern in the second first conductive light-shielding layer.

24. The display panel of claim 23, wherein, The first conductive light-shielding pattern in each group of conductive light-shielding pattern groups is coupled to the corresponding first conductive light-shielding pattern in the second first conductive light-shielding layer through a third conductive connection part; The first conductive light-shielding layer has a third hollow area between adjacent first conductive light-shielding patterns, and the third hollow area extends to between adjacent third conductive connection parts; the area of the third hollow area is greater than or equal to 1.2 times the area of the second hollow area.

25. The display panel of claim 24, wherein, The distance between adjacent third conductive connection parts in the first direction is less than the maximum length of the first conductive light-shielding pattern in the second first conductive light-shielding layer in the first direction.

26. The display panel of claim 24, wherein, The distance between adjacent third conductive connection parts in the first direction is greater than or equal to the distance between adjacent clock signal lines coupled to the gate drive circuit.

27. The display panel of claim 24, wherein, The first first conductive light-shielding layer is coupled to the first voltage signal input end through a first common transmission line, and the second first conductive light-shielding layer is coupled to the first voltage signal input end through a second common transmission line. A fourth hollow area is formed between the first common transmission line and the second common transmission line, and the area of the fourth hollow area is greater than the area of the third hollow area.

28. The display panel of claim 22, wherein, The orthogonal projection of the end of the input line coupled to the transmission line on the substrate substrate has a first distance d1 from the orthogonal projection of the second conductive light-shielding layer on the substrate substrate; The first first conductive light-shielding layer has a second distance d2 from the second conductive light-shielding layer near the boundary of the display area; The second first conductive light-shielding layer has a third distance d3 from the second conductive light-shielding layer away from the boundary of the display area; d2 < d1 ≤ d3 is satisfied. d2 ≥ 20 μm.

29. The display panel of claim 28, wherein, The orthogonal projection of the end of the input line coupled to the transmission line on the substrate substrate and the orthogonal projection of the second first conductive light-shielding layer on the substrate substrate have a fourth distance d4, and d4 ≥ d2.

30. The display panel of claim 28, wherein, The second conductive light-shielding layer includes an inner circumferential part, an outer circumferential part, and a plurality of connection parts, the inner circumferential part is coupled to the outer circumferential part through the plurality of connection parts; the inner circumferential part is located in the display area, the outer circumferential part and the plurality of connection parts are located in the peripheral area, and at least part of the outer circumferential part extends along the boundary of the display area; 31. The display panel of claim 24, wherein, The orthogonal projection of the inner circumferential part on the substrate substrate overlaps the orthogonal projection of the active layer of the drive transistor on the substrate substrate; The orthogonal projection of the connection part on the substrate substrate at least partially overlaps the orthogonal projection of the fan-out line in the display panel on the substrate substrate; ​ A projection of the connection portion on the substrate substrate at least partially overlaps with a projection of a gate unit in the display panel on the substrate substrate. A line width of the connection portion is less than a line width of the peripheral portion.

32. The display panel of claim 31, wherein, A fifth hollow area is formed between adjacent connection portions, and an area of the fifth hollow area is greater than an area of the third hollow area.

33. The display panel of claim 1, wherein, The display panel further comprises a second power bus and a cathode layer, and the second power bus is coupled with the cathode layer. A projection of the first conductive light-shielding layer on the substrate substrate is located between a projection of the second power bus on the substrate substrate and a display area of the display panel.

34. The display panel of claim 33, wherein, A minimum distance between a projection of the first conductive light-shielding layer on the substrate substrate and a projection of the second power bus on the substrate substrate is greater than or equal to 25 μm.

35. A display device comprising the display panel according to any one of claims 1-34.

36. A manufacturing method of a display panel, for manufacturing the display panel according to any one of claims 1-34, the manufacturing method comprising: manufacturing a first conductive light-shielding layer on a substrate substrate; manufacturing at least one gate driving circuit on the substrate substrate, the gate driving circuit comprising a plurality of shift registers cascaded, and the shift register comprising a transistor structure; manufacturing a first voltage signal input end for independently inputting a first voltage signal; the first conductive light-shielding layer is coupled with the first voltage signal input end, and a projection of the first conductive light-shielding layer on the substrate substrate overlaps with a projection of an active layer of at least part of the transistor structure in the shift register on the substrate substrate.

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