Shift register unit and driving method therefor, and light emission control circuit and display apparatus

Abstract

Provided are a shift register unit and a driving method therefor, and a light emission control circuit and a display apparatus, which belong to the technical field of display. The shift register unit comprises an input circuit (01) and an output circuit (02). Since the input circuit (01) can reliably and flexibly control the potentials of a pull-up node (Q) and a pull-down node (QB) under the control of received signals, the output circuit (02) can reliably output a high-potential or low-potential power source signal to an output end (OUT) under the control of the pull-up node (Q) and the pull-down node (QB). Therefore, the shift register unit can reliably output a light emission control signal to pixels by means of the output end, thereby reliably driving the pixels to emit light, such that a display effect of a display panel is relatively good.

Description

Shift register unit and its driving method, light-emitting control circuit, display device Technical Field

[0001] This application relates to the field of display technology, and in particular to a shift register unit and its driving method, a light-emitting control circuit, and a display device. Background Technology

[0002] A light-emitting control circuit is a circuit used to drive a display panel to display images. Considering the narrow bezel design, light-emitting control circuits are often integrated onto the display panel using gate-on-array (GOA) technology, and therefore can also be called a GOA circuit.

[0003] In related technologies, GOA circuits generally include cascaded multi-stage shift register units (also called GOA units). These multiple GOA units are connected to multiple rows of pixels in the display panel and are used to transmit the required light-emitting control signals to the multiple rows of pixels to drive them to emit light. Furthermore, each GOA unit generally includes multiple transistors, each of which is mostly an N-type transistor made of oxide material.

[0004] However, due to limitations in manufacturing processes and materials, current GOA units are often unable to reliably output light-emitting control signals to pixels, thus failing to reliably drive pixel light emission and resulting in poor display performance of the display panel.

[0005] Summary of the Invention

[0006] A shift register unit and its driving method, a light-emitting control circuit, and a display device are provided. The technical solution is as follows:

[0007] On the one hand, a shift register unit is provided, the shift register unit comprising:

[0008] An input circuit is connected to an input terminal, a clock terminal, a first power supply terminal, a target signal terminal, a pull-up node, and a pull-down node, respectively. It is used to control the connection and disconnection between the input terminal and the pull-up node, the connection and disconnection between the target signal terminal and the pull-down node, and the connection and disconnection between the first power supply terminal and the pull-down node, in response to an input signal provided by the input terminal, a clock signal provided by the clock terminal, a first power supply signal provided by the first power supply terminal, and a target signal provided by the target signal terminal. The target signal terminal is either a second power supply terminal or shared with the clock terminal.

[0009] The output circuit is connected to the pull-up node, the pull-down node, the third power supply terminal, the fourth power supply terminal, and the output terminal, respectively, and is used to control the connection and disconnection between the third power supply terminal and the output terminal in response to the potential of the pull-up node, and to control the connection and disconnection between the fourth power supply terminal and the output terminal in response to the potential of the pull-down node.

[0010] Optionally, the input circuit includes:

[0011] The first input sub-circuit is connected to the clock terminal, the input terminal, and the pull-up node respectively, and is used to control the on / off state of the input terminal and the pull-up node in response to the clock signal;

[0012] The second input sub-circuit is connected to the input terminal, the first power supply terminal, the clock terminal, the control terminal, the intermediate node, and the pull-down node, respectively, and is used to control the potential of the intermediate node in response to the input signal, the first power supply signal, and the clock signal, and to control the on / off state of the first power supply terminal and the pull-down node in response to the control signal provided by the control terminal; wherein, the control terminal shares the same connection with the input terminal or is connected to the pull-up node;

[0013] The third input sub-circuit is connected to the intermediate node, the target signal terminal, and the pull-down node respectively, and is used to control the on / off state of the target signal terminal and the pull-down node in response to the potential of the intermediate node.

[0014] Optionally, the second input sub-circuit includes:

[0015] The first input unit is connected to the input terminal, the first power supply terminal, the clock terminal, and the intermediate node, respectively, and is used to control the connection and disconnection between the first power supply terminal and the intermediate node in response to the input signal, and to control the potential of the intermediate node in response to the clock signal, or to control the connection and disconnection between the first power supply terminal and the intermediate node in response to the input signal and the clock signal.

[0016] The second input unit is connected to the control terminal, the first power terminal, and the pull-down node respectively, and is used to control the connection and disconnection of the first power terminal and the pull-down node in response to the control signal.

[0017] Optionally, when the first input unit controls the switching between the first power supply terminal and the intermediate node in response to the input signal, and controls the potential of the intermediate node in response to the clock signal, the first input unit includes: a first transistor and a first capacitor; and the gate of the first transistor is connected to the input terminal, the first electrode of the first transistor is connected to the first power supply terminal, the second electrode of the first transistor is connected to the intermediate node, one end of the first capacitor is connected to the clock terminal, and the other end of the first capacitor is connected to the intermediate node;

[0018] When the first input unit controls the on / off state of the first power supply terminal and the intermediate node in response to the input signal and the clock signal, the first input unit includes: a first transistor and a second transistor; and the gate of the first transistor is connected to the input terminal, the first electrode of the first transistor is connected to the first power supply terminal, the second electrode of the first transistor is connected to the first electrode of the second transistor, the gate of the second transistor is connected to the clock terminal, and the second electrode of the second transistor is connected to the intermediate node.

[0019] The second input unit includes a third transistor; and the gate of the third transistor is connected to the control terminal, the first terminal of the third transistor is connected to the first power supply terminal, and the second terminal of the third transistor is connected to the pull-down node.

[0020] Optionally, the first transistor includes two first sub-transistors with their first and second terminals connected in series; the third transistor includes two second sub-transistors with their first and second terminals connected in series; the shift register unit further includes:

[0021] A first control circuit is connected to the intermediate node, the fifth power supply terminal, the series node of the two first sub-transistors, and the series node of the two second sub-transistors, respectively, and is used to control the on / off state of the fifth power supply terminal and the connected series node in response to the potential of the intermediate node.

[0022] Optionally, the first control circuit includes: a fourth transistor;

[0023] Furthermore, the gate of the fourth transistor is connected to the intermediate node, the first terminal of the fourth transistor is connected to the fifth power supply terminal, and the second terminal of the fourth transistor is connected to the series node of the two first sub-transistors and the series node of the two second sub-transistors.

[0024] Optionally, the first input sub-circuit includes: a fifth transistor;

[0025] Furthermore, the gate of the fifth transistor is connected to the clock terminal, the first terminal of the fifth transistor is connected to the input terminal, and the second terminal of the fifth transistor is connected to the pull-up node.

[0026] Optionally, the third input sub-circuit includes: a sixth transistor;

[0027] Furthermore, the gate of the sixth transistor is connected to the intermediate node, the first terminal of the sixth transistor is connected to the target signal terminal, and the second terminal of the sixth transistor is connected to the pull-down node.

[0028] Optionally, the pull-up node includes: a first pull-up node and a second pull-up node; the input circuit is connected to the first pull-up node, and the output circuit is connected to the second pull-up node; the shift register unit further includes:

[0029] The second control circuit is connected to the sixth power supply terminal, the first pull-up node and the second pull-up node respectively, and is used to control the on and off of the first pull-up node and the second pull-up node in response to the sixth power supply signal provided by the sixth power supply terminal.

[0030] And / or,

[0031] The pull-down node includes: a first pull-down node and a second pull-down node; the input circuit is connected to the first pull-down node, and the output circuit is connected to the second pull-down node; the shift register unit further includes:

[0032] The third control circuit is connected to the clock terminal, the first pull-down node, and the second pull-down node respectively, and is used to control the on / off state of the first pull-down node and the second pull-down node in response to the clock signal.

[0033] Optionally, the second control circuit includes a seventh transistor; the third control circuit includes an eighth transistor.

[0034] Furthermore, the gate of the seventh transistor is connected to the sixth power supply terminal, the first terminal of the seventh transistor is connected to the first pull-up node, and the second terminal of the seventh transistor is connected to the second pull-up node;

[0035] The gate of the eighth transistor is connected to the clock terminal, the first terminal of the eighth transistor is connected to the first pull-down node, and the second terminal of the eighth transistor is connected to the second pull-down node.

[0036] Optionally, the shift register unit further includes:

[0037] A reset circuit is connected to a reset control terminal, a reset power supply terminal, and the second pull-down node, respectively, and is used to control the on / off state of the reset power supply terminal and the second pull-down node in response to a reset control signal provided by the reset control terminal; wherein the reset power supply terminal is shared with the third power supply terminal or the fourth power supply terminal.

[0038] Optionally, the reset circuit includes: a ninth transistor;

[0039] The gate of the ninth transistor is connected to the reset control terminal, the first terminal of the ninth transistor is connected to the reset power supply terminal, and the second terminal of the ninth transistor is connected to the second pull-down node.

[0040] Optionally, the output circuit includes: a tenth transistor, a second capacitor, an eleventh transistor, and a third capacitor;

[0041] Furthermore, the gate of the tenth transistor is connected to the pull-up node, the first terminal of the tenth transistor is connected to the third power supply terminal, and the second terminal of the tenth transistor is connected to the output terminal;

[0042] One end of the second capacitor is connected to the pull-up node, and the other end of the second capacitor is connected to the output terminal;

[0043] The gate of the eleventh transistor is connected to the pull-down node, the first terminal of the eleventh transistor is connected to the fourth power supply terminal, and the second terminal of the eleventh transistor is connected to the output terminal.

[0044] One end of the third capacitor is connected to the pull-down node, and the other end of the third capacitor is connected to the fourth power supply terminal.

[0045] Optionally, the eleventh transistor includes two third sub-transistors connected in series with their first and second terminals; the shift register unit further includes:

[0046] The fourth control circuit is connected to the output terminal, the seventh power supply terminal, and the series node of the two third sub-transistors, respectively, and is used to control the on / off state of the seventh power supply terminal and the connected series node in response to the signal output through the output terminal.

[0047] Optionally, the fourth control circuit includes: a twelfth transistor;

[0048] The gate of the twelfth transistor is connected to the output terminal, the first terminal of the twelfth transistor is connected to the seventh power supply terminal, and the second terminal of the twelfth transistor is connected to the series node of the two third sub-transistors.

[0049] Optionally, the output terminal includes: a shift output terminal and a drive output terminal, wherein the shift output terminal is used to connect to other cascaded shift register units, and the drive output terminal is used to connect to pixels in the display panel; furthermore, the output circuit is also connected to an eighth power supply terminal and a ninth power supply terminal; the output circuit includes:

[0050] The first output sub-circuit is connected to the pull-up node, the pull-down node, the third power supply terminal, the fourth power supply terminal, and the shift output terminal, respectively, and is used to control the on / off state of the third power supply terminal and the shift output terminal in response to the potential of the pull-up node, and to control the on / off state of the fourth power supply terminal and the shift output terminal in response to the potential of the pull-down node.

[0051] The second output sub-circuit is connected to the pull-up node, the pull-down node, the eighth power supply terminal, the ninth power supply terminal, and the drive output terminal, respectively. It is used to control the connection and disconnection between the eighth power supply terminal and the drive output terminal in response to the potential of the pull-up node, and to control the connection and disconnection between the ninth power supply terminal and the drive output terminal in response to the potential of the pull-down node.

[0052] Optionally, the potential of the ninth power signal provided by the ninth power terminal is less than the potential of the fourth power signal provided by the fourth power terminal.

[0053] Optionally, the first output sub-circuit includes: a tenth transistor, a second capacitor, an eleventh transistor, and a third capacitor; the second output sub-circuit includes: a twelfth transistor and a thirteenth transistor;

[0054] Furthermore, the gate of the tenth transistor is connected to the pull-up node, the first terminal of the tenth transistor is connected to the third power supply terminal, and the second terminal of the tenth transistor is connected to the shift output terminal.

[0055] One end of the second capacitor is connected to the pull-up node, and the other end of the second capacitor is connected to the shift output terminal;

[0056] The gate of the eleventh transistor is connected to the pull-down node, the first terminal of the eleventh transistor is connected to the fourth power supply terminal, and the second terminal of the eleventh transistor is connected to the shift output terminal.

[0057] One end of the third capacitor is connected to the pull-down node, and the other end of the third capacitor is connected to the fourth power supply terminal.

[0058] The gate of the twelfth transistor is connected to the pull-up node, the first terminal of the twelfth transistor is connected to the eighth power supply terminal, and the second terminal of the twelfth transistor is connected to the drive output terminal.

[0059] The gate of the thirteenth transistor is connected to the pull-down node, the first terminal of the thirteenth transistor is connected to the ninth power supply terminal, and the second terminal of the thirteenth transistor is connected to the drive output terminal.

[0060] On the other hand, a method for driving a shift register unit is provided, for driving the shift register unit as described in the above aspect; the method includes:

[0061] In the first stage, the input circuit responds to the input signal provided by the input terminal, the clock signal provided by the clock terminal, the first power signal provided by the first power supply terminal, and the target signal provided by the target signal terminal, controlling the input terminal to be connected to the pull-up node, controlling the target signal terminal to be disconnected from the pull-down node, and controlling the first power supply terminal to be connected to the pull-down node. The output circuit responds to the potential of the pull-up node, controlling the third power supply terminal to be connected to the output terminal, and responds to the potential of the pull-down node, controlling the fourth power supply terminal to be disconnected from the output terminal.

[0062] In the second stage, the input circuit responds to the input signal, the clock signal, the first power signal, and the target signal by controlling the input terminal to be connected to the pull-up node, controlling the target signal terminal to be connected to the pull-down node, and controlling the first power terminal to be disconnected from the pull-down node. The output circuit responds to the potential of the pull-up node by controlling the third power terminal to be disconnected from the output terminal, and responds to the potential of the pull-down node by controlling the fourth power terminal to be connected to the output terminal.

[0063] In another aspect, a light-emitting control circuit is provided, the light-emitting control circuit comprising: cascaded multi-stage shift register units as described in the above aspect.

[0064] In another aspect, a display device is provided, the display device comprising: a display panel, and a light-emitting control circuit as described in yet another aspect above; the display panel comprising a plurality of pixels;

[0065] The light emission control circuit is connected to the plurality of pixels via its output terminal and is used to transmit light emission control signals to the plurality of pixels to drive the plurality of pixels to emit light. Attached Figure Description

[0066] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0067] Figure 1 is a schematic diagram of the structure of a shift register unit provided in an embodiment of this application;

[0068] Figure 2 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0069] Figure 3 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0070] Figure 4 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0071] Figure 5 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0072] Figure 6 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0073] Figure 7 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0074] Figure 8 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0075] Figure 9 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0076] Figure 10 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0077] Figure 11 is a schematic diagram of the structure of a shift register control module in a shift register unit provided in an embodiment of this application;

[0078] Figure 12 is a schematic diagram of the shift register control module in another shift register unit provided in an embodiment of this application;

[0079] Figure 13 is a schematic diagram of the shift register control module in another shift register unit provided in an embodiment of this application;

[0080] Figure 14 is a schematic diagram of the shift register control module in another shift register unit provided in an embodiment of this application;

[0081] Figure 15 is a schematic diagram of the shift register control module in another shift register unit provided in an embodiment of this application;

[0082] Figure 16 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0083] Figure 17 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0084] Figure 18 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0085] Figure 19 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0086] Figure 20 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0087] Figure 21 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0088] Figure 22 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0089] Figure 23 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0090] Figure 24 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0091] Figure 25 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0092] Figure 26 is a flowchart illustrating a method for driving a shift register unit according to an embodiment of this application;

[0093] Figure 27 is a schematic diagram of the driving timing of a shift register unit provided in an embodiment of this application;

[0094] Figure 28 is a schematic diagram of the driving timing of another shift register unit provided in an embodiment of this application;

[0095] Figure 29 is a schematic diagram of a light-emitting control circuit provided in an embodiment of this application;

[0096] Figure 30 is a schematic diagram of another light-emitting control circuit provided in an embodiment of this application;

[0097] Figure 31 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0098] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0099] It should be noted that the transistors used in the embodiments of this application can be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. An example of a FET is a metal-oxide-semiconductor (MOS) FET, also known as a MOS transistor. Furthermore, based on their function in the circuit, the transistors used in the embodiments of this application are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains are interchangeable. In the embodiments of this application, the source can be referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the control electrode, also known as the gate; the signal input terminal is the source, and the signal output terminal is the drain. In addition, the switching transistors used in the embodiments of this application can include either P-type transistors or N-type transistors. A P-type transistor conducts when the gate is at a low potential and is cut off when the gate is at a high potential; an N-type transistor conducts when the gate is at a high potential and is cut off when the gate is at a low potential. Furthermore, multiple signals in the various embodiments of this application correspond to a first potential and a second potential. The first potential can refer to an effective potential, and the second potential can refer to an ineffective potential. Furthermore, the first potential and the second potential only represent that the potential of the signal has two state variables, and do not mean that the first potential or the second potential has a specific value throughout the text.

[0100] In the display field, especially in organic light-emitting diode (OLED) displays, backplanes have gradually transitioned from amorphous silicon (a-Si) to oxide and then to low-temperature polycrystalline oxide (LTPO). All-oxygen TFT backplanes will also be a future technological route for display development. Here, "material" refers to the material of the transistors in the backplane, and the example transistor is the one included in a GOA (Glass On-Area) circuit.

[0101] Specifically, the threshold voltage (Vth) of transistors fabricated from oxide materials is generally between 0.4 volts (V) and 1 V. Under long-term bias temperature stress (BTS) operating conditions, especially negative bias stress (NBTS), Vth may become negatively biased. When Vth is less than or equal to 0, the transistor exhibits leakage current under off-state conditions, causing the GOA circuit, which includes the transistor, to fail to reliably output the required signal to the pixel. For example, the signal output by the GOA circuit is prone to step-like patterns. Consequently, the GOA circuit cannot reliably drive the pixel to emit light, affecting the yield of the display panel and resulting in poor display quality. Here, the signal output by the GOA circuit can be the light emission control signal (EM) output by the light-emitting control transistor in the pixel circuit included with the pixel.

[0102] Based on this, this application proposes a stepless and leakage-proof oxide TFT EM GOA circuit (i.e., a GOA circuit capable of outputting a light emission control signal EM and whose transistors are oxide TFT transistors) based on an all-oxide TFT architecture to improve the yield and display effect of the display panel. The GOA circuit includes multiple cascaded GOA units. Of course, in some other embodiments, it is not limited to an all-oxide TFT architecture, nor is it limited to outputting a light emission control signal EM.

[0103] Figure 1 is a schematic diagram of a shift register unit (i.e., a GOA unit) provided in an embodiment of this application. As shown in Figure 1, the shift register unit includes an input circuit 01 and an output circuit 02.

[0104] Input circuit 01 is connected to input terminal IN, clock terminal CK, first power supply terminal V1, target signal terminal Vo, pull-up node Q, and pull-down node QB, respectively. Furthermore, input circuit 01 is used to control the on / off state of input terminal IN and pull-up node Q, control the on / off state of target signal terminal Vo and pull-down node QB, and control the on / off state of first power supply terminal V1 and pull-down node QB, in response to the input signal provided by input terminal IN, the clock signal provided by clock terminal CK, the first power supply signal provided by first power supply terminal V1, and the target signal provided by target signal terminal Vo.

[0105] The target signal terminal Vo is either the second power supply terminal V2 or shared with the clock terminal CK. That is, the target signal terminal Vo can be a separate second power supply terminal V2, and the target signal can be the second power supply signal provided by the second power supply terminal V2; or, the target signal terminal Vo can be the clock terminal CK, and the target signal can be the clock signal provided by the clock terminal CK.

[0106] Optionally, the clock signal provided by the clock terminal CK can be a periodic pulse signal. The potential of the first power supply signal provided by the first power supply terminal V1 can be a low potential, and the potential of the second power supply signal provided by the second power supply terminal V2 can be a high potential. Correspondingly, the first power supply terminal V1 can also be called the pull-down power supply terminal VGL, and the second power supply terminal V2 can also be called the pull-up power supply terminal VGH. Furthermore, each transistor described in the following embodiments can be an N-type transistor, and correspondingly, the first potential (i.e., the effective potential) can be a high potential, and the second potential (i.e., the ineffective potential) can be a low potential. Here, high potential and low potential are relative.

[0107] For example, referring to Figure 1, the target signal terminal Vo is shown as the second power supply terminal V2. Based on this, the input circuit 01 can control the input terminal IN to be connected to the pull-up node Q when the potential of the input signal provided by the input terminal IN is a first potential (e.g., a high potential) and the potential of the clock signal provided by the clock terminal CK is a high potential. It can also control the second power supply terminal V2, as the target signal terminal Vo, to be disconnected from the pull-down node QB, and control the first power supply terminal V1 to be connected to the pull-down node QB. This allows the high-potential input signal provided by the input terminal IN to be transmitted to the pull-up node Q, and allows the low-potential first power supply signal provided by the first power supply terminal V1 to be transmitted to the pull-down node QB. Input circuit 01 can control input terminal IN to conduct with pull-up node Q when the input signal provided by input terminal IN is at a second potential (e.g., low potential) and the clock signal provided by clock terminal CK is at a high potential. It can also control the second power supply terminal V2 as the target signal terminal Vo to conduct with pull-down node QB, and control the first power supply terminal V1 to disconnect from pull-down node QB. This allows the low-potential input signal provided by input terminal IN to be transmitted to pull-up node Q, and the high-potential second power supply signal provided by second power supply terminal V2 to be transmitted to pull-down node QB. Accordingly, input circuit 01 can also be called a control circuit. Of course, this is only an illustrative explanation of part of the control method of input circuit 01.

[0108] Output circuit 02 is connected to pull-up node Q, pull-down node QB, third power supply terminal V3, fourth power supply terminal V4, and output terminal OUT. Furthermore, output circuit 02 controls the switching between the third power supply terminal V3 and output terminal OUT in response to the potential of pull-up node Q, and controls the switching between the fourth power supply terminal V4 and output terminal OUT in response to the potential of pull-down node QB.

[0109] Optionally, the potential of the third power signal provided by the third power supply terminal V3 can be a high potential, and the potential of the fourth power signal provided by the fourth power supply terminal V4 can be a low potential. Correspondingly, the third power supply terminal V3 can also be called the pull-up power supply terminal VGH, and the fourth power supply terminal V4 can also be called the pull-down power supply terminal VGL. Furthermore, the third power supply terminal V3 and the second power supply terminal V2 can be shared or independent of each other. Similarly, the fourth power supply terminal V4 and the first power supply terminal V1 can be shared or independent of each other. That is, the power supply terminal connected to the input circuit 01 can be the power supply terminal connected to the output circuit 02, or it can be an additional power supply terminal. In other words, the power supply terminal connected to the input circuit 01 and the power supply terminal connected to the output circuit 02 can be the same power supply terminal; or the power supply terminal connected to the input circuit 01 and the power supply terminal connected to the output circuit 02 can be different power supply terminals.

[0110] A shared power supply terminal simplifies wiring, saving costs and facilitating narrow bezel designs. Wiring here refers to laying out the power lines connected to the power supply terminal on the display panel, providing the necessary power signals. Other terminals can similarly be connected to signal lines that provide the required signals. For example, the clock terminal CK can be connected to a clock signal line to receive the clock signal. Setting each power supply terminal independently ensures that the power signals received by the input circuit 01 and the output circuit 02 do not interfere with each other, thus ensuring reliable operation of both the input circuit 01 and the output circuit 02, allowing the shift register unit to reliably output signals to the output terminal OUT. The effects of sharing or separating other power supplies as described in the following embodiments are similar and will not be elaborated upon individually.

[0111] For example, output circuit 02 can control the third power supply terminal V3 to conduct with output terminal OUT when the potential of pull-up node Q is at a first potential (e.g., high potential), allowing the high-potential third power supply signal provided by the third power supply terminal V3 to be transmitted to output terminal OUT; and can control the third power supply terminal V3 to disconnect from output terminal OUT when the potential of pull-up node Q is at a second potential (e.g., low potential). Similarly, output circuit 02 can control the fourth power supply terminal V4 to conduct with output terminal OUT when the potential of pull-down node QB is at a first potential (e.g., high potential), allowing the low-potential fourth power supply signal provided by the fourth power supply terminal V4 to be transmitted to output terminal OUT; and can control the fourth power supply terminal V4 to disconnect from output terminal OUT when the potential of pull-down node QB is at a second potential (e.g., low potential). In this way, output circuit 02 can output signals with both high and low potentials via output terminal OUT.

[0112] Optionally, the output terminal OUT can be connected to a pixel. Correspondingly, the signal output from OUT can be transmitted to the pixel as a light emission control signal to drive the pixel to emit light. Furthermore, OUT can also be connected to the input terminal IN of other cascaded shift register units to transmit the required input signals to the input terminals IN of those units. Of course, the input terminal IN of the first-stage shift register unit can be connected to an additional enable signal line STV to receive the start signal provided by STV.

[0113] Based on the above description, the input circuit 01 provided in this application embodiment can transmit signals to the pull-up node Q and pull-down node QB under the control of the signals provided by the connected signal terminals, thereby controlling the potential of the pull-up node Q and the potential of the pull-down node QB. The output circuit 02 can transmit high-potential and low-potential power signals to the output terminal OUT under the control of the potential of the pull-up node Q and the pull-down node QB. In this way, signal output of the shift register unit can be realized. Furthermore, the sign of the pulse of the input signal provided by the input terminal IN can determine the sign of the pulse of the signal output by the shift register unit through the output terminal OUT.

[0114] In summary, this application provides a shift register unit. This shift register unit includes an input circuit and an output circuit. Because the input circuit can reliably and flexibly control the potentials of the pull-up and pull-down nodes under the control of various received signals, the output circuit can reliably output high or low potential power signals to the output terminal under the control of the pull-up and pull-down nodes. Therefore, this shift register unit can reliably output light-emitting control signals to the pixels via the output terminal, thereby reliably driving the pixels to emit light and resulting in better display effects on the display panel.

[0115] Optionally, Figure 2 is a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 2, the input circuit 01 may include: a first input sub-circuit 011, a second input sub-circuit 012, and a third input sub-circuit 013.

[0116] The first input sub-circuit 011 can be connected to the clock terminal CK, the input terminal IN, and the pull-up node Q, respectively. Furthermore, the first input sub-circuit 011 can be used to control the on / off state of the input terminal IN and the pull-up node Q in response to a clock signal. That is, the first input sub-circuit 011 can be used to control the potential of the pull-up node Q.

[0117] For example, the first input sub-circuit 011 can control the input terminal IN to be connected to the pull-up node Q when the clock signal potential is a first potential (e.g., high potential), so that the input signal provided by the input terminal IN can be transmitted to the pull-up node Q; and can control the input terminal IN to be disconnected from the pull-up node Q when the clock signal potential is a second potential (e.g., low potential).

[0118] The second input sub-circuit 012 can be connected to the input terminal IN, the first power supply terminal V1, the clock terminal CK, the control terminal Con, the intermediate node Q0, and the pull-down node QB, respectively. Furthermore, the second input sub-circuit 012 can control the potential of the intermediate node Q0 in response to the input signal, the first power supply signal, and the clock signal, and control the on / off state of the first power supply terminal V1 and the pull-down node QB in response to the control signal provided by the control terminal Con.

[0119] The control terminal Con can be shared with the input terminal IN or connected to the pull-up node Q. That is, the control terminal Con can be the input terminal IN, and correspondingly, the control signal provided by the control terminal Con can be the input signal provided by the input terminal IN. Alternatively, the control terminal Con can be connected to the pull-up node Q, and correspondingly, the control signal provided by the control terminal Con can be the signal transmitted to the pull-up node Q. In other words, the second input sub-circuit 012 can be used to control the potentials of the intermediate node Q0 and the pull-down node QB.

[0120] For example, the second input sub-circuit 012 can control the potential of intermediate node Q0 to be low in response to a high-level input signal, a low-level first power supply signal, and a low-level clock signal when the potential of the input signal is a first potential (e.g., high potential) and the potential of the clock signal is a second potential (e.g., low potential); and can control the potential of intermediate node Q0 to be high in response to a low-level input signal, a low-level first power supply signal, and a high-level clock signal when the potential of the input signal is a second potential (e.g., low potential) and the potential of the clock signal is a first potential (e.g., high potential).

[0121] For example, the control terminal Con shown in Figure 2 can be the input terminal IN, and correspondingly, the control signal provided by the control terminal Con is the input signal provided by the input terminal IN. Based on this, the second input sub-circuit 012 can also control the first power supply terminal V1 to conduct with the pull-down node QB when the potential of the input signal (i.e., the control signal) provided by the input terminal IN is a first potential (e.g., a high potential), so that the low-potential first power signal provided by the first power supply terminal V1 can be transmitted to the pull-down node QB; and can control the first power supply terminal V1 to disconnect from the pull-down node QB when the potential of the input signal (i.e., the control signal) provided by the input terminal IN is a second potential (e.g., a low potential).

[0122] The third input sub-circuit 013 can be connected to the intermediate node Q0, the target signal terminal Vo (i.e., the clock terminal CK or the second power supply terminal V2), and the pull-down node QB, respectively. Furthermore, this third input sub-circuit 013 can be used to control the on / off state of the target signal terminal Vo and the pull-down node QB in response to the potential of the intermediate node Q0. That is, the third input sub-circuit 013 can also be used to control the potential of the pull-down node QB.

[0123] For example, the target signal terminal Vo shown in Figure 2 is the second power supply terminal V2. Based on this, the third input sub-circuit 013 can control the second power supply terminal V2 as the target signal terminal Vo to be connected to the pull-down node QB when the potential of the intermediate node Q0 is the first potential (e.g., high potential), so that the high potential second power signal provided by the second power supply terminal V2 can be transmitted to the pull-down node QB; and can control the second power supply terminal V2 as the target signal terminal Vo to be disconnected from the pull-down node QB when the potential of the intermediate node Q0 is the second potential (e.g., low potential).

[0124] Optionally, Figure 3 is a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 3, the second input sub-circuit 012 may include: a first input unit 0121 and a second input unit 0122.

[0125] The first input unit 0121 can be connected to the input terminal IN, the first power supply terminal V1, the clock terminal CK, and the intermediate node Q0, respectively. Furthermore, the first input unit 0121 can be used to control the on / off state of the first power supply terminal V1 and the intermediate node Q0 in response to an input signal, and to control the potential of the intermediate node Q0 in response to a clock signal; alternatively, the first input unit 0121 can be used to control the on / off state of the first power supply terminal V1 and the intermediate node Q0 in response to both an input signal and a clock signal. In other words, the first input unit 0121 can be used to control the potential of the intermediate node Q0 through at least two control methods.

[0126] For example, in the first control method: the first input unit 0121 can control the first power supply terminal V1 to conduct with the intermediate node Q0 when the potential of the input signal is a first potential (e.g., high potential), so that the low-potential first power signal provided by the first power supply terminal V1 can be transmitted to the intermediate node Q0; and can control the first power supply terminal V1 to disconnect from the intermediate node Q0 when the potential of the input signal is a second potential (e.g., low potential). Furthermore, the first input unit 0121 can control the potential of the intermediate node Q0 to be high when the potential of the clock signal is a first potential (e.g., high potential); and can control the potential of the intermediate node Q0 to be low when the potential of the clock signal is a second potential (e.g., low potential).

[0127] For example, in the second control method: the first input unit 0121 can control the first power supply terminal V1 to conduct with the intermediate node Q0 when the potential of the input signal and the potential of the clock signal are both at a first potential (e.g., high potential), so that the low potential first power signal provided by the first power supply terminal V1 can be transmitted to the intermediate node Q0; and can control the first power supply terminal V1 to disconnect from the intermediate node Q0 when the potential of the input signal and / or the potential of the clock signal are at a second potential (e.g., low potential).

[0128] The second input unit 0122 can be connected to the control terminal Con (i.e., input terminal IN or connected to the pull-up node Q), the first power supply terminal V1, and the pull-down node QB, respectively. Furthermore, the second input unit 0122 can be used to control the on / off state of the first power supply terminal V1 and the pull-down node QB in response to a control signal. That is, the second input unit 0122 can be used to control the potential of the pull-down node QB.

[0129] For example, the control terminal Con shown in Figure 3 is also the input terminal IN. Correspondingly, the control signal provided by the control terminal Con is the input signal provided by the input terminal IN. Based on this, the second input unit 0122 can control the first power supply terminal V1 to conduct with the pull-down node QB when the potential of the input signal (i.e., the control signal) provided by the input terminal IN is a first potential (e.g., a high potential), so that the low-potential first power signal provided by the first power supply terminal V1 can be transmitted to the pull-down node QB; and can control the first power supply terminal V1 to disconnect from the pull-down node QB when the potential of the input signal (i.e., the control signal) provided by the input terminal IN is a second potential (e.g., a low potential).

[0130] Optionally, in the case where the first input unit 0121 controls the switching between the first power supply terminal V1 and the intermediate node Q0 in response to the input signal, and controls the potential of the intermediate node Q0 in response to the clock signal, that is, based on the first control method described above, as shown in Figure 4, in an implementation corresponding to the first control method:

[0131] The first input unit 0121 may include a first transistor T1 and a first capacitor C1. The gate of the first transistor T1 may be connected to the input terminal IN, the first terminal of the first transistor T1 may be connected to the first power supply terminal V1, and the second terminal of the first transistor T1 may be connected to the intermediate node Q0. One end of the first capacitor C1 may be connected to the clock terminal CK, and the other end of the first capacitor C1 may be connected to the intermediate node Q0.

[0132] Optionally, when the first input unit 0121 controls the switching between the first power supply terminal V1 and the intermediate node Q0 in response to the input signal and the clock signal, that is, based on the second control method described above, as shown in Figure 5, in another implementation corresponding to the second control method:

[0133] The first input unit 0121 may include a first transistor T1 and a second transistor T2. Furthermore, the gate of the first transistor T1 may be connected to the input terminal IN, the first electrode of the first transistor T1 may be connected to the first power supply terminal V1, the second electrode of the first transistor T1 may be connected to the first electrode of the second transistor T2, the gate of the second transistor T2 may be connected to the clock terminal CK, and the second electrode of the second transistor T2 may be connected to the intermediate node Q0.

[0134] Optionally, referring to Figures 4 and 5, the second input unit 0122 may include a third transistor T3. Furthermore, the gate of the third transistor T3 can be connected to the control terminal Con, the first terminal of the third transistor T3 can be connected to the first power supply terminal V1, and the second terminal of the third transistor T3 can be connected to the pull-down node QB. For example, the control terminal Con shown in Figures 4 and 5 is the input terminal IN.

[0135] Optionally, referring to Figures 4 and 5, the first transistor T1 may include two first sub-transistors T11 and T12 connected in series with their first and second terminals. The third transistor T3 may include two second sub-transistors T31 and T32 connected in series with their first and second terminals. That is, the first transistor T1 and the third transistor T3 can be transistors with a dual-gate structure or a dual-TFT series architecture.

[0136] In this configuration, the gates of both first sub-transistors T11 and T12 can be connected to the input terminal IN. The first terminal of the first sub-transistor T11 can be connected to the first power supply terminal V1, and the second terminal of the first sub-transistor T11 can be connected to the first terminal of the first sub-transistor T12. The second terminal of the first sub-transistor T12 can be connected to the intermediate node Q0 or the first terminal of the second sub-transistor T2. Similarly, the gates of both second sub-transistors T31 and T32 can be connected to the control terminal Con (e.g., the input terminal IN). The first terminal of the second sub-transistor T31 can be connected to the first power supply terminal V1, and the second terminal of the second sub-transistor T31 can be connected to the first terminal of the second sub-transistor T32. The second terminal of the second sub-transistor T32 can be connected to the pull-down node QB.

[0137] Furthermore, based on this, referring to Figures 4 and 5, it can be seen that the shift register unit may also include: a first control circuit 03.

[0138] The first control circuit 03 can be connected to the intermediate node Q0, the fifth power supply terminal V5, the series node P1 of the two first sub-transistors T11 and T12, and the series node P2 of the two second sub-transistors T31 and T32. Furthermore, the first control circuit 03 can be used to control the switching on and off of the fifth power supply terminal V5 and the connected series nodes (i.e., P1 & P2) in response to the potential of the intermediate node Q0. Based on this connection, it can also be seen that the series node P1 of the two first sub-transistors T11 and T12 and the series node P2 of the two second sub-transistors T31 and T32 are also interconnected. That is, the first control circuit 03 can be used to control the potential of the series nodes P1 & P2.

[0139] Optionally, the potential of the fifth power signal provided by the fifth power terminal V5 can be a high potential. Correspondingly, the fifth power terminal V5 can also be referred to as the pull-up power terminal VGH. Furthermore, the fifth power terminal V5 can be independent of other power terminals (e.g., the second power terminal V2 / the third power terminal V3). That is, the fifth power terminal V5 can be a separate power terminal, which can be connected to a separate power line. Alternatively, the fifth power terminal V5 can be set as GVGH (i.e., Global VGH). Of course, in some other embodiments, the fifth power terminal V5 can also be shared with the other power terminals (e.g., the second power terminal V2 / the third power terminal V3).

[0140] As is understandable, VGH typically refers to the high-voltage source used to drive the display panel, primarily for controlling the panel's on / off state and brightness. GVGH, on the other hand, can refer to an additional, independent voltage source distinct from VGH, usually powered by a separate voltage source.

[0141] For example, the first control circuit 03 can control the fifth power supply terminal V5 to conduct with the series nodes P1 & P2 when the potential of the intermediate node Q0 is a first potential (e.g., high potential), so that the high potential fifth power signal provided by the fifth power supply terminal V5 can be transmitted to the series nodes P1 & P2; and can control the fifth power supply terminal V5 to disconnect from the series nodes P1 & P2 when the potential of the intermediate node Q0 is a second potential (e.g., low potential).

[0142] It is understandable that, taking the first transistor T1 as an example, by setting this transistor as a dual-gate structure, the leakage problem that exists during the turn-on process can be effectively reduced, ensuring that the potential of the intermediate node Q0 can be reliably controlled by this transistor, thereby ensuring that the shift register unit can reliably output a signal to the output terminal OUT. The leakage problem is usually caused by the input signal received by the gate of the first transistor T1 having a rising edge from low potential to high potential and a falling edge from high potential to low potential, resulting in a conflict with the potential of the intermediate node Q0. Setting the third transistor T3 as a dual-gate structure transistor has the same effect, ensuring that the potential of the pull-down node QB can be reliably controlled by this transistor, which will not be elaborated further here. Of course, in some other embodiments, the first transistor T1 and / or the third transistor T3 can also be single-gate structure transistors like the second transistor T2.

[0143] Furthermore, by configuring both the first transistor T1 and the third transistor T3 as dual-gate transistors, the shift register unit also includes a first control circuit 03 to perform the aforementioned functions. This prevents the first power supply terminal V1 from mistakenly connecting with the intermediate node Q1 and the pull-down node QB when the potential of the signal received at the gate changes abruptly or becomes unstable, thus preventing leakage of the low-potential first power supply signal to the intermediate node Q1 and the pull-down node QB. In other words, it further enhances the leakage protection capability, ensuring better potential stability of the intermediate node Q1 and the pull-down node QB, thereby further ensuring that the shift register unit can reliably output a signal to the output terminal OUT.

[0144] Furthermore, as mentioned earlier, by making the fifth power terminal V5 independent of the other power terminals, interference between the power signals provided by the power terminals can be avoided, thus preventing leakage current from occurring and improving leakage current protection. Conversely, sharing the fifth power terminal V5 with the other power terminals simplifies wiring, saves costs, and facilitates narrow bezel designs.

[0145] Optionally, based on Figure 4, Figure 6 shows a schematic diagram of another shift register unit provided in an embodiment of this application. Referring to Figure 6, it can be seen that the first control circuit 03 may include: a fourth transistor T4.

[0146] Furthermore, the gate of the fourth transistor T4 can be connected to the intermediate node Q0, the first terminal of the fourth transistor T4 can be connected to the fifth power supply terminal V5, and the second terminal of the fourth transistor T4 can be connected to the series node P1 of the two first sub-transistors T11 and T12 and the series node P2 of the two second sub-transistors T31 and T32.

[0147] Optionally, the fourth transistor T4 can be a single-gate structure or a dual-gate structure. Setting the fourth transistor T4 to a dual-gate structure can further improve leakage current protection.

[0148] Optionally, referring to Figures 4 through 6, it can be seen that the first input sub-circuit 011 may include a fifth transistor T5. The third input sub-circuit 013 may include a sixth transistor T6.

[0149] Furthermore, the gate of the fifth transistor T5 can be connected to the clock terminal CK, the first terminal of the fifth transistor T5 can be connected to the input terminal IN, and the second terminal of the fifth transistor T5 can be connected to the pull-up node Q.

[0150] The gate of the sixth transistor T6 can be connected to the intermediate node Q0, the first terminal of the sixth transistor T6 can be connected to the target signal terminal Vo, and the second terminal of the sixth transistor T6 can be connected to the pull-down node QB. For example, the target signal terminal Vo shown in Figures 4 to 6 is the second power supply terminal V2.

[0151] Optionally, based on Figure 6, Figure 7 shows a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 7, the pull-up node Q may include: a first pull-up node Q1 and a second pull-up node Q2. The input circuit 01 may be connected to the first pull-up node Q1, and the output circuit 02 may be connected to the second pull-up node Q2. That is, the input circuit 01 can control the potential of the first pull-up node Q1; while the output circuit 02 can output a signal to the output terminal OUT under the control of the potential of the second pull-up node Q2.

[0152] Based on this, referring to Figure 7, it can also be seen that the shift register unit may include: a second control circuit 04.

[0153] The second control circuit 04 can be connected to the sixth power supply terminal V6, the first pull-up node Q1, and the second pull-up node Q2, respectively. Furthermore, the second control circuit 04 can be used to control the on / off state of the first pull-up node Q1 and the second pull-up node Q2 in response to the sixth power supply signal provided by the sixth power supply terminal V6.

[0154] Optionally, the potential of the sixth power signal provided by the sixth power supply terminal V6 can be a high potential; correspondingly, the sixth power supply terminal V6 can also be called the pull-up power supply terminal VGH. Furthermore, the sixth power supply terminal V6 and the third power supply terminal V3 can be shared or can be independent of each other. That is, the power supply terminal connected to the second control circuit 04 can be the power supply terminal connected to the output circuit 02, or it can be an additional power supply terminal.

[0155] For example, the second control circuit 04 can control the first pull-up node Q1 and the second pull-up node Q2 to be turned on under the control of the high-potential sixth power supply signal, so that the signal transmitted to the first pull-up node Q1 can be further transmitted to the second pull-up node Q2.

[0156] It is understandable that by dividing the pull-up node Q into two pull-up nodes and setting the second control circuit 04 to perform the above function, the first pull-up node Q1 and the second pull-up node Q2 can be isolated, avoiding the problem of voltage backflow from the output circuit 02 causing the potential of the first pull-up node Q1 to be unstable. This also protects the transistor (e.g., the fifth transistor T5) that controls the potential of the first pull-up node Q1, thereby ensuring better output stability of the shift register unit.

[0157] And / or,

[0158] Referring again to Figure 7, similar to the pull-up node Q, the pull-down node QB can also include: a first pull-down node QB1 and a second pull-down node QB2. The input circuit 01 can be connected to the first pull-down node QB1, and the output circuit 02 can be connected to the second pull-down node QB2. That is, the input circuit 01 can control the potential of the first pull-down node QB1; while the output circuit 02, under the control of the potential of the second pull-down node QB2, can output a signal to the output terminal OUT.

[0159] Based on this, referring to Figure 7, it can also be seen that the shift register unit may include: a third control circuit 05.

[0160] The third control circuit 05 can be connected to the clock terminal CK, the first pull-down node QB1, and the second pull-down node QB2, respectively. Furthermore, the third control circuit 05 can be used to control the on / off state of the first pull-down node QB1 and the second pull-down node QB2 in response to a clock signal.

[0161] For example, the third control circuit 05 can control the first pull-down node QB1 and the second pull-down node QB2 to be turned on when the clock signal potential is a first potential (e.g., high potential), so that the signal transmitted to the first pull-down node QB1 can be further transmitted to the second pull-down node QB2; and can control the first pull-down node QB1 and the second pull-down node QB2 to be disconnected when the clock signal potential is a second potential (e.g., low potential).

[0162] It is understandable that by dividing the pull-down node QB into two pull-down nodes and setting the third control circuit 05 to perform the above function, the purpose of isolating the first pull-down node QB1 and the second pull-down node QB2 can be achieved, thereby ensuring better output stability of the shift register unit.

[0163] Optionally, based on Figure 7, Figure 8 shows a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 8, the second control circuit 04 may include a seventh transistor T7. The third control circuit 05 may include an eighth transistor T8.

[0164] Furthermore, the gate of the seventh transistor T7 can be connected to the sixth power supply terminal V6, the first terminal of the seventh transistor T7 can be connected to the first pull-up node Q1, and the second terminal of the seventh transistor T7 can be connected to the second pull-up node Q2.

[0165] The gate of the eighth transistor T8 can be connected to the clock terminal CK, the first terminal of the eighth transistor T8 can be connected to the first pull-down node QB1, and the second terminal of the eighth transistor T8 can be connected to the second pull-down node QB2.

[0166] Optionally, based on Figure 8, Figure 9 shows a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 9, the shift register unit may further include a reset circuit 06.

[0167] The reset circuit 06 can be connected to the reset control terminal TRST, the reset power supply terminal Vrst, and the second pull-down node QB2, respectively. Furthermore, the reset circuit 06 can be used to control the on / off state of the reset power supply terminal Vrst and the second pull-down node QB2 in response to the reset control signal provided by the reset control terminal TRST. That is, the reset circuit 06 can be used to control the potential of the second pull-down node QB2.

[0168] The reset power supply terminal Vrst can be shared with either the third power supply terminal V3 or the fourth power supply terminal V4. That is, the reset power supply terminal Vrst can be the third power supply terminal V3 (i.e., the pull-up power supply terminal VGH) or the fourth power supply terminal V4 (i.e., the pull-down power supply terminal VGL).

[0169] For example, referring to Figure 9, the reset power supply terminal Vrst is shared with the third power supply terminal V3. Based on this, the reset circuit 06 can control the third power supply terminal V3 to conduct with the second pull-down node QB2 when the reset control signal provided by the reset control terminal TRST is at a first potential (e.g., a high potential), allowing the high-potential third power signal provided by the third power supply terminal V3 to be transmitted to the second pull-down node QB2; and can control the third power supply terminal V3 to disconnect from the second pull-down node QB2 when the reset control signal provided by the reset control terminal TRST is at a second potential (e.g., a low potential).

[0170] It is understandable that by sharing the reset power supply terminal Vrst with the third power supply terminal V3, and by transmitting a high-level third power supply signal to the second pull-down node QB2 under the control of the reset control signal, it can be ensured that the transistor connected to the second pull-down node QB2 in the output circuit 02 can be fully turned on. This allows for a reliable output of a low-level fourth power supply signal to the output terminal OUT under the control of the potential of the second pull-down node QB2. Similarly, by sharing the reset power supply terminal Vrst with the fourth power supply terminal V4, and by transmitting a low-level fourth power supply signal to the second pull-down node QB2 under the control of the reset control signal, it can be ensured that the transistor connected to the second pull-down node QB2 in the output circuit 02 can be fully turned off. This avoids the erroneous output of the fourth power supply signal when it is not necessary to output a low-level fourth power supply signal to the output terminal OUT. In summary, by configuring this reset circuit 06, the output stability and reliability of the shift register unit can be ensured to be good. The typical reset circuit 06 is used to control the reset power supply terminal Vrst to conduct with the second pull-down node QB2 at power-on, thereby achieving the initialization reset of the second pull-down node QB2.

[0171] Of course, in some other embodiments, the reset circuit 06 can also be connected to the first pull-up node Q1 and / or the second pull-up node Q2 to control the on / off state of the reset power supply terminal Vrst and the connected pull-up node in response to the reset control signal provided by the reset control terminal TRST. This allows the output circuit 02 to reliably output a high-potential third power supply signal to the output terminal OUT under the control of the second pull-up node Q2, thereby further improving the output stability and reliability of the shift register unit.

[0172] Optionally, based on Figure 9, Figure 10 shows a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 10, the reset circuit 06 may include: a ninth transistor T9.

[0173] The gate of the ninth transistor T9 can be connected to the reset control terminal TRST, the first terminal of the ninth transistor T9 can be connected to the reset power supply terminal Vrst (e.g., the third power supply terminal V3), and the second terminal of the ninth transistor T9 can be connected to the second pull-down node QB2.

[0174] Optionally, in the embodiments of this application, the portion including the input circuit 01, the first control circuit 03, and the third control circuit 05 can be referred to as a leakage-proof shift register control module. Referring to the above embodiments, Figures 11 to 15 respectively show five types of shift register control modules: a, b, c, d, and e.

[0175] For example, referring to structure a shown in Figure 11, the shift register control module includes a first transistor T1, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, an eighth transistor T8, and a first capacitor C1. The first transistor T1 and the third transistor T3 are dual-gate transistors. Furthermore, as described above, the first transistor T1, the first capacitor C1, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 belong to input circuit 01, the fourth transistor T4 belongs to the first control circuit 03, and the eighth transistor T8 belongs to the third control circuit 05. The target signal terminal Vo connected to this shift register control module is the second power supply terminal V2, and the connected control terminal Con is the input terminal IN.

[0176] For example, referring to structure b shown in Figure 12, the shift register control module includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8. The first transistor T1 and the third transistor T3 are dual-gate transistors. Furthermore, as previously described, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 belong to input circuit 01, the fourth transistor T4 belongs to the first control circuit 03, and the eighth transistor T8 belongs to the third control circuit 05. The target signal terminal Vo connected to this shift register control module is the second power supply terminal V2, and the connected control terminal Con is the input terminal IN. Comparing Figures 12 and 11, it can be seen that structure b, compared to structure a, mainly replaces the first capacitor C1 with the second transistor T2.

[0177] For example, referring to structure c shown in Figure 13, the shift register control module includes a first transistor T1, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, an eighth transistor T8, and a first capacitor C1. The first transistor T1 and the third transistor T3 are dual-gate transistors. Furthermore, as previously described, the first transistor T1, the first capacitor C1, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 belong to input circuit 01, the fourth transistor T4 belongs to the first control circuit 03, and the eighth transistor T8 belongs to the third control circuit 05. The target signal terminal Vo connected to this shift register control module is the clock terminal CK, and the connected control terminal Con is the input terminal IN. Comparing Figures 13 and 11, it can be seen that structure c, compared to structure a, mainly replaces the second power supply terminal V2 with the clock terminal CK for the target signal terminal Vo.

[0178] For example, referring to structure d shown in Figure 14, the shift register control module includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8. The first transistor T1 and the third transistor T3 are dual-gate transistors. Furthermore, as previously described, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 belong to input circuit 01, the fourth transistor T4 belongs to the first control circuit 03, and the eighth transistor T8 belongs to the third control circuit 05. The target signal terminal Vo connected to this shift register control module is the clock terminal CK, and the connected control terminal Con is the input terminal IN. Comparing Figures 14 and 13, it can be seen that structure d, compared to structure c, mainly replaces the first capacitor C1 with the second transistor T2.

[0179] For example, referring to structure e shown in Figure 15, the shift register control module includes a first transistor T1, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a first capacitor C1. The first transistor T1 and the third transistor T3 are dual-gate transistors. Furthermore, as previously described, the first transistor T1, the first capacitor C1, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 belong to the input circuit 01, and the fourth transistor T4 belongs to the first control circuit 03. The target signal terminal Vo connected to this shift register control module is the second power supply terminal V2, and the connected control terminal Con is the first pull-up node Q1. Comparing Figures 15 and 11, it can be seen that structure e, compared to structure a, mainly omits the third control circuit 05 and replaces the control terminal Con with the first pull-up node Q1 instead of the input terminal IN.

[0180] Of course, it is understood that the structures shown in Figures 11 to 15 are merely schematic representations of multiple shift register control modules, and the implementation of the shift register control modules is not limited to these. For example, as can be seen from Figures 11 to 15, in some embodiments, the first transistor T1 and / or the third transistor T3 can be single-gate transistors; correspondingly, the first control circuit 03 can be omitted, i.e., the fourth transistor T4 can be omitted. In other embodiments, the first capacitor C1 and the first transistor T1 can be omitted; correspondingly, the first control circuit 03 can be omitted, i.e., the fourth transistor T4 can be omitted. Based on this, the target signal terminal Vo can be the second power supply terminal V2. In yet another embodiment, based on the above-described alternative embodiment, the sixth transistor T6 can also be a dual-gate transistor. In some other embodiments, in addition to including the third transistor T3, two transistors connected in series between the first pull-up node Q1 and the first power supply terminal V1 may be included, and the gates of these two transistors may be connected to another clock terminal and the second pull-down node QB1, respectively; or, two transistors connected in series between the second pull-down node QB1 and the first power supply terminal V1 may be included, and the gates of these two transistors may be connected to another clock terminal and the first pull-up node Q1, respectively. The above are all illustrative and do not limit the implementation methods described in the embodiments of this application.

[0181] Optionally, the various shift register control modules described in the above embodiments are shown as modules. From the perspective of the output circuit 02, Figures 16 to 20 respectively show schematic diagrams of the structures of various shift register units provided in the embodiments of this application. First, referring to Figures 16 to 20 and the foregoing description, it can be seen that the shift register control module can be connected to at least the clock terminal CK, the input terminal IN, the first pull-up node Q1, and the second pull-down node QB2. Furthermore, a seventh transistor T7 can be included between the shift register control module and the output circuit 02 to isolate the first pull-up node Q1 and the second pull-up node Q2.

[0182] Furthermore, as can be seen from Figure 16, the output circuit 02 may include: the tenth transistor T10, the second capacitor C2, the eleventh transistor T11, and the third capacitor C3.

[0183] Furthermore, the gate of the tenth transistor T10 can be connected to the pull-up node Q, the first terminal of the tenth transistor T10 can be connected to the third power supply terminal V3, and the second terminal of the tenth transistor T10 can be connected to the output terminal OUT.

[0184] One end of the second capacitor C2 can be connected to the pull-up node Q, and the other end of the second capacitor C2 can be connected to the output terminal OUT.

[0185] The gate of the eleventh transistor T11 can be connected to the pull-down node QB, the first terminal of the eleventh transistor T11 can be connected to the fourth power supply terminal V4, and the second terminal of the eleventh transistor T11 can be connected to the output terminal OUT.

[0186] One end of the third capacitor C3 can be connected to the pull-down node QB, and the other end of the third capacitor C3 can be connected to the fourth power supply terminal V4.

[0187] Understandably, as mentioned earlier, based on dividing the pull-up node Q into the first pull-up node Q1 and the second pull-up node Q2, the gate of the tenth transistor T10 and one end of the second capacitor C2 can be connected to the second pull-up node Q2. Similarly, based on dividing the pull-down node QB into the first pull-down node QB1 and the second pull-down node QB2, the gate of the eleventh transistor T11 and one end of the third capacitor C3 can be connected to the second pull-down node QB2.

[0188] Optionally, referring to Figure 17, in some embodiments, the eleventh transistor T11 may include two third sub-transistors T111 and T112 connected in series with the first and second terminals. That is, like the first transistor T1 and the third transistor T3, the eleventh transistor T11 may also be a transistor with a dual-gate structure.

[0189] Among them, the gates of the two third sub-transistors T111 and T112 can both be connected to the pull-down node QB (e.g., the second pull-down node QB2), the first terminal of the third sub-transistor T111 can be connected to the fourth power supply terminal V4, the second terminal of the third sub-transistor T111 can be connected to the first terminal of the third sub-transistor T112, and the second terminal of the third sub-transistor T112 can be connected to the output terminal OUT.

[0190] Furthermore, based on this, referring to Figure 17, it can be seen that the shift register unit may also include: a fourth control circuit 07.

[0191] The fourth control circuit 07 can be connected to the output terminal OUT, the seventh power supply terminal V7, and the series node P3 of the two third sub-transistors T111 and T112, respectively. Furthermore, this fourth control circuit 07 can be used to control the on / off state of the seventh power supply terminal V7 and the connected series node P3 in response to a signal output through the output terminal OUT. That is, the fourth control circuit 07 can be used to control the potential of the series node P3.

[0192] Optionally, like the fifth power supply terminal V5, the potential of the seventh power signal provided by the seventh power supply terminal V7 can be a high potential. Correspondingly, the seventh power supply terminal V7 can also be referred to as the pull-up power supply terminal VGH. Furthermore, like the fifth power supply terminal V5, the seventh power supply terminal V7 can be independent of other power supply terminals (e.g., the second power supply terminal V2 / the third power supply terminal V3). That is, the seventh power supply terminal V7 can be a separate power supply terminal, which can be connected to a separate power line. Alternatively, the seventh power supply terminal V7 can be set as GVGH. Based on this, in some embodiments, the seventh power supply terminal V7 can be shared with the fifth power supply terminal V5. Of course, in some other embodiments, the seventh power supply terminal V7 can also be shared with the other power supply terminals (e.g., the second power supply terminal V2 / the third power supply terminal V3).

[0193] For example, the fourth control circuit 07 can control the seventh power supply terminal V7 to conduct with the series node P3 when the signal output through the output terminal OUT is at a first potential (e.g., a high potential), so that the high-potential seventh power supply signal provided by the seventh power supply terminal V7 can be transmitted to the series node P3; and can control the seventh power supply terminal V7 to disconnect from the series node P3 when the potential of the signal output through the output terminal OUT is at a second potential (e.g., a low potential).

[0194] It is understandable that, similar to the first transistor T1, setting the eleventh transistor T11 as a dual-gate transistor can also achieve the purpose of preventing leakage current, ensuring that a low-potential fourth power supply signal is reliably output to the output terminal OUT through the eleventh transistor T11. Furthermore, by setting the eleventh transistor T11 as a dual-gate transistor and including a fourth control circuit 07 in the shift register unit to perform the above functions, the leakage current prevention capability can be further improved. Of course, in some other embodiments, the eleventh transistor T11 can also be a single-gate transistor.

[0195] Furthermore, by making the seventh power terminal V7 independent of the other power terminals, similar to the fifth power terminal V5, interference between the power signals provided by the power terminals can be avoided, thus improving the leakage protection capability. Sharing the seventh power terminal V7 with the other power terminals simplifies wiring, saves costs, and facilitates narrow bezel designs.

[0196] Optionally, in some embodiments, among the two third sub-transistors T111 and T112 included in the eleventh transistor T11, the channel width-to-length ratio of the transistor directly connected to the output terminal OUT (e.g., the third sub-transistor T111) can be greater than the channel width-to-length ratio of the transistor not directly connected to the output terminal OUT (e.g., the third sub-transistor T112). This ensures that the eleventh transistor T11 has good output drive capability.

[0197] Optionally, in some embodiments, the tenth transistor T10, which connects the pull-up node Q and the output terminal OUT, can also be designed as a dual-gate structure, just like the eleventh transistor T11. Furthermore, the fourth control circuit 07 can be connected to the series node of the dual-gate structure of the tenth transistor T10 to achieve the same purpose.

[0198] Optionally, based on Figure 17, and continuing to refer to Figure 18, it can be seen that the fourth control circuit 07 may include: the twelfth transistor T12.

[0199] The gate of the twelfth transistor T12 can be connected to the output terminal OUT, the first terminal of the twelfth transistor T12 can be connected to the seventh power supply terminal V7, and the second terminal of the twelfth transistor T12 can be connected to the series node P3 of the two third sub-transistors T111 and T112.

[0200] Optionally, referring to Figure 19, in some embodiments, the output terminal OUT may include a shift output terminal CR1 and a drive output terminal OUT1. The shift output terminal CR1 can be connected to other cascaded shift register units, and the drive output terminal OUT1 can be connected to pixels in the display panel. Furthermore, as described above, the shift output terminal CR1 can be connected to the input terminal IN of other cascaded shift register units. That is, the output terminal OUT can be divided into two output terminals to output signals to other shift register units to drive them, thus achieving cascaded driving; and to output signals to pixels to drive them to emit light, thus achieving light emission driving. In this way, compared to simultaneously outputting signals to other shift register units and pixels through the same output terminal OUT, cascaded driving and light emission driving can be made independent of each other, ensuring better cascade functionality and reliable pixel light emission driving.

[0201] Furthermore, the output circuit 02 can also be connected to the eighth power supply terminal V8 and the ninth power supply terminal V9. Additionally, the output circuit 02 may include: a first output sub-circuit 021 and a second output sub-circuit 022.

[0202] The first output sub-circuit 021 can be connected to the pull-up node Q, the pull-down node QB, the third power supply terminal V3, the fourth power supply terminal V4, and the shift output terminal CR1, respectively. Furthermore, the first output sub-circuit 021 can control the switching between the third power supply terminal V3 and the shift output terminal CR1 in response to the potential of the pull-up node Q, and control the switching between the fourth power supply terminal V4 and the shift output terminal CR1 in response to the potential of the pull-down node QB. That is, the first output sub-circuit 021 can output the required input signal to the input terminal IN of other shift register units via the shift output terminal CR1.

[0203] For example, the first output sub-circuit 021 can control the third power supply terminal V3 to conduct with the shift output terminal CR1 when the potential of the pull-up node Q is a first potential (e.g., high potential), so that the high-potential third power supply signal provided by the third power supply terminal V3 can be transmitted to the shift output terminal CR1; and can control the third power supply terminal V3 to disconnect from the shift output terminal CR1 when the potential of the pull-up node Q is a second potential (e.g., low potential). Similarly, the first output sub-circuit 021 can control the fourth power supply terminal V4 to conduct with the shift output terminal CR1 when the potential of the pull-down node QB is a first potential (e.g., high potential), so that the low-potential fourth power supply signal provided by the fourth power supply terminal V4 can be transmitted to the shift output terminal CR1; and can control the fourth power supply terminal V4 to disconnect from the shift output terminal CR1 when the potential of the pull-down node QB is a second potential (e.g., low potential).

[0204] The second output sub-circuit 022 can be connected to the pull-up node Q, the pull-down node QB, the eighth power supply terminal V8, the ninth power supply terminal V9, and the drive output terminal OUT1, respectively. Furthermore, this second output sub-circuit 022 can control the switching between the eighth power supply terminal V8 and the drive output terminal OUT1 in response to the potential of the pull-up node Q, and control the switching between the ninth power supply terminal V9 and the drive output terminal OUT1 in response to the potential of the pull-down node QB. That is, the second output sub-circuit 022 can output the required light-emitting control signal to the pixel via the drive output terminal OUT1.

[0205] Optionally, the eighth power supply terminal V8 can provide a high potential for the eighth power signal, and the ninth power supply terminal V9 can provide a low potential for the ninth power signal. Correspondingly, the eighth power supply terminal V8 can also be called the pull-up power supply terminal VGH, and the ninth power supply terminal V9 can also be called the pull-down power supply terminal VGL. Furthermore, the eighth power supply terminal V8 and the third power supply terminal V3 can be shared or independent of each other. Similarly, the ninth power supply terminal V9 and the fourth power supply terminal V4 can be shared or independent of each other.

[0206] For example, the second output sub-circuit 022 can control the eighth power supply terminal V8 to conduct with the drive output terminal OUT1 when the potential of the pull-up node Q is a first potential (e.g., high potential), so that the high-potential eighth power signal provided by the eighth power supply terminal V8 can be transmitted to the drive output terminal OUT1; and can control the eighth power supply terminal V8 to disconnect from the drive output terminal OUT1 when the potential of the pull-up node Q is a second potential (e.g., low potential). Similarly, the second output sub-circuit 022 can control the ninth power supply terminal V9 to conduct with the drive output terminal OUT1 when the potential of the pull-down node QB is a first potential (e.g., high potential), so that the low-potential ninth power signal provided by the ninth power supply terminal V9 can be transmitted to the drive output terminal OUT1; and can control the ninth power supply terminal V9 to disconnect from the drive output terminal OUT1 when the potential of the pull-down node QB is a second potential (e.g., low potential).

[0207] It is understandable that, based on dividing the pull-up node Q into a first pull-up node Q1 and a second pull-up node Q2, and dividing the pull-down node QB into a first pull-down node QB1 and a second pull-down node QB2, as shown in Figure 19 and as described above, both the first output sub-circuit 021 and the second output sub-circuit 022 can be connected to the second pull-up node Q2 and the second pull-down node QB2. Of course, in some other embodiments, the second output sub-circuit 022 can also be connected to the first pull-down node QB1.

[0208] Optionally, in some other embodiments, based on dividing the output circuit 02 into a first output sub-circuit 021 and a second output sub-circuit 022, the second pull-down node QB2 can be further divided into two pull-down nodes (e.g., pull-down node 1 and pull-down node 2). Furthermore, another transistor connected to the seventh transistor T7 is positioned between pull-down node 1 and pull-down node 2 to isolate them. Simultaneously, the first output sub-circuit 021 is connected to pull-down node 1, and the second output sub-circuit 022 is connected to pull-down node 2, enabling the first output sub-circuit 021 and the second output sub-circuit 022 to independently output signals under the control of different pull-down nodes, thereby improving output flexibility and reliability.

[0209] Optionally, based on Figure 19 and referring to Figure 20, the first output sub-circuit 021 may include: a tenth transistor T10, a second capacitor C2, an eleventh transistor T11, and a third capacitor C3. The second output sub-circuit 022 may include: a twelfth transistor T12 and a thirteenth transistor T13.

[0210] Furthermore, the gate of the tenth transistor T10 can be connected to the pull-up node Q, the first terminal of the tenth transistor T10 can be connected to the third power supply terminal V3, and the second terminal of the tenth transistor T10 can be connected to the shift output terminal CR1.

[0211] One end of the second capacitor C2 can be connected to the pull-up node Q, and the other end of the second capacitor C2 can be connected to the shift output terminal CR1.

[0212] The gate of the eleventh transistor T11 can be connected to the pull-down node QB, the first terminal of the eleventh transistor T11 can be connected to the fourth power supply terminal V4, and the second terminal of the eleventh transistor T11 can be connected to the shift output terminal CR1.

[0213] One end of the third capacitor C3 can be connected to the pull-down node QB, and the other end of the third capacitor C3 can be connected to the fourth power supply terminal V4.

[0214] The gate of the twelfth transistor T12 can be connected to the pull-up node Q, the first terminal of the twelfth transistor T12 can be connected to the eighth power supply terminal V8, and the second terminal of the twelfth transistor T12 can be connected to the drive output terminal OUT1.

[0215] The gate of the thirteenth transistor T13 can be connected to the pull-down node QB, the first terminal of the thirteenth transistor T13 can be connected to the ninth power supply terminal V9, and the second terminal of the thirteenth transistor T13 can be connected to the drive output terminal OUT1.

[0216] The second capacitor C2 can raise the potential of the pull-up node Q through bootstrapping, ensuring that the tenth transistor T10 and the twelfth transistor T12 can be fully turned on, avoiding a step between the high-potential third power supply signal output by the tenth transistor T10 and the high-potential eighth power supply signal output by the twelfth transistor T12. The effect of the third capacitor C3 is similar and will not be described again. Based on this, in some embodiments, a capacitor can also be connected in series between the drive output terminal OUT1 and the second pull-down node QB2 to achieve the same effect.

[0217] It is understandable that, based on dividing the pull-up node Q into the first pull-up node Q1 and the second pull-up node Q2, and dividing the pull-down node QB into the first pull-down node QB1 and the second pull-down node QB2, as shown in Figure 20 and as described above, the gate of the tenth transistor T10, the gate of the twelfth transistor T12, and one end of the second capacitor C2 can all be connected to the second pull-up node Q2; the gate of the eleventh transistor T11, the gate of the thirteenth transistor T13, and one end of the third capacitor C3 can all be connected to the second pull-down node QB2.

[0218] Optionally, in this embodiment, the eighth power supply terminal V8 and the third power supply terminal V3 can be independent of each other, and the ninth power supply terminal V9 and the fourth power supply terminal V4 can be independent of each other. For distinction, in Figure 20, the third power supply terminal V3 and the eighth power supply terminal V8, which are both pull-up power supply terminals VGH, are labeled as VGH1 and VGH2, respectively; the fourth power supply terminal V4 and the ninth power supply terminal V9, which are both pull-down power supply terminals VGL, are labeled as VGL1 and VGL2, respectively. Based on this structure, the output circuit 02 can also be considered to adopt a dual VGH and dual VGL design. In this way, the second output sub-circuit 022 can independently transmit the required signal to the pixel via the drive output terminal OUT1, improving the ability to drive the pixel to emit light, reducing leakage current, and thus ensuring reliable pixel emission.

[0219] Furthermore, based on the design employing dual VGH and dual VGL, the low potential of the ninth power signal provided by the ninth power terminal V9 (i.e., VGL2) can be lower than the low potential of the fourth power signal provided by the fourth power terminal V4 (i.e., VGL1). In this embodiment, the potential relationship refers to the absolute value of the potentials. For example, the low potential of the power signal provided by VGL2 can differ from the low potential of the power signal provided by VGL1 by approximately 2V. In some embodiments, the low potential of the power signal provided by VGL2 can be between -5V and -10V, and the low potential of the power signal provided by VGL1 can be between -7V and -12V. For example, the low potential of the power signal provided by VGL2 can be -8V, and the low potential of the power signal provided by VGL1 can be -10V. This also ensures that when the potential of the pull-down node QB (e.g., the second pull-down node QB2) is at the low potential Vgl1 of the power supply signal provided by VGL1, the gate-source voltage difference Vgs of the thirteenth transistor T13 is much smaller than the threshold voltage Vth of the thirteenth transistor T13, ensuring that the thirteenth transistor T13 is fully turned off and ensuring a reliable signal output to the drive output terminal OUT1. The gate-source voltage difference Vgs of the thirteenth transistor T13 satisfies: Vgs = Vgl2 - Vgl1, where Vgl2 refers to the potential of the power supply signal provided by VGL2.

[0220] Similarly, the potential of the eighth power supply signal provided by the eighth power supply terminal V8 can also be less than the potential of the third power supply signal provided by the third power supply terminal V3, so as to ensure the reliable turn-off of the twelfth transistor T12. Of course, the potential of the eighth power supply signal provided by the eighth power supply terminal V8 can also be equal to the potential of the third power supply signal provided by the third power supply terminal V3.

[0221] Optionally, the above embodiments are merely illustrative of various possible implementations of the output circuit 02, and do not limit its implementation. For example, referring to Figures 16 to 20 and the foregoing description, in some embodiments, the tenth transistor T10 can also be configured as a dual-gate structure. In other embodiments, another capacitor can be connected in series between the thirteenth transistor T13 and the second pull-down node QB2.

[0222] Optionally, taking the shift register control module of structure a shown in Figure 11 as an example, and referring to Figure 9, as well as Figures 16 to 20, and Figures 21 to 24, we can see schematic diagrams of the shift register unit under various implementation methods. Taking the shift register control module of structure e shown in Figure 15 as an example, and referring to Figure 16, Figure 25 schematically shows a schematic diagram of the shift register unit under one implementation method. Furthermore, the design of the pull-up power supply terminal VGH and the pull-down power supply terminal VGL are schematically indicated in Figures 21 to 25.

[0223] Optionally, the power signals provided by the pull-up power supply terminal VGH and the pull-down power supply terminal VGL described in this application embodiment can be fixed-potential power signals or dynamically adjustable power signals. During use, a separate control chip can flexibly adjust these signals based on the display screen, ensuring good display flexibility and achieving a good display effect.

[0224] As described above, the key transistor for preventing leakage current mentioned in the embodiments of this application includes: the fourth transistor T4 shown in Figure 21 and the twelfth transistor T12 shown in Figure 23. This key transistor can be a single transistor, i.e., a single-gate structure; or it can be a dual-gate structure transistor. The pull-up power supply terminal VGH connected to this key transistor can be connected to a separate power line, distinguishing it from the power lines connected to other pull-up power supply terminals VGH, or it can be set as GVGH separately. Furthermore, it is understood that each transistor described in the embodiments of this application can be a single-gate structure or a dual-gate structure.

[0225] Optionally, the dual-gate structure described in this application embodiment can cover various methods such as bottom gate connected to the source, bottom gate connected to the top gate, and bottom gate connected to other signals. The bottom gate refers to a gate metal layer that is closer to the substrate than the top gate and is used to form a transistor; conversely, the top gate refers to another gate metal layer that is farther from the substrate than the bottom gate and is used to form a transistor; the source refers to one of the electrodes included in the source and drain metal layers used to form a transistor.

[0226] As described above, current oxide transistors are affected by process fluctuations and BTS (Bottom-Threshold Voltage) issues, causing the threshold voltage Vth to become negatively biased, resulting in significant leakage current. This leads to the failure of the shift register unit and unstable output. In contrast, this application's embodiment, combining a novel shift register control module and a leakage-proof structure, designs a stepless and shiftable all-oxide EMGA (Electro-Metal Oxide-Oxide-GOA) that can effectively drive the display panel, resulting in a better display effect.

[0227] In summary, this application provides a shift register unit. This shift register unit includes an input circuit and an output circuit. Because the input circuit can reliably and flexibly control the potentials of the pull-up and pull-down nodes under the control of various received signals, the output circuit can reliably output high or low potential power signals to the output terminal under the control of the pull-up and pull-down nodes. Therefore, this shift register unit can reliably output light-emitting control signals to the pixels via the output terminal, thereby reliably driving the pixels to emit light and resulting in better display effects on the display panel.

[0228] This application also provides a method for driving a shift register unit, used to drive the shift register unit as described in the above embodiments. As shown in FIG26, the method includes:

[0229] Step 2601, First stage: The input circuit responds to the input signal provided by the input terminal, the clock signal provided by the clock terminal, the first power signal provided by the first power supply terminal, and the target signal provided by the target signal terminal. It controls the input terminal to be connected to the pull-up node, controls the target signal terminal to be disconnected from the pull-down node, and controls the first power supply terminal to be connected to the pull-down node. The output circuit responds to the potential of the pull-up node, controls the third power supply terminal to be connected to the output terminal, and responds to the potential of the pull-down node, controls the fourth power supply terminal to be disconnected from the output terminal.

[0230] Step 2602, Second Stage: The input circuit responds to the input signal, clock signal, first power signal and target signal, controls the input terminal to be connected to the pull-up node, controls the target signal terminal to be connected to the pull-down node, and controls the first power terminal to be disconnected from the pull-down node. The output circuit responds to the potential of the pull-up node, controls the third power terminal to be disconnected from the output terminal, and responds to the potential of the pull-down node, controls the fourth power terminal to be connected to the output terminal.

[0231] Taking the structure shown in Figure 21 as an example, where each transistor in the shift register unit is an N-type transistor, the first potential (i.e., the effective potential) is high, the second potential (i.e., the ineffective potential) is low, the target signal terminal Vo is the second power supply terminal V2, and the control terminal Con is the input terminal IN, the driving method of the shift register unit is explained as follows, in conjunction with the signal timing diagram shown in Figure 27:

[0232] (1) During stage t01, the input signal provided by the input terminal IN (e.g., the enable signal line STV) is at a high potential, and the clock signal provided by the clock terminal CK is at a high potential. This allows the two first sub-transistors T11 and T12 of the first transistor T1, the two second sub-transistors T31 and T32 of the third transistor T3, the fifth transistor T5, and the eighth transistor T8 to all be turned on. Furthermore, since the sixth power supply terminal V6 can provide a high-potential sixth power supply signal, the seventh transistor T7 can also be turned on. Furthermore, the low-potential first power signal provided by the first power supply terminal V1 can be transmitted to the intermediate node Q0 via the two activated first sub-transistors T11 and T12, and to the first pull-down node QB1 via the two activated second sub-transistors T31 and T32. The high-potential input signal provided by the input terminal IN can be transmitted to the first pull-up node Q1 via the activated fifth transistor T5. The low-potential first power signal transmitted to the first pull-down node QB1 can then be transmitted to the second pull-down node QB1 via the activated eighth transistor T8. The high-potential input signal transmitted to the first pull-up node Q1 can then be transmitted to the second pull-up node Q2 via the activated seventh transistor T7. That is, in stage t01, the potential of the first pull-up node Q1 and the potential of the second pull-up node Q2 can be kept high, and the potentials of the intermediate node Q0, the first pull-down node QB1, and the second pull-down node QB2 can all be kept low. This also allows the tenth transistor T10 to be turned on, and the fourth transistor T4, the sixth transistor T6, and the eleventh transistor T11 to be turned off. Furthermore, the high-potential third power supply signal provided by the third power supply terminal V3 can be transmitted to the output terminal OUT via the turned-on tenth transistor T10, and a high-potential signal (e.g., a light-emitting control signal) can be output via the output terminal OUT.

[0233] (2) In stage t02, the input signal provided by input terminal IN is at a low potential, and the clock signal provided by clock terminal CK is at a low potential. This allows the two first sub-transistors T11 and T12 of the first transistor T1, the two second sub-transistors T31 and T32 of the third transistor T3, and the fourth transistor T4, fifth transistor T5, sixth transistor T6, and eighth transistor T8 to all be turned off. Based on this, it can be seen that the second pull-up node Q2 and the second pull-down node QB2 can both be in a floating state. Correspondingly, the potentials of the second pull-up node Q2 and the second pull-down node QB2 can both be maintained at the potentials of the adjacent previous stage (i.e., stage t01). Since the potential of the second pull-up node Q2 was high and the potential of the second pull-down node QB2 was low in the previous stage t01, it can be seen that in stage t02, the potential of the second pull-up node Q2 can be maintained at a high potential, and the potential of the second pull-down node QB2 can be maintained at a low potential. Therefore, the tenth transistor T10 can remain on, and the eleventh transistor T11 can remain off. Furthermore, the high-potential third power supply signal provided by the third power supply terminal V3 can continue to be transmitted to the output terminal OUT via the on-screen tenth transistor T10, and a high-potential signal can be continuously output through the output terminal OUT.

[0234] (3) During stage t03, the input signal provided by the input terminal IN is at a low potential, and the clock signal provided by the clock terminal CK is at a high potential. This pulls the potential of the intermediate node Q0 high, thereby turning off the two first sub-transistors T11 and T12 of the first transistor T1, and the two second sub-transistors T31 and T32 of the third transistor T3, and turning on the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8. Furthermore, since the sixth power supply terminal V6 can provide a high-potential sixth power supply signal, the seventh transistor T7 can also be turned on. Furthermore, this not only allows the high-potential fifth power signal provided by the fifth power supply terminal V5 to be transmitted to the series nodes P1 & P2 via the activated fourth transistor T4, preventing leakage, but also allows the low-potential input signal provided by the input terminal IN to be transmitted to the first pull-up node Q1 via the activated fifth transistor T5. It also allows the high-potential second power signal provided by the second power supply terminal V2 (as the target signal terminal) to be transmitted to the first pull-down node QB1 via the activated sixth transistor T6. Additionally, the low-potential input signal transmitted to the first pull-up node Q1 can be transmitted to the second pull-up node Q2 via the activated seventh transistor T7, and the high-potential second power signal transmitted to the first pull-down node QB1 can be transmitted to the second pull-down node QB2 via the activated eighth transistor T8. In other words, during stage t01, the potentials of the first pull-up node Q1 and the second pull-up node Q2 can be made low, while the potentials of the intermediate node Q0, the first pull-down node QB1, and the second pull-down node QB2 can all be made high. Therefore, the tenth transistor T10 can be turned off, and the eleventh transistor T11 can be turned on. Furthermore, the low-potential fourth power supply signal provided by the fourth power supply terminal V4 can be transmitted to the output terminal OUT via the turned-on eleventh transistor T11, and a low-potential signal can be output through the output terminal OUT.

[0235] (4) In stage t04, the input signal provided by input terminal IN is at a low potential, and the clock signal provided by clock terminal CK is at a low potential. This allows the two first sub-transistors T11 and T12 of the first transistor T1, the two second sub-transistors T31 and T32 of the third transistor T3, and the fourth transistor T4, fifth transistor T5, sixth transistor T6, and eighth transistor T8 to all be turned off. Based on this, it can be seen that the second pull-up node Q2 and the second pull-down node QB2 can both be in a floating state. Correspondingly, the potentials of the second pull-up node Q2 and the second pull-down node QB2 can both be maintained at the potentials of the adjacent previous stage (i.e., stage t03). Since the potential of the second pull-up node Q2 was low and the potential of the second pull-down node QB2 was high in the previous stage t03, it can be seen that in stage t04, the potential of the second pull-up node Q2 can be maintained at a low potential, and the potential of the second pull-down node QB2 can be maintained at a high potential. Therefore, the eleventh transistor T11 can remain on, while the tenth transistor T10 can remain off. Consequently, the low-potential fourth power supply signal provided by the fourth power supply terminal V4 can continue to be transmitted to the output terminal OUT via the on-state eleventh transistor T11, and a low-potential signal can be continuously output through the output terminal OUT.

[0236] (5) In stage t05, the input signal provided by input terminal IN is at a high potential, and the clock signal provided by clock terminal CK is at a low potential. This allows the two first sub-transistors T11 and T12 of the first transistor T1, and the two second sub-transistors T31 and T32 of the third transistor T3, to be turned on, while the fifth transistor T5 and the eighth transistor T8 are turned off. Furthermore, the low-potential first power signal provided by the first power supply terminal V1 can be transmitted to the intermediate node Q0 via the two turned-on first sub-transistors T11 and T12, and to the first pull-down node QB1 via the two turned-on second sub-transistors T31 and T32. That is, in stage t05, the potential of the intermediate node Q0 and the potential of the first pull-down node QB1 are both low. This also allows the fourth transistor T4 and the sixth transistor T6 to be turned off. Furthermore, with both the fifth transistor T5 and the eighth transistor T8 turned off, it is known that the second pull-up node Q2 and the second pull-down node QB2 can both be in a floating state. Correspondingly, the potentials of the second pull-up node Q2 and the second pull-down node QB2 can both remain at the levels of the adjacent previous stage (i.e., stage t04). Since the potential of the second pull-up node Q2 was low and the potential of the second pull-down node QB2 was high in the previous stage t04, it is known that in stage t05, the potential of the second pull-up node Q2 can remain low and the potential of the second pull-down node QB2 can remain high. Therefore, the eleventh transistor T11 can remain on, and the tenth transistor T10 can remain off. Consequently, the low-potential fourth power supply signal provided by the fourth power supply terminal V4 can continue to be transmitted to the output terminal OUT via the turned-on eleventh transistor T11, and the low-potential signal can be continuously output through the output terminal OUT.

[0237] (6) During stage t06, the input signal provided by input terminal IN is at a high potential, and the clock signal provided by clock terminal CK is at a high potential. This allows the two first sub-transistors T11 and T12 of the first transistor T1, the two second sub-transistors T31 and T32 of the third transistor T3, the fifth transistor T5, and the eighth transistor T8 to all be turned on. Furthermore, since the sixth power supply terminal V6 can provide a high-potential sixth power supply signal, the seventh transistor T7 can also be turned on. Furthermore, the low-potential first power signal provided by the first power supply terminal V1 can be transmitted to the intermediate node Q0 via the two activated first sub-transistors T11 and T12, and to the first pull-down node QB1 via the two activated second sub-transistors T31 and T32. The high-potential input signal provided by the input terminal IN can be transmitted to the first pull-up node Q1 via the activated fifth transistor T5. The low-potential first power signal transmitted to the first pull-down node QB1 can then be transmitted to the second pull-down node QB1 via the activated eighth transistor T8. The high-potential input signal transmitted to the first pull-up node Q1 can then be transmitted to the second pull-up node Q2 via the activated seventh transistor T7. That is, in stage t06, the potential of the first pull-up node Q1 and the second pull-up node Q2 can be made high, and the potentials of the intermediate node Q0, the first pull-down node QB1, and the second pull-down node QB2 can all be made low. This allows the tenth transistor T10 to turn on, while the fourth transistor T4, sixth transistor T6, and eleventh transistor T11 are all turned off. Furthermore, the high-potential third power supply signal provided by the third power supply terminal V3 can be transmitted to the output terminal OUT via the turned-on tenth transistor T10, resulting in a high-potential signal being output from OUT. That is, the signal output from OUT changes from a low potential in the previous t05 stage to a high potential. Based on this, through the coupling effect of the second capacitor C2, the potential of the second pull-up node Q2 can be continuously pulled high in the t06 stage, typically to a level higher than the high potential of the third power supply signal. At this time, the seventh transistor T7 can enter the cutoff state, effectively turning it off, thus reliably maintaining the high potential of the second pull-up node Q2 and ensuring the continuous operation of the tenth transistor T10. Therefore, as shown in Figure 27, the signal output by this shift register unit is stepless.

[0238] It is understood that the operation of the shift register unit described in other embodiments is similar, and will not be repeated here.

[0239] It is also understood that the clock input CK of each shift register unit can be connected to the clock signal line CLK. Furthermore, in one implementation, two clock signal lines CLK1 and CLK2 can be provided for connecting cascaded multi-stage shift register units, and the clock input CK of two adjacent shift register units can be connected to these two clock signal lines CLK1 and CLK2 respectively. That is, the clock input CK of two adjacent shift register units can be connected to different clock signal lines, allowing for the use of a two-phase clock to drive the multi-stage shift register units. The timing diagram shown in Figure 27 illustrates the operation of a shift register unit using a two-phase clock drive as an example. Referring to Figure 27, it can be seen that the clock signals provided by the two clock signal lines CLK1 and CLK2 are exactly opposite during the same time period. Based on this, Figure 27 not only schematically shows the signal output by the current stage shift register unit to its connected output terminal OUT, but also schematically shows the signal output by the next stage shift register unit adjacent to the current stage shift register unit to its connected output terminal OUT.

[0240] Of course, it is not limited to using a 2-phase clock drive. For example, in some other embodiments, a 4-phase clock can be used to drive the multi-stage shift register units. Each group of four adjacent shift register units is a set, and the clock terminal CK of the four shift register units can be alternately connected to four different clock signal lines CLK1 to CLK4 in sequence. Based on this, Figure 28 also schematically shows the signals output by the first-stage shift register unit GOA-1 to the fourth-stage shift register unit GOA-4 through their respective output terminals OUT when using a 4-phase clock drive, labeled as OUT-1 to OUT-4 respectively.

[0241] It is also understandable that, since the driving method of the shift register unit can have the same technical effect as the shift register unit described in the previous embodiments, the technical effect of the driving method of the shift register unit will not be described again here for the sake of brevity.

[0242] This application also provides a light-emitting control circuit. As shown in FIG29, the light-emitting control circuit includes: cascaded multi-stage shift register units as described in the foregoing embodiments, i.e., GOA units, also called GOA. The figure schematically shows 6 cascaded GOA units, labeled GOA-1 to GOA-6 respectively.

[0243] Optionally, referring to Figure 29, the output terminal OUT of the i-th level GOA unit can be connected to the input terminal IN of the (i+L)-th level GOA unit. The output terminal OUT of the i-th level GOA unit can also be connected to a pixel to transmit the required input signal to the input terminal IN of the (i+L)-th level GOA unit and the required light-emitting control signal to the pixel. Here, 1 ≤ i ≤ ML, M is the total number of GOA units, M ≥ 1, and L is a positive integer greater than or equal to 1. Of course, the input terminal IN of the first level GOA unit can be connected to the enable signal line STV to receive the enable signal provided by the enable signal line STV, thus realizing shift driving.

[0244] It is understandable that, based on dividing the output terminal OUT into the shift output terminal CR1 and the drive output terminal OUT1, the shift output terminal CR1 of the i-th level GOA unit can be connected to the input terminal IN of the (i+L)-th level GOA unit, and the drive output terminal OUT1 of the i-th level GOA unit can be connected to the pixels in the display panel.

[0245] Optionally, as can be seen from the foregoing description and Figure 29, the clock terminal CK of each GOA unit can also be connected to a clock signal line. Furthermore, in one implementation, a two-phase clock can be used to drive the light-emitting control circuit. That is, as shown in Figure 29, two clock signal lines CLK1 and CLK2 can be provided for connecting multiple cascaded GOA units, and the clock terminals CK of two adjacent and cascaded GOA units can be connected to these two clock signal lines CLK1 and CLK2 respectively. Alternatively, in another implementation, a four-phase clock can be used to drive the light-emitting control circuit. That is, as shown in Figure 30, four clock signal lines CLK1 to CLK4 can be set for connecting multiple cascaded GOA units. Furthermore, the clock terminal CK of the 4M-3 level GOA unit can be connected to the clock signal line CLK1, the clock terminal CK of the 4M-2 level GOA unit can be connected to the clock signal line CLK2, the clock terminal CK of the 4M-1 level GOA unit can be connected to the clock signal line CLK3, and the clock terminal CK of the 4M level GOA unit can be connected to the clock signal line CLK4. Here, M is the total number of stages of the shift register, and M≥1.

[0246] Of course, it is not limited to the cascaded architecture of 2-phase or 4-phase clocks described above. For example, in some other embodiments, special cascaded architectures such as 6-phase or 8-phase clocks can also be covered. Furthermore, it is not limited to cascading every two adjacent GOA units. For example, in some other embodiments, odd-numbered GOA units can be cascaded, and even-numbered GOA units can be cascaded.

[0247] It is understood that since the light-emitting control circuit can have essentially the same technical effect as the shift register unit described in the previous embodiment, the technical effect of the light-emitting control circuit will not be described again here for the sake of brevity.

[0248] This application also provides a display device. As shown in FIG31, the display device includes: a display panel 100, and a light-emitting control circuit 000 as described in the foregoing embodiments.

[0249] The display panel 100 includes multiple pixels (not shown in the figure). The light emission control circuit 000 is connected to the multiple pixels via an output terminal OUT (e.g., drive output terminal OUT1) and is used to transmit light emission control signals to the multiple pixels to drive the multiple pixels to emit light.

[0250] Optionally, the display panel in the display device may generally include a substrate, and the substrate may have a display area and a non-display area at least partially surrounding the display area. Multiple pixels may be located in the display area, and the light-emitting control circuit 000 may be located in the non-display area. Furthermore, at least one pixel may include interconnected pixel circuitry and light-emitting elements, and the pixel circuitry may include at least one light-emitting control transistor. The GOA unit in the light-emitting control circuit 000 may be connected to the gate of the at least one light-emitting control transistor via its output terminal to transmit the required light-emitting control signal to the gate of the at least one light-emitting control transistor.

[0251] Optionally, the display device described in this application embodiment can be any product or component with display function, such as an organic light-emitting diode (OLED) display device, an active-matrix organic light-emitting diode (AMOLED) display device, or a liquid crystal display device. Furthermore, the display device can be any suitable display device, including but not limited to mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, navigators, and e-books, etc., any product or component with display function.

[0252] Optionally, the light-emitting control circuit described in this application is not limited to use in display panels, that is, it is not limited to use in the display field. For example, in some other embodiments, it can also be applied to other scenarios such as chips or integrated circuits.

[0253] Since the display device can have essentially the same technical effect as the light-emitting control circuit described in the previous embodiments, for the sake of brevity, the technical effect of the display device will not be described again here.

[0254] It should be noted that the terminology used in the embodiments of this application is for illustrative purposes only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in the implementation of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0255] For example, the words “first,” “second,” or “third,” and similar terms used in the patent application specification and claims of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0256] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0257] The word “includes” or similar terms means that the elements or objects preceding “includes” or “include” cover the elements or objects listed after “includes” or “include” or their equivalents, and do not exclude other elements or objects.

[0258] Terms like "up," "down," "left," or "right" are used only to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Connection" or "coupled" refers to an electrical connection.

[0259] The "and / or" signifies that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0260] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A shift register unit, the shift register unit comprising: An input circuit is connected to an input terminal, a clock terminal, a first power supply terminal, a target signal terminal, a pull-up node, and a pull-down node, respectively. It is used to control the connection and disconnection between the input terminal and the pull-up node, the connection and disconnection between the target signal terminal and the pull-down node, and the connection and disconnection between the first power supply terminal and the pull-down node, in response to an input signal provided by the input terminal, a clock signal provided by the clock terminal, a first power supply signal provided by the first power supply terminal, and a target signal provided by the target signal terminal. The target signal terminal is either a second power supply terminal or shared with the clock terminal. The output circuit is connected to the pull-up node, the pull-down node, the third power supply terminal, the fourth power supply terminal, and the output terminal, respectively, and is used to control the connection and disconnection between the third power supply terminal and the output terminal in response to the potential of the pull-up node, and to control the connection and disconnection between the fourth power supply terminal and the output terminal in response to the potential of the pull-down node.

2. The shift register unit according to claim 1, wherein, The input circuit includes: The first input sub-circuit is connected to the clock terminal, the input terminal, and the pull-up node respectively, and is used to control the on / off state of the input terminal and the pull-up node in response to the clock signal; The second input sub-circuit is connected to the input terminal, the first power supply terminal, the clock terminal, the control terminal, the intermediate node, and the pull-down node, respectively, and is used to control the potential of the intermediate node in response to the input signal, the first power supply signal, and the clock signal, and to control the on / off state of the first power supply terminal and the pull-down node in response to the control signal provided by the control terminal; wherein, the control terminal shares the same connection with the input terminal or is connected to the pull-up node; The third input sub-circuit is connected to the intermediate node, the target signal terminal, and the pull-down node respectively, and is used to control the on / off state of the target signal terminal and the pull-down node in response to the potential of the intermediate node.

3. The shift register unit according to claim 2, wherein, The second input sub-circuit includes: The first input unit is connected to the input terminal, the first power supply terminal, the clock terminal, and the intermediate node, respectively, and is used to control the on / off state of the first power supply terminal and the intermediate node in response to the input signal, and to control the potential of the intermediate node in response to the clock signal, or, in response to... The input signal and the clock signal control the connection and disconnection between the first power supply terminal and the intermediate node; The second input unit is connected to the control terminal, the first power terminal, and the pull-down node respectively, and is used to control the connection and disconnection of the first power terminal and the pull-down node in response to the control signal.

4. The shift register unit according to claim 3, wherein, When the first input unit controls the switching between the first power supply terminal and the intermediate node in response to the input signal, and controls the potential of the intermediate node in response to the clock signal, the first input unit includes: a first transistor and a first capacitor; and the gate of the first transistor is connected to the input terminal, the first electrode of the first transistor is connected to the first power supply terminal, the second electrode of the first transistor is connected to the intermediate node, one end of the first capacitor is connected to the clock terminal, and the other end of the first capacitor is connected to the intermediate node; When the first input unit controls the on / off state of the first power supply terminal and the intermediate node in response to the input signal and the clock signal, the first input unit includes: a first transistor and a second transistor; and the gate of the first transistor is connected to the input terminal, the first electrode of the first transistor is connected to the first power supply terminal, the second electrode of the first transistor is connected to the first electrode of the second transistor, the gate of the second transistor is connected to the clock terminal, and the second electrode of the second transistor is connected to the intermediate node. The second input unit includes a third transistor; and the gate of the third transistor is connected to the control terminal, the first terminal of the third transistor is connected to the first power supply terminal, and the second terminal of the third transistor is connected to the pull-down node.

5. The shift register unit according to claim 4, wherein, The first transistor includes two first sub-transistors with their first and second terminals connected in series; the third transistor includes two second sub-transistors with their first and second terminals connected in series; the shift register unit further includes: A first control circuit is connected to the intermediate node, the fifth power supply terminal, the series node of the two first sub-transistors, and the series node of the two second sub-transistors, respectively, and is used to control the on / off state of the fifth power supply terminal and the connected series node in response to the potential of the intermediate node.

6. The shift register unit according to claim 5, wherein, The first control circuit includes: a fourth transistor; Furthermore, the gate of the fourth transistor is connected to the intermediate node, the first terminal of the fourth transistor is connected to the fifth power supply terminal, and the second terminal of the fourth transistor is connected to the series node of the two first sub-transistors and the series node of the two second sub-transistors.

7. The shift register unit according to any one of claims 2 to 6, wherein, The first input sub-circuit includes: a fifth transistor; Furthermore, the gate of the fifth transistor is connected to the clock terminal, the first terminal of the fifth transistor is connected to the input terminal, and the second terminal of the fifth transistor is connected to the pull-up node.

8. The shift register unit according to any one of claims 2 to 7, wherein, The third input sub-circuit includes: a sixth transistor; The gate of the sixth transistor is connected to the intermediate node, the first terminal of the sixth transistor is connected to the target signal terminal, and the second terminal of the sixth transistor is connected to the pull-down node.

9. The shift register unit according to any one of claims 1 to 8, wherein, The pull-up node includes: a first pull-up node and a second pull-up node; the input circuit is connected to the first pull-up node, and the output circuit is connected to the second pull-up node; the shift register unit further includes: The second control circuit is connected to the sixth power supply terminal, the first pull-up node and the second pull-up node respectively, and is used to control the on and off of the first pull-up node and the second pull-up node in response to the sixth power supply signal provided by the sixth power supply terminal. And / or, The pull-down node includes: a first pull-down node and a second pull-down node; the input circuit is connected to the first pull-down node, and the output circuit is connected to the second pull-down node; the shift register unit further includes: The third control circuit is connected to the clock terminal, the first pull-down node, and the second pull-down node respectively, and is used to control the on / off state of the first pull-down node and the second pull-down node in response to the clock signal.

10. The shift register unit according to claim 9, wherein, The second control circuit includes a seventh transistor; the third control circuit includes an eighth transistor. Furthermore, the gate of the seventh transistor is connected to the sixth power supply terminal, the first terminal of the seventh transistor is connected to the first pull-up node, and the second terminal of the seventh transistor is connected to the second pull-up node; The gate of the eighth transistor is connected to the clock terminal, the first terminal of the eighth transistor is connected to the first pull-down node, and the second terminal of the eighth transistor is connected to the second pull-down node.

11. The shift register unit according to claim 9 or 10, wherein, The shift register unit further includes: A reset circuit is connected to a reset control terminal, a reset power supply terminal, and the second pull-down node, respectively, and is used to control the on / off state of the reset power supply terminal and the second pull-down node in response to a reset control signal provided by the reset control terminal; wherein the reset power supply terminal is shared with the third power supply terminal or the fourth power supply terminal.

12. The shift register unit according to claim 11, wherein, The reset circuit includes: a ninth transistor; The gate of the ninth transistor is connected to the reset control terminal, the first terminal of the ninth transistor is connected to the reset power supply terminal, and the second terminal of the ninth transistor is connected to the second pull-down node.

13. The shift register unit according to any one of claims 1 to 12, wherein, The output circuit includes: a tenth transistor, a second capacitor, an eleventh transistor, and a third capacitor; Furthermore, the gate of the tenth transistor is connected to the pull-up node, the first terminal of the tenth transistor is connected to the third power supply terminal, and the second terminal of the tenth transistor is connected to the output terminal; One end of the second capacitor is connected to the pull-up node, and the other end of the second capacitor is connected to the output terminal; The gate of the eleventh transistor is connected to the pull-down node, the first terminal of the eleventh transistor is connected to the fourth power supply terminal, and the second terminal of the eleventh transistor is connected to the output terminal. One end of the third capacitor is connected to the pull-down node, and the other end of the third capacitor is connected to the fourth power supply terminal.

14. The shift register unit according to claim 13, wherein, The eleventh transistor includes: two third sub-transistors connected in series with their first and second terminals; the shift register unit further includes: The fourth control circuit is connected to the output terminal, the seventh power supply terminal, and the series node of the two third sub-transistors, respectively, and is used to control the on / off state of the seventh power supply terminal and the connected series node in response to the signal output through the output terminal.

15. The shift register unit according to claim 14, wherein, The fourth control circuit includes: a twelfth transistor; The gate of the twelfth transistor is connected to the output terminal, the first terminal of the twelfth transistor is connected to the seventh power supply terminal, and the second terminal of the twelfth transistor is connected to the series node of the two third sub-transistors.

16. The shift register unit according to any one of claims 1 to 15, wherein, The output terminal includes a shift output terminal and a drive output terminal. The shift output terminal is used to connect to other cascaded shift register units, and the drive output terminal is used to connect to pixels in the display panel. Furthermore, the output circuit is also connected to an eighth power supply terminal and a ninth power supply terminal. The output circuit includes: The first output sub-circuit is connected to the pull-up node, the pull-down node, the third power supply terminal, the fourth power supply terminal, and the shift output terminal, respectively, and is used to control the on / off state of the third power supply terminal and the shift output terminal in response to the potential of the pull-up node, and to control the on / off state of the fourth power supply terminal and the shift output terminal in response to the potential of the pull-down node. The second output sub-circuit is connected to the pull-up node, the pull-down node, the eighth power supply terminal, the ninth power supply terminal, and the drive output terminal, respectively. It is used to control the connection and disconnection between the eighth power supply terminal and the drive output terminal in response to the potential of the pull-up node, and to control the connection and disconnection between the ninth power supply terminal and the drive output terminal in response to the potential of the pull-down node.

17. The shift register unit according to claim 16, wherein, The potential of the ninth power signal provided by the ninth power terminal is less than the potential of the fourth power signal provided by the fourth power terminal.

18. The shift register unit according to claim 16 or 17, wherein, The first output sub-circuit includes: a tenth transistor, a second capacitor, an eleventh transistor, and a third capacitor; the second output sub-circuit includes: a twelfth transistor and a thirteenth transistor; Furthermore, the gate of the tenth transistor is connected to the pull-up node, the first terminal of the tenth transistor is connected to the third power supply terminal, and the second terminal of the tenth transistor is connected to the shift output terminal. One end of the second capacitor is connected to the pull-up node, and the other end of the second capacitor is connected to the shift output terminal; The gate of the eleventh transistor is connected to the pull-down node, the first terminal of the eleventh transistor is connected to the fourth power supply terminal, and the second terminal of the eleventh transistor is connected to the shift output terminal. One end of the third capacitor is connected to the pull-down node, and the other end of the third capacitor is connected to the fourth power supply terminal. The gate of the twelfth transistor is connected to the pull-up node, the first terminal of the twelfth transistor is connected to the eighth power supply terminal, and the second terminal of the twelfth transistor is connected to the drive output terminal. The gate of the thirteenth transistor is connected to the pull-down node, the first terminal of the thirteenth transistor is connected to the ninth power supply terminal, and the second terminal of the thirteenth transistor is connected to the drive output terminal.

19. A method for driving a shift register unit, used to drive a shift register unit as described in any one of claims 1 to 18; the method comprising: In the first stage, the input circuit responds to the input signal provided by the input terminal, the clock signal provided by the clock terminal, the first power signal provided by the first power supply terminal, and the target signal provided by the target signal terminal, controlling the input terminal to be connected to the pull-up node, controlling the target signal terminal to be disconnected from the pull-down node, and controlling the first power supply terminal to be connected to the pull-down node. The output circuit responds to the potential of the pull-up node, controlling the third power supply terminal to be connected to the output terminal, and responds to the potential of the pull-down node, controlling the fourth power supply terminal to be disconnected from the output terminal. In the second stage, the input circuit responds to the input signal, the clock signal, the first power signal, and the target signal by controlling the input terminal to be connected to the pull-up node, controlling the target signal terminal to be connected to the pull-down node, and controlling the first power terminal to be disconnected from the pull-down node. The output circuit responds to the potential of the pull-up node by controlling the third power terminal to be disconnected from the output terminal, and responds to the potential of the pull-down node by controlling the fourth power terminal to be connected to the output terminal.

20. A light-emitting control circuit, the light-emitting control circuit comprising: Cascaded multi-stage shift register units as described in any one of claims 1 to 18.

21. A display device, the display device comprising: The display panel, and the light-emitting control circuit as described in claim 20; The display panel includes multiple pixels; The light emission control circuit is connected to the plurality of pixels via its output terminal and is used to transmit light emission control signals to the plurality of pixels to drive the plurality of pixels to emit light.

Images