Semiconductor structure, manufacturing method therefor, and electronic device

Abstract

A semiconductor structure, a manufacturing method therefor, and an electronic device. The semiconductor structure comprises: active pillars, which extend in a vertical direction; word lines, which extend in a first horizontal direction and are coupled with the active pillars to form transistors; and bit lines, which extend in a second horizontal direction and are coupled to the active pillars, wherein the second horizontal direction intersects with the first horizontal direction. The word lines comprise first gate portions and second gate portions that cover sidewalls of the active pillars and are connected to each other, the first gate portions being located on at least one side of the active pillars in the first horizontal direction, the second gate portions being located on at least one side of the active pillars in the second horizontal direction, and the average size of the first gate portions in the vertical direction being different from the average size of the second gate portions in the vertical direction. The semiconductor structure can reduce leakage current caused by gate-induced drain leakage, thereby improving device performance.

Description

Semiconductor structure and its manufacturing method, electronic equipment

[0001] This application claims priority to Chinese Patent Application No. 202411545203.9, filed on October 31, 2024, entitled "Semiconductor Structure and Manufacturing Method Thereof, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure, a method for manufacturing the same, and an electronic device. Background Technology

[0003] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared to static memory (SRAM), DRAM has advantages such as simpler structure, lower manufacturing cost, and higher storage density. With technological advancements, DRAM applications are becoming increasingly widespread. DRAM consists of multiple memory cells, each including a transistor and a capacitor coupled to the transistor. One of the transistor's source and drain is connected to a bit line, the other is connected to a capacitor, and the transistor's gate is connected to a word line. Under the control of the word line, the transistor writes data to or reads data from the capacitor via the bit line.

[0004] With the development of semiconductor technology, an architectural scheme has been proposed to replace planar transistors or buried transistors in DRAM with vertical transistors (whose channels extend at least partially in a vertical direction). In this architecture, vertically extending active pillars are formed on the substrate, and gates are formed on the sides of the active pillars. Summary of the Invention

[0005] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising: an active pillar extending in a vertical direction; a word line extending in a first horizontal direction and coupled to the active pillar to form a transistor; and a bit line extending in a second horizontal direction and coupled to the active pillar, wherein the second horizontal direction intersects the first horizontal direction; wherein the word line includes a first gate portion and a second gate portion covering the sidewalls of the active pillar and connected to each other, the first gate portion being located on at least one side of the active pillar in the first horizontal direction, the second gate portion being located on at least one side of the active pillar in the second horizontal direction, and the average size of the first gate portion in the vertical direction being different from the average size of the second gate portion in the vertical direction.

[0006] In some embodiments, the active post includes a first source / drain region, a channel region, and a second source / drain region arranged sequentially in a vertical direction, wherein the average dimension of one of the first gate portion and the second gate portion in the vertical direction is smaller than the channel length of the channel region in the vertical direction.

[0007] In some embodiments, the maximum dimension of one of the first gate portion and the second gate portion in the vertical direction is smaller than the channel length of the channel region in the vertical direction.

[0008] In some embodiments, the average size of the first gate portion in the vertical direction is smaller than the average size of the second gate portion in the vertical direction.

[0009] In some embodiments, the word line includes two first gate portions located on opposite sides of the active post in a first horizontal direction and two second gate portions located on opposite sides of the active post in a second horizontal direction.

[0010] In some embodiments, the average size of the first gate portion in the horizontal direction perpendicular to the first horizontal direction is smaller than the average size of the second gate portion in the horizontal direction perpendicular to the second horizontal direction.

[0011] In some embodiments, the top surface of the first gate portion is lower than or flush with the top surface of the second gate portion.

[0012] In some embodiments, the word line includes a first gate portion located on one side of the active post in a first horizontal direction and two second gate portions located on opposite sides of the active post in a second horizontal direction.

[0013] In some embodiments, the average size of the first gate portion in the horizontal direction perpendicular to the first horizontal direction is greater than the average size of the second gate portion in the horizontal direction perpendicular to the second horizontal direction, and the top surface of the first gate portion is lower than the top surface of the second gate portion.

[0014] In some embodiments, the average size of the first gate portion in the horizontal direction perpendicular to the first horizontal direction is equal to the average size of the second gate portion in the horizontal direction perpendicular to the second horizontal direction, and the top surface of the first gate portion is flush with the top surface of the second gate portion.

[0015] In some embodiments, the average size of the first gate portion in the vertical direction is greater than the average size of the second gate portion in the vertical direction.

[0016] In some embodiments, the word line includes two first gate portions located on opposite sides of the active post in a first horizontal direction and two second gate portions located on opposite sides of the active post in a second horizontal direction.

[0017] In some embodiments, the word line includes a first gate portion located on one side of the active post in a first horizontal direction and two second gate portions located on opposite sides of the active post in a second horizontal direction.

[0018] In some embodiments, the average size of the first gate portion in the horizontal direction perpendicular to the first horizontal direction is smaller than the average size of the second gate portion in the horizontal direction perpendicular to the second horizontal direction.

[0019] In some embodiments, the bottom surface of the first gate portion is lower than or flush with the bottom surface of the second gate portion.

[0020] In some embodiments, the semiconductor structure further includes a data storage unit coupled to a transistor.

[0021] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing a semiconductor substrate; etching the semiconductor substrate to form active pillars extending in a vertical direction; forming word lines, wherein the word lines extend in a first horizontal direction and are coupled to the active pillars; forming bit lines, wherein the bit lines extend in a second horizontal direction and are coupled to the active pillars, the second horizontal direction intersecting the first horizontal direction; wherein the word lines include a first gate portion and a second gate portion covering the sidewalls of the active pillars and connected to each other, the first gate portion being located on at least one side of the active pillar in the first horizontal direction, the second gate portion being located on at least one side of the active pillar in the second horizontal direction, and the average size of the first gate portion in the vertical direction being different from the average size of the second gate portion in the vertical direction.

[0022] According to a third aspect of the present disclosure, an electronic device is provided, including a processor and a memory provided in any embodiment of the present disclosure. The memory is coupled to the processor.

[0023] In the semiconductor structure provided in the embodiments of this disclosure, the average size of the first gate portion in the vertical direction is different from the average size of the second gate portion in the vertical direction. This helps to reduce the lateral overlap area between one of the first and second gate portions and the source / drain regions in the active pillar, thereby reducing the leakage current caused by gate-induced drain leakage (GIDL) and thus improving device performance. Attached Figure Description

[0024] Figure 1A is a partial planar structural schematic diagram of a semiconductor structure provided in some embodiments of this disclosure;

[0025] Figure 1B is a schematic diagram of a partial cross-sectional structure taken along line A1-A2 in Figure 1A, according to some embodiments of the present disclosure;

[0026] Figure 1C is a schematic diagram of a partial cross-sectional structure taken along line B1-B2 in Figure 1A according to some embodiments of the present disclosure;

[0027] Figure 1D is a schematic diagram of a structure surrounding a first gate portion and a second gate portion of the same active pillar according to some embodiments of the present disclosure;

[0028] Figure 1E is a schematic diagram of another structure surrounding the first gate portion and the second gate portion of the same active pillar provided in some embodiments of this disclosure;

[0029] Figure 2A is a schematic diagram of a partial cross-sectional structure taken along line A1-A2 in Figure 1A according to some embodiments of the present disclosure;

[0030] Figure 2B is a schematic diagram of a partial cross-sectional structure taken along line B1-B2 in Figure 1A according to some embodiments of the present disclosure;

[0031] Figure 2C is a schematic diagram of another structure surrounding the first gate portion and the second gate portion of the same active pillar provided in some embodiments of this disclosure;

[0032] Figure 2D is a schematic diagram of another structure surrounding the first gate portion and the second gate portion of the same active pillar provided in some embodiments of this disclosure;

[0033] Figure 3A is a partial planar structural schematic diagram of a semiconductor structure provided in some other embodiments of this disclosure;

[0034] Figure 3B is a schematic diagram of a partial cross-sectional structure taken along line A1-A2 in Figure 3A, according to some embodiments of the present disclosure;

[0035] Figure 3C is a schematic diagram of a partial cross-sectional structure taken along line B1-B2 in Figure 3A according to some embodiments of the present disclosure;

[0036] Figure 3D is a schematic diagram of the structure of a first gate portion and a second gate portion surrounding the same active pillar provided in some embodiments of this disclosure;

[0037] Figure 3E is a schematic diagram of another structure surrounding the first gate portion and the second gate portion of the same active pillar provided in some embodiments of this disclosure;

[0038] Figure 4A is a schematic diagram of a partial cross-sectional structure taken along line A1-A2 in Figure 3A according to some embodiments of the present disclosure;

[0039] Figure 4B is a schematic diagram of a partial cross-sectional structure taken along line B1-B2 in Figure 3A according to some embodiments of the present disclosure;

[0040] Figure 4C is a schematic diagram of another structure surrounding the first gate portion and the second gate portion of the same active pillar provided in some embodiments of this disclosure;

[0041] Figure 4D is a schematic diagram of another structure surrounding the first gate portion and the second gate portion of the same active pillar provided in some embodiments of this disclosure;

[0042] Figures 5A-5D are schematic cross-sectional views of certain stages of a semiconductor structure manufacturing method according to some embodiments of this disclosure;

[0043] Figures 6A-6D are schematic cross-sectional views of certain stages of a semiconductor structure manufacturing method according to some other embodiments of this disclosure;

[0044] Figures 7A-7E are schematic cross-sectional views of certain stages of a semiconductor structure manufacturing method provided in some embodiments of this disclosure;

[0045] Figures 8A-8D are schematic cross-sectional views of certain stages of a semiconductor structure manufacturing method according to some embodiments of this disclosure;

[0046] Figure 9 is a schematic block diagram of the structure of an electronic device provided in some embodiments of this disclosure. Detailed Implementation

[0047] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0048] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0049] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0050] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0051] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0052] In embodiments of this disclosure, the term "coupling" refers to the operative connection of two (or more) conductive structures to each other. Depending on actual needs, this may include, but is not limited to, the following: 1) two conductive structures are directly electrically connected; 2) two conductive structures are indirectly electrically connected (through other conductive structures); 3) although two conductive structures are not electrically connected (e.g., an insulating layer is provided between them), one of the two conductive structures can control the electrical performance of the other two conductive structures in response to an electrical signal, for example, a gate (or word line) is coupled to an active region (or channel region).

[0053] It should be noted that the technical solutions and technical features described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0054] This disclosure provides at least some embodiments of a semiconductor structure comprising: an active pillar extending in a vertical direction; a word line extending in a first horizontal direction and coupled to the active pillar to form a transistor; and a bit line extending in a second horizontal direction and coupled to the active pillar, wherein the second horizontal direction intersects the first horizontal direction; wherein the word line includes a first gate portion and a second gate portion covering the sidewalls of the active pillar and connected to each other, the first gate portion being located on at least one side of the active pillar in the first horizontal direction, the second gate portion being located on at least one side of the active pillar in the second horizontal direction, and the average size of the first gate portion in the vertical direction being different from the average size of the second gate portion in the vertical direction.

[0055] In the semiconductor structure provided in the embodiments of this disclosure, the average size of the first gate portion in the vertical direction is different from the average size of the second gate portion in the vertical direction. This helps to reduce the lateral overlap area between one of the first and second gate portions and the source / drain regions in the active pillar, thereby reducing the leakage current caused by gate-induced drain leakage (GIDL) and thus improving device performance.

[0056] The semiconductor structure provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0057] Figure 1A is a partial planar structural schematic diagram of a semiconductor structure provided by some embodiments of the present disclosure; Figure 1B is a partial cross-sectional structural schematic diagram of a structure taken along line A1-A2 in Figure 1A provided by some embodiments of the present disclosure; Figure 1C is a partial cross-sectional structural schematic diagram of a structure taken along line B1-B2 in Figure 1A provided by some embodiments of the present disclosure; Figure 1D is a structural schematic diagram of a first gate portion and a second gate portion surrounding the same active pillar provided by some embodiments of the present disclosure; and Figure 1E is a structural schematic diagram of another first gate portion and a second gate portion surrounding the same active pillar provided by some embodiments of the present disclosure.

[0058] As shown in Figures 1A-1E, the semiconductor structure includes an active pillar 110, a word line 120, and a bit line 140. The active pillar 110 extends along a vertical direction Z; the word line 120 extends along a first horizontal direction X and is coupled to the active pillar 120 to form a transistor TR; the bit line 140 extends along a second horizontal direction Y and is coupled to the active pillar 120. The second horizontal direction Y intersects the first horizontal direction X. For example, the second horizontal direction Y is perpendicular to the first horizontal direction X. The word line 120 includes a first gate portion 121 and a second gate portion 122 that cover the sidewalls of the active pillar 110 and are connected to each other. The first gate portion 121 is located on at least one side of the active pillar 110 in the first horizontal direction X, and the second gate portion 122 is located on at least one side of the active pillar in the second horizontal direction Y. The average size of the first gate portion 121 in the vertical direction Z is different from the average size of the second gate portion 122 in the vertical direction Z. In this disclosure, the value of the "average size" of a component in a certain direction can be obtained by integrating and summing the dimensions of the component in that direction and then taking the average value.

[0059] For example, in some examples, as shown in Figures 1A-1E, the word line 120 includes two first gate portions 121 located on opposite sides of the active pillar 110 in the first horizontal direction X, and two second gate portions 122 located on opposite sides of the active pillar 110 in the second horizontal direction Y. For example, as shown in Figure 1A, the first gate portions 121 and the second gate portions 123 are connected by a gate connection portion 123; of course, in some examples, the gate connection portion 123 may be part of the first gate portion 121 or part of the second gate portion 123.

[0060] For example, as shown in Figures 1D and 1E, the active pillar 110 includes a first source / drain region 110a, a channel region 110b, and a second source / drain region 110c arranged sequentially in the vertical direction Z. The average size of one of the first gate portion 121 and the second gate portion 122 in the vertical direction Z is smaller than the channel length of the channel region 110b in the vertical direction Z. For example, the maximum size of one of the first gate portion 121 and the second gate portion 122 in the vertical direction Z is smaller than the channel length of the channel region 110b in the vertical direction Z.

[0061] For example, in some examples, as shown in Figures 1D and 1E, the average size (or maximum size) of the first gate portion 121 in the vertical direction Z is smaller than the average size (or maximum size) of the second gate portion 122 in the vertical direction Z. For example, as shown in Figures 1D and 1E, the average size of the first gate portion 121 in the vertical direction Z is smaller than the channel length of the channel region 110b in the vertical direction Z, and the average size of the second gate portion 122 in the vertical direction Z is larger than the channel length of the channel region 110b in the vertical direction Z. For example, if the average size of the gate connection portion 123 in the vertical direction Z is closer to the average size of the first gate portion 121 in the vertical direction Z, the gate connection portion 123 can be considered as part of the first gate portion 121; conversely, if the average size of the gate connection portion 123 in the vertical direction Z is closer to the average size of the second gate portion 122 in the vertical direction Z, the gate connection portion 123 can be considered as part of the second gate portion 122.

[0062] For example, in some examples, as shown in Figures 1D and 1E, at least a portion of the channel region 110b is located outside the region defined by the planes containing the top and bottom surfaces of the first gate portion 121, while the entire channel region 110b is located within the region defined by the planes containing the top and bottom surfaces of the first gate portion 121. For example, as shown in Figure 1D, the first gate portion 121 does not laterally overlap with either the first source / drain region 110a or the second source / drain region 110c; or, as shown in Figure 1E, the first gate portion 121 laterally overlaps with the second source / drain region 110c but not with the first source / drain region 110a. Conversely, as shown in Figures 1D and 1E, the second gate portion 122 laterally overlaps with both the first source / drain region 110a and the second source / drain region 110c.

[0063] For example, in some examples, as shown in FIG1A, the average size of the first gate portion 121 in the horizontal direction perpendicular to the first horizontal direction X is smaller than the average size of the second gate portion in the horizontal direction perpendicular to the second horizontal direction Y. For example, when the second horizontal direction Y is perpendicular to the first horizontal direction X, the horizontal direction perpendicular to the first horizontal direction X is the second horizontal direction Y, and the horizontal direction perpendicular to the second horizontal direction Y is the first horizontal direction X.

[0064] For example, in some examples, as shown in FIG1D, the top surface of the first gate portion 121 is lower than the top surface of the second gate portion 122. For example, in other examples, as shown in FIG1E, the top surface of the first gate portion 121 is flush with the top surface of the second gate portion 122.

[0065] For example, as shown in Figures 1A-1E, the semiconductor structure may further include a gate dielectric layer 130 disposed between the active pillar 110 and the word line 120. For example, both the first gate portion 121 and the second gate portion 122 cover the gate dielectric layer 130, and the gate dielectric layer 130 may be a component of the transistor TR.

[0066] For example, as shown in Figures 1B and 1C, the semiconductor structure may further include a data storage unit SE coupled to a transistor TR. The embodiments of this disclosure use a capacitor as an example to illustrate the data storage unit SE, but this should not be construed as a limitation of the disclosure. For example, in some examples, as shown in Figures 1B and 1C, the capacitor SE may include a first electrode 150, a second electrode 160, and a capacitor dielectric layer 170 disposed between the first electrode 150 and the second electrode 160. For example, the second electrodes 160 of multiple capacitor SEs may be formed as a common electrode 160. It is understood that the data storage unit SE is not limited to a capacitor; for example, the data storage unit SE may also be a FeRAM memory cell (such as a ferroelectric capacitor), a PCM memory cell, an MRAM memory cell, etc. That is, the semiconductor structure provided in the embodiments of this disclosure can be formed as DRAM, FeRAM (ferroelectric random access memory), PCM (phase-change memory), MRAM (magnetic random access memory), etc.

[0067] For example, in some examples, as shown in Figures 1B and 1C, the first electrode 150 can be coupled to the corresponding active post 110 via contact pad 115; the bit line 140 can be coupled to the corresponding active post 110 via bit line contact plug 135. For example, in other examples, at least one of the contact pad 115 and the bit line contact plug 135 can be omitted.

[0068] For example, the material of the active pillar 110 can include any suitable semiconductor material, such as silicon, germanium, gallium arsenide, etc. For example, the materials of the gate dielectric layer 130 and the capacitor dielectric layer 170 include any suitable dielectric material, such as silicon dioxide, silicon nitride, high-K dielectric materials, or any combination thereof; for example, high-K dielectric materials can include, but are not limited to, hafnium oxide (HfO2), zirconium oxide (ZrO2), etc. For example, the materials of the word line 120, bit line 140, contact pad 115, bit line contact plug 135, first electrode 150, and second electrode 160 can each include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicides, doped polysilicon, or any combination thereof.

[0069] Figure 2A is a partial cross-sectional view of an embodiment of the present disclosure taken along line A1-A2 in Figure 1A. Figure 2B is a partial cross-sectional view of an embodiment of the present disclosure taken along line B1-B2 in Figure 1A. Figure 2C is another structural diagram of a first gate portion and a second gate portion surrounding the same active pillar, provided by some embodiments of the present disclosure. Figure 2D is yet another structural diagram of a first gate portion and a second gate portion surrounding the same active pillar, provided by some embodiments of the present disclosure. The main difference between the semiconductor structures in the embodiments shown in Figures 2A-2D and those in the embodiments shown in Figures 1B-1E is that, as shown in Figures 2A-2D, the average dimension of the first gate portion 121 in the vertical direction Z is greater than the average dimension of the second gate portion 122 in the vertical direction Z. The following mainly describes the differences and some similarities between the embodiments shown in Figures 2A-2D and those shown in Figures 1B-1E. For similarities or differences not described, please refer to the relevant descriptions of the embodiments shown in Figures 1B-1E.

[0070] For example, in some examples, as shown in Figures 1A and 2A-2D, the word line 120 includes two first gate portions 121 located on opposite sides of the active pillar 110 in the first horizontal direction X and two second gate portions 122 located on opposite sides of the active pillar 110 in the second horizontal direction Y.

[0071] For example, in some examples, as shown in Figures 2C and 2D, the average size of the first gate portion 121 in the horizontal direction perpendicular to the first horizontal direction X is smaller than the average size of the second gate portion in the horizontal direction perpendicular to the second horizontal direction Y. For example, when the second horizontal direction Y is perpendicular to the first horizontal direction X, the horizontal direction perpendicular to the first horizontal direction X is the second horizontal direction Y, and the horizontal direction perpendicular to the second horizontal direction Y is the first horizontal direction X.

[0072] For example, in some examples, as shown in FIG2C, the bottom surface of the first gate portion 121 is lower than the bottom surface of the second gate portion 122. For example, in other examples, as shown in FIG2D, the bottom surface of the first gate portion 121 is flush with the bottom surface of the second gate portion 122.

[0073] Figure 3A is a partial planar structural schematic diagram of a semiconductor structure provided in some embodiments of this disclosure; Figure 3B is a partial cross-sectional structural schematic diagram taken along line A1-A2 in Figure 3A provided in some embodiments of this disclosure; Figure 3C is a partial cross-sectional structural schematic diagram taken along line B1-B2 in Figure 3A provided in some embodiments of this disclosure; Figure 3D is a structural schematic diagram of a first gate portion and a second gate portion surrounding the same active pillar provided in some embodiments of this disclosure; and Figure 3E is a structural schematic diagram of another first gate portion and a second gate portion surrounding the same active pillar provided in some embodiments of this disclosure. The main difference between the semiconductor structures in the embodiments shown in Figures 3A-3E and those in the embodiments shown in Figures 1A-1E is that, as shown in Figures 3A-3E, the word line 120 includes a first gate portion 121 located on one side of the active pillar 110 in the first horizontal direction X and two second gate portions 122 located on opposite sides of the active pillar 110 in the second horizontal direction Y. That is, in the embodiments shown in Figures 1A-1E, the transistor TR has a fully encircling gate structure; while in the embodiments shown in Figures 3A-3E, the transistor TR has a three-sided encircling gate structure. The following mainly describes the differences and some similarities between the embodiments shown in Figures 3A-3E and the embodiments shown in Figures 1A-1E. For similarities or differences not described, please refer to the relevant descriptions of the embodiments shown in Figures 1A-1E.

[0074] For example, in some examples, as shown in Figures 3A and 3C, multiple active columns 110 are arranged in the second horizontal direction Y in an alternating manner with a first spacing D1 and a second spacing D2, wherein the first spacing D1 is greater than the second spacing D2.

[0075] For example, in some examples, as shown in Figures 3A-3E, the average size (or maximum size) of the first gate portion 121 in the vertical direction Z is smaller than the average size (or maximum size) of the second gate portion 122 in the vertical direction Z.

[0076] For example, in some examples, as shown in FIG3D, the average size of the first gate portion 121 in the horizontal direction perpendicular to the first horizontal direction X is greater than the average size of the second gate portion in the horizontal direction perpendicular to the second horizontal direction Y, and the top surface of the first gate portion 121 is lower than the top surface of the second gate portion 122. For example, in other examples, as shown in FIG3E, the average size of the first gate portion 121 in the horizontal direction perpendicular to the first horizontal direction X is equal to the average size of the second gate portion in the horizontal direction perpendicular to the second horizontal direction Y, and the top surface of the first gate portion 121 is flush with the top surface of the second gate portion 122.

[0077] For example, in some examples, as shown in Figure 3C, the semiconductor structure may also include an air gap AG located between adjacent transistors TR in the second horizontal direction Y. The air gap AG can reduce coupling effects between adjacent transistors TR (e.g., coupling effects between adjacent word lines 120, coupling effects between adjacent active pillars 110, etc.).

[0078] It should be noted that, in order to save area and optimize layout, the planar shape of the active column 110 in the embodiments shown in Figures 3A-3E is different from the planar shape of the active column 110 in the embodiments shown in Figures 1A-1E. It is understood that the planar shape of the active column 110 has no substantial impact on the implementation of the technical solution. Therefore, the embodiments of this disclosure do not limit the planar shape of the active column 110.

[0079] Figure 4A is a partial cross-sectional view of an embodiment of the present disclosure taken along line A1-A2 in Figure 3A. Figure 4B is a partial cross-sectional view of an embodiment of the present disclosure taken along line B1-B2 in Figure 3A. Figure 4C is another structural diagram of a first gate portion and a second gate portion surrounding the same active pillar, provided by some embodiments of the present disclosure. Figure 4D is yet another structural diagram of a first gate portion and a second gate portion surrounding the same active pillar, provided by some embodiments of the present disclosure. The main difference between the semiconductor structures in the embodiments shown in Figures 4A-4D and those in the embodiments shown in Figures 3B-3E is that, as shown in Figures 4A-4D, the average dimension of the first gate portion 121 in the vertical direction Z is greater than the average dimension of the second gate portion 122 in the vertical direction Z. The following mainly describes the differences and some similarities between the embodiments shown in Figures 4A-4D and those shown in Figures 3B-3E. For similarities or differences not described, please refer to the relevant descriptions of the foregoing embodiments.

[0080] For example, in some examples, as shown in Figures 3A and 4A-4D, word line 120 includes a first gate portion 121 located on one side of active post 110 in the first horizontal direction X and two second gate portions 122 located on opposite sides of active post 110 in the second horizontal direction Y.

[0081] For example, in some examples, as shown in Figures 4C and 4D, the average size of the first gate portion 121 in the horizontal direction perpendicular to the first horizontal direction X is smaller than the average size of the second gate portion in the horizontal direction perpendicular to the second horizontal direction Y. For example, when the second horizontal direction Y is perpendicular to the first horizontal direction X, the horizontal direction perpendicular to the first horizontal direction X is the second horizontal direction Y, and the horizontal direction perpendicular to the second horizontal direction Y is the first horizontal direction X.

[0082] For example, in some examples, as shown in FIG4C, the bottom surface of the first gate portion 121 is lower than the bottom surface of the second gate portion 122. For example, in other examples, as shown in FIG4D, the bottom surface of the first gate portion 121 is flush with the bottom surface of the second gate portion 122.

[0083] In the semiconductor structure provided in the embodiments of this disclosure, the average size of the first gate portion in the vertical direction is different from the average size of the second gate portion in the vertical direction. This helps to reduce the lateral overlap area between one of the first gate portion and the second gate portion and the source / drain region in the active pillar, thereby reducing the leakage current caused by GIDL and thus improving device performance.

[0084] At least some embodiments of this disclosure also provide a method for manufacturing a semiconductor structure, which can be used to manufacture the semiconductor structure provided in the foregoing embodiments. For example, the manufacturing method may include the following steps S100 to S400.

[0085] S100: Provides a semiconductor substrate;

[0086] S200: Etching the semiconductor substrate to form active pillars extending in the vertical direction;

[0087] S300: Forming a word line, wherein the word line extends along a first horizontal direction and is coupled to an active pillar, the word line includes a first gate portion and a second gate portion that cover the sidewalls of the active pillar and are connected to each other, the first gate portion is located on at least one side of the active pillar in the first horizontal direction, the second gate portion is located on at least one side of the active pillar in the second horizontal direction, and the average size of the first gate portion in the vertical direction is different from the average size of the second gate portion in the vertical direction.

[0088] S400: Form a bit line, wherein the bit line extends along a second horizontal direction and is coupled to an active post, and the second horizontal direction intersects with the first horizontal direction.

[0089] Figures 5A-5D are schematic cross-sectional views of certain stages of a semiconductor structure manufacturing method according to some embodiments of the present disclosure. In Figures 5A-5D, the left sub-figure corresponds to a cross-section taken along line A1-A2 in Figure 1A, and the right sub-figure corresponds to a cross-section taken along line B1-B2 in Figure 1A. Hereinafter, steps S200 to S300 of a semiconductor structure manufacturing method according to some embodiments of the present disclosure will be described with reference to Figures 5A-5D.

[0090] Referring to Figure 5A, the semiconductor substrate 100 can be etched first to form a trench T1 extending along the second horizontal direction Y, and an isolation layer 101 can be formed in the trench T1. Then, using a patterned hard mask layer 201 as a mask, the semiconductor substrate 100 and the isolation layer 101 are etched to form a trench T2 extending along the first horizontal direction X, thereby defining the active pillar 110. For example, the depth of the trench T2 is less than the depth of the trench T1.

[0091] Next, referring to FIG5B, vertically stacked isolation layers 103 and 105 can be formed on the sidewalls of trench T2. For example, isolation layers 103 and 105 can each be formed using atomic layer deposition and etch-back processes. The material of isolation layer 105 is the same as that of isolation layer 101, for example, both can be oxides (such as silicon dioxide).

[0092] Next, referring to FIG5C, the hard mask layer 201 can be removed to form an isolation layer 107 filling the trench T2. For example, the isolation layer 107 can be formed using a deposition process and a chemical mechanical polishing / etch-back process. The material of the isolation layer 107 is the same as that of the isolation layer 103, for example, both can be nitrides (such as silicon nitride).

[0093] Next, referring to FIG5D, a selective wet etching process can be used to remove part of the isolation layer 101 and the isolation layer 105, thereby forming a receiving groove 106 on both sides of the active pillar 110 in the first horizontal direction X. The receiving groove 106 is used to accommodate the first gate portion 121 of the word line 120 formed subsequently. The top surface of the remaining isolation layer 101 is lower than the bottom surface of the receiving groove 106.

[0094] Next, referring to Figures 1B-1E, the gate dielectric layer 130 and the word line 120 can be formed sequentially. For example, the gate dielectric layer 130 can be formed using atomic layer deposition and / or thermal oxidation processes; the word line 120 can be formed using atomic layer deposition and etch-back processes. For example, the etch-back process can be controlled so that the top surface of the second gate portion 122 is higher than the top surface of the first gate portion 121 (as shown in Figure 1D) or the top surface of the second gate portion 122 is flush with the top surface of the first gate portion 121 (as shown in Figure 1E).

[0095] Figures 6A-6D are schematic cross-sectional views of certain stages of a semiconductor structure manufacturing method according to some embodiments of the present disclosure. In Figures 6A-6D, the left sub-figure corresponds to the cross-section taken along line A1-A2 in Figure 1A, and the right sub-figure corresponds to the cross-section taken along line B1-B2 in Figure 1A. Hereinafter, steps S200 to S300 of a semiconductor structure manufacturing method according to some embodiments of the present disclosure will be described with reference to Figures 6A-6D.

[0096] Referring to FIG. 6A, the semiconductor substrate 100 can be etched to form a trench T3 extending along the second horizontal direction Y and a trench T4 extending along the first horizontal direction X, thereby defining the active pillar 110. For example, the opening width W1 of the trench T3 (i.e., the dimension of the opening of the trench T3 in the horizontal direction perpendicular to the second horizontal direction Y) is smaller than the opening width W2 of the trench T4 (i.e., the dimension of the opening of the trench T4 in the horizontal direction perpendicular to the first horizontal direction X), thereby utilizing the etching load effect, etching the semiconductor substrate 100 can yield a shallower trench T3 and a deeper trench T4. Here, only one etching of the semiconductor substrate 100 is required; in contrast, the embodiment shown in FIG. 5A requires two etchings of the semiconductor substrate 100.

[0097] Next, referring to Figure 6B, an isolation layer 301 can be formed to fill trenches T3 and T4. A chemical mechanical polishing (CMP) / etch-back process is used to make the top surface of the isolation layer 301 flush with the top surface of the active pillar 110. Then, the isolation layer 301 is etched back, and based on the etching load effect, the top surface of the remaining portion of the isolation layer 301 located in trench T3 is higher than the top surface of the remaining portion of the isolation layer 301 located in trench T4. For example, the material of the isolation layer 301 may include oxides (such as silicon dioxide), nitrides (silicon nitride), or oxides oxynitrides (silicon oxynitride), etc.

[0098] Next, referring to Figure 6C, the gate dielectric layer 130 can be formed first using atomic layer deposition and / or thermal oxidation processes; then, the word line material layer 120' can be formed using a deposition process, and the top surface of the word line material layer 120' can be made flush with the top surface of the gate dielectric layer 130 located on the active pillar 110 using a chemical mechanical polishing / etch-back process; then, a patterned hard mask layer 401 can be formed, and the openings in the patterned hard mask layer 401 expose a portion of the word line material layer 120' in the trench T4.

[0099] Next, referring to FIG6D, a patterned hard mask layer 401 can be used as a mask to etch a word line material layer 120' to form a groove T5 for defining mutually discrete initial word lines. The initial word lines include a first initial gate portion 121' and a second initial gate portion 122' covering the sidewalls of the active pillar 110 and connected to each other. The two first initial gate portions 121' are located on opposite sides of the active pillar 110 in the first horizontal direction X, and the two second initial gate portions 122' are located on opposite sides of the active pillar 110 in the second horizontal direction Y. The width of an initial gate portion 121' (i.e., the dimension of the first initial gate portion 121' in the horizontal direction perpendicular to the first horizontal direction X) is smaller than the width of the second initial gate portion 122' (i.e., the dimension of the second initial gate portion 122' in the horizontal direction perpendicular to the second horizontal direction Y), and the bottom surface of the first initial gate portion 121' is lower than the bottom surface of the second initial gate portion 122'. Then, the patterned hard mask layer 401 is removed, and an isolation layer 303 is formed in the groove T5. The isolation layer 303 is used to ensure that adjacent initial word lines are insulated from each other. For example, the isolation layer 303 can be formed using a deposition process and a chemical mechanical polishing / etch-back process. For example, the material of the isolation layer 303 can include oxides (such as silicon dioxide), nitrides (silicon nitride), or oxides nitrides (silicon oxynitride), etc. For example, in some examples, an air gap (not shown in the figure) can be formed in the isolation layer 303 by controlling the process parameters of the deposition process to reduce the coupling effect between adjacent word lines 120 formed subsequently.

[0100] Next, the initial word line can be etched back. Based on the etching load effect, the top surface of the remaining first initial gate portion 121' (i.e., the first gate portion 121) can be made higher than the top surface of the remaining second initial gate portion 122' (i.e., the second gate portion 121), thereby obtaining the word line 120 in the embodiment shown in FIG2C.

[0101] It should be noted that in the etching step of the semiconductor substrate 100 in FIG6A, the opening width W1 of trench T1 can be controlled to be equal to the opening width W2 of trench T2, thereby the depth of trench T1 is equal to the depth of trench T2; furthermore, in the step of etching back the isolation layer 301 in FIG6B, the top surface of the portion of the remaining isolation layer 301 located in trench T1 is flush with the top surface of the portion of the remaining isolation layer 301 located in trench T2; thus, in the word line subsequently formed, the bottom surface of the first gate portion 121 is flush with the bottom surface of the second gate portion 122, and the top surface of the first gate portion 121 is higher than the top surface of the second gate portion 122, that is, the word line 120 in the embodiment shown in FIG2D can be obtained.

[0102] In other words, the word line 120 in the embodiments shown in Figures 1A and 2A-2D can be formed by utilizing the etching load effect.

[0103] Figures 7A-7E are schematic cross-sectional views of certain stages of a semiconductor structure manufacturing method according to some embodiments of the present disclosure. In Figures 7A-7E, the left sub-figure corresponds to the cross-section taken along line A1-A2 in Figure 3A, and the right sub-figure corresponds to the cross-section taken along line B1-B2 in Figure 3A. Hereinafter, steps S200 to S300 of a semiconductor structure manufacturing method according to some embodiments of the present disclosure will be described with reference to Figures 7A-7E.

[0104] Referring to Figure 7A, the semiconductor substrate 100 can be etched first to form trenches T61 and T62 extending along the first horizontal direction X, and an isolation layer 501 filling the trenches T61 and T62 can be formed. The trenches T61 and T62 are arranged alternately, the opening width of the trench T61 is greater than the opening width of the trench T62, and the depth of the trench T61 is greater than the depth of the trench T62 due to the etching load effect. Then, using a patterned hard mask layer 601 as a mask, the semiconductor substrate 100 and the isolation layer 501 are etched to form a trench T7 extending along the second horizontal direction Y, thereby defining the active pillar 110.

[0105] Next, referring to FIG7B, an isolation layer 503 filling the trench T7 can be formed, and the isolation layer 503 is etched back until the top surface of the remaining isolation layer 503 is lower than the top surface of the isolation layer 501; then, the patterned hard mask layer 601 is removed. For example, the material of the isolation layer 503 is the same as the material of the isolation layer 501, for example, both can be oxides (such as silicon dioxide).

[0106] Next, referring to FIG7C, the isolation layers 501 and 503 can be etched back simultaneously, such that the top surface of the remaining isolation layer 503 is lower than the top surface of the portion of the remaining isolation layer 501 located in the trench T61; at the same time, due to the etching load effect, the top surface of the portion of the remaining isolation layer 501 located in the trench T62 is higher than the top surface of the portion of the remaining isolation layer 501 located in the trench T61.

[0107] Next, referring to Figure 7D, the gate dielectric layer 130 can be formed first using atomic layer deposition and / or thermal oxidation processes; then, the word line material layer 120' can be formed using a deposition process, and the top surface of the word line material layer 120' can be made flush with the top surface of the gate dielectric layer 130 located on the active pillar 110 using a chemical mechanical polishing / etch-back process; then, a patterned hard mask layer 603 can be formed, and the openings in the patterned hard mask layer 603 can expose part of the word line material layer 120' in the trench T61 and the word line material layer 120' in the trench T62.

[0108] Next, referring to FIG7E, a patterned hard mask layer 603 can be used as a mask to etch a word line material layer 120' to form a groove T8 for defining mutually discrete initial word lines. The initial word lines include a first initial gate portion 121' and a second initial gate portion 122' covering the sidewalls of the active pillar 110 and connected to each other. One first initial gate portion 121' is located on one side of the active pillar 110 in the first horizontal direction X, and the two second initial gate portions 122' are located on opposite sides of the active pillar 110 in the second horizontal direction Y. The width of the gate portion 121' (i.e., the dimension of the first initial gate portion 121' in the horizontal direction perpendicular to the first horizontal direction X) is greater than or equal to the width of the second initial gate portion 122' (i.e., the dimension of the second initial gate portion 122' in the horizontal direction perpendicular to the second horizontal direction Y), and the bottom surface of the first initial gate portion 121' is higher than the bottom surface of the second initial gate portion 122'. Then, the patterned hard mask layer 401 is removed, and an isolation layer 505 is formed in the groove T8. The isolation layer 505 is used to ensure that adjacent initial word lines are insulated from each other. For example, the material of the isolation layer 505 may include oxides (such as silicon dioxide), nitrides (silicon nitride), or oxide oxynitrides (silicon oxynitride), etc. For example, in some examples, an air gap (refer to the air gap AG in FIG. 3C) can be formed in the isolation layer 505 by controlling the process parameters of the deposition process to reduce the coupling effect between adjacent word lines 120 formed subsequently.

[0109] Next, the initial word line can be etched back. Based on the etching load effect, the top surface of the remaining first initial gate portion 121' (i.e., the first gate portion 121) can be made lower than or flush with the top surface of the remaining second initial gate portion 122' (i.e., the second gate portion 121), thereby obtaining the word line 120 in the embodiment shown in FIG3D or 3E.

[0110] Figures 8A-8D are schematic cross-sectional views of certain stages of a semiconductor structure manufacturing method according to some embodiments of the present disclosure. In Figures 8A-8D, the left sub-figure corresponds to the cross-section taken along line A1-A2 in Figure 3A, and the right sub-figure corresponds to the cross-section taken along line B1-B2 in Figure 3A. Hereinafter, steps S200 to S300 of a semiconductor structure manufacturing method according to some embodiments of the present disclosure will be described with reference to Figures 8A-8D.

[0111] Referring to Figure 8A, the semiconductor substrate 100 can be etched to form trenches T91 and T92 extending along a first horizontal direction X and a trench T10 extending along a second horizontal direction Y, thereby defining the active pillar 110. For example, trenches T61 and T62 are arranged alternately, and the opening width W4 of trench T92 and the opening width W5 of trench T10 are both smaller than the opening width W3 of trench T91. Thus, by utilizing the etching load effect, the semiconductor substrate 100 can be etched to obtain trenches T92 and T10 with shallow depths and trench T91 with greater depths. Here, only one etching operation is required on the semiconductor substrate 100.

[0112] Next, referring to FIG8B, an isolation layer 701 filling trenches T91, T92, and T92 can be formed. A chemical mechanical polishing (CMP) / etch-back process is used to make the top surface of the isolation layer 701 flush with the top surface of the active pillar 110. Then, the isolation layer 701 is etched back. Due to the etching load effect, the top surface of the remaining isolation layer 701 located in trench T91 is lower than the top surface of the remaining isolation layer 701 located in trenches T92 and T10. For example, the material of the isolation layer 701 may include oxides (such as silicon dioxide), nitrides (silicon nitride), or oxides oxynitrides (silicon oxynitride), etc.

[0113] Next, referring to Figure 8C, the gate dielectric layer 130 can be formed first using atomic layer deposition and / or thermal oxidation processes; then, the word line material layer 120' can be formed using a deposition process, and the top surface of the word line material layer 120' can be made flush with the top surface of the gate dielectric layer 130 located on the active pillar 110 using a chemical mechanical polishing / etch-back process; then, a patterned hard mask layer 801 can be formed, and the openings in the patterned hard mask layer 801 expose part of the word line material layer 120' in the trench T91 and the word line material layer 120' in the trench T92.

[0114] Next, referring to FIG8D, a patterned hard mask layer 803 can be used as a mask to etch a word line material layer 120' to form a groove T11 for defining mutually discrete initial word lines. The initial word lines include a first initial gate portion 121' and a second initial gate portion 122' covering the sidewalls of the active pillar 110 and connected to each other. One first initial gate portion 121' is located on one side of the active pillar 110 in the first horizontal direction X, and the two second initial gate portions 122' are located on opposite sides of the active pillar 110 in the second horizontal direction Y. The width of the initial gate portion 121' (i.e., the dimension of the first initial gate portion 121' in the horizontal direction perpendicular to the first horizontal direction X) is smaller than the width of the second initial gate portion 122' (i.e., the dimension of the second initial gate portion 122' in the horizontal direction perpendicular to the second horizontal direction Y), and the bottom surface of the first initial gate portion 121' is higher than the bottom surface of the second initial gate portion 122'. Then, the patterned hard mask layer 801 is removed, and an isolation layer 703 is formed in the groove T11. The isolation layer 703 is used to ensure that adjacent initial word lines are insulated from each other. For example, the material of the isolation layer 703 may include oxides (such as silicon dioxide), nitrides (silicon nitride), or oxynitrides (silicon oxynitride), etc. For example, in some examples, by controlling the process parameters of the deposition process, an air gap (refer to the air gap AG in FIG. 4B) can be formed in the isolation layer 703 to reduce the coupling effect between the subsequently formed adjacent word lines 120.

[0115] Next, the initial word line can be etched back. Based on the etching load effect, the top surface of the remaining first initial gate portion 121' (i.e., the first gate portion 121) can be made higher than the top surface of the remaining second initial gate portion 122' (i.e., the second gate portion 121), thereby obtaining the word line 120 in the embodiment shown in FIG4C.

[0116] It should be noted that in the etching step of the semiconductor substrate 100 in FIG8A, the opening width W5 of the trench T10 can be controlled to be equal to the opening width W3 of the trench T91, thereby the depth of the trench T10 is equal to the depth of the trench T91; furthermore, in the step of etching back the isolation layer 701 in FIG8B, the top surface of the portion of the remaining isolation layer 701 located in the trench T10 is flush with the top surface of the portion of the remaining isolation layer 701 located in the trench T91; thus, in the word line subsequently formed, the bottom surface of the first gate portion 121 is flush with the bottom surface of the second gate portion 122, and the top surface of the first gate portion 121 is higher than the top surface of the second gate portion 122, that is, the word line 120 in the embodiment shown in FIG4D can be obtained.

[0117] The embodiments disclosed herein do not limit the method of forming the bit line in step S400, and can refer to commonly used methods in the prior art. For example, in some embodiments, in step S400, the semiconductor substrate 100 can be thinned from the back side until one end of the active pillar 110 is exposed, and then the bit line 140 is formed.

[0118] For example, the above manufacturing method may also include steps such as forming a first source / drain region 110a and a second source / drain region 110c in the active pillar 110, forming a data storage unit SE, forming a contact pad 115, and forming a bit line contact plug 135; the implementation of these steps can refer to commonly used methods in the prior art, and is not limited here.

[0119] It should be noted that details not described in the embodiments of the manufacturing method disclosed herein can be referred to the relevant descriptions of the foregoing embodiments of the semiconductor structure, and will not be repeated here.

[0120] The technical effects and other details of the manufacturing method provided in the embodiments of this disclosure can be found in the relevant descriptions of the foregoing embodiments of the semiconductor structure, and will not be repeated here.

[0121] At least some embodiments of this disclosure also provide an electronic device. FIG9 is a schematic block diagram of an electronic device provided in some embodiments of this disclosure. As shown in FIG9, the electronic device 1 includes a processor 20 and a memory 10 coupled to each other, wherein the memory 10 includes the semiconductor structure provided in any of the foregoing embodiments.

[0122] For example, processor 20 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), etc. Memory 10 may be configured to store data to be processed by processor 20 and / or data processed by the processor.

[0123] For example, electronic device 1 includes, but is not limited to, mobile phones, tablets, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, in-vehicle devices, servers, workstations, etc.

[0124] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, comprising: An active column (110) extends in the vertical direction (Z); A word line (120) extends along a first horizontal direction (X) and is coupled to the active pillar to form a transistor (TR); Bit line (140) extends along a second horizontal direction (Y) and is coupled to the active post, wherein the second horizontal direction intersects the first horizontal direction; The word line includes a first gate portion (121) and a second gate portion (122) that cover the sidewall of the active post and are connected to each other. The first gate portion is located on at least one side of the active post in the first horizontal direction, and the second gate portion is located on at least one side of the active post in the second horizontal direction. The average size of the first gate portion in the vertical direction is different from the average size of the second gate portion in the vertical direction.

2. The semiconductor structure according to claim 1, wherein, The active post includes a first source / drain region (110a), a channel region (110b), and a second source / drain region (110c) arranged sequentially in the vertical direction. The average size of one of the first gate portion and the second gate portion in the vertical direction is smaller than the channel length of the channel region in the vertical direction.

3. The semiconductor structure according to claim 2, wherein, The maximum dimension of one of the first gate portion and the second gate portion in the vertical direction is smaller than the channel length of the channel region in the vertical direction.

4. The semiconductor structure according to any one of claims 1-3, wherein, The average size of the first gate portion in the vertical direction is smaller than the average size of the second gate portion in the vertical direction.

5. The semiconductor structure according to claim 4, wherein, The word line includes two first gate portions located on opposite sides of the active post in the first horizontal direction and two second gate portions located on opposite sides of the active post in the second horizontal direction.

6. The semiconductor structure according to claim 5, wherein, The average size of the first gate portion in the horizontal direction perpendicular to the first horizontal direction is smaller than the average size of the second gate portion in the horizontal direction perpendicular to the second horizontal direction.

7. The semiconductor structure according to claim 6, wherein, The top surface of the first gate portion is lower than or flush with the top surface of the second gate portion.

8. The semiconductor structure according to claim 4, wherein, The word line includes a first gate portion located on one side of the active post in the first horizontal direction and two second gate portions located on opposite sides of the active post in the second horizontal direction.

9. The semiconductor structure according to claim 8, wherein, The average size of the first gate portion in the horizontal direction perpendicular to the first horizontal direction is greater than the average size of the second gate portion in the horizontal direction perpendicular to the second horizontal direction, and the top surface of the first gate portion is lower than the top surface of the second gate portion.

10. The semiconductor structure according to claim 8, wherein, The average size of the first gate portion in the horizontal direction perpendicular to the first horizontal direction is equal to the average size of the second gate portion in the horizontal direction perpendicular to the second horizontal direction, and the top surface of the first gate portion is flush with the top surface of the second gate portion.

11. The semiconductor structure according to any one of claims 1-3, wherein, The average dimension of the first gate portion in the vertical direction is greater than the average dimension of the second gate portion in the vertical direction.

12. The semiconductor structure according to claim 11, wherein, The word line includes two first gate portions located on opposite sides of the active post in the first horizontal direction and two second gate portions located on opposite sides of the active post in the second horizontal direction.

13. The semiconductor structure according to claim 11, wherein, The word line includes a first gate portion located on one side of the active post in the first horizontal direction and two second gate portions located on opposite sides of the active post in the second horizontal direction.

14. The semiconductor structure according to claim 12 or 13, wherein, The average size of the first gate portion in the horizontal direction perpendicular to the first horizontal direction is smaller than the average size of the second gate portion in the horizontal direction perpendicular to the second horizontal direction.

15. The semiconductor structure according to claim 14, wherein, The bottom surface of the first gate portion is lower than or flush with the bottom surface of the second gate portion.

16. The semiconductor structure according to any one of claims 1-3, further comprising: A data storage unit (SE) is coupled to the transistor.

17. A method for manufacturing a semiconductor structure, comprising: Provides a semiconductor substrate (100); The semiconductor substrate is etched to form an active pillar (110) extending in the vertical direction (Z); A word line (120) is formed, wherein the word line extends along a first horizontal direction (X) and is coupled to the active pillar; A bit line (140) is formed, wherein the bit line extends along a second horizontal direction (Y) and is coupled to the active post, the second horizontal direction intersecting the first horizontal direction; The word line includes a first gate portion (121) and a second gate portion (122) that cover the sidewall of the active post and are connected to each other. The first gate portion is located on at least one side of the active post in the first horizontal direction, and the second gate portion is located on at least one side of the active post in the second horizontal direction. The average size of the first gate portion in the vertical direction is different from the average size of the second gate portion in the vertical direction.

18. An electronic device (1), comprising: Processor (20); as well as A memory (10), wherein the memory is coupled to the processor, the memory comprising a semiconductor structure according to any one of claims 1-16.

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