Semiconductor structure and manufacturing method therefor

Abstract

A semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a plurality of stack sub-structures located on a substrate, wherein the plurality of stack sub-structures are arranged at intervals in a first direction, and each stack sub-structure comprises active layers and first dielectric layers alternately stacked in a vertical direction; a word line layer, wherein the word line layer is located on the top surfaces of the stack sub-structures and perpendicular to a sidewall in the first direction, and the bottom end of the word line layer is lower than the bottom surfaces of the stack sub-structures; a first word line isolation structure, located between the stack sub-structures; and a second word line isolation structure, wherein the second word line isolation structure comprises a first isolation portion, a second isolation portion, and a third isolation portion that are sequentially connected, the first isolation portion and the third isolation portion extend in the vertical direction, the second isolation portion extends in a second direction and is connected to the bottoms of the first isolation portion and the third isolation portion, and the bottom end of the word line layer is connected to the top of the second isolation portion. The semiconductor structure can improve the reliability of the semiconductor structure.

Description

Semiconductor structure and its preparation method

[0001] Cross-referencing

[0002] This disclosure claims priority to Chinese invention patent application No. 202411571317.0, filed on November 4, 2024, entitled "Semiconductor Structure and Preparation Method Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0004] The development of dynamic memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. As the size of semiconductor device structures shrinks, the technological barriers encountered by existing structures are becoming increasingly apparent. Therefore, developing more novel structures based on existing structures is a powerful means to break through existing technological barriers.

[0005] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM that includes multilayer horizontal cell (MHC), typically comprising multiple transistors stacked on a substrate, has met the above requirements.

[0006] However, during the formation of vertical conductors (such as word lines) in three-dimensional dynamic random access memory, the limitations of dry etching processes can easily lead to short circuits in the conductors caused by residual conductive material, resulting in reduced memory reliability. Summary of the Invention

[0007] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising: a semiconductor structure characterized in that it includes: a plurality of stacked substructures located on a substrate, the plurality of stacked substructures being arranged at intervals along a first direction, each stacked substructure including an active layer and a first dielectric layer alternately stacked along a vertical direction; a word line layer located on the top surface of the stacked substructures and a sidewall perpendicular to the first direction, and the bottom end of the word line layer being lower than the bottom surface of the stacked substructures; a first word line isolation structure located between the stacked substructures; and a second word line isolation structure including a first isolation portion, a second isolation portion, and a third isolation portion connected in sequence, the first isolation portion and the third isolation portion extending along a vertical direction, the second isolation portion extending along a second direction and connecting the bottoms of the first isolation portion and the third isolation portion, and the bottom end of the word line layer being connected to the top of the second isolation portion.

[0008] In some embodiments, the substrate includes protrusions located under the stacked substructure, a second isolation portion is located between the protrusions, and the top surface of the second isolation portion is lower than the top surface of the protrusions.

[0009] In some embodiments, the device further includes: a gate dielectric layer covering the sidewall of the active layer perpendicular to the first direction; a substrate protection layer covering the sidewall and bottom of the groove formed between adjacent protrusions, the substrate protection layer being sandwiched between the second isolation portion and the substrate; wherein the thickness of the substrate protection layer is greater than the thickness of the gate dielectric layer, and the ratio of the thickness of the substrate protection layer to the thickness of the first dielectric layer is in the range of 0.5-0.6.

[0010] In some embodiments, the width of the first word line isolation structure along the second direction is equal to the width of the word line layer along the second direction, and the width of the second word line isolation structure along the second direction is equal to the width of the stacked substructure along the second direction.

[0011] In some embodiments, the width of the first word line isolation structure along the first direction is equal to the spacing between adjacent word line layers along the first direction, and the width of the second word line isolation structure along the first direction is equal to the spacing between adjacent stacked substructures along the first direction.

[0012] According to a second aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising: forming a plurality of stacked substructures on a substrate, the plurality of stacked substructures being arranged along a first direction, each stacked substructure including an active layer and a first dielectric layer alternately stacked along a vertical direction; forming a sacrificial structure located between the stacked substructures; forming a word line material layer and a first word line isolation structure, the word line material layer being located on the top surface of the stacked substructures, a sidewall perpendicular to the first direction, and a portion of the surface of the sacrificial structure, the first word line isolation structure being located between the stacked substructures; removing the sacrificial structure to form a connecting trench; removing a portion of the word line material layer exposed by the connecting trench to form a word line layer, the word line layer being located on the top surface of the stacked substructures and a sidewall perpendicular to the first direction, and the bottom end of the word line layer being lower than the bottom surface of the stacked substructures; forming a second word line isolation structure filling the connecting trench, the second word line isolation structure including a first isolation portion, a second isolation portion, and a third isolation portion connected sequentially, the first isolation portion and the third isolation portion extending along a vertical direction, the second isolation portion extending along a second direction and connecting the bottoms of the first isolation portion and the third isolation portion, the bottom end of the word line layer being connected to the top of the second isolation portion.

[0013] In some embodiments, forming a stacked substructure on a substrate includes: forming a stacked structure on the substrate, the stacked structure including alternating first semiconductor layers and second semiconductor layers; removing portions of the stacked structure and the substrate to form a plurality of first through-holes and a patterned stacked structure, the plurality of first through-holes being arranged along a first direction and penetrating the stacked structure, the patterned stacked structure being located between the first through-holes; laterally etching along the first through-holes to remove portions of the first semiconductor layers to form first gap trenches, the first gap trenches communicating with the plurality of first through-holes; and depositing a first dielectric layer to form the stacked substructure, the first dielectric layer filling the first gap trenches and covering the sidewalls of the plurality of first through-holes.

[0014] In some embodiments, forming a sacrificial structure located between stacked substructures includes: forming a vertical sacrificial portion that fills a plurality of first through holes; removing a portion of the vertical sacrificial portion to form a sacrificial structure, the sacrificial structure including a first sacrificial portion, a second sacrificial portion and a third sacrificial portion connected in sequence, the first sacrificial portion and the third sacrificial portion extending in a vertical direction, the second sacrificial portion extending in a second direction and connecting the bottoms of the first sacrificial portion and the third sacrificial portion, the top surface of the second sacrificial portion being lower than the bottom surface of the stacked substructure.

[0015] In some embodiments, the first sacrificial portion, the second sacrificial portion, and the third sacrificial portion surround a word line trench; forming a word line material layer and a first word line isolation structure includes: removing a portion of the first dielectric layer exposed in the word line trench located on the sidewall of the first through hole; forming a gate dielectric layer on the sidewall of the active layer exposed in the word line trench; forming a conformally conformally covering the inner wall of the word line trench; and filling the first word line isolation structure.

[0016] In some embodiments, removing the sacrificial structure includes: performing planarization to expose the top surfaces of the first sacrificial portion and the third sacrificial portion; and removing the first sacrificial portion, the second sacrificial portion, and the third sacrificial portion using a wet etching process.

[0017] In this embodiment of the disclosure, since the line layer is used as a whole to cover the top surface and sidewalls of a stacked substructure, the interconnection between the two word line layer portions corresponding to the same transistor can be ensured, word line layer open circuit is avoided, and the bottom of adjacent word line layers is disconnected. Furthermore, the first word line isolation structure and the second word line isolation structure are used together to isolate adjacent word line layers, which can avoid short circuits between word line layers and effectively reduce the coupling between word line layers, thereby improving the reliability of the semiconductor structure. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 is a partial three-dimensional schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0020] Figure 2 is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0021] Figures 3A to 13B are top views and cross-sectional views illustrating the fabrication process of a semiconductor structure according to embodiments of the present disclosure; wherein, Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A to 13A are top views of the semiconductor structure, and Figures 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B to 13B are cross-sectional views of the semiconductor structure. Detailed Implementation

[0022] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0023] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0024] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0025] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0026] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0027] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0028] Taking a three-dimensional dynamic random access memory (DRAM) as an example, semiconductor structures employ a vertically stacked memory cell architecture. Each memory cell includes horizontally arranged transistors and capacitors, which improves the integration density of the DRAM. During word line formation, a typical process involves a single deposition step followed by etching to separate adjacent word lines. However, with increasing semiconductor integration density, dry etching for high aspect ratio word lines becomes more challenging. For example, residual conductive material can cause short circuits in the word lines. Increasing the RF power of the plasma can damage the word lines, reducing the reliability of the semiconductor structure. Furthermore, after separating adjacent word lines, additional process steps are needed to interconnect the two word lines corresponding to the same transistor. Alignment during interconnect fabrication is difficult and prone to short circuits. Therefore, improving the reliability of word lines in semiconductor structures is a pressing issue.

[0029] In view of this, in order to solve the above problems, this disclosure provides a semiconductor structure and a method for preparing the same.

[0030] Figure 1 is a partial three-dimensional schematic diagram of a semiconductor structure according to an exemplary embodiment. It is understood that, for ease of illustrating the internal structure of the semiconductor structure, a partial cross-section of the semiconductor structure is shown by dividing the three-dimensional semiconductor structure into two parts; in the actual structure, these two parts can be an integral structure. Figure 2 is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Figures 3A to 13B are top and cross-sectional schematic diagrams of a semiconductor structure during fabrication according to an embodiment of the present disclosure. In Figures 1 and 3A to 13B, the first direction D1 and the second direction D2 are horizontal directions parallel to the plane of the substrate 110, and the first direction D1 intersects the second direction D2; for example, the first direction D1 may be perpendicular to the second direction D2. The vertical direction D3 is the direction intersecting the plane of the substrate 110; for example, the vertical direction D3 is perpendicular to the plane of the substrate 110.

[0031] Referring to FIG1, the semiconductor structure includes multiple stacked substructures STa located on a substrate 110. The multiple stacked substructures STa are arranged at intervals along a first direction D1. Each stacked substructure STa includes an active layer 112 and a first dielectric layer 114 alternately stacked along a vertical direction D3; a word line layer 320 located on the top surface of the stacked substructure STa and a sidewall perpendicular to the first direction D1, and the bottom end of the word line layer 320 is lower than the bottom surface of the stacked substructure STa; and a first word line isolation structure 310. The first word line isolation structure 310 is located between the stacked substructures STa; the second word line isolation structure 330 includes a first isolation portion 331, a second isolation portion 332 and a third isolation portion 333 connected in sequence. The first isolation portion 331 and the third isolation portion 333 extend along the vertical direction D3, the second isolation portion 332 extends along the second direction D2 and connects the bottom of the first isolation portion 331 and the third isolation portion 333, and the bottom end of the word line layer 320 is connected to the top of the second isolation portion 332.

[0032] In the semiconductor structure provided in this disclosure, firstly, the word line layer as a whole covers the top surface and sidewalls of a stacked substructure, ensuring interconnection between two parts of the word line layer corresponding to the same transistor, preventing word line layer open circuits, forming a dual-gate structure for the active layer of each transistor, and improving the gate control capability of the transistor. Secondly, the bottom of adjacent word line layers is disconnected, and a first word line isolation structure and a second word line isolation structure are used together to isolate adjacent word line layers, preventing short circuits between word line layers and effectively reducing coupling between word line layers. Thirdly, the second word line isolation structure includes three sequentially connected parts in a "U" shape, which improves the consistency of the width shape of the word line layer in the second direction, thereby improving the reliability of the semiconductor structure.

[0033] The substrate 110 is made of semiconductor materials, such as elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. The active layer 112 can be made of single-crystal silicon, polycrystalline silicon, germanium, silicon-germanium, and oxide semiconductor materials (e.g., zinc tin oxide (ZnS)). x Sn y O, commonly known as "ZTO"), indium zinc oxide (In x Zn y O, commonly known as "IZO"), zinc oxide (Zn) x O), Indium gallium zinc oxide (In x Ga yZn z O, commonly known as "IGZO"), indium gallium silicon oxide (In x Ga y Si z O, commonly known as "IGSO"), indium tin oxide (In) x Sn y O (commonly known as "ITO") and one or more other similar materials). The material of the first dielectric layer 114 is an insulating material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxynitride.

[0034] In some embodiments, the substrate 110 is made of single-crystal silicon. The active layer 112 in the stacked substructure STa can be formed from the substrate 110 using an epitaxial growth process. The active layer 112 can be doped with doped ions and used as the source, channel layer, and drain of a transistor. The first dielectric layer 114 is made of silicon oxide.

[0035] In some embodiments, the stacked substructure STa further includes a hard mask layer 113 located on top of the alternately stacked active layer 112 and first dielectric layer 114. The hard mask layer 113 is used to protect the topmost active layer 112 or the first dielectric layer 114. The thickness of the hard mask layer 113 along the vertical direction D3 is greater than the thickness of the active layer 112 or the first dielectric layer 114 along the vertical direction D3.

[0036] In some embodiments, referring to FIG1, the word line layer 320 has an inverted U-shaped morphology in cross-section along the first direction D1 and the vertical direction D3. That is, the word line layer 320 includes a first word line portion 321, a second word line portion 322, and a third word line portion 323 connected in sequence. The first word line portion 321 and the third word line portion 323 are located on the sidewall of the stacked substructure STa perpendicular to the first direction D1. The second word line portion 322 connects the top of the first word line portion 321 and the third word line portion 323, and the second word line portion 322 is located on the top surface of the stacked substructure STa. The word line layers 320 corresponding to different stacked substructures STa are disconnected at the bottom, and a first word line isolation structure 310 is sandwiched between adjacent word line layers 320.

[0037] In some embodiments, the top surface of the substrate 110 is in direct contact with the first dielectric layer 114, and the bottom end of the word line layer 320 is lower than the top surface of the bottom first dielectric layer 114 in the stacked substructure STa, and is flush with or higher than the top surface of the protrusion 110a of the substrate 110.

[0038] The word line layer 320 may be made of a conductive material. The conductive material may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanium). For example, the material of the word line layer 320 may be titanium nitride.

[0039] In some embodiments, referring to FIG1, the first word line isolation structure 310 may be a single-layer structure or a multi-layer structure. For example, the first word line isolation structure 310 may be a two-layer structure composed of a silicon nitride layer and a silicon oxide layer, wherein the silicon nitride layer conformally covers the surface of the word line layer 320, the silicon oxide layer fills the spaces between the silicon nitride layers, and the top surface of the first word line isolation structure 310 is higher than the top surface of the word line layer 320. It is understood that the first word line isolation structure 310 may also include other low dielectric constant materials to reduce the parasitic capacitance between the word line layers 320.

[0040] In some embodiments, referring to FIG1, the second word line isolation structure 330 includes a first isolation portion 331, a second isolation portion 332, and a third isolation portion 333, which have a "U" shape in cross-section along the second direction D2 and the vertical direction D3. The second isolation portion 332 of the second word line isolation structure 330 is located below the first word line isolation structure 310 and the word line layer 320, and the top of the second word line isolation structure 330 is connected to the bottom end of the first word line isolation structure 310 and the word line layer 320. The width of the second word line isolation structure 330 along the first direction D1 is greater than the width of the first word line isolation structure 310 along the first direction D1. The second word line isolation structure 330 can be a single-layer structure or a multi-layer structure. For example, the second word line isolation structure 330 can be a double-layer structure composed of a silicon nitride layer and a silicon oxide layer. The silicon nitride layer of the second isolation portion 332 has a ring-shaped morphology in the cross-section along the first direction D1 and the vertical direction D3, and the silicon oxide layer fills the ring-shaped silicon nitride layer. The silicon nitride layer of the second isolation portion 332 is connected to the bottom end of the word line layer 320 and to the bottom end of the silicon nitride layer of the first word line isolation structure 310.

[0041] In some embodiments, the width of the first word line isolation structure 310 along the second direction D2 is equal to the width of the word line layer 320 along the second direction D2, and the width of the second word line isolation structure 330 along the second direction D2 is equal to the width of the stacked substructure STa along the second direction D2. The first isolation portion 331 and the third isolation portion 333 are respectively located on both sides of the first word line portion 321 along the second direction D2 and the third word line portion 323 along the second direction D2 of the word line layer 320. The first isolation portion 331 and the third isolation portion 333 define the width of the first word line portion 321 and the third word line portion 323 along the second direction D2, and the spacing between the first isolation portion 331 and the third isolation portion 333 is equal to the width of the first word line isolation structure 310 along the second direction D2.

[0042] In some embodiments, the width of the first word line isolation structure 310 along the first direction D1 is equal to the spacing between adjacent word line layers 320 along the first direction D1, and the width of the second word line isolation structure 330 along the first direction D1 is equal to the spacing between adjacent stacked substructures STa along the first direction D1.

[0043] In some embodiments, the thicknesses of the first isolation portion 331 and the third isolation portion 333 along the second direction D2 and the thickness of the second isolation portion 332 along the vertical direction D3 can be substantially the same.

[0044] In some embodiments, the substrate 110 includes protrusions 110a located under the stacked substructure STa, and a second isolation portion 332 is located between the protrusions 110a, with the top surface of the second isolation portion 332 being lower than the top surface of the protrusions 110a. By forming grooves between the protrusions 110a on the surface of the substrate 110, a word line layer 320 extending into the substrate 110 can be formed, with the bottom end of the word line layer 320 flush with or lower than the top surface of the protrusions 110a. The word line layer 320 is isolated from the substrate 110 by the second isolation portion 332, reducing coupling between word line layers 320 and leakage current between the word line layer 320 and the substrate 110 while ensuring the utilization rate of the word line layer 320. The ratio of the overlap height of the word line layer 320 and the protrusions 110a in the vertical direction D3 to the height of the protrusions 110a in the vertical direction D3 ranges from 0 to 0.3.

[0045] In some embodiments, the semiconductor structure further includes a gate dielectric layer 301, which at least covers the sidewalls of the active layer 112 perpendicular to the first direction D1; a substrate protection layer 115, which covers the sidewalls and bottom of the grooves formed between adjacent protrusions 110a, and is sandwiched between the second isolation portion 332 and the substrate 110; wherein the thickness of the substrate protection layer 115 is greater than the thickness of the gate dielectric layer 301, and the ratio of the thickness of the substrate protection layer 115 to the thickness of the first dielectric layer 114 is in the range of 0.5-0.6.

[0046] In some embodiments, an in-situ steam generation (ISSG) or rapid thermal oxidation (RTO) process can be used to form the gate dielectric layer 301 on the surface of the active layer 112. Optionally, an atomic layer deposition (ALD) or plasma vapor deposition (PVD) process can also be used to form the gate dielectric layer 301. The gate dielectric layer 301 may only cover the sidewalls of the active layer 112 perpendicular to the first direction D1. In one example, the gate dielectric layer 301 also covers the sidewalls of the first dielectric layer 114 perpendicular to the first direction D1 and the sidewalls and top surface of the hard mask layer 113. The gate dielectric layer 301 is sandwiched between the word line layer 320 and the stacked substructure STa. The gate dielectric layer 301 may also be sandwiched between the word line layer 320 and the first word line isolation structure 310.

[0047] In some embodiments, the substrate protective layer 115 is formed simultaneously with the first dielectric layer 114, and the substrate protective layer 115 and the first dielectric layer 114 are made of the same material. The thickness of the first dielectric layer 114 along the vertical direction D3 is at most twice the thickness of the substrate protective layer 115 along the vertical direction D3.

[0048] Figure 2 is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A to 13A are top views illustrating the fabrication process of a semiconductor structure according to an embodiment of the present disclosure; Figures 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B to 13B are cross-sectional views illustrating the fabrication process of a semiconductor structure according to an embodiment of the present disclosure. The method for fabricating a semiconductor structure provided by the embodiments of the present disclosure will be described in detail below with reference to Figures 2, 3A to 13A, and 3B to 13B. Referring to Figure 2, the fabrication method includes at least the following steps:

[0049] S21: Form a plurality of stacked substructures on the substrate, the plurality of stacked substructures being arranged along a first direction, the stacked substructures including an active layer and a first dielectric layer alternately stacked along the vertical direction;

[0050] S22: Form a sacrificial structure located between stacked substructures;

[0051] S23: Form a word line material layer and a first word line isolation structure. The word line material layer is located on the top surface of the stacked substructure, the sidewall perpendicular to the first direction, and part of the surface of the sacrificial structure. The first word line isolation structure is located between the stacked substructures.

[0052] S24: Remove the sacrificial structure to form a connecting slot;

[0053] S25: Remove the exposed portion of the word line material layer in the connecting slot to form a word line layer. The word line layer is located on the top surface of the stacked substructure and the sidewall perpendicular to the first direction, and the bottom end of the word line layer is lower than the bottom surface of the stacked substructure.

[0054] S26: A second word line isolation structure is formed to fill the connecting groove. The second word line isolation structure includes a first isolation part, a second isolation part and a third isolation part connected in sequence. The first isolation part and the third isolation part extend in a vertical direction. The second isolation part extends in a second direction and connects the bottom ends of the first isolation part and the third isolation part. The bottom end of the word line layer is connected to the top of the second isolation part.

[0055] It should be understood that the steps shown in Figure 2 are not exclusive, and other steps may be performed before, after, or between any of the steps shown in the operation; the order of the steps shown in Figure 2 can be adjusted according to actual needs.

[0056] In the semiconductor structure manufacturing method disclosed herein, firstly, by pre-defining the position of the second word line isolation structure through a sacrificial structure, the consistency of the width morphology of the word line layer in the second direction can be precisely controlled. Secondly, by removing the connecting trench formed after removing the sacrificial structure to disconnect part of the word line material layer to form the word line layer, it is possible to ensure that the bottom of adjacent word line layers is disconnected, thereby avoiding short circuits caused by word line material layer residue and reducing damage to the active layer and substrate. Thirdly, by using both the first and second word line isolation structures to isolate adjacent word line layers, short circuits between word line layers can be avoided and coupling between adjacent word line layers can be effectively reduced.

[0057] In some embodiments, after providing a substrate 110, forming a stacked substructure STa on the substrate 110 includes: as shown in FIG3A and FIG3B, forming a stacked structure ST' on the substrate 110, the stacked structure ST' including alternating first semiconductor layers 111' and second semiconductor layers 112'; as shown in FIG4A and FIG4B, removing a portion of the stacked structure ST' and the substrate 110 to form a plurality of first through holes K1 and a patterned stacked structure ST, the plurality of first through holes K1 being arranged along a first direction D1 and penetrating the stacked structure ST', the patterned stacked structure ST being located between the first through holes K1; as shown in FIG5A and FIG5B, etching along the transverse direction K1 of the first through holes to remove a portion of the first semiconductor layer 111 to form a first gap trench T1, the first gap trench T1 communicating with the plurality of first through holes K1; depositing a first dielectric layer 114 to form the stacked substructure STa, the first dielectric layer 114 filling the first gap trench T1 and covering the sidewalls of the plurality of first through holes K1.

[0058] In some embodiments, referring to Figures 3A and 3B, where the left image in Figure 3B is a cross-sectional view along section AA' in Figure 3A, and the right image in Figure 3B is a cross-sectional view along section BB' in Figure 3A. The first semiconductor layer 111' and the second semiconductor layer 112' are made of different materials. The material of the second semiconductor layer 112' can be monocrystalline silicon, polycrystalline silicon, germanium, silicon-germanium, and oxide semiconductor materials (e.g., zinc tin oxide (ZnO)). x Sn y O, commonly known as "ZTO"), indium zinc oxide (In x Zn y O, commonly known as "IZO"), zinc oxide (Zn) x O), Indium gallium zinc oxide (In x Ga y Zn z O, commonly known as "IGZO"), indium gallium silicon oxide (In x Ga y Si z Silicon in silicon (commonly known as "IGSO") and one or more similar materials. For example, the second semiconductor layer 112' is single-crystal silicon, and the first semiconductor layer 111' is silicon germanide. The first semiconductor layer 111' and the second semiconductor layer 112' can be formed alternately by epitaxial growth or deposition processes. The deposition processes can include chemical vapor deposition, atomic layer deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition, etc.

[0059] In some embodiments, referring to Figures 4A and 4B, where the left image in Figure 4B is a cross-sectional view along section AA' in Figure 4A, and the right image in Figure 4B is a cross-sectional view along section BB' in Figure 4A. A patterned hard mask layer 113 is formed on the stacked structure ST', and the stacked structure ST' is etched using the hard mask layer 113 as a mask to obtain a plurality of first through-holes K1. The plurality of first through-holes K1 divide the stacked structure ST' into patterned stacked structures ST spaced apart along a first direction D1. The first through-holes K1 penetrate into the substrate 110, i.e., the bottom surface of the first through-holes K1 is lower than the top surface of the substrate 110. A protrusion 110a and a groove between the protrusions 110a are formed on the surface of the substrate 110. The plurality of first through-holes K1 divide the second semiconductor layer 112' into patterned second semiconductor layers, used as active layers 112, and the plurality of first through-holes K1 divide the first semiconductor layer 111' into patterned first semiconductor layers 111.

[0060] In some embodiments, referring to Figures 5A and 5B, where the left view in Figure 5B is a cross-sectional view along section AA' in Figure 5A, and the right view in Figure 5B is a cross-sectional view along section BB' in Figure 5A, the patterned first semiconductor layer 111 can be removed by a wet etching process to form a first gap trench T1 between adjacent active layers 112 in the vertical direction D3. A first dielectric layer 114 is formed by a deposition process to fill the first gap trench T1. The ratio of the thickness of the first dielectric layer 114 covering the inner wall of the groove between the protrusions 110a to the height of the first gap trench T1 in the vertical direction D3 is in the range of 0.5-0.6. The stacked substructure STa includes active layers 112 and first dielectric layers 114 alternately stacked along the vertical direction D3.

[0061] In some embodiments, a second through-hole is formed simultaneously with the formation of the first through-hole K1. The second through-hole extends along a first direction and penetrates the stacked structure vertically. Two second through-holes may be located on either side of the plurality of first through-holes along a second direction, used to remove the first dielectric layer on both sides of the patterned stacked structure ST while forming the first gap groove T1. Along the second through-holes, a portion of the active layer 112 may also be removed to form a bitline trench, forming a bitline structure connected to the end of the active layer 112 within the bitline trench. The bitline structure extends along the first direction, and the plurality of bitline structures may be spaced apart vertically.

[0062] In some embodiments, referring to FIG6A, 6B, 7A and 7B, a sacrificial structure 210 located between stacked substructures STa is formed, including: forming a vertical sacrificial portion 201 that fills a plurality of first through holes K1; removing a portion of the vertical sacrificial portion 201 to form the sacrificial structure 210. The sacrificial structure 210 includes a first sacrificial portion 211, a second sacrificial portion 212 and a third sacrificial portion 213 connected in sequence. The first sacrificial portion 211 and the third sacrificial portion 213 extend along a vertical direction D3. The second sacrificial portion 212 extends along a second direction D2 and connects the bottom ends of the first sacrificial portion 211 and the third sacrificial portion 213. The top surface of the second sacrificial portion 212 is lower than the bottom surface of the stacked substructure STa.

[0063] In some embodiments, referring to Figures 6A and 6B, where the left view in Figure 6B is a cross-sectional view along section AA' in Figure 6A, and the right view in Figure 6B is a cross-sectional view along section BB' in Figure 6A, a sacrificial material is filled to form vertical sacrificial portions 201 and horizontal sacrificial portions 202 in a plurality of first through-holes K1. The horizontal sacrificial portions 202 connect the top surfaces of a plurality of vertical sacrificial portions 201 spaced apart along a first direction D1. The top surfaces of the vertical sacrificial portions 201 are flush with the top surface of the stacked substructure STa. In other examples, the horizontal sacrificial portions 202 may not be formed. The sacrificial material may be polysilicon, photoresist, silicon carbide, or other materials that have a high etch selectivity with the active layer 112 and the first dielectric layer 114.

[0064] In some embodiments, referring to Figures 7A and 7B, where the left view in Figure 7B is a cross-sectional view along section AA' in Figure 7A and the right view in Figure 7B is a cross-sectional view along section BB' in Figure 7A, the first sacrificial portion 211, the second sacrificial portion 212, and the third sacrificial portion 213 surround a word line trench K2. Forming a word line material layer 302 and a first word line isolation structure 310 includes: referring to Figures 8A and 8B, removing the portion of the first dielectric layer 114 exposed on the sidewall of the first through-hole K1 in the word line trench K2; referring to Figures 9A and 9B, forming a gate dielectric layer 301 on the sidewall of the active layer 112 exposed in the word line trench K2; and referring to Figures 10A and 10B, forming a conformally conformally covering the inner wall of the word line trench K2 and filling the first word line isolation structure 310.

[0065] In some embodiments, referring to Figures 8A and 8B, where the left view in Figure 8B is a cross-sectional view along section AA' in Figure 8A, and the right view in Figure 8B is a cross-sectional view along section BB' in Figure 8A, after removing part of the vertical sacrificial portion 201 and the first dielectric layer 114 of the sidewalls of the stacked substructure STa, the second sacrificial portion 212 and the substrate protective layer 115 located in the groove between the protrusions 110a are retained. The top surfaces of the second sacrificial portion 212 and the substrate protective layer 115 are flush with each other and lower than the top surface of the protrusions 110a.

[0066] In some embodiments, referring to Figures 9A and 9B, where the left view in Figure 9B is a cross-sectional view along section AA' in Figure 9A, and the right view in Figure 9B is a cross-sectional view along section BB' in Figure 9A, a gate dielectric layer 301 can be formed using a deposition process. The gate dielectric layer 301 covers the sidewalls and top surface of the stacked substructure STa exposed by the word line trench K2, and also covers the top surface of the second sacrificial portion 212. The thickness of the gate dielectric layer 301 is less than the thickness of the first dielectric layer 114. By removing a portion of the first dielectric layer 114 and reforming the gate dielectric layer 301, the thickness and quality of the gate dielectric layer 301 can be ensured.

[0067] In some embodiments, referring to Figures 10A and 10B, where the left image in Figure 10B is a cross-sectional view along section AA' in Figure 10A, and the right image in Figure 10B is a cross-sectional view along section BB' in Figure 10A. After conformally depositing the word line material layer 302, a first word line isolation structure 310 is filled. The first word line isolation structure 310 may be a two-layer structure composed of a silicon nitride layer and a silicon oxide layer, wherein the silicon nitride layer conformally covers the surface of the word line material layer 302, the silicon oxide layer fills the spaces between the silicon nitride layers, and the top surface of the silicon oxide layer is higher than the top surface of the word line layer 302.

[0068] In some embodiments, removing the sacrificial structure 210 includes: referring to Figures 10A and 10B, after forming the first word line isolation structure 310, performing a planarization process to remove the gate dielectric layer 301 located on the top surface of the sacrificial structure 210 to expose the top surfaces of the first sacrificial portion 211 and the third sacrificial portion 213; referring to Figures 11A and 11B, wherein the left image in Figure 11B is a cross-sectional view along section AA' in Figure 11A, and the right image in Figure 11B is a cross-sectional view along section BB' in Figure 11A, using a wet etching process to remove the first sacrificial portion 211, the second sacrificial portion 212, and the third sacrificial portion 213 to form a connecting trench K3.

[0069] In some embodiments, referring to Figures 12A and 12B, where the left view in Figure 12B is a cross-sectional view along section AA' in Figure 12A and the right view in Figure 12B is a cross-sectional view along section BB' in Figure 12A, the exposed portion of the word line material layer 302 of the connecting slot K3 is removed to form a word line layer 320. The word line layer 320 is located on the top surface of the stacked substructure STa and the sidewall perpendicular to the first direction D1, and the bottom end of the word line layer 320 is lower than the stacked substructure STa. The bottom surface; forming a second word line isolation structure 304 that fills the connecting groove K3. The second word line isolation structure 330 includes a first isolation part 331, a second isolation part 332 and a third isolation part 333 connected in sequence. The first isolation part 331 and the third isolation part 333 extend along the vertical direction D3. The second isolation part 332 extends along the second direction D2 and connects the bottom ends of the first isolation part 331 and the third isolation part 333. The bottom end of the word line layer 320 is connected to the top of the second isolation part 332.

[0070] In some embodiments, referring to Figures 13A and 13B, where the left view in Figure 13B is a cross-sectional view along section AA' in Figure 13A, and the right view in Figure 13B is a cross-sectional view along section BB' in Figure 13A, a second word line isolation structure 330 is formed to fill the connecting groove K3. The second word line isolation structure 330 includes a first isolation portion 331, a second isolation portion 332, and a third isolation portion 333 connected in sequence. The first isolation portion 331 and the third isolation portion 333 extend along the vertical direction D3, and the second isolation portion 332 extends along the second direction D2 and connects the bottom ends of the first isolation portion 331 and the third isolation portion 333. The bottom end of the word line layer 320 is connected to the top of the second isolation portion 332.

[0071] In some embodiments, the semiconductor structure includes a memory, which may be a dynamic random access memory, such as a three-dimensional dynamic random access memory. The memory may also be a memory known in the art, such as a phase-change memory or a ferroelectric memory.

[0072] The various semiconductor structures illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).

[0073] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, comprising: Multiple stacked substructures (STa) are located on a substrate (110), the multiple stacked substructures are arranged at intervals along a first direction (D1), and each stacked substructure includes an active layer (112) and a first dielectric layer (114) alternately stacked along a vertical direction (D3); A word line layer (302) is located on the top surface of the stacked substructure and on the sidewall perpendicular to the first direction, and the bottom end of the word line layer is lower than the bottom surface of the stacked substructure. The first word line isolation structure (310) is located between the stacked substructures; The second character line isolation structure (330) includes a first isolation part (331), a second isolation part (332) and a third isolation part (333) connected in sequence. The first isolation part and the third isolation part extend along the vertical direction. The second isolation part extends along the second direction (D2) and connects the bottom of the first isolation part and the bottom of the third isolation part. The bottom end of the character line layer is connected to the top of the second isolation part.

2. The semiconductor structure according to claim 1, wherein, The substrate includes a protrusion (110a) located under the stacked substructure, the second isolation portion is located between the protrusions, and the top surface of the second isolation portion is lower than the top surface of the protrusion.

3. The semiconductor structure according to claim 2, wherein, Also includes: A gate dielectric layer (301) covers the sidewall of the active layer perpendicular to the first direction; A substrate protective layer (115) covers the sidewalls and bottom of the groove formed between adjacent protrusions, and is sandwiched between the second isolation portion and the substrate. The thickness of the substrate protective layer is greater than the thickness of the gate dielectric layer, and the ratio of the thickness of the substrate protective layer to the thickness of the first dielectric layer is in the range of 0.5-0.

6.

4. The semiconductor structure according to claim 1, wherein, The width of the first word line isolation structure along the second direction is equal to the width of the word line layer along the second direction, and the width of the second word line isolation structure along the second direction is equal to the width of the stacked substructure along the second direction.

5. The semiconductor structure according to claim 1, wherein, The width of the first word line isolation structure along the first direction is equal to the spacing between adjacent word line layers along the first direction, and the width of the second word line isolation structure along the first direction is equal to the spacing between adjacent stacked substructures along the first direction.

6. The semiconductor structure according to claim 1, wherein, The character line layer has an inverted U-shaped morphology in cross-sections along the first direction and the vertical direction.

7. The semiconductor structure according to claim 6, wherein, The character line layer includes a first character line portion (321), a second character line portion (322), and a third character line portion (323) connected in sequence. The first character line portion (321) and the third character line portion (323) are located on the side wall of the stacked substructure perpendicular to the first direction. The second character line portion connects the top of the first character line portion and the third character line portion, and the second character line portion is located on the top surface of the stacked substructure.

8. The semiconductor structure according to claim 3, wherein, The substrate protective layer and the first dielectric layer are made of the same material, and the thickness of the first dielectric layer along the vertical direction is at most twice the thickness of the substrate protective layer along the vertical direction.

9. A method for fabricating a semiconductor structure, comprising: Multiple stacked substructures (STa) are formed on a substrate (110), the multiple stacked substructures are arranged along a first direction (D1), and the stacked substructures include an active layer (112) and a first dielectric layer (114) alternately stacked along a vertical direction (D3); A sacrificial structure (210) is formed between the stacked substructures; A word line material layer (302) and a first word line isolation structure (310) are formed. The word line material layer is located on the top surface of the stacked substructure, the sidewall perpendicular to the first direction, and a portion of the surface of the sacrificial structure. The first word line isolation structure is located between the stacked substructures. Remove the sacrificial structure to form a connecting groove (K3); The exposed portion of the word line material layer of the connecting slot is removed to form a word line layer (320), the word line layer being located on the top surface of the stacked substructure and the sidewall perpendicular to the first direction, and the bottom end of the word line layer being lower than the bottom surface of the stacked substructure; A second word line isolation structure (304) is formed to fill the connecting groove. The second word line isolation structure includes a first isolation part (331), a second isolation part (332), and a third isolation part (333) connected in sequence. The first isolation part and the third isolation part extend along the vertical direction. The second isolation part extends along the second direction and connects the bottom of the first isolation part and the bottom of the third isolation part. The bottom end of the word line layer is connected to the top of the second isolation part.

10. The preparation method according to claim 9, wherein, Forming a stacked substructure on a substrate includes: A stacked structure (ST') is formed on a substrate, the stacked structure comprising alternating first semiconductor layer (111') and second semiconductor layer (112'); A portion of the stacked structure and the substrate are removed to form a plurality of first through holes (K1) and a patterned stacked structure (ST), the plurality of first through holes being arranged along a first direction and penetrating the stacked structure, the patterned stacked structure being located between the first through holes; Laterally etch along the first through hole to remove part of the first semiconductor layer to form a first gap trench (T1), the first gap trench connecting a plurality of the first through holes; A first dielectric layer (114) is deposited to form a stacked substructure, the first dielectric layer filling the first gap groove and covering the sidewalls of the plurality of first through holes.

11. The preparation method according to claim 10, wherein, Forming a sacrificial structure located between the stacked substructures includes: A vertical sacrificial portion (201) is formed to fill the plurality of first through holes; A portion of the vertical sacrificial portion is removed to form a sacrificial structure (210), the sacrificial structure comprising a first sacrificial portion (211), a second sacrificial portion (212), and a third sacrificial portion (213) connected in sequence, the first sacrificial portion and the third sacrificial portion extending along the vertical direction, the second sacrificial portion extending along a second direction and connecting the bottoms of the first sacrificial portion and the third sacrificial portion, the top surface of the second sacrificial portion being lower than the bottom surface of the stacked substructure.

12. The preparation method according to claim 11, wherein, The first, second, and third sacrificial sections are enclosed by a character-shaped trench (K2); Forming a character line material layer and a first character line isolation structure, including: Remove the portion of the first dielectric layer located on the sidewall of the first through hole that is exposed by the word line groove. A gate dielectric layer (301) is formed on the sidewall of the active layer exposed in the word line trench; A character line material layer (302) is formed to cover the inner wall of the character line groove in a conformal manner, and the first character line isolation structure is filled in.

13. The preparation method according to claim 11, wherein, Removing the sacrificial structure includes: A planarization process is performed to expose the top surfaces of the first sacrificial portion and the third sacrificial portion; The first sacrificial part, the second sacrificial part, and the third sacrificial part are removed by wet etching process.

14. The preparation method according to claim 10, wherein, The bottom surface of the first through hole is lower than the top surface of the substrate.

15. The preparation method according to claim 11, wherein, The process of forming the vertical sacrificial portion (201) that fills the plurality of first through holes further includes: A horizontal sacrificial portion (202) is formed, which connects to the top surfaces of a plurality of vertical sacrificial portions spaced apart along the first direction.

16. [Amended according to Rule 26, 04.03.2025] According to the preparation method of claim 12, wherein, The substrate includes a protrusion (110a) located under the stacked substructure; when a portion of the vertical sacrificial portion and a portion of the first dielectric layer are removed, a second sacrificial portion and a substrate protective layer (115) located in the groove between the protrusions are retained; the top surfaces of the second sacrificial portion and the substrate protective layer are flush and lower than the top surface of the protrusion.

Images