Semiconductor structure and manufacturing method therefor

Abstract

A semiconductor structure and a method for forming same. The semiconductor structure may at least comprise: a substrate; bit line structures located on the substrate, the plurality of bit line structures extending in a first direction and being arranged at intervals in a second direction, and the first direction being perpendicular to the second direction; first dielectric layers located between respective adjacent bit line structures and arranged at intervals in the first direction; contact structures located between respective adjacent bit line structures, each contact structure being spaced apart from a first dielectric layer; and conductive structures located above the contact structures, the top of each conductive structure being flush with the top of a first dielectric layer. The size of each contact structure gradually decreases from the top of the contact structure to the surface of the substrate in a direction perpendicular to the substrate.

Description

A semiconductor structure and its manufacturing method

[0001] Cross-references

[0002] This application claims priority to Chinese Patent Application No. 202411538538.8, filed on October 30, 2024, entitled “A Semiconductor Structure and a Method for Manufacturing the Same”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0004] In the manufacturing process of DRAM (Dynamic Random Access Memory), as chip size continues to shrink, the challenges in the process become increasingly significant, which may lead to poor connection performance of conductive and contact structures, short circuits between adjacent conductive structures or adjacent contact structures, and other problems. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and its manufacturing method, which at least helps to solve the problems of deterioration of pad structure and contact nodes, and short circuits between different conductive structures.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including:

[0007] Base;

[0008] Bit line structure, located on the substrate, multiple bit line structures extend along a first direction and are spaced apart along a second direction, the first direction being perpendicular to the second direction;

[0009] A first dielectric layer is located between adjacent bit line structures and spaced apart along a first direction;

[0010] A contact structure is located between adjacent bit line structures, and the contact structure is spaced apart from the first dielectric layer;

[0011] A conductive structure is located above the contact structure, and the top of the conductive structure is flush with the top of the first dielectric layer.

[0012] The dimensions of the contact structure gradually decrease from the top of the contact structure to the surface of the substrate along a direction perpendicular to the substrate.

[0013] In some embodiments, the conductive structure includes a first conductive structure and a second conductive structure, the first conductive structure being flush with the top surface of the first dielectric layer, and the second conductive structure being located between the first conductive structure and the contact structure, the conductive structure gradually increasing in size from top to bottom along a direction perpendicular to the substrate.

[0014] In some embodiments, the contact area between the conductive structure and the contact structure is greater than the cross-sectional area of ​​the conductive structure at any location, and also greater than the cross-sectional area of ​​the contact structure at any location.

[0015] In some embodiments, a top conductive structure is also included, which is located above the conductive structure and covers a portion of the top surface of the first dielectric layer.

[0016] In some embodiments, the size of the first dielectric layer decreases from top to bottom and then increases, and the first dielectric layer also has an air gap, which is lower than the interface between the conductive structure and the contact structure.

[0017] In some embodiments, the contact structure includes a first contact structure and a second contact structure, the first contact structure being embedded in the substrate, the second contact structure being located above the first contact structure, and the second contact structure having a gradually decreasing size from top to bottom along a direction perpendicular to the substrate.

[0018] Another aspect of this disclosure provides a method for forming a semiconductor structure, including:

[0019] Provide a base;

[0020] A bit line structure is formed on the substrate. The bit line structure extends along a first direction and is spaced along a second direction. The first direction is perpendicular to the second direction. There is a first opening between adjacent bit line structures.

[0021] A first conductive layer is formed in the first opening;

[0022] The first conductive layer is etched along a third direction to form a second opening, and the remaining first conductive layer serves as the second conductive layer. The second conductive layer and the second opening are spaced apart along a first direction, and the third direction is perpendicular to the substrate.

[0023] The first dielectric layer is filled into the second opening;

[0024] The second conductive layer is etched back to form the third opening, and the remaining second conductive layer serves as the contact structure.

[0025] A conductive structure is formed in the third opening, and the conductive structure is located above the contact structure;

[0026] The dimensions of the contact structure gradually decrease from the top of the contact structure to the surface of the substrate along a direction perpendicular to the substrate.

[0027] In some embodiments, the conductive structure includes a first conductive structure and a second conductive structure. The first conductive structure is located in the third opening and is flush with the top surface of the first dielectric layer. The second conductive structure is located between the first conductive structure and the contact structure. The size of the conductive structure gradually increases from top to bottom along the direction perpendicular to the substrate.

[0028] In some embodiments, the contact area between the conductive structure and the contact structure is greater than the cross-sectional area of ​​the conductive structure at any location, and also greater than the cross-sectional area of ​​the contact structure at any location.

[0029] In some embodiments, a top conductive structure is also included, which is formed above the conductive structure and covers a portion of the top surface of the first dielectric layer.

[0030] In some embodiments, the size of the first dielectric layer decreases from top to bottom and then increases; the first dielectric layer also has an air gap, which is lower than the interface between the conductive structure and the contact structure.

[0031] In some embodiments, the size of the second conductive layer increases first and then decreases from top to bottom, and the method for forming the second conductive layer includes: performing an oxidation process, an etching process, and a deoxidation process in a cycle.

[0032] In some embodiments, oxygen is used for the oxidation process, the bias voltage of the oxidation process is gradually increased, and the oxygen flow rate is gradually increased; the etching gas in the etching process is chlorine and / or hydrogen bromide gas, the regulating gas in the etching process is oxygen, the flow rate of the etching gas remains constant, and the flow rate of the regulating gas first increases and then decreases; the deoxidation process removes the byproducts generated during the etching process using plasma, and the bias voltage of the deoxidation process is gradually increased.

[0033] In some embodiments, prior to forming the first conductive layer, the substrate is further etched along the first opening to form a first initial opening, and the first conductive layer further fills the first initial opening.

[0034] In some embodiments, the contact structure includes a first contact structure and a second contact structure, the first contact structure being located at a first initial opening, the second contact structure being located above the first contact structure, and the second contact structure having a gradually decreasing size from top to bottom along a direction perpendicular to the substrate.

[0035] In some embodiments, before etching the first conductive layer along a third direction to form the second opening, the method further includes: forming a stacked film layer on the first conductive layer, etching the stacked film layer to form the second initial opening, and etching the first conductive layer along the second initial opening to form the second opening.

[0036] In some embodiments, filling the second opening with a first dielectric layer specifically includes:

[0037] A first initial dielectric layer is filled into the second opening, and the first initial dielectric layer also covers the surface of the second conductive layer. The first initial dielectric layer is then etched back to form a fourth opening, and a second initial dielectric layer is formed in the fourth opening. The first initial dielectric layer and the second initial dielectric layer together constitute the first dielectric layer.

[0038] The technical solution provided in this disclosure improves connection performance by gradually reducing the size of the contact structure from the top of the contact structure to the surface of the substrate along the direction perpendicular to the substrate, i.e., the size of the top of the contact structure is larger. This results in a larger contact area between the contact structure and the conductive structure formed later, and also improves connection performance. Furthermore, the distance between adjacent contact structures and adjacent conductive structures is relatively large to prevent short circuits. Attached Figure Description

[0039] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 is a top view schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0041] Figures 2 to 20 are process flow diagrams of a semiconductor structure formation method provided in an embodiment of the present disclosure, wherein Figures 2 to 5 are cross-sectional views along the B-B' direction in Figure 1, Figures 6 to 20 are cross-sectional views along the D-D' direction in Figure 1, and Figure 17 is a top view of Figure 16.

[0042] Figure 21 is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0043] Figure 22 is a schematic diagram of a semiconductor structure provided in another embodiment of this disclosure. Detailed Implementation

[0044] As is known from the background technology, in the manufacturing process of DRAM (Dynamic Random Access Memory), as chip size continues to shrink, the challenges in the process become increasingly significant, which may lead to a deterioration in the connection performance of conductive and contact structures, and problems such as short circuits between adjacent conductive structures or adjacent contact structures.

[0045] This disclosure provides a semiconductor structure and its manufacturing method. By gradually reducing the size of the contact structure from the top of the contact structure to the surface of the substrate along the direction perpendicular to the substrate, i.e., the size of the top of the contact structure is larger, the contact area between the contact structure and the conductive structure formed later is larger, thereby improving the connection performance; and the distance between adjacent contact structures and adjacent conductive structures is large, preventing short circuits from occurring.

[0046] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0047] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0048] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0049] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0050] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0051] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0052] Figure 1 is a top view of a semiconductor structure provided in an embodiment of the present disclosure; Figures 2 to 20 are process flow diagrams of a semiconductor structure formation method provided in an embodiment of the present disclosure, wherein Figures 2 to 5 are cross-sectional views along the B-B' direction in Figure 1, Figures 6 to 20 are cross-sectional views along the D-D' direction in Figure 1, Figure 17 is a top view of Figure 16; Figure 21 is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 22 is a schematic diagram of a semiconductor structure provided in another embodiment of the present disclosure.

[0053] Referring to Figure 1, a top view of a semiconductor structure is provided here for ease of subsequent description. It includes an active region 102 that extends along a certain inclined direction. Multiple active regions 102 are spaced apart along the extension direction and perpendicular to the extension direction. The blank area between adjacent active regions 102 is an isolation structure (not shown in the figure). A word line structure 104 passes through multiple active regions 102 and extends along a second direction Y. Adjacent word line structures 104 are spaced apart along a first direction X. A bit line structure 20 extends along the first direction X. Multiple bit line structures 20 are spaced apart along the second direction Y.

[0054] Figures 2 to 20 are process flow diagrams of a semiconductor structure formation method provided in an embodiment of this disclosure, wherein Figures 2 to 5 are cross-sectional views along the B-B' direction in Figure 1, and Figures 6 to 20 are cross-sectional views along the D-D' direction in Figure 1. Because the structures presented differ depending on the cutting direction, Figures 2 to 5 are cross-sectional views along the B-B' direction in Figure 1, and Figures 6 to 20 are cross-sectional views along the D-D' direction in Figure 1, in order to more clearly present the inventive concept of this application.

[0055] This application provides a method for forming a semiconductor structure, comprising: providing a substrate 10; forming bit line structures 20 on the substrate 10, the bit line structures 20 extending along a first direction X and spaced apart along a second direction Y, the first direction being perpendicular to X and the second direction Y, and having a first opening 301 between adjacent bit line structures 20; forming a first conductive layer 401 in the first opening 301; etching the first conductive layer 401 along a third direction Z to form a second opening 302, the remaining first conductive layer 401 serving as a second conductive layer 402, the second conductive layer 402 and the second opening 302 being spaced apart along the first direction X, the third direction Z being perpendicular to the substrate; filling the second opening 302 with a first dielectric layer 601; etching back the second conductive layer 402 to form a third opening 303, the remaining second conductive layer 402 serving as a contact structure 70; forming a conductive structure 80 in the third opening 303, the conductive structure 80 being located above the contact structure 70; the contact structure 70 gradually decreasing in size from the top of the contact structure 70 to the surface of the substrate 10 along a direction perpendicular to the substrate 10.

[0056] Please refer to Figure 2 for details. A method for forming a semiconductor structure includes: providing a substrate 10; the substrate 10 includes an isolation structure 101, an active region 102 between adjacent isolation structures 101, forming a bit line structure 20 on the substrate 10, the bit line structure 20 extending along a first direction X and spaced along a second direction Y, the bit line structure 20 having a certain height in a third direction, the first direction X being perpendicular to the second direction Y, and a first opening 301 between adjacent bit line structures 20.

[0057] Next, referring to Figure 4, a first conductive layer 401 is formed in the first opening 301; the first conductive layer 401 also covers the top of the bit line structure 20.

[0058] Referring further to Figure 3, before forming the first conductive layer 401, the substrate 10 is further etched along the first opening 301 to form the first initial opening 301', and the first conductive layer 401 also fills the first initial opening 301'.

[0059] Next, please refer to Figure 5 to remove part of the first conductive layer 401 above the bit line structure 20. Specifically, chemical mechanical polishing (CMP) can be used to remove part of the first conductive layer 401 above the bit line structure 20.

[0060] Next, referring to Figures 6 to 11, before etching the first conductive layer 401 along the third direction Z to form the second opening 302, the method further includes: forming a stacked film layer 50 on the first conductive layer 401, etching the stacked film layer 50 to form the second initial opening 302', and etching the first conductive layer 4011 along the second initial opening 302' to form the second opening 302.

[0061] Referring specifically to Figure 6, a stacked film layer 50 is formed on the first conductive layer 401, and a photoresist layer 506 is formed on the stacked film layer 50. The photoresist layer 506 has a first photolithographic opening K1. The stacked film layer 50 includes a first film layer 501, a second film layer 502, a third film layer 503, a fourth film layer 504, and a fifth film layer 505 arranged sequentially from bottom to top. The fifth film layer 505 can be an anti-reflection layer. The first film layer 501, the second film layer 502, the third film layer 503, and the fourth film layer 504 can be hard mask layers. The first film layer 501, the second film layer 502, the third film layer 503, the fourth film layer 504, and the fifth film layer 505 can each include one or more layers. In one embodiment, the fifth film layer 505 can be silicon hydroxide, and the first film layer 501, the second film layer 502, the third film layer 503, and the fourth film layer 504 can be spin-on hard masks (SOH). Hardmasks, silicon oxynitride, silicon oxide, and amorphous carbon are one or more of these.

[0062] Next, referring to Figure 7, the fifth film layer 505 and the fourth film layer 504 are etched through the first lithographic opening K1 to form the second lithographic opening K2. Referring to Figure 8, the third film layer 503 is etched using Self-Aligned Double Patterning (SADP) to double the feature density of the second lithographic opening K2, forming the third lithographic opening K3. Referring to Figure 9, the second film layer 502 is etched using SADP to form the fourth lithographic opening K4, with the density of the fourth lithographic opening K4 being double that of the third lithographic opening K3. Referring to Figures 9 and 10, the first film layer 501 is etched along the fourth lithographic opening K4 to form the second initial opening 302'.

[0063] Referring to Figure 11, the first conductive layer 401 is etched along the second initial opening 302'. The remaining first conductive layer 401 serves as the second conductive layer 402. The size of the second conductive layer 402 from the top to the surface of the substrate 10 first increases and then decreases, as shown in the enlarged view framed by the dashed line in Figure 11. The size of the second conductive layer 402 along the third direction Z from the top to the surface of the substrate 10 first increases and then decreases, exhibiting an "oval shape," i.e., its sides are arc-shaped. In another embodiment, as shown in Figure 12, the size of the second conductive layer 402 along the third direction Z from the top to the surface of the substrate 10 first increases and then decreases, its sides are linear, and the size is largest in the middle of the second conductive layer 402. The specific method for forming the second conductive layer 402 includes: cyclically performing an oxidation process, an etching process, and a deoxidation process to make the size of the second conductive layer 402 along the third direction Z from the top to the surface of the substrate 10 first increase and then decrease. Specifically, the oxidation process uses oxygen, with the bias voltage and oxygen flow rate gradually increasing; the etching process uses chlorine and / or hydrogen bromide as the etching gas, and oxygen as the regulating gas, with the etching gas flow rate remaining constant while the regulating gas flow rate first increases and then decreases; the deoxidation process uses plasma to remove byproducts generated during the etching process, with the bias voltage gradually increasing.

[0064] The oxidation, etching, and deoxidation processes for forming the second conductive layer 402 will be described in detail below. Since a natural oxide layer may exist on the wafer surface before it enters the process chamber for the aforementioned oxidation, etching, and deoxidation processes, a deoxidation process is required to remove this natural oxide layer. Specifically, the surface exposed by the second initial opening 302' as shown in Figure 10 may have a natural oxide layer. Therefore, a deoxidation process is used to remove the natural oxide layer before the oxidation, etching, and deoxidation processes. This deoxidation process primarily involves removing the natural oxide layer present on the surface through plasma bombardment. Next, during the formal process, using the first film layer 501 as a mask, an oxidation process, an etching process, and a deoxidation process are cycled along the second initial opening 302'. The reason for performing the oxidation process first is that the etched sidewalls need to be protected during the etching of the first conductive layer 401. Therefore, the sidewall oxidation process is performed at the beginning of each cycle. Although the sidewalls and bottom are oxidized simultaneously during oxidation, the subsequent etching process is directional, i.e., it is etched vertically. Therefore, the bottom oxide layer can be removed and the first conductive layer 401 can continue to be etched. Byproducts generated during the etching process need to be bombarded and removed. This process is the deoxidation process. Through the above cycle, the etching of the first conductive layer 401 can be achieved.

[0065] To control the second conductive layer 402 formed by etching into the "oval shape" shown in Figure 11 or the shape shown in Figure 12, the gas trends during each cycle process are as follows: First, the oxidation process is mainly to protect the sidewalls; the higher the oxygen concentration, the better the oxidation effect and the better the sidewall protection. As etching progresses, the aspect ratio of the second opening 302 increases, and increasing the oxygen concentration is necessary to ensure oxygen is present at the bottom of the second opening 302. Therefore, during the etching of the first conductive layer 401 to form the second conductive layer, the oxygen flow rate gradually increases, with an adjustment range of 30 sccm to 100 sccm. A higher bias power during the oxidation process allows more oxygen to enter the bottom of the second opening 302 and enhances the plasma density and activity, which helps to improve the rate and efficiency of the oxidation reaction. Therefore, during the oxidation process, the bias power needs to gradually increase with the increase in depth, with an adjustment range of 0V to 50V. That is, both the oxygen flow rate and the bias power gradually increase during the oxidation process. Secondly, the main etching gases during the etching process are chlorine (Cl2) and / or hydrogen bromide (HBr), with nitrogen fluoride (NF3) and helium (He) as auxiliary gases and oxygen (O2) as a regulating gas. In the etching process, nitrogen fluoride and helium act as carrier gases, bringing the etching gases into the process chamber. During etching, O2 reacts with silicon to form Si-O bonds. Increasing the amount of O2 generates more Si-O bonds, thus inhibiting the formation rate of SiCl4 and SiBr4, resulting in a larger size (CD) of the etched second conductive layer. Conversely, decreasing the amount of O2 reduces the size (CD) of the second conductive layer. In other words, O2 acts as a protective gas during the etching process. The amounts of Cl2 / HBr and NF3 / He can be maintained within a certain range throughout the etching process, but the O2 flow rate needs to increase first and then decrease. That is, the O2 flow rate gradually increases before the CD of the second conductive layer reaches its maximum, and then gradually decreases after the CD reaches its maximum. Secondly, the deoxidation process is actually a process of bombarding byproducts with plasma and then removing them. Since the byproducts at the bottom of the second opening 302 are relatively difficult to remove as the etching depth increases, it is necessary to increase the bias power to increase the removal efficiency of the bottom oxide layer and byproducts. Therefore, during the etching of the first conductive layer 401 to form the second conductive layer, the bias power of the deoxidation process is gradually increased. The bias power adjustment range is 0V to 300V. The higher the bias power, the cleaner the bottom oxide layer and byproducts are removed, while less oxide layer is consumed on the sidewalls. Through the control of the above process and the cycle of oxidation, etching and deoxidation, the second conductive layer 402 is controlled to be shaped into the "oval" shape in Figure 11 or the shape in Figure 12.

[0066] This application will use the "rugby ball" shape in Figure 11 as an example for subsequent processes, but it should be noted that the subsequent processes are also applicable to Figure 12. Next, referring to Figures 13 to 15, the first dielectric layer 60 is filled into the second opening 302. Specifically, this includes: filling the second opening 302 with a first initial dielectric layer 601, which also covers the surface of the second conductive layer 402; etching back the first initial dielectric layer 601 to form a fourth opening 304; and forming a second initial dielectric layer 602 in the fourth opening 304. The first and second initial dielectric layers 601 together constitute the first dielectric layer 60. Specifically, as shown in Figure 14, the fourth opening 304 can be V-shaped. The fourth opening 304 can remove air bubbles generated during the filling process of the first initial dielectric layer 601. In one specific embodiment, the depth of the first initial dielectric layer 601 from the top to the bottom of the first film layer 501 along the Z direction is H1, and the depth of the fourth opening 304 from the top of the first film layer 501 to the bottom of the fourth opening 304 along the Z direction is H2. That is, the depth H2 of the fourth opening 304 is greater than or equal to two-thirds of H1 and less than or equal to four-fifths of H1. 1, In other words, the depth of the fourth opening 304 is more than half the depth of the first initial dielectric layer 601, meaning the depth of the fourth opening 304 exceeds the maximum size of the second conductive layer 402. Next, referring to Figure 15, the second initial dielectric layer 602 is filled into the fourth opening 304. The first initial dielectric layer 601 and the second initial dielectric layer 602 together constitute the first dielectric layer 60. Because the original second opening 302 had a large depth-to-width ratio, air bubbles might form in the lower middle part during the filling process. However, because the depth-to-width ratio of the fourth opening 304 is reduced, the newly filled second initial dielectric layer 602 will not generate air bubbles, thus improving the film quality of the first dielectric layer 60. In a specific embodiment, a portion of the first dielectric layer 60 at the top of the first film layer 501 is removed using a CMP process. The size of the remaining first dielectric layer 60 decreases from top to bottom and then increases, with the largest size in the middle of the first dielectric layer 60. As shown in FIG15 in a specific embodiment, the first dielectric layer also has an air gap 90, which is lower than the bottom of the second initial dielectric layer 602. Since the conductivity of the air gap 90 is lower than that of the first dielectric layer 60, the presence of the air gap 90 can better isolate the adjacent second conductive layer 402.

[0067] Next, please refer to Figure 16. The second conductive layer 402 is etched back along the third direction Z to form the third opening 303. The remaining second conductive layer 402 serves as the contact structure 70. The contact structure 70 includes a first contact structure 701 and a second contact structure 702. The first contact structure 701 is located in the first initial opening 301', and the second contact structure 702 is located above the first contact structure 701. The size of the second contact structure 702 gradually decreases from top to bottom along the direction perpendicular to the substrate 10. It should be noted that the end point of the back etching is at the point where the size of the second conductive layer 402 is the largest, that is, the top size of the contact structure 70 is the largest.

[0068] Figure 17 is a top view of Figure 16; referring to Figure 17, the bit line structure 20 extends along the first direction X and is spaced along the second direction Y, the first direction X is perpendicular to the second direction Y; the first dielectric layer 60 is located between adjacent bit line structures 20 and is spaced along the first direction X; there are also multiple contact structures 70 between adjacent bit line structures 20, the contact structures 70 and the first dielectric layer 60 are spaced along the first direction X.

[0069] Referring to Figure 18, a conductive structure 80 is formed in the third opening 303, located above the contact structure 70. The conductive structure 80 includes a first conductive structure 801 and a second conductive structure 802. The first conductive structure 801 is located in the third opening 303 and is flush with the top surface of the first dielectric layer 60. The second conductive structure 802 is located between the first conductive structure 801 and the contact structure 70. The conductive structure 80 gradually increases in size from top to bottom along a direction perpendicular to the substrate 10. The contact area between the second conductive structure 802 and the contact structure 70 is greater than the cross-sectional area of ​​the conductive structure 80 at any location, and also greater than the cross-sectional area of ​​the contact structure 70 at any location. That is, the contact position between the conductive structure 80 and the contact structure 70 is located at the minimum CD of the first dielectric layer 60. The maximum contact area can reduce the contact resistance between the contact structure 70 and the conductive structure 80, improving the connection performance between the conductive structure and the contact structure.

[0070] As shown in Figure 18, the size of the contact structure 70 gradually decreases from the top of the contact structure 70 to the surface of the substrate 10 along the direction perpendicular to the substrate 10, while the size of the conductive structure 80 gradually increases from the top to the bottom along the direction perpendicular to the substrate 10. The contact area between the conductive structure 80 and the contact structure 70 is the largest. As shown in Figures 10 and 11, in the prior art, the second conductive layer 402 formed by etching the first conductive layer 401 along the second initial opening 302' does not have the trend of CD first increasing and then decreasing. That is, the second conductive layer in the prior art will not form the "rugby ball" shape shown in Figure 11 or the shape shown in Figure 12. In fact, in the prior art, the second conductive layer is only etched along the size exposed by the second initial opening 302', that is, the size of the second conductive layer from top to bottom is only about the size exposed by the second initial opening 302'. In other words, the CD of the finally formed contact structure in the prior art does not show a trend of gradually decreasing from top to bottom, and the conductive structure does not show a trend of gradually increasing from top to bottom. Therefore, there is no maximum contact area between the conductive structure and the contact structure in the prior art. In this application, by adjusting the cycle of oxidation, etching, and deoxidation processes, the dimensions of the second conductive layer 402 along the direction perpendicular to the substrate 10, from its top to the surface of the substrate 10, first increase and then decrease. This maximizes the contact area between the final conductive structure 80 and the contact structure 70, improving their connection performance. Furthermore, as shown in Figure 18, the dimensions of the first dielectric layer 60 first decrease and then increase from top to bottom, meaning the first dielectric layer 60 at the position corresponding to the conductive structure 80 exhibits an inverted trapezoidal shape. This increases the spacing between adjacent conductive structures, preventing short circuits caused by adjacent isolation structures being too close. Since the second opening 302 itself has a tendency to decrease and then increase CD from top to bottom, a larger top opening during the formation of the first dielectric layer 60 prevents the formation of a top air gap. Similarly, the first dielectric layer 60 at the position corresponding to the contact structure 70 exhibits a trapezoidal shape, further increasing the spacing between adjacent contact structures 70 and preventing short circuits caused by adjacent contact structures 70 being too close. Since the bottom of the contact structure and the top of the conductive structure are the most likely places for short circuits in the prior art, the first dielectric layer 60 at the top of the conductive structure 80 and the bottom of the contact structure 70 in this application has a larger CD, which improves the isolation effect between adjacent conductive structures 80 and between adjacent contact structures 70, prevents short circuits from occurring, and improves the performance of the semiconductor structure.In another embodiment, the first dielectric layer 60 also has an air gap 90, which is lower than the interface between the conductive structure 80 and the contact structure 70. Specifically, the air gap 90 is lower than the bottom of the second initial dielectric layer 602. Since the conductivity of the air gap 90 is lower than that of the first dielectric layer 60, the presence of the air gap 90 can better isolate adjacent contact structures 70 and further prevent short circuits between adjacent contact structures 70. Of course, in other embodiments, the air gap 90 may not exist in the first dielectric layer 60. In a specific embodiment, the contact structure 70 can be polycrystalline silicon, the first conductive structure 801 can be one or more of copper, tungsten, titanium, and titanium nitride, and the second conductive structure can be one or more of cobalt silicide, titanium silicide, and nickel silicide.

[0071] Referring next to Figure 19, in other embodiments, a conductive structure 80 is formed in the third opening 303, and an initial top conductive structure 803' is formed above the conductive structure 80. The initial top conductive structure 803' is located above the conductive structure 80 and covers the top surface of the first dielectric layer 60. It should be noted that the initial top conductive structure 803' can be formed simultaneously with the conductive structure 80, or it can be formed step by step, that is, the conductive structure 80 can be formed first and then the initial top conductive structure 803' can be formed.

[0072] Next, referring to Figure 20, a portion of the initial top conductive structure 803' is etched to expose a portion of the top of the first dielectric layer 60. The remaining initial top conductive structure 803' constitutes the top conductive structure 803. The top conductive structure 803 is formed above the conductive structure 80 and covers a portion of the top surface of the first dielectric layer 60. The top conductive structure 803 and the conductive structure 80 can together constitute the landing pad structure LP. The contact structure 70 can serve as a contact node NC. The material of the top conductive structure 803 can be one or more of copper, tungsten, titanium, and titanium nitride.

[0073] In this embodiment, by adjusting the cycle of oxidation, etching, and deoxidation processes, the dimensions of the second conductive layer 402 along the direction perpendicular to the substrate 10, from its top to the surface of the substrate 10, first increase and then decrease. This maximizes the contact area between the final conductive structure 80 and the contact structure 70, improving their connection performance. The dimensions of the first dielectric layer 60 first decrease and then increase from top to bottom, improving the isolation between adjacent conductive structures 80 and adjacent contact structures 70, preventing short circuits, and enhancing semiconductor structure performance.

[0074] Figure 21 is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure. The enlarged structure within the dashed box is shown on the right. Referring to Figures 17 and 21, a semiconductor structure includes: a substrate 10; bit line structures 20 located on the substrate 10, multiple bit line structures 20 extending along a first direction X and spaced apart along a second direction Y, the first direction X being perpendicular to the second direction Y; a first dielectric layer 60 located between adjacent bit line structures 20 and spaced apart along the first direction X; contact structures 70 located between adjacent bit line structures 20, the contact structures 70 being spaced apart from the first dielectric layer 60; a conductive structure 80 located above the contact structures 70, the top of the conductive structure 80 being flush with the top of the first dielectric layer 60; the dimensions of the contact structures 70 gradually decrease from the top of the contact structure 70 to the surface of the substrate 10 along the Z direction perpendicular to the substrate 10. The conductive structure 80 includes a first conductive structure 801 and a second conductive structure 802. The first conductive structure 801 is flush with the top surface of the first dielectric layer 60, and the second conductive structure 802 is located between the first conductive structure 801 and the contact structure 70. The conductive structure 80 gradually increases in size from top to bottom along a direction perpendicular to the substrate 10. The contact area between the second conductive structure 802 and the contact structure 70 is greater than the cross-sectional area of ​​the conductive structure 80 at any location, and also greater than the cross-sectional area of ​​the contact structure 70 at any location. In one embodiment, the semiconductor structure further includes a top conductive structure 803, which is located above the conductive structure 80 and covers a portion of the top surface of the first dielectric layer 60. The size of the first dielectric layer 60 decreases first and then increases from top to bottom. In one specific embodiment, the first dielectric layer 60 also has an air gap 90, which is lower than the interface between the conductive structure 80 and the contact structure 70. The contact structure 70 includes a first contact structure 701 and a second contact structure 702. The first contact structure 701 is embedded in the substrate 10, and the second contact structure 702 is located above the first contact structure. The dimensions of the second contact structure 702 gradually decrease from top to bottom along the direction perpendicular to the substrate 10. The embedding of the first contact structure 701 in the substrate 10 increases the contact area between the contact structure 70 and the substrate 10. As shown in Figure 21, the conductive structure 80 and the contact structure 70 together form a "rugby ball" shape. The dimensions of the conductive structure 80 gradually increase from top to bottom along the direction perpendicular to the substrate 10, while the dimensions of the contact structure 70 from top to surface of the substrate 10 gradually decrease. The cross-sections of both the conductive structure 80 and the contact structure 70 are arc-shaped.

[0075] Figure 22 is a schematic diagram of a semiconductor structure provided in another embodiment of this disclosure. The enlarged structure within the dashed box is shown on the right. The parts identical to those in Figure 21 will not be described again; the difference is that the cross-sections of the conductive structure 80 and the contact structure 70 are both linear.

[0076] Referring to Figures 21 and 22, in the semiconductor structure of this application, the dimension of the contact structure 70 at the position flush with the substrate 10 is CD3, the dimension of the top of the conductive structure 180 is CD2, and the dimension of the interface between the contact structure 70 and the conductive structure 80 is CD1. That is, the contact area between the conductive structure 80 and the contact structure 70 is greater than the cross-sectional area of ​​the conductive structure 80 at any position, and also greater than the cross-sectional area of ​​the contact structure 70 at any position. In the prior art, the CD of the final formed contact structure does not show a gradual decreasing trend from top to bottom, nor does the conductive structure show a gradual increasing trend from top to bottom. Therefore, in the prior art, there is no maximum contact area between the conductive structure and the contact structure. In this application, the contact area between the conductive structure 80 and the contact structure 70 is the largest, improving the connection performance of the conductive structure 80 and the contact structure 70. The size of the first dielectric layer 60 decreases and then increases from top to bottom, meaning that the first dielectric layer 60 at the position corresponding to the conductive structure 80 has an inverted trapezoidal shape. This increases the spacing between adjacent conductive structures, preventing short circuits caused by adjacent isolation structures being too close. Similarly, the first dielectric layer 60 at the position corresponding to the contact structure 70 has a regular trapezoidal shape, increasing the spacing between adjacent contact structures 70 and preventing short circuits caused by adjacent contact structures 70 being too close. Since the bottom of the contact structure and the top of the conductive structure are the most prone to short circuits in the prior art, the first dielectric layer 60 at the top of the conductive structure 80 and the bottom of the contact structure 70 in this application has a larger CD, improving the isolation effect between adjacent conductive structures 80 and adjacent contact structures 70, preventing short circuits, and improving the performance of the semiconductor structure.

[0077] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base (10); Bit line structures (20) are located on the substrate (10). Multiple bit line structures (20) extend along a first direction (X) and are spaced apart along a second direction (Y). The first direction (X) is perpendicular to the second direction (Y). A first dielectric layer (60) is located between adjacent bit line structures (20) and spaced apart along the first direction (X); A contact structure (70) is located between adjacent bit line structures (20), and the contact structure (70) is spaced apart from the first dielectric layer (60); A conductive structure (80) is located above the contact structure (70), and the top of the conductive structure (80) is flush with the top of the first dielectric layer (60). The dimensions of the contact structure (70) gradually decrease from the top of the contact structure (70) to the surface of the substrate (10) along a direction perpendicular to the substrate (10).

2. The semiconductor structure according to claim 1, characterized in that, The conductive structure (80) includes a first conductive structure (801) and a second conductive structure (802). The first conductive structure (801) is flush with the top surface of the first dielectric layer (60). The second conductive structure (802) is located between the first conductive structure (801) and the contact structure (70). The conductive structure (80) gradually increases in size from top to bottom along a direction perpendicular to the substrate (10).

3. The semiconductor structure according to claim 1, characterized in that, The contact area between the conductive structure (80) and the contact structure (70) is greater than the cross-sectional area of ​​the conductive structure (80) at any position, and is also greater than the cross-sectional area of ​​the contact structure (70) at any position.

4. The semiconductor structure according to claim 1, characterized in that, It also includes a top conductive structure (803) located above the conductive structure (80) and covering part of the top surface of the first dielectric layer (60).

5. The semiconductor structure according to claim 1, characterized in that, The size of the first dielectric layer (60) decreases from top to bottom and then increases. The first dielectric layer (60) also has an air gap (90) which is below the interface between the conductive structure (80) and the contact structure (70).

6. The semiconductor structure according to claim 1, characterized in that, The contact structure (70) includes a first contact structure (701) and a second contact structure (702). The first contact structure (701) is embedded in the substrate (10), and the second contact structure (702) is located above the first contact structure (701). The second contact structure (702) gradually decreases in size from top to bottom along a direction perpendicular to the substrate (10).

7. A method for forming a semiconductor structure, characterized in that, include: Provide a base (10); Bit line structures (20) are formed on the substrate (10), the bit line structures (20) extend along a first direction (X) and are spaced apart along a second direction (Y), the first direction (X) is perpendicular to the second direction (Y), and a first opening (301) is provided between adjacent bit line structures (20); A first conductive layer (401) is formed in the first opening (301); The first conductive layer (401) is etched along a third direction (Z) to form a second opening (302), and the remaining first conductive layer (401) serves as the second conductive layer (402). The second conductive layer (402) and the second opening (302) are spaced apart along the first direction (X), and the third direction (Z) is perpendicular to the substrate (10). The second opening (302) is filled with a first dielectric layer (60); The second conductive layer (402) is etched back to form a third opening (303), and the remaining second conductive layer (402) serves as a contact structure (70). A conductive structure (80) is formed in the third opening (303), the conductive structure (80) being located above the contact structure (70); The dimensions of the contact structure (70) gradually decrease from the top of the contact structure (70) to the surface of the substrate (10) along a direction perpendicular to the substrate (10).

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The conductive structure (80) includes a first conductive structure (801) and a second conductive structure (802). The first conductive structure (801) is located in the third opening (303) and is flush with the top surface of the first dielectric layer (60). The second conductive structure (802) is located between the first conductive structure (801) and the contact structure (70). The conductive structure (80) gradually increases in size from top to bottom along a direction perpendicular to the substrate (10).

9. The method for forming a semiconductor structure according to claim 7, characterized in that, The contact area between the conductive structure (80) and the contact structure (70) is greater than the cross-sectional area of ​​the conductive structure (80) at any position, and is also greater than the cross-sectional area of ​​the contact structure (70) at any position.

10. The method for forming a semiconductor structure according to claim 7, characterized in that, It also includes a top conductive structure (803) formed above the conductive structure (80) and covering part of the top surface of the first dielectric layer (60).

11. The method for forming a semiconductor structure according to claim 7, characterized in that, The size of the first dielectric layer (60) decreases from top to bottom and then increases; the first dielectric layer (60) also has an air gap (90) which is below the interface between the conductive structure (80) and the contact structure (70).

12. The method for forming a semiconductor structure according to any one of claims 7-11, characterized in that, The size of the second conductive layer (402) increases from top to bottom and then decreases. The method for forming the second conductive layer (402) includes cyclically performing an oxidation process, an etching process, and a deoxidation process.

13. The method for forming a semiconductor structure according to claim 12, characterized in that, The oxidation process uses oxygen, with the bias voltage and flow rate of the oxygen gradually increasing. The etching process uses chlorine and / or hydrogen bromide as the etching gas, and oxygen as the regulating gas. The flow rate of the etching gas remains constant, while the flow rate of the regulating gas first increases and then decreases. The deoxidation process removes byproducts generated during the etching process using plasma, with the bias voltage of the deoxidation process gradually increasing.

14. The method for forming a semiconductor structure according to claim 7, characterized in that, Before forming the first conductive layer (401), the substrate (10) is further etched along the first opening (301) to form a first initial opening (301'), and the first conductive layer (401) also fills the first initial opening (301').

15. The method for forming a semiconductor structure according to claim 14, characterized in that, The contact structure (70) includes a first contact structure (701) and a second contact structure (702). The first contact structure (701) is located at the first initial opening (301'), and the second contact structure (702) is located above the first contact structure (701). The second contact structure (702) gradually decreases in size from top to bottom along a direction perpendicular to the substrate (10).

16. The method for forming a semiconductor structure according to claim 7, characterized in that, Before etching the first conductive layer (401) along the third direction (Z) to form the second opening (302), the method further includes: forming a stacked film layer (50) on the first conductive layer (401), etching the stacked film layer (50) to form a second initial opening (302'), and etching the first conductive layer (401) along the second initial opening (302') to form the second opening (302).

17. The method for forming a semiconductor structure according to claim 7, characterized in that, Filling the second opening (302) with the first dielectric layer (60) specifically includes: A first initial dielectric layer (601) is filled into the second opening (302), the first initial dielectric layer (601) also covers the surface of the second conductive layer (402), the first initial dielectric layer (601) is etched back to form a fourth opening (304), a second initial dielectric layer (602) is formed in the fourth opening (304), the first initial dielectric layer (601) and the second initial dielectric layer (602) together constitute the first dielectric layer (60).

Images